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author therealmogminer@gmail.com <therealmogminer@gmail.com>2016-10-21 14:50:37 +0200
committer therealmogminer@gmail.com <therealmogminer@gmail.com>2016-10-21 14:50:56 +0200
commit12aa436b966fef173c9c254ecdba36033a475f5a (patch)
tree4a59ae4f5600cebcf8fa22265d496732ebf4c060 /src/devices/cpu/arm7/arm7thmb.cpp
parent66c56d1c9a63e8a3945e9e0c06981aa490d2b371 (diff)
-arm7: Performed some minor optimization. [Ryan Holtz]
Diffstat (limited to 'src/devices/cpu/arm7/arm7thmb.cpp')
-rw-r--r--src/devices/cpu/arm7/arm7thmb.cpp408
1 files changed, 204 insertions, 204 deletions
diff --git a/src/devices/cpu/arm7/arm7thmb.cpp b/src/devices/cpu/arm7/arm7thmb.cpp
index 3dfd46094aa..fd26210d7bc 100644
--- a/src/devices/cpu/arm7/arm7thmb.cpp
+++ b/src/devices/cpu/arm7/arm7thmb.cpp
@@ -289,30 +289,30 @@ void arm7_cpu_device::tg00_0(UINT32 pc, UINT32 op) /* Shift left */
UINT32 rs, rd, rrs;
INT32 offs;
- SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK));
+ set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK));
rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- rrs = GET_REGISTER(rs);
+ rrs = GetRegister(rs);
offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
if (offs != 0)
{
- SET_REGISTER(rd, rrs << offs);
+ SetRegister(rd, rrs << offs);
if (rrs & (1 << (31 - (offs - 1))))
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
else
{
- SET_REGISTER(rd, rrs);
+ SetRegister(rd, rrs);
}
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -323,34 +323,34 @@ void arm7_cpu_device::tg00_1(UINT32 pc, UINT32 op) /* Shift right */
rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- rrs = GET_REGISTER(rs);
+ rrs = GetRegister(rs);
offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
if (offs != 0)
{
- SET_REGISTER(rd, rrs >> offs);
+ SetRegister(rd, rrs >> offs);
if (rrs & (1 << (offs - 1)))
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
else
{
- SET_REGISTER(rd, 0);
+ SetRegister(rd, 0);
if (rrs & 0x80000000)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -365,7 +365,7 @@ void arm7_cpu_device::tg01_0(UINT32 pc, UINT32 op)
{
rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- rrs = GET_REGISTER(rs);
+ rrs = GetRegister(rs);
offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
if (offs == 0)
{
@@ -375,72 +375,72 @@ void arm7_cpu_device::tg01_0(UINT32 pc, UINT32 op)
{
if (rrs >> 31)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
- SET_REGISTER(rd, (rrs & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
+ SetRegister(rd, (rrs & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
}
else
{
if ((rrs >> (offs - 1)) & 1)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
- SET_REGISTER(rd,
+ SetRegister(rd,
(rrs & 0x80000000)
? ((0xFFFFFFFF << (32 - offs)) | (rrs >> offs))
: (rrs >> offs));
}
- SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
}
void arm7_cpu_device::tg01_10(UINT32 pc, UINT32 op) /* ADD Rd, Rs, Rn */
{
- UINT32 rn = GET_REGISTER((op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
- UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
+ UINT32 rn = GetRegister((op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
+ UINT32 rs = GetRegister((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, rs + rn);
- HandleThumbALUAddFlags(GET_REGISTER(rd), rs, rn);
+ SetRegister(rd, rs + rn);
+ HandleThumbALUAddFlags(GetRegister(rd), rs, rn);
}
void arm7_cpu_device::tg01_11(UINT32 pc, UINT32 op) /* SUB Rd, Rs, Rn */
{
- UINT32 rn = GET_REGISTER((op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
- UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
+ UINT32 rn = GetRegister((op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT);
+ UINT32 rs = GetRegister((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, rs - rn);
- HandleThumbALUSubFlags(GET_REGISTER(rd), rs, rn);
+ SetRegister(rd, rs - rn);
+ HandleThumbALUSubFlags(GetRegister(rd), rs, rn);
}
void arm7_cpu_device::tg01_12(UINT32 pc, UINT32 op) /* ADD Rd, Rs, #imm */
{
UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
- UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
+ UINT32 rs = GetRegister((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, rs + imm);
- HandleThumbALUAddFlags(GET_REGISTER(rd), rs, imm);
+ SetRegister(rd, rs + imm);
+ HandleThumbALUAddFlags(GetRegister(rd), rs, imm);
}
void arm7_cpu_device::tg01_13(UINT32 pc, UINT32 op) /* SUB Rd, Rs, #imm */
{
UINT32 imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
- UINT32 rs = GET_REGISTER((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
+ UINT32 rs = GetRegister((op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT);
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, rs - imm);
- HandleThumbALUSubFlags(GET_REGISTER(rd), rs,imm);
+ SetRegister(rd, rs - imm);
+ HandleThumbALUSubFlags(GetRegister(rd), rs,imm);
}
@@ -450,15 +450,15 @@ void arm7_cpu_device::tg02_0(UINT32 pc, UINT32 op)
{
UINT32 rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
UINT32 op2 = (op & THUMB_INSN_IMM);
- SET_REGISTER(rd, op2);
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ SetRegister(rd, op2);
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
void arm7_cpu_device::tg02_1(UINT32 pc, UINT32 op)
{
- UINT32 rn = GET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
+ UINT32 rn = GetRegister((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
UINT32 op2 = op & THUMB_INSN_IMM;
UINT32 rd = rn - op2;
HandleThumbALUSubFlags(rd, rn, op2);
@@ -468,19 +468,19 @@ void arm7_cpu_device::tg02_1(UINT32 pc, UINT32 op)
void arm7_cpu_device::tg03_0(UINT32 pc, UINT32 op) /* ADD Rd, #Offset8 */
{
- UINT32 rn = GET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
+ UINT32 rn = GetRegister((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
UINT32 op2 = op & THUMB_INSN_IMM;
UINT32 rd = rn + op2;
- SET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
+ SetRegister((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
HandleThumbALUAddFlags(rd, rn, op2);
}
void arm7_cpu_device::tg03_1(UINT32 pc, UINT32 op) /* SUB Rd, #Offset8 */
{
- UINT32 rn = GET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
+ UINT32 rn = GetRegister((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT);
UINT32 op2 = op & THUMB_INSN_IMM;
UINT32 rd = rn - op2;
- SET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
+ SetRegister((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, rd);
HandleThumbALUSubFlags(rd, rn, op2);
}
@@ -490,9 +490,9 @@ void arm7_cpu_device::tg04_00_00(UINT32 pc, UINT32 op) /* AND Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, GET_REGISTER(rd) & GET_REGISTER(rs));
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ SetRegister(rd, GetRegister(rd) & GetRegister(rs));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -500,9 +500,9 @@ void arm7_cpu_device::tg04_00_01(UINT32 pc, UINT32 op) /* EOR Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, GET_REGISTER(rd) ^ GET_REGISTER(rs));
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ SetRegister(rd, GetRegister(rd) ^ GetRegister(rs));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -510,42 +510,42 @@ void arm7_cpu_device::tg04_00_02(UINT32 pc, UINT32 op) /* LSL Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rrd = GET_REGISTER(rd);
- INT32 offs = GET_REGISTER(rs) & 0x000000ff;
+ UINT32 rrd = GetRegister(rd);
+ INT32 offs = GetRegister(rs) & 0x000000ff;
if (offs > 0)
{
if (offs < 32)
{
- SET_REGISTER(rd, rrd << offs);
+ SetRegister(rd, rrd << offs);
if (rrd & (1 << (31 - (offs - 1))))
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
else if (offs == 32)
{
- SET_REGISTER(rd, 0);
+ SetRegister(rd, 0);
if (rrd & 1)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
else
{
- SET_REGISTER(rd, 0);
- SET_CPSR(GET_CPSR & ~C_MASK);
+ SetRegister(rd, 0);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -553,42 +553,42 @@ void arm7_cpu_device::tg04_00_03(UINT32 pc, UINT32 op) /* LSR Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rrd = GET_REGISTER(rd);
- INT32 offs = GET_REGISTER(rs) & 0x000000ff;
+ UINT32 rrd = GetRegister(rd);
+ INT32 offs = GetRegister(rs) & 0x000000ff;
if (offs > 0)
{
if (offs < 32)
{
- SET_REGISTER(rd, rrd >> offs);
+ SetRegister(rd, rrd >> offs);
if (rrd & (1 << (offs - 1)))
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
else if (offs == 32)
{
- SET_REGISTER(rd, 0);
+ SetRegister(rd, 0);
if (rrd & 0x80000000)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
else
{
- SET_REGISTER(rd, 0);
- SET_CPSR(GET_CPSR & ~C_MASK);
+ SetRegister(rd, 0);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
}
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -596,39 +596,39 @@ void arm7_cpu_device::tg04_00_04(UINT32 pc, UINT32 op) /* ASR Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rrs = GET_REGISTER(rs)&0xff;
- UINT32 rrd = GET_REGISTER(rd);
+ UINT32 rrs = GetRegister(rs)&0xff;
+ UINT32 rrd = GetRegister(rd);
if (rrs != 0)
{
if (rrs >= 32)
{
if (rrd >> 31)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
- SET_REGISTER(rd, (GET_REGISTER(rd) & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
+ SetRegister(rd, (GetRegister(rd) & 0x80000000) ? 0xFFFFFFFF : 0x00000000);
}
else
{
if ((rrd >> (rrs-1)) & 1)
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
- SET_REGISTER(rd, (rrd & 0x80000000)
+ SetRegister(rd, (rrd & 0x80000000)
? ((0xFFFFFFFF << (32 - rrs)) | (rrd >> rrs))
: (rrd >> rrs));
}
}
- SET_CPSR(GET_CPSR & ~(N_MASK | Z_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(N_MASK | Z_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -637,9 +637,9 @@ void arm7_cpu_device::tg04_00_05(UINT32 pc, UINT32 op) /* ADC Rd, Rs */
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UINT32 op2 = (GET_CPSR & C_MASK) ? 1 : 0;
- UINT32 rn = GET_REGISTER(rd) + GET_REGISTER(rs) + op2;
- HandleThumbALUAddFlags(rn, GET_REGISTER(rd), (GET_REGISTER(rs))); // ?
- SET_REGISTER(rd, rn);
+ UINT32 rn = GetRegister(rd) + GetRegister(rs) + op2;
+ HandleThumbALUAddFlags(rn, GetRegister(rd), (GetRegister(rs))); // ?
+ SetRegister(rd, rn);
}
void arm7_cpu_device::tg04_00_06(UINT32 pc, UINT32 op) /* SBC Rd, Rs */
@@ -647,28 +647,28 @@ void arm7_cpu_device::tg04_00_06(UINT32 pc, UINT32 op) /* SBC Rd, Rs */
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
UINT32 op2 = (GET_CPSR & C_MASK) ? 0 : 1;
- UINT32 rn = GET_REGISTER(rd) - GET_REGISTER(rs) - op2;
- HandleThumbALUSubFlags(rn, GET_REGISTER(rd), (GET_REGISTER(rs))); //?
- SET_REGISTER(rd, rn);
+ UINT32 rn = GetRegister(rd) - GetRegister(rs) - op2;
+ HandleThumbALUSubFlags(rn, GetRegister(rd), (GetRegister(rs))); //?
+ SetRegister(rd, rn);
}
void arm7_cpu_device::tg04_00_07(UINT32 pc, UINT32 op) /* ROR Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rrd = GET_REGISTER(rd);
- UINT32 imm = GET_REGISTER(rs) & 0x0000001f;
- SET_REGISTER(rd, (rrd >> imm) | (rrd << (32 - imm)));
+ UINT32 rrd = GetRegister(rd);
+ UINT32 imm = GetRegister(rs) & 0x0000001f;
+ SetRegister(rd, (rrd >> imm) | (rrd << (32 - imm)));
if (rrd & (1 << (imm - 1)))
{
- SET_CPSR(GET_CPSR | C_MASK);
+ set_cpsr(GET_CPSR | C_MASK);
}
else
{
- SET_CPSR(GET_CPSR & ~C_MASK);
+ set_cpsr(GET_CPSR & ~C_MASK);
}
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -676,8 +676,8 @@ void arm7_cpu_device::tg04_00_08(UINT32 pc, UINT32 op) /* TST Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd) & GET_REGISTER(rs)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd) & GetRegister(rs)));
R15 += 2;
}
@@ -685,34 +685,34 @@ void arm7_cpu_device::tg04_00_09(UINT32 pc, UINT32 op) /* NEG Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rrs = GET_REGISTER(rs);
- SET_REGISTER(rd, 0 - rrs);
- HandleThumbALUSubFlags(GET_REGISTER(rd), 0, rrs);
+ UINT32 rrs = GetRegister(rs);
+ SetRegister(rd, 0 - rrs);
+ HandleThumbALUSubFlags(GetRegister(rd), 0, rrs);
}
void arm7_cpu_device::tg04_00_0a(UINT32 pc, UINT32 op) /* CMP Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rn = GET_REGISTER(rd) - GET_REGISTER(rs);
- HandleThumbALUSubFlags(rn, GET_REGISTER(rd), GET_REGISTER(rs));
+ UINT32 rn = GetRegister(rd) - GetRegister(rs);
+ HandleThumbALUSubFlags(rn, GetRegister(rd), GetRegister(rs));
}
void arm7_cpu_device::tg04_00_0b(UINT32 pc, UINT32 op) /* CMN Rd, Rs - check flags, add dasm */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rn = GET_REGISTER(rd) + GET_REGISTER(rs);
- HandleThumbALUAddFlags(rn, GET_REGISTER(rd), GET_REGISTER(rs));
+ UINT32 rn = GetRegister(rd) + GetRegister(rs);
+ HandleThumbALUAddFlags(rn, GetRegister(rd), GetRegister(rs));
}
void arm7_cpu_device::tg04_00_0c(UINT32 pc, UINT32 op) /* ORR Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, GET_REGISTER(rd) | GET_REGISTER(rs));
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ SetRegister(rd, GetRegister(rd) | GetRegister(rs));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -720,10 +720,10 @@ void arm7_cpu_device::tg04_00_0d(UINT32 pc, UINT32 op) /* MUL Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 rn = GET_REGISTER(rd) * GET_REGISTER(rs);
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_REGISTER(rd, rn);
- SET_CPSR(GET_CPSR | HandleALUNZFlags(rn));
+ UINT32 rn = GetRegister(rd) * GetRegister(rs);
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ SetRegister(rd, rn);
+ set_cpsr(GET_CPSR | HandleALUNZFlags(rn));
R15 += 2;
}
@@ -731,9 +731,9 @@ void arm7_cpu_device::tg04_00_0e(UINT32 pc, UINT32 op) /* BIC Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, GET_REGISTER(rd) & (~GET_REGISTER(rs)));
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ SetRegister(rd, GetRegister(rd) & (~GetRegister(rs)));
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -741,10 +741,10 @@ void arm7_cpu_device::tg04_00_0f(UINT32 pc, UINT32 op) /* MVN Rd, Rs */
{
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- UINT32 op2 = GET_REGISTER(rs);
- SET_REGISTER(rd, ~op2);
- SET_CPSR(GET_CPSR & ~(Z_MASK | N_MASK));
- SET_CPSR(GET_CPSR | HandleALUNZFlags(GET_REGISTER(rd)));
+ UINT32 op2 = GetRegister(rs);
+ SetRegister(rd, ~op2);
+ set_cpsr(GET_CPSR & ~(Z_MASK | N_MASK));
+ set_cpsr(GET_CPSR | HandleALUNZFlags(GetRegister(rd)));
R15 += 2;
}
@@ -759,11 +759,11 @@ void arm7_cpu_device::tg04_01_01(UINT32 pc, UINT32 op) /* ADD Rd, HRs */
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UINT32 rd = op & THUMB_HIREG_RD;
- SET_REGISTER(rd, GET_REGISTER(rd) + GET_REGISTER(rs+8));
+ SetRegister(rd, GetRegister(rd) + GetRegister(rs+8));
// emulate the effects of pre-fetch
if (rs == 7)
{
- SET_REGISTER(rd, GET_REGISTER(rd) + 4);
+ SetRegister(rd, GetRegister(rd) + 4);
}
R15 += 2;
@@ -773,7 +773,7 @@ void arm7_cpu_device::tg04_01_02(UINT32 pc, UINT32 op) /* ADD HRd, Rs */
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UINT32 rd = op & THUMB_HIREG_RD;
- SET_REGISTER(rd+8, GET_REGISTER(rd+8) + GET_REGISTER(rs));
+ SetRegister(rd+8, GetRegister(rd+8) + GetRegister(rs));
if (rd == 7)
{
R15 += 2;
@@ -786,11 +786,11 @@ void arm7_cpu_device::tg04_01_03(UINT32 pc, UINT32 op) /* Add HRd, HRs */
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UINT32 rd = op & THUMB_HIREG_RD;
- SET_REGISTER(rd+8, GET_REGISTER(rd+8) + GET_REGISTER(rs+8));
+ SetRegister(rd+8, GetRegister(rd+8) + GetRegister(rs+8));
// emulate the effects of pre-fetch
if (rs == 7)
{
- SET_REGISTER(rd+8, GET_REGISTER(rd+8) + 4);
+ SetRegister(rd+8, GetRegister(rd+8) + 4);
}
if (rd == 7)
{
@@ -802,32 +802,32 @@ void arm7_cpu_device::tg04_01_03(UINT32 pc, UINT32 op) /* Add HRd, HRs */
void arm7_cpu_device::tg04_01_10(UINT32 pc, UINT32 op) /* CMP Rd, Rs */
{
- UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
- UINT32 rd = GET_REGISTER(op & THUMB_HIREG_RD);
+ UINT32 rs = GetRegister(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
+ UINT32 rd = GetRegister(op & THUMB_HIREG_RD);
UINT32 rn = rd - rs;
HandleThumbALUSubFlags(rn, rd, rs);
}
void arm7_cpu_device::tg04_01_11(UINT32 pc, UINT32 op) /* CMP Rd, Hs */
{
- UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
- UINT32 rd = GET_REGISTER(op & THUMB_HIREG_RD);
+ UINT32 rs = GetRegister(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
+ UINT32 rd = GetRegister(op & THUMB_HIREG_RD);
UINT32 rn = rd - rs;
HandleThumbALUSubFlags(rn, rd, rs);
}
void arm7_cpu_device::tg04_01_12(UINT32 pc, UINT32 op) /* CMP Hd, Rs */
{
- UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
- UINT32 rd = GET_REGISTER((op & THUMB_HIREG_RD) + 8);
+ UINT32 rs = GetRegister(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT));
+ UINT32 rd = GetRegister((op & THUMB_HIREG_RD) + 8);
UINT32 rn = rd - rs;
HandleThumbALUSubFlags(rn, rd, rs);
}
void arm7_cpu_device::tg04_01_13(UINT32 pc, UINT32 op) /* CMP Hd, Hs */
{
- UINT32 rs = GET_REGISTER(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
- UINT32 rd = GET_REGISTER((op & THUMB_HIREG_RD) + 8);
+ UINT32 rs = GetRegister(((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT) + 8);
+ UINT32 rd = GetRegister((op & THUMB_HIREG_RD) + 8);
UINT32 rn = rd - rs;
HandleThumbALUSubFlags(rn, rd, rs);
}
@@ -839,7 +839,7 @@ void arm7_cpu_device::tg04_01_20(UINT32 pc, UINT32 op) /* MOV Rd, Rs (undefined)
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UINT32 rd = op & THUMB_HIREG_RD;
- SET_REGISTER(rd, GET_REGISTER(rs));
+ SetRegister(rd, GetRegister(rs));
R15 += 2;
}
@@ -847,10 +847,10 @@ void arm7_cpu_device::tg04_01_21(UINT32 pc, UINT32 op) /* MOV Rd, Hs */
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UINT32 rd = op & THUMB_HIREG_RD;
- SET_REGISTER(rd, GET_REGISTER(rs + 8));
+ SetRegister(rd, GetRegister(rs + 8));
if (rs == 7)
{
- SET_REGISTER(rd, GET_REGISTER(rd) + 4);
+ SetRegister(rd, GetRegister(rd) + 4);
}
R15 += 2;
}
@@ -859,7 +859,7 @@ void arm7_cpu_device::tg04_01_22(UINT32 pc, UINT32 op) /* MOV Hd, Rs */
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
UINT32 rd = op & THUMB_HIREG_RD;
- SET_REGISTER(rd + 8, GET_REGISTER(rs));
+ SetRegister(rd + 8, GetRegister(rs));
if (rd != 7)
{
R15 += 2;
@@ -876,11 +876,11 @@ void arm7_cpu_device::tg04_01_23(UINT32 pc, UINT32 op) /* MOV Hd, Hs */
UINT32 rd = op & THUMB_HIREG_RD;
if (rs == 7)
{
- SET_REGISTER(rd + 8, GET_REGISTER(rs+8)+4);
+ SetRegister(rd + 8, GetRegister(rs+8)+4);
}
else
{
- SET_REGISTER(rd + 8, GET_REGISTER(rs+8));
+ SetRegister(rd + 8, GetRegister(rs+8));
}
if (rd != 7)
{
@@ -895,14 +895,14 @@ void arm7_cpu_device::tg04_01_23(UINT32 pc, UINT32 op) /* MOV Hd, Hs */
void arm7_cpu_device::tg04_01_30(UINT32 pc, UINT32 op)
{
UINT32 rd = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 addr = GET_REGISTER(rd);
+ UINT32 addr = GetRegister(rd);
if (addr & 1)
{
addr &= ~1;
}
else
{
- SET_CPSR(GET_CPSR & ~T_MASK);
+ set_cpsr(GET_CPSR & ~T_MASK);
if (addr & 2)
{
addr += 2;
@@ -914,7 +914,7 @@ void arm7_cpu_device::tg04_01_30(UINT32 pc, UINT32 op)
void arm7_cpu_device::tg04_01_31(UINT32 pc, UINT32 op)
{
UINT32 rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
- UINT32 addr = GET_REGISTER(rs+8);
+ UINT32 addr = GetRegister(rs+8);
if (rs == 7)
{
addr += 2;
@@ -925,7 +925,7 @@ void arm7_cpu_device::tg04_01_31(UINT32 pc, UINT32 op)
}
else
{
- SET_CPSR(GET_CPSR & ~T_MASK);
+ set_cpsr(GET_CPSR & ~T_MASK);
if (addr & 2)
{
addr += 2;
@@ -937,13 +937,13 @@ void arm7_cpu_device::tg04_01_31(UINT32 pc, UINT32 op)
/* BLX */
void arm7_cpu_device::tg04_01_32(UINT32 pc, UINT32 op)
{
- UINT32 addr = GET_REGISTER((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT);
- SET_REGISTER(14, (R15 + 2) | 1);
+ UINT32 addr = GetRegister((op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT);
+ SetRegister(14, (R15 + 2) | 1);
// are we also switching to ARM mode?
if (!(addr & 1))
{
- SET_CPSR(GET_CPSR & ~T_MASK);
+ set_cpsr(GET_CPSR & ~T_MASK);
if (addr & 2)
{
addr += 2;
@@ -965,7 +965,7 @@ void arm7_cpu_device::tg04_01_33(UINT32 pc, UINT32 op)
void arm7_cpu_device::tg04_0203(UINT32 pc, UINT32 op)
{
UINT32 readword = READ32((R15 & ~2) + 4 + ((op & THUMB_INSN_IMM) << 2));
- SET_REGISTER((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, readword);
+ SetRegister((op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT, readword);
R15 += 2;
}
@@ -976,8 +976,8 @@ void arm7_cpu_device::tg05_0(UINT32 pc, UINT32 op) /* STR Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
- WRITE32(addr, GET_REGISTER(rd));
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
+ WRITE32(addr, GetRegister(rd));
R15 += 2;
}
@@ -986,8 +986,8 @@ void arm7_cpu_device::tg05_1(UINT32 pc, UINT32 op) /* STRH Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
- WRITE16(addr, GET_REGISTER(rd));
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
+ WRITE16(addr, GetRegister(rd));
R15 += 2;
}
@@ -996,8 +996,8 @@ void arm7_cpu_device::tg05_2(UINT32 pc, UINT32 op) /* STRB Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
- WRITE8(addr, GET_REGISTER(rd));
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
+ WRITE8(addr, GetRegister(rd));
R15 += 2;
}
@@ -1006,13 +1006,13 @@ void arm7_cpu_device::tg05_3(UINT32 pc, UINT32 op) /* LDSB Rd, [Rn, Rm] todo, a
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
UINT32 op2 = READ8(addr);
if (op2 & 0x00000080)
{
op2 |= 0xffffff00;
}
- SET_REGISTER(rd, op2);
+ SetRegister(rd, op2);
R15 += 2;
}
@@ -1021,9 +1021,9 @@ void arm7_cpu_device::tg05_4(UINT32 pc, UINT32 op) /* LDR Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
UINT32 op2 = READ32(addr);
- SET_REGISTER(rd, op2);
+ SetRegister(rd, op2);
R15 += 2;
}
@@ -1032,9 +1032,9 @@ void arm7_cpu_device::tg05_5(UINT32 pc, UINT32 op) /* LDRH Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
UINT32 op2 = READ16(addr);
- SET_REGISTER(rd, op2);
+ SetRegister(rd, op2);
R15 += 2;
}
@@ -1043,9 +1043,9 @@ void arm7_cpu_device::tg05_6(UINT32 pc, UINT32 op) /* LDRB Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
UINT32 op2 = READ8(addr);
- SET_REGISTER(rd, op2);
+ SetRegister(rd, op2);
R15 += 2;
}
@@ -1054,13 +1054,13 @@ void arm7_cpu_device::tg05_7(UINT32 pc, UINT32 op) /* LDSH Rd, [Rn, Rm] */
UINT32 rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
UINT32 rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
UINT32 rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
- UINT32 addr = GET_REGISTER(rn) + GET_REGISTER(rm);
+ UINT32 addr = GetRegister(rn) + GetRegister(rm);
UINT32 op2 = READ16(addr);
if (op2 & 0x00008000)
{
op2 |= 0xffff0000;
}
- SET_REGISTER(rd, op2);
+ SetRegister(rd, op2);
R15 += 2;
}
@@ -1071,7 +1071,7 @@ void arm7_cpu_device::tg06_0(UINT32 pc, UINT32 op) /* Store */
UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = op & THUMB_ADDSUB_RD;
INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
- WRITE32(GET_REGISTER(rn) + offs, GET_REGISTER(rd));
+ WRITE32(GetRegister(rn) + offs, GetRegister(rd));
R15 += 2;
}
@@ -1080,7 +1080,7 @@ void arm7_cpu_device::tg06_1(UINT32 pc, UINT32 op) /* Load */
UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = op & THUMB_ADDSUB_RD;
INT32 offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
- SET_REGISTER(rd, READ32(GET_REGISTER(rn) + offs)); // fix
+ SetRegister(rd, READ32(GetRegister(rn) + offs)); // fix
R15 += 2;
}
@@ -1091,7 +1091,7 @@ void arm7_cpu_device::tg07_0(UINT32 pc, UINT32 op) /* Store */
UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = op & THUMB_ADDSUB_RD;
INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
- WRITE8(GET_REGISTER(rn) + offs, GET_REGISTER(rd));
+ WRITE8(GetRegister(rn) + offs, GetRegister(rd));
R15 += 2;
}
@@ -1100,7 +1100,7 @@ void arm7_cpu_device::tg07_1(UINT32 pc, UINT32 op) /* Load */
UINT32 rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = op & THUMB_ADDSUB_RD;
INT32 offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
- SET_REGISTER(rd, READ8(GET_REGISTER(rn) + offs));
+ SetRegister(rd, READ8(GetRegister(rn) + offs));
R15 += 2;
}
@@ -1111,7 +1111,7 @@ void arm7_cpu_device::tg08_0(UINT32 pc, UINT32 op) /* Store */
UINT32 imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- WRITE16(GET_REGISTER(rs) + (imm << 1), GET_REGISTER(rd));
+ WRITE16(GetRegister(rs) + (imm << 1), GetRegister(rd));
R15 += 2;
}
@@ -1120,7 +1120,7 @@ void arm7_cpu_device::tg08_1(UINT32 pc, UINT32 op) /* Load */
UINT32 imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
UINT32 rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
UINT32 rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
- SET_REGISTER(rd, READ16(GET_REGISTER(rs) + (imm << 1)));
+ SetRegister(rd, READ16(GetRegister(rs) + (imm << 1)));
R15 += 2;
}
@@ -1130,7 +1130,7 @@ void arm7_cpu_device::tg09_0(UINT32 pc, UINT32 op) /* Store */
{
UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
INT32 offs = (UINT8)(op & THUMB_INSN_IMM);
- WRITE32(GET_REGISTER(13) + ((UINT32)offs << 2), GET_REGISTER(rd));
+ WRITE32(GetRegister(13) + ((UINT32)offs << 2), GetRegister(rd));
R15 += 2;
}
@@ -1138,8 +1138,8 @@ void arm7_cpu_device::tg09_1(UINT32 pc, UINT32 op) /* Load */
{
UINT32 rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
INT32 offs = (UINT8)(op & THUMB_INSN_IMM);
- UINT32 readword = READ32(GET_REGISTER(13) + ((UINT32)offs << 2));
- SET_REGISTER(rd, readword);
+ UINT32 readword = READ32(GetRegister(13) + ((UINT32)offs << 2));
+ SetRegister(rd, readword);
R15 += 2;
}
@@ -1149,7 +1149,7 @@ void arm7_cpu_device::tg0a_0(UINT32 pc, UINT32 op) /* ADD Rd, PC, #nn */
{
UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
- SET_REGISTER(rd, ((R15 + 4) & ~2) + offs);
+ SetRegister(rd, ((R15 + 4) & ~2) + offs);
R15 += 2;
}
@@ -1157,7 +1157,7 @@ void arm7_cpu_device::tg0a_1(UINT32 pc, UINT32 op) /* ADD Rd, SP, #nn */
{
UINT32 rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
INT32 offs = (UINT8)(op & THUMB_INSN_IMM) << 2;
- SET_REGISTER(rd, GET_REGISTER(13) + offs);
+ SetRegister(rd, GetRegister(13) + offs);
R15 += 2;
}
@@ -1167,7 +1167,7 @@ void arm7_cpu_device::tg0b_0(UINT32 pc, UINT32 op) /* ADD SP, #imm */
{
UINT32 addr = (op & THUMB_INSN_IMM);
addr &= ~THUMB_INSN_IMM_S;
- SET_REGISTER(13, GET_REGISTER(13) + ((op & THUMB_INSN_IMM_S) ? -(addr << 2) : (addr << 2)));
+ SetRegister(13, GetRegister(13) + ((op & THUMB_INSN_IMM_S) ? -(addr << 2) : (addr << 2)));
R15 += 2;
}
@@ -1192,8 +1192,8 @@ void arm7_cpu_device::tg0b_4(UINT32 pc, UINT32 op) /* PUSH {Rlist} */
{
if (op & (1 << offs))
{
- SET_REGISTER(13, GET_REGISTER(13) - 4);
- WRITE32(GET_REGISTER(13), GET_REGISTER(offs));
+ SetRegister(13, GetRegister(13) - 4);
+ WRITE32(GetRegister(13), GetRegister(offs));
}
}
R15 += 2;
@@ -1201,14 +1201,14 @@ void arm7_cpu_device::tg0b_4(UINT32 pc, UINT32 op) /* PUSH {Rlist} */
void arm7_cpu_device::tg0b_5(UINT32 pc, UINT32 op) /* PUSH {Rlist}{LR} */
{
- SET_REGISTER(13, GET_REGISTER(13) - 4);
- WRITE32(GET_REGISTER(13), GET_REGISTER(14));
+ SetRegister(13, GetRegister(13) - 4);
+ WRITE32(GetRegister(13), GetRegister(14));
for (INT32 offs = 7; offs >= 0; offs--)
{
if (op & (1 << offs))
{
- SET_REGISTER(13, GET_REGISTER(13) - 4);
- WRITE32(GET_REGISTER(13), GET_REGISTER(offs));
+ SetRegister(13, GetRegister(13) - 4);
+ WRITE32(GetRegister(13), GetRegister(GetRegister(offs)));
}
}
R15 += 2;
@@ -1250,8 +1250,8 @@ void arm7_cpu_device::tg0b_c(UINT32 pc, UINT32 op) /* POP {Rlist} */
{
if (op & (1 << offs))
{
- SET_REGISTER(offs, READ32(GET_REGISTER(13)));
- SET_REGISTER(13, GET_REGISTER(13) + 4);
+ SetRegister(offs, READ32(GetRegister(13)));
+ SetRegister(13, GetRegister(13) + 4);
}
}
R15 += 2;
@@ -1263,11 +1263,11 @@ void arm7_cpu_device::tg0b_d(UINT32 pc, UINT32 op) /* POP {Rlist}{PC} */
{
if (op & (1 << offs))
{
- SET_REGISTER(offs, READ32(GET_REGISTER(13)));
- SET_REGISTER(13, GET_REGISTER(13) + 4);
+ SetRegister(offs, READ32(GetRegister(13)));
+ SetRegister(13, GetRegister(13) + 4);
}
}
- UINT32 addr = READ32(GET_REGISTER(13));
+ UINT32 addr = READ32(GetRegister(13));
if (m_archRev < 5)
{
R15 = addr & ~1;
@@ -1280,7 +1280,7 @@ void arm7_cpu_device::tg0b_d(UINT32 pc, UINT32 op) /* POP {Rlist}{PC} */
}
else
{
- SET_CPSR(GET_CPSR & ~T_MASK);
+ set_cpsr(GET_CPSR & ~T_MASK);
if (addr & 2)
{
addr += 2;
@@ -1289,7 +1289,7 @@ void arm7_cpu_device::tg0b_d(UINT32 pc, UINT32 op) /* POP {Rlist}{PC} */
R15 = addr;
}
- SET_REGISTER(13, GET_REGISTER(13) + 4);
+ SetRegister(13, GetRegister(13) + 4);
}
void arm7_cpu_device::tg0b_e(UINT32 pc, UINT32 op)
@@ -1313,16 +1313,16 @@ void arm7_cpu_device::tg0b_f(UINT32 pc, UINT32 op)
void arm7_cpu_device::tg0c_0(UINT32 pc, UINT32 op) /* Store */
{
UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
- UINT32 ld_st_address = GET_REGISTER(rd);
+ UINT32 ld_st_address = GetRegister(rd);
for (INT32 offs = 0; offs < 8; offs++)
{
if (op & (1 << offs))
{
- WRITE32(ld_st_address & ~3, GET_REGISTER(offs));
+ WRITE32(ld_st_address & ~3, GetRegister(offs));
ld_st_address += 4;
}
}
- SET_REGISTER(rd, ld_st_address);
+ SetRegister(rd, ld_st_address);
R15 += 2;
}
@@ -1330,18 +1330,18 @@ void arm7_cpu_device::tg0c_1(UINT32 pc, UINT32 op) /* Load */
{
UINT32 rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
int rd_in_list = op & (1 << rd);
- UINT32 ld_st_address = GET_REGISTER(rd);
+ UINT32 ld_st_address = GetRegister(rd);
for (INT32 offs = 0; offs < 8; offs++)
{
if (op & (1 << offs))
{
- SET_REGISTER(offs, READ32(ld_st_address & ~1));
+ SetRegister(offs, READ32(ld_st_address & ~1));
ld_st_address += 4;
}
}
if (!rd_in_list)
{
- SET_REGISTER(rd, ld_st_address);
+ SetRegister(rd, ld_st_address);
}
R15 += 2;
}
@@ -1539,7 +1539,7 @@ void arm7_cpu_device::tg0d_e(UINT32 pc, UINT32 op) // COND_AL:
void arm7_cpu_device::tg0d_f(UINT32 pc, UINT32 op) // COND_NV: // SWI (this is sort of a "hole" in the opcode encoding)
{
m_pendingSwi = 1;
- ARM7_CHECKIRQ;
+ arm7_check_irq_state();
}
/* B #offs */
@@ -1556,10 +1556,10 @@ void arm7_cpu_device::tg0e_0(UINT32 pc, UINT32 op)
void arm7_cpu_device::tg0e_1(UINT32 pc, UINT32 op)
{
- UINT32 addr = GET_REGISTER(14);
+ UINT32 addr = GetRegister(14);
addr += (op & THUMB_BLOP_OFFS) << 1;
addr &= 0xfffffffc;
- SET_REGISTER(14, (R15 + 4) | 1);
+ SetRegister(14, (R15 + 4) | 1);
R15 = addr;
}
@@ -1573,15 +1573,15 @@ void arm7_cpu_device::tg0f_0(UINT32 pc, UINT32 op)
addr |= 0xff800000;
}
addr += R15 + 4;
- SET_REGISTER(14, addr);
+ SetRegister(14, addr);
R15 += 2;
}
void arm7_cpu_device::tg0f_1(UINT32 pc, UINT32 op) /* BL */
{
- UINT32 addr = GET_REGISTER(14) & ~1;
+ UINT32 addr = GetRegister(14) & ~1;
addr += (op & THUMB_BLOP_OFFS) << 1;
- SET_REGISTER(14, (R15 + 2) | 1);
+ SetRegister(14, (R15 + 2) | 1);
R15 = addr;
//R15 += 2;
}