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author Olivier Galibert <galibert@pobox.com>2017-12-16 13:21:01 +0100
committer Olivier Galibert <galibert@pobox.com>2017-12-16 13:22:21 +0100
commit0932b9c2ae7c59681144e8b65862ed541a01c47f (patch)
tree0294d40bffb0520ea178057318ed03c3a15d4d77 /src/devices/bus/ti99
parent77829f86719aa73ec3eddf08a9c7dfa71c89f5f3 (diff)
ide: Add non-space cs access methods, use them wherever possible [O. Galibert]
Diffstat (limited to 'src/devices/bus/ti99')
-rw-r--r--src/devices/bus/ti99/peb/tn_ide.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/devices/bus/ti99/peb/tn_ide.cpp b/src/devices/bus/ti99/peb/tn_ide.cpp
index 781078528aa..83bcf0031f8 100644
--- a/src/devices/bus/ti99/peb/tn_ide.cpp
+++ b/src/devices/bus/ti99/peb/tn_ide.cpp
@@ -160,7 +160,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
case 2: /* IDE registers set 1 (CS1Fx) */
if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
{ /* first read triggers 16-bit read cycle */
- m_input_latch = (! (addr & 0x10)) ? m_ata->read16_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0;
+ m_input_latch = (! (addr & 0x10)) ? m_ata->read16_cs0((addr >> 1) & 0x7) : 0;
}
/* return latched input */
@@ -171,7 +171,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
case 3: /* IDE registers set 2 (CS3Fx) */
if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
{ /* first read triggers 16-bit read cycle */
- m_input_latch = (! (addr & 0x10)) ? m_ata->read16_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0;
+ m_input_latch = (! (addr & 0x10)) ? m_ata->read16_cs1((addr >> 1) & 0x7) : 0;
}
/* return latched input */
@@ -243,7 +243,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write)
if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
{ /* second write triggers 16-bit write cycle */
- m_ata->write16_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
+ m_ata->write16_cs0((addr >> 1) & 0x7, m_output_latch);
}
break;
case 3: /* IDE registers set 2 (CS3Fx) */
@@ -261,7 +261,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write)
if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
{ /* second write triggers 16-bit write cycle */
- m_ata->write16_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
+ m_ata->write16_cs1((addr >> 1) & 0x7, m_output_latch);
}
break;
}