summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/bus/odyssey2/slot.h
diff options
context:
space:
mode:
author AJR <ajrhacker@users.noreply.github.com>2017-05-04 22:14:19 -0400
committer Vas Crabb <cuavas@users.noreply.github.com>2017-05-06 14:33:17 +1000
commit48f24cb5f3482b062e45f33ae9e65f1f16d0188d (patch)
tree852ad1704af4a8603663f8ade88d95675ad12a14 /src/devices/bus/odyssey2/slot.h
parent4930ecef121841dc30a349d154e3e940a319914e (diff)
mcs48: Convert ports to devcb (nw)
- T0, T1 and PROG handlers are now 1-bit rather than 8-bit - Eliminate several T0/T1 handlers that DEVCB macros can take care of now - T0 CLK output emulation (untested)
Diffstat (limited to 'src/devices/bus/odyssey2/slot.h')
-rw-r--r--src/devices/bus/odyssey2/slot.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/devices/bus/odyssey2/slot.h b/src/devices/bus/odyssey2/slot.h
index 07f6be8f7ab..284300072ad 100644
--- a/src/devices/bus/odyssey2/slot.h
+++ b/src/devices/bus/odyssey2/slot.h
@@ -37,7 +37,7 @@ public:
virtual void write_bank(int bank) {}
virtual DECLARE_WRITE8_MEMBER(io_write) {}
- virtual DECLARE_READ8_MEMBER(t0_read) { return 0; }
+ virtual DECLARE_READ_LINE_MEMBER(t0_read) { return 0; }
void rom_alloc(uint32_t size, const char *tag);
void ram_alloc(uint32_t size);
@@ -88,12 +88,12 @@ public:
virtual std::string get_default_card_software(get_default_card_software_hook &hook) const override;
// reading and writing
- virtual DECLARE_READ8_MEMBER(read_rom04);
- virtual DECLARE_READ8_MEMBER(read_rom0c);
- virtual DECLARE_WRITE8_MEMBER(io_write);
- virtual DECLARE_READ8_MEMBER(t0_read) { if (m_cart) return m_cart->t0_read(space, offset); else return 0; }
+ DECLARE_READ8_MEMBER(read_rom04);
+ DECLARE_READ8_MEMBER(read_rom0c);
+ DECLARE_WRITE8_MEMBER(io_write);
+ DECLARE_READ_LINE_MEMBER(t0_read) { if (m_cart) return m_cart->t0_read(); else return 0; }
- virtual void write_bank(int bank) { if (m_cart) m_cart->write_bank(bank); }
+ void write_bank(int bank) { if (m_cart) m_cart->write_bank(bank); }
protected: