diff options
author | 2020-06-18 20:13:33 +0200 | |
---|---|---|
committer | 2020-06-18 20:13:33 +0200 | |
commit | 57cf17dc52bcd4571a68576dd6597ddf9fae41a8 (patch) | |
tree | 9fef8bce07d80de37886a6dc44c340da05517388 /src/devices/bus/interpro | |
parent | e96ed3b0ebd5920e8aff2914a6ff28b435210717 (diff) |
finally retired the READ8/16/32/64 and WRITE8/16/32/64 macros (nw)
Diffstat (limited to 'src/devices/bus/interpro')
-rw-r--r-- | src/devices/bus/interpro/sr/edge.cpp | 14 | ||||
-rw-r--r-- | src/devices/bus/interpro/sr/edge.h | 66 | ||||
-rw-r--r-- | src/devices/bus/interpro/sr/gt.cpp | 28 | ||||
-rw-r--r-- | src/devices/bus/interpro/sr/gt.h | 108 |
4 files changed, 108 insertions, 108 deletions
diff --git a/src/devices/bus/interpro/sr/edge.cpp b/src/devices/bus/interpro/sr/edge.cpp index b8927438efc..c3ccbc14669 100644 --- a/src/devices/bus/interpro/sr/edge.cpp +++ b/src/devices/bus/interpro/sr/edge.cpp @@ -763,7 +763,7 @@ u32 edge2plus_framebuffer_device_base::screen_update(screen_device &screen, bitm return 0; } -WRITE32_MEMBER(edge1_device_base::control_w) +void edge1_device_base::control_w(offs_t offset, u32 data, u32 mem_mask) { // clear interrupt if (m_control & HOLDA_INT_H && !(data & HOLDA_INT_H)) @@ -799,7 +799,7 @@ WRITE_LINE_MEMBER(edge1_device_base::holda) m_status &= ~DSP_1_HOLDA_H; } -WRITE32_MEMBER(edge2plus_processor_device_base::control_w) +void edge2plus_processor_device_base::control_w(offs_t offset, u32 data, u32 mem_mask) { COMBINE_DATA(&m_control); @@ -841,7 +841,7 @@ void edge2plus_processor_device_base::dsp1_map(address_map &map) } -WRITE32_MEMBER(edge2plus_framebuffer_device_base::lut_select_w) +void edge2plus_framebuffer_device_base::lut_select_w(u32 data) { LOG("select ramdac %d\n", data); @@ -865,12 +865,12 @@ WRITE_LINE_MEMBER(edge1_device_base::scc_irq) irq0(state); } -READ32_MEMBER(edge1_device_base::reg0_r) +u32 edge1_device_base::reg0_r() { return ((m_reg0 & ~VBLANK) | (m_screen->vblank() ? VBLANK : 0)); } -WRITE32_MEMBER(edge1_device_base::kernel_w) +void edge1_device_base::kernel_w(offs_t offset, u32 data, u32 mem_mask) { COMBINE_DATA(&m_kernel); @@ -887,14 +887,14 @@ WRITE_LINE_MEMBER(edge2plus_processor_device_base::scc_irq) irq0(state); } -WRITE32_MEMBER(edge2plus_processor_device_base::kernel_w) +void edge2plus_processor_device_base::kernel_w(offs_t offset, u32 data, u32 mem_mask) { COMBINE_DATA(&m_kernel); m_status |= KREG_IN_FULL; // FIXME: what clears this? } -READ32_MEMBER(edge2plus_processor_device_base::reg0_r) +u32 edge2plus_processor_device_base::reg0_r() { LOG("reg0_r vblank %d\n", m_screen->vblank()); diff --git a/src/devices/bus/interpro/sr/edge.h b/src/devices/bus/interpro/sr/edge.h index ad6c6dfbb1b..d12bfc45394 100644 --- a/src/devices/bus/interpro/sr/edge.h +++ b/src/devices/bus/interpro/sr/edge.h @@ -31,26 +31,26 @@ protected: DECLARE_WRITE_LINE_MEMBER(scc_irq); - DECLARE_READ32_MEMBER(reg0_r); - DECLARE_WRITE32_MEMBER(reg0_w) { COMBINE_DATA(&m_reg0); } + u32 reg0_r(); + void reg0_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_reg0); } - DECLARE_READ32_MEMBER(control_r) { return m_control; }; - DECLARE_WRITE32_MEMBER(control_w); - DECLARE_READ32_MEMBER(status_r) { return m_status; }; - DECLARE_WRITE32_MEMBER(status_w) { COMBINE_DATA(&m_status); } - DECLARE_READ32_MEMBER(fifo_r) { return m_fifo; }; - DECLARE_WRITE32_MEMBER(fifo_w) { COMBINE_DATA(&m_fifo); } - DECLARE_READ32_MEMBER(kernel_r) { return m_kernel; }; - DECLARE_WRITE32_MEMBER(kernel_w); + u32 control_r() { return m_control; }; + void control_w(offs_t offset, u32 data, u32 mem_mask = ~0); + u32 status_r() { return m_status; }; + void status_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_status); } + u32 fifo_r() { return m_fifo; }; + void fifo_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_fifo); } + u32 kernel_r() { return m_kernel; }; + void kernel_w(offs_t offset, u32 data, u32 mem_mask = ~0); - DECLARE_READ32_MEMBER(attention_r) { return m_attention; }; - DECLARE_WRITE32_MEMBER(attention_w) { COMBINE_DATA(&m_attention); } + u32 attention_r() { return m_attention; }; + void attention_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_attention); } - DECLARE_WRITE32_MEMBER(ififo_lwm_w) { COMBINE_DATA(&m_ififo_lwm); } - DECLARE_WRITE32_MEMBER(ififo_hwm_w) { COMBINE_DATA(&m_ififo_hwm); } + void ififo_lwm_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ififo_lwm); } + void ififo_hwm_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ififo_hwm); } - DECLARE_READ32_MEMBER(srx_master_control_r) { return m_srx_master_control; } - DECLARE_WRITE32_MEMBER(srx_master_control_w) { COMBINE_DATA(&m_srx_master_control); } + u32 srx_master_control_r() { return m_srx_master_control; } + void srx_master_control_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_srx_master_control); } required_device<screen_device> m_screen; required_device<ram_device> m_sram; @@ -112,21 +112,21 @@ protected: DECLARE_WRITE_LINE_MEMBER(holda); DECLARE_WRITE_LINE_MEMBER(scc_irq); - DECLARE_READ32_MEMBER(control_r) { return m_control; }; - DECLARE_WRITE32_MEMBER(control_w); - DECLARE_READ32_MEMBER(status_r) { return m_status; }; - DECLARE_WRITE32_MEMBER(status_w) { COMBINE_DATA(&m_status); } - DECLARE_READ32_MEMBER(kernel_r) { return m_kernel; }; - DECLARE_WRITE32_MEMBER(kernel_w); - DECLARE_WRITE32_MEMBER(mapping_w) { COMBINE_DATA(&m_mapping); } - DECLARE_READ32_MEMBER(attention_r) { return m_attention; }; - DECLARE_WRITE32_MEMBER(attention_w) { COMBINE_DATA(&m_attention); } + u32 control_r() { return m_control; }; + void control_w(offs_t offset, u32 data, u32 mem_mask = ~0); + u32 status_r() { return m_status; }; + void status_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_status); } + u32 kernel_r() { return m_kernel; }; + void kernel_w(offs_t offset, u32 data, u32 mem_mask = ~0); + void mapping_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_mapping); } + u32 attention_r() { return m_attention; }; + void attention_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_attention); } - DECLARE_WRITE32_MEMBER(ififo_lwm_w) { COMBINE_DATA(&m_ififo_lwm); } - DECLARE_WRITE32_MEMBER(ififo_hwm_w) { COMBINE_DATA(&m_ififo_hwm); } + void ififo_lwm_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ififo_lwm); } + void ififo_hwm_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ififo_hwm); } - DECLARE_READ32_MEMBER(reg0_r); - DECLARE_WRITE32_MEMBER(reg0_w) { COMBINE_DATA(&m_reg0); } + u32 reg0_r(); + void reg0_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_reg0); } private: @@ -159,12 +159,12 @@ protected: u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); - DECLARE_WRITE32_MEMBER(lut_select_w); + void lut_select_w(u32 data); - DECLARE_WRITE32_MEMBER(unk_300_w) { m_unk_304 = 0x1000; } - DECLARE_READ32_MEMBER(unk_304_r) { m_unk_304 ^= 0x1000; return m_unk_304; } + void unk_300_w(u32 data) { m_unk_304 = 0x1000; } + u32 unk_304_r() { m_unk_304 ^= 0x1000; return m_unk_304; } - DECLARE_WRITE32_MEMBER(select_w) { COMBINE_DATA(&m_select); } + void select_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_select); } required_device<screen_device> m_screen; required_device<ram_device> m_sram; diff --git a/src/devices/bus/interpro/sr/gt.cpp b/src/devices/bus/interpro/sr/gt.cpp index a5411ce7c19..768bf221ec5 100644 --- a/src/devices/bus/interpro/sr/gt.cpp +++ b/src/devices/bus/interpro/sr/gt.cpp @@ -621,7 +621,7 @@ void gt_device_base::device_start() m_done_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gt_device_base::done), this)); } -WRITE32_MEMBER(gt_device_base::control_w) +void gt_device_base::control_w(offs_t offset, u32 data, u32 mem_mask) { if (data & GFX_BSGA_RST) { @@ -681,7 +681,7 @@ void gt_device_base::bsga_clip_status(s16 x, s16 y) LOG("bsga_clip_status result 0x%04x\n", m_bsga_status); } -WRITE32_MEMBER(gt_device_base::ri_xfer_w) +void gt_device_base::ri_xfer_w(offs_t offset, u32 data, u32 mem_mask) { LOG("ri_xfer_w 0x%08x mem_mask 0x%08x (%s)\n", data, mem_mask, machine().describe_context()); @@ -707,7 +707,7 @@ WRITE32_MEMBER(gt_device_base::ri_xfer_w) } } -WRITE32_MEMBER(gt_device_base::bsga_xin1yin1_w) +void gt_device_base::bsga_xin1yin1_w(offs_t offset, u32 data, u32 mem_mask) { m_bsga_xin1 = (m_bsga_xin1 & ~(mem_mask >> 0)) | ((data & mem_mask) >> 0); m_bsga_yin1 = (m_bsga_yin1 & ~(mem_mask >> 16)) | ((data & mem_mask) >> 16); @@ -726,7 +726,7 @@ WRITE32_MEMBER(gt_device_base::bsga_xin1yin1_w) m_bsga_tmp = m_bsga_xin1; } -WRITE32_MEMBER(gt_device_base::bsga_xin2yin2_w) +void gt_device_base::bsga_xin2yin2_w(offs_t offset, u32 data, u32 mem_mask) { m_bsga_xin2 = (m_bsga_xin2 & ~(mem_mask >> 0)) | ((data & mem_mask) >> 0); m_bsga_yin2 = (m_bsga_yin2 & ~(mem_mask >> 16)) | ((data & mem_mask) >> 16); @@ -743,7 +743,7 @@ WRITE32_MEMBER(gt_device_base::bsga_xin2yin2_w) m_line_timer->adjust(attotime::zero); } -WRITE16_MEMBER(gt_device_base::bsga_yin2_w) +void gt_device_base::bsga_yin2_w(offs_t offset, u16 data, u16 mem_mask) { COMBINE_DATA(&m_bsga_yin2); @@ -757,14 +757,14 @@ WRITE16_MEMBER(gt_device_base::bsga_yin2_w) m_line_timer->adjust(attotime::zero); } -READ16_MEMBER(gt_device_base::bsga_status_r) +u16 gt_device_base::bsga_status_r() { LOG("bsga_status_r 0x%04x (%s)\n", m_bsga_status, machine().describe_context()); return m_bsga_status; } -WRITE32_MEMBER(gt_device_base::bsga_float_w) +void gt_device_base::bsga_float_w(offs_t offset, u32 data) { // TODO: when we figure out exactly what this is supposed to do, convert it // to use softfloat instead. @@ -812,7 +812,7 @@ WRITE32_MEMBER(gt_device_base::bsga_float_w) LOG("bsga_float_w result 0x%04x overflow %s\n", m_bsga_xin, m_bsga_status & STATUS_FLOAT_OFLOW ? "set" : "clear"); } -WRITE16_MEMBER(gt_device_base::blit_width_w) +void gt_device_base::blit_width_w(offs_t offset, u16 data, u16 mem_mask) { // writing to blit width starts blit operation LOG("blit_width_w 0x%04x (%s)\n", data, machine().describe_context()); @@ -960,7 +960,7 @@ TIMER_CALLBACK_MEMBER(gt_device_base::done) m_control &= ~u32(param); } -WRITE8_MEMBER(gt_device_base::plane_enable_w) +void gt_device_base::plane_enable_w(u8 data) { if (m_control & GFX_GRPHCS_BUSY) return; @@ -971,7 +971,7 @@ WRITE8_MEMBER(gt_device_base::plane_enable_w) m_plane_enable = (data << 24) | (data << 16) | (data << 8) | (data << 0); } -WRITE8_MEMBER(gt_device_base::plane_data_w) +void gt_device_base::plane_data_w(u8 data) { if (m_control & GFX_GRPHCS_BUSY) return; @@ -1373,7 +1373,7 @@ void gt_device_base::bresenham_line(s16 major, s16 minor, s16 major_step, s16 mi LOG("bresenham_line end %d,%d\n", shallow ? major : minor, shallow ? minor : major); } -WRITE8_MEMBER(gt_device_base::contrast_dac_w) +void gt_device_base::contrast_dac_w(u8 data) { m_ramdac[0]->set_contrast(data); @@ -1384,7 +1384,7 @@ WRITE8_MEMBER(gt_device_base::contrast_dac_w) /* * GTDB support (SRX, SCC and mouse). */ -WRITE32_MEMBER(gtdb_device::srx_mapping_w) +void gtdb_device::srx_mapping_w(u32 data) { const offs_t srx_base = data << 24; @@ -1429,7 +1429,7 @@ void gtdb_device::mouse_status_w(offs_t offset, u32 data, u32 mem_mask) irq0(CLEAR_LINE); } -READ32_MEMBER(gtdb_device::mouse_x_r) +u32 gtdb_device::mouse_x_r() { const u32 result = m_mouse_x; @@ -1438,7 +1438,7 @@ READ32_MEMBER(gtdb_device::mouse_x_r) return result; } -READ32_MEMBER(gtdb_device::mouse_y_r) +u32 gtdb_device::mouse_y_r() { const u32 result = m_mouse_y; diff --git a/src/devices/bus/interpro/sr/gt.h b/src/devices/bus/interpro/sr/gt.h index 0fd02864c3b..aeeb70941ea 100644 --- a/src/devices/bus/interpro/sr/gt.h +++ b/src/devices/bus/interpro/sr/gt.h @@ -56,44 +56,44 @@ public: GFX_MONSENSE_60HZ = 0x0e000000, }; - DECLARE_READ32_MEMBER(control_r) { return m_control | (m_screen[0]->vblank() ? GFX_VERT_BLNK : 0); } - DECLARE_WRITE32_MEMBER(control_w); + u32 control_r() { return m_control | (m_screen[0]->vblank() ? GFX_VERT_BLNK : 0); } + void control_w(offs_t offset, u32 data, u32 mem_mask = ~0); - DECLARE_WRITE8_MEMBER(contrast_dac_w); + void contrast_dac_w(u8 data); - DECLARE_WRITE32_MEMBER(blit_src_address_w) { COMBINE_DATA(&m_blit_src_address); } - DECLARE_WRITE32_MEMBER(blit_dst_address_w) { COMBINE_DATA(&m_blit_dst_address); } - DECLARE_WRITE16_MEMBER(blit_width_w); + void blit_src_address_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_blit_src_address); } + void blit_dst_address_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_blit_dst_address); } + void blit_width_w(offs_t offset, u16 data, u16 mem_mask = ~0); - DECLARE_READ8_MEMBER(plane_enable_r) { return m_plane_enable; } - DECLARE_WRITE8_MEMBER(plane_enable_w); - DECLARE_READ8_MEMBER(plane_data_r) { return m_plane_data; } - DECLARE_WRITE8_MEMBER(plane_data_w); + u8 plane_enable_r() { return m_plane_enable; } + void plane_enable_w(u8 data); + u8 plane_data_r() { return m_plane_data; } + void plane_data_w(u8 data); - DECLARE_READ16_MEMBER(bsga_width_r) { return m_bsga_width; } - DECLARE_WRITE16_MEMBER(bsga_width_w) { COMBINE_DATA(&m_bsga_width); } - DECLARE_READ16_MEMBER(bsga_tmp_r) { return m_bsga_tmp; } - DECLARE_WRITE16_MEMBER(bsga_tmp_w) { COMBINE_DATA(&m_bsga_tmp); } + u16 bsga_width_r() { return m_bsga_width; } + void bsga_width_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_width); } + u16 bsga_tmp_r() { return m_bsga_tmp; } + void bsga_tmp_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_tmp); } - DECLARE_READ16_MEMBER(bsga_xmin_r) { return m_bsga_xmin; } - DECLARE_WRITE16_MEMBER(bsga_xmin_w) { COMBINE_DATA(&m_bsga_xmin); } - DECLARE_READ16_MEMBER(bsga_ymin_r) { return m_bsga_ymin; } - DECLARE_WRITE16_MEMBER(bsga_ymin_w) { COMBINE_DATA(&m_bsga_ymin); } + u16 bsga_xmin_r() { return m_bsga_xmin; } + void bsga_xmin_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_xmin); } + u16 bsga_ymin_r() { return m_bsga_ymin; } + void bsga_ymin_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_ymin); } - DECLARE_READ16_MEMBER(bsga_acc0_r) { return (m_bsga_width - m_bsga_xin1); } - DECLARE_READ16_MEMBER(bsga_acc1_r) { return -(m_bsga_width - m_bsga_xin1); } + u16 bsga_acc0_r() { return (m_bsga_width - m_bsga_xin1); } + u16 bsga_acc1_r() { return -(m_bsga_width - m_bsga_xin1); } - DECLARE_READ16_MEMBER(bsga_xmax_r) { return m_bsga_xmax; } - DECLARE_WRITE16_MEMBER(bsga_xmax_w) { COMBINE_DATA(&m_bsga_xmax); } - DECLARE_READ16_MEMBER(bsga_ymax_r) { return m_bsga_ymax; } - DECLARE_WRITE16_MEMBER(bsga_ymax_w) { COMBINE_DATA(&m_bsga_ymax); bsga_clip_status(m_bsga_xin1, m_bsga_yin1); } + u16 bsga_xmax_r() { return m_bsga_xmax; } + void bsga_xmax_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_xmax); } + u16 bsga_ymax_r() { return m_bsga_ymax; } + void bsga_ymax_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_ymax); bsga_clip_status(m_bsga_xin1, m_bsga_yin1); } - DECLARE_READ16_MEMBER(bsga_src0_r) { return m_bsga_xin1; } - DECLARE_READ16_MEMBER(bsga_src1_r) { return m_bsga_xin1; } + u16 bsga_src0_r() { return m_bsga_xin1; } + u16 bsga_src1_r() { return m_bsga_xin1; } - DECLARE_WRITE16_MEMBER(bsga_xin1_w) { COMBINE_DATA(&m_bsga_xin1); m_bsga_xin = m_bsga_xin1; m_bsga_tmp = m_bsga_xin1; } - DECLARE_WRITE16_MEMBER(bsga_yin1_w) { COMBINE_DATA(&m_bsga_yin1); m_bsga_yin = m_bsga_yin1; } - DECLARE_WRITE32_MEMBER(bsga_xin1yin1_w); + void bsga_xin1_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_xin1); m_bsga_xin = m_bsga_xin1; m_bsga_tmp = m_bsga_xin1; } + void bsga_yin1_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_yin1); m_bsga_yin = m_bsga_yin1; } + void bsga_xin1yin1_w(offs_t offset, u32 data, u32 mem_mask = ~0); enum bsga_status_mask : u16 { @@ -115,32 +115,32 @@ public: STATUS_CLIP1_MASK = 0x01e0, STATUS_CLIP_MASK = 0x1fe0 }; - DECLARE_READ16_MEMBER(bsga_status_r); + u16 bsga_status_r(); - DECLARE_WRITE32_MEMBER(bsga_xin2yin2_w); + void bsga_xin2yin2_w(offs_t offset, u32 data, u32 mem_mask = ~0); - DECLARE_WRITE16_MEMBER(bsga_xin2_w) { COMBINE_DATA(&m_bsga_xin2); m_bsga_xin = m_bsga_xin2; } - DECLARE_WRITE16_MEMBER(bsga_yin2_w); + void bsga_xin2_w(offs_t offset, u16 data, u16 mem_mask = ~0) { COMBINE_DATA(&m_bsga_xin2); m_bsga_xin = m_bsga_xin2; } + void bsga_yin2_w(offs_t offset, u16 data, u16 mem_mask = ~0); // FIXME: perhaps tmp is a counter of xin/yin and can be used to return correct value? - DECLARE_READ16_MEMBER(bsga_xin_r) { return m_bsga_xin; } - DECLARE_READ16_MEMBER(bsga_yin_r) { return m_bsga_yin; } + u16 bsga_xin_r() { return m_bsga_xin; } + u16 bsga_yin_r() { return m_bsga_yin; } - DECLARE_WRITE32_MEMBER(ri_initial_distance_w) { COMBINE_DATA(&m_ri_initial_distance); } - DECLARE_WRITE32_MEMBER(ri_distance_both_w) { COMBINE_DATA(&m_ri_distance_both); } - DECLARE_WRITE32_MEMBER(ri_distance_major_w) { COMBINE_DATA(&m_ri_distance_major); } - DECLARE_WRITE32_MEMBER(ri_initial_address_w) { COMBINE_DATA(&m_ri_initial_address); } - DECLARE_WRITE32_MEMBER(ri_address_both_w) { COMBINE_DATA(&m_ri_address_both); } - DECLARE_WRITE32_MEMBER(ri_address_major_w) { COMBINE_DATA(&m_ri_address_major); } - DECLARE_WRITE32_MEMBER(ri_initial_error_w) { COMBINE_DATA(&m_ri_initial_error); } - DECLARE_WRITE32_MEMBER(ri_error_both_w) { COMBINE_DATA(&m_ri_error_both); } - DECLARE_WRITE32_MEMBER(ri_error_major_w) { COMBINE_DATA(&m_ri_error_major); } + void ri_initial_distance_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_initial_distance); } + void ri_distance_both_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_distance_both); } + void ri_distance_major_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_distance_major); } + void ri_initial_address_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_initial_address); } + void ri_address_both_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_address_both); } + void ri_address_major_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_address_major); } + void ri_initial_error_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_initial_error); } + void ri_error_both_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_error_both); } + void ri_error_major_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_error_major); } - DECLARE_WRITE32_MEMBER(ri_stop_count_w) { COMBINE_DATA(&m_ri_stop_count); } - DECLARE_WRITE32_MEMBER(ri_control_w) { COMBINE_DATA(&m_ri_control); } - DECLARE_WRITE32_MEMBER(ri_xfer_w); + void ri_stop_count_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_stop_count); } + void ri_control_w(offs_t offset, u32 data, u32 mem_mask = ~0) { COMBINE_DATA(&m_ri_control); } + void ri_xfer_w(offs_t offset, u32 data, u32 mem_mask = ~0); - DECLARE_WRITE32_MEMBER(bsga_float_w); + void bsga_float_w(offs_t offset, u32 data); protected: virtual void device_start() override; @@ -263,7 +263,7 @@ protected: DECLARE_WRITE_LINE_MEMBER(serial_irq); void mouse_status_w(offs_t offset, u32 data, u32 mem_mask = ~0); - DECLARE_WRITE32_MEMBER(srx_mapping_w); + void srx_mapping_w(u32 data); enum int_status_mask { @@ -273,10 +273,10 @@ protected: MOUSE_Y = 0x40, SERIAL = 0x80, }; - DECLARE_READ32_MEMBER(mouse_int_r) { return m_mouse_int; } - DECLARE_WRITE32_MEMBER(mouse_int_w) { mem_mask &= ~0x7; COMBINE_DATA(&m_mouse_int); } - DECLARE_READ32_MEMBER(mouse_x_r); - DECLARE_READ32_MEMBER(mouse_y_r); + u32 mouse_int_r() { return m_mouse_int; } + void mouse_int_w(offs_t offset, u32 data, u32 mem_mask = ~0) { mem_mask &= ~0x7; COMBINE_DATA(&m_mouse_int); } + u32 mouse_x_r(); + u32 mouse_y_r(); enum vfifo_control_mask { @@ -284,7 +284,7 @@ protected: FIFO_LW_INTR = 0x40, FIFO_HW_INTR = 0x80, }; - DECLARE_READ32_MEMBER(fifo_control_r) { return m_fifo_control; } + u32 fifo_control_r() { return m_fifo_control; } //virtual void device_start() override; virtual void device_add_mconfig(machine_config &config) override; |