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author AJR <ajrhacker@users.noreply.github.com>2023-11-22 08:56:17 -0500
committer AJR <ajrhacker@users.noreply.github.com>2023-11-22 08:56:17 -0500
commit428fbb7c554bfc0b1c19e095df702a1468ad6d71 (patch)
treee60bd35ae6909472775aac8af1d2827bb528c891 /scripts/src/cpu.lua
parent7d4de65b7badac19b24873f9d8c4f3d65d530abd (diff)
unidasm: Add disassembler for Tensilica Xtensa architecture
Diffstat (limited to 'scripts/src/cpu.lua')
-rw-r--r--scripts/src/cpu.lua10
1 files changed, 10 insertions, 0 deletions
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index 60bdee13b54..d5012a8714a 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -3909,3 +3909,13 @@ if opt_tool(CPUS, "EVOLUTION") then
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/evolution/evod.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/evolution/evod.h")
end
+
+--------------------------------------------------
+-- Tensilica Xtensa, disassembler only
+--@src/devices/cpu/xtensa/xtensa.h,CPUS["XTENSA"] = true
+--------------------------------------------------
+
+if opt_tool(CPUS, "XTENSA") then
+ table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/xtensa/xtensad.cpp")
+ table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/xtensa/xtensad.h")
+end