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author yz70s <yz70s@users.noreply.github.com>2019-03-14 20:29:23 +0100
committer yz70s <yz70s@users.noreply.github.com>2019-03-14 21:03:12 +0100
commita81cb8469e8f3548205dc0add226365fdddce59c (patch)
tree9d930136d8082df89c1d5cb19bb3f95134b8d165 /scripts/src/cpu.lua
parentf1dacfc3377a16eb803ca32be218a6d6898e4135 (diff)
i386: add a simple cache to the athlon xp processor (nw)
. A single 64K 2-way set associative cache Used for both instructions and data Enabled only for addresses in the first megabyte Works always in writeback mode . It is needed by the nforce motherboard bios that uses it to simulate a block of ram at address d0000 before ddr ram is configured
Diffstat (limited to 'scripts/src/cpu.lua')
-rw-r--r--scripts/src/cpu.lua1
1 files changed, 1 insertions, 0 deletions
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index 631af0dbcff..090093df856 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -1087,6 +1087,7 @@ if (CPUS["I386"]~=null) then
files {
MAME_DIR .. "src/devices/cpu/i386/i386.cpp",
MAME_DIR .. "src/devices/cpu/i386/i386.h",
+ MAME_DIR .. "src/devices/cpu/i386/cache.h",
MAME_DIR .. "src/devices/cpu/i386/cycles.h",
MAME_DIR .. "src/devices/cpu/i386/i386op16.hxx",
MAME_DIR .. "src/devices/cpu/i386/i386op32.hxx",