From a81cb8469e8f3548205dc0add226365fdddce59c Mon Sep 17 00:00:00 2001 From: yz70s Date: Thu, 14 Mar 2019 20:29:23 +0100 Subject: i386: add a simple cache to the athlon xp processor (nw) . A single 64K 2-way set associative cache Used for both instructions and data Enabled only for addresses in the first megabyte Works always in writeback mode . It is needed by the nforce motherboard bios that uses it to simulate a block of ram at address d0000 before ddr ram is configured --- scripts/src/cpu.lua | 1 + 1 file changed, 1 insertion(+) (limited to 'scripts/src/cpu.lua') diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index 631af0dbcff..090093df856 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -1087,6 +1087,7 @@ if (CPUS["I386"]~=null) then files { MAME_DIR .. "src/devices/cpu/i386/i386.cpp", MAME_DIR .. "src/devices/cpu/i386/i386.h", + MAME_DIR .. "src/devices/cpu/i386/cache.h", MAME_DIR .. "src/devices/cpu/i386/cycles.h", MAME_DIR .. "src/devices/cpu/i386/i386op16.hxx", MAME_DIR .. "src/devices/cpu/i386/i386op32.hxx", -- cgit v1.2.3-70-g09d2