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author arbee <rb6502@users.noreply.github.com>2024-05-27 20:40:42 -0400
committer arbee <rb6502@users.noreply.github.com>2024-05-27 20:40:42 -0400
commit6957c469983fe32c9725eb3787020b6cedd36b75 (patch)
tree7b12ba5d3d6b2a08ec63ae9c72badad521339beb /scripts/src/benchmarks.lua
parentcd25f2de50864c2897ca7f5aa604696c87a49807 (diff)
cpu/m68000: Updated 680x0 FPU to Softfloat 3 from 2. (MT5411 and MT8793). [R. Belmont]
- Update to Softloat 3 from 2 - FREM and FMOD now generate the quotient bits in FPSR, required by Apple's SANE to do sin/cos/tan properly. - FMOVE of a float to a Dx integer register generates the exception status bits, fixing square roots in SANE - Rewrote how FMOVEM instructions are decoded and executed, fixing issues including skipping too few or too many opcode bytes and causing serious weird behavior. - FPU instructions all now have more realistic cycle timings for a 68881. - All FPU instructions now generate exception bits in FPSR. 3rdparty/softfloat3: Updates [R. Belmont] - Softfloat3 was always being built for a big-endian host, causing incorrect math on LE x64 and AArch64 machines. - Fixed up Softfloat3 to build properly as part of MAME and up-ported the Bochs extensions. In latest Bochs, they were only partially up-ported and Softfloat3 had been hacked up to be more like 2; here they're fixed to work with stock Softfloat3.
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