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author | 2019-04-25 11:02:04 +0700 | |
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committer | 2019-04-25 11:02:04 +0700 | |
commit | eff5477f0fb92439c80b17f1260c727bddff44ed (patch) | |
tree | c025f8ee314066b4521f6ca0c9d0cf8ef8c3b8fb /docs/source | |
parent | db980f2b428c8be639b0108f2ca07bb8f77cce93 (diff) |
mips: preserve upper 32 bits for single-precision fp operations (nw)
While this behaviour is undefined according to the MIPS R4000 Microprocessor User's Manual, various factors point toward it most likely being correct, including:
1. The fact MIPS-I exposes 16x64-bit floating-point registers, but internally implements them as pairs of 32-bit registers (with only the even-numbered pairs being valid for arithmetic operations), making it somewhat likely MOV.S, like LWC1 and SWC1, can access either half.
2. Explicit mention in IDT documentation and "See MIPS Run", i.e. "The odd-numbered registers can be accessed by move and load/store instructions", and other commentary.
3. The presence of paired-single operations in later MIPS32/64 specifications, which operate on independent single-precision values stored in each of the lower and upper halves of a single floating-point register.
Diffstat (limited to 'docs/source')
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