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author couriersud <couriersud@gmx.org>2019-04-19 13:54:51 +0200
committer couriersud <couriersud@gmx.org>2019-04-21 12:05:44 +0200
commit6b96f7ba60a384ff8d219ad480b9b2dd77e2986e (patch)
tree18fb3c2a8142a935a4a9b6fa30d20628ab7516c6 /docs/source/conf.py
parente826ac0a569b5dec014f99b79ace61969374d0b6 (diff)
netlist: Add power terminals to most logic devices.
This fixes an over simplification. Logic devices implicitly assumed that GND/VDD actually is connected to GND(i.e. 0V). There is no immediate benefit from this change. It is a preparation for the future scalability. Now all power terminals (typically 7/14, 8/16) have to be explicitly connected to the supply rails. Also added a validation mode to the netlist core. This is not intended for running, but solely to better indentify pins which are not properly connected.
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