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author Patrick Mackinlay <pmackinlay@hotmail.com>2026-04-09 00:42:29 +0700
committer GitHub <noreply@github.com>2026-04-09 03:42:29 +1000
commit73d8882b86e45d83e8b6188965ef488ef8662d15 (patch)
tree6224c575bd2632860d543768a02354a861bbed0e /3rdparty
parentbf3f8ec10e264dfbecabd7ceccb8d652756a2594 (diff)
3rdparty/asmjit: Sync with upstream version 1.21. (#15205)
From asmjit/asmjit@0bd5787b54b575ed94bf32ac452153b34385c514
Diffstat (limited to '3rdparty')
-rw-r--r--3rdparty/asmjit/CMakeLists.txt897
-rw-r--r--3rdparty/asmjit/CMakePresets.json53
-rw-r--r--3rdparty/asmjit/CONTRIBUTING.md22
-rw-r--r--3rdparty/asmjit/README.md59
-rw-r--r--3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen.cpp (renamed from 3rdparty/asmjit/testing/bench/asmjit_bench_codegen.cpp)7
-rw-r--r--3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen.h (renamed from 3rdparty/asmjit/testing/bench/asmjit_bench_codegen.h)4
-rw-r--r--3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen_a64.cpp (renamed from 3rdparty/asmjit/testing/bench/asmjit_bench_codegen_a64.cpp)4
-rw-r--r--3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen_x86.cpp (renamed from 3rdparty/asmjit/testing/bench/asmjit_bench_codegen_x86.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_overhead.cpp (renamed from 3rdparty/asmjit/testing/bench/asmjit_bench_overhead.cpp)264
-rw-r--r--3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_regalloc.cpp (renamed from 3rdparty/asmjit/testing/bench/asmjit_bench_regalloc.cpp)16
-rw-r--r--3rdparty/asmjit/asmjit-testing/commons/asmjitutils.h (renamed from 3rdparty/asmjit/testing/commons/asmjitutils.h)16
-rw-r--r--3rdparty/asmjit/asmjit-testing/commons/cmdline.h (renamed from 3rdparty/asmjit/testing/commons/cmdline.h)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/commons/performancetimer.h (renamed from 3rdparty/asmjit/testing/commons/performancetimer.h)1
-rw-r--r--3rdparty/asmjit/asmjit-testing/commons/random.h (renamed from 3rdparty/asmjit/testing/commons/random.h)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_assembler.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler.h (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_assembler.h)1
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_a64.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_assembler_a64.cpp)9
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_x64.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_assembler_x64.cpp)5
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_x86.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_assembler_x86.cpp)5
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_compiler.cpp)9
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler.h (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_compiler.h)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler_a64.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_compiler_a64.cpp)5
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler_x86.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_compiler_x86.cpp)7
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_emitters.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_emitters.cpp)3
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_environment.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_environment.cpp)2
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_instinfo.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_instinfo.cpp)2
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_misc.h (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_misc.h)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_runner.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_runner.cpp)4
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_unicompiler.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler_avx2fma.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_unicompiler_avx2fma.cpp)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler_sse2.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_unicompiler_sse2.cpp)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/asmjit_test_x86_sections.cpp (renamed from 3rdparty/asmjit/testing/tests/asmjit_test_x86_sections.cpp)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/broken.cpp (renamed from 3rdparty/asmjit/testing/tests/broken.cpp)0
-rw-r--r--3rdparty/asmjit/asmjit-testing/tests/broken.h (renamed from 3rdparty/asmjit/testing/tests/broken.h)0
-rw-r--r--3rdparty/asmjit/asmjit/a64.h (renamed from 3rdparty/asmjit/src/asmjit/a64.h)20
-rw-r--r--3rdparty/asmjit/asmjit/arm.h (renamed from 3rdparty/asmjit/src/asmjit/arm.h)10
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64archtraits_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h)10
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64assembler.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp)40
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64assembler.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64assembler.h)6
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64builder.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64builder.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64builder.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64builder.h)6
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64compiler.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64compiler.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64compiler.h)10
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64emithelper.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp)22
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64emithelper_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h)10
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64emitter.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64emitter.h)8
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64formatter.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp)16
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64formatter_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h)12
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64func.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64func.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64func_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64func_p.h)2
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64globals.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64globals.h)2
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64instapi.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp)18
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64instapi_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h)9
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64instdb.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64instdb.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64instdb.h)2
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64instdb_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64instdb_p.h)8
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64operand.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64operand.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64operand.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64operand.h)50
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64rapass.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/a64rapass.cpp)30
-rw-r--r--3rdparty/asmjit/asmjit/arm/a64rapass_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/a64rapass_p.h)16
-rw-r--r--3rdparty/asmjit/asmjit/arm/armformatter.cpp (renamed from 3rdparty/asmjit/src/asmjit/arm/armformatter.cpp)18
-rw-r--r--3rdparty/asmjit/asmjit/arm/armformatter_p.h (renamed from 3rdparty/asmjit/src/asmjit/arm/armformatter_p.h)8
-rw-r--r--3rdparty/asmjit/asmjit/arm/armglobals.h (renamed from 3rdparty/asmjit/src/asmjit/arm/armglobals.h)4
-rw-r--r--3rdparty/asmjit/asmjit/arm/armutils.h (renamed from 3rdparty/asmjit/src/asmjit/arm/armutils.h)4
-rw-r--r--3rdparty/asmjit/asmjit/asmjit-scope-begin.h (renamed from 3rdparty/asmjit/src/asmjit/asmjit-scope-begin.h)0
-rw-r--r--3rdparty/asmjit/asmjit/asmjit-scope-end.h (renamed from 3rdparty/asmjit/src/asmjit/asmjit-scope-end.h)0
-rw-r--r--3rdparty/asmjit/asmjit/asmjit.h (renamed from 3rdparty/asmjit/src/asmjit/asmjit.h)4
-rw-r--r--3rdparty/asmjit/asmjit/asmjit.natvis (renamed from 3rdparty/asmjit/src/asmjit.natvis)0
-rw-r--r--3rdparty/asmjit/asmjit/core.h (renamed from 3rdparty/asmjit/src/asmjit/core.h)99
-rw-r--r--3rdparty/asmjit/asmjit/core/api-build_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/api-build_p.h)4
-rw-r--r--3rdparty/asmjit/asmjit/core/api-config.h (renamed from 3rdparty/asmjit/src/asmjit/core/api-config.h)16
-rw-r--r--3rdparty/asmjit/asmjit/core/archcommons.h (renamed from 3rdparty/asmjit/src/asmjit/core/archcommons.h)2
-rw-r--r--3rdparty/asmjit/asmjit/core/archtraits.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/archtraits.cpp)12
-rw-r--r--3rdparty/asmjit/asmjit/core/archtraits.h (renamed from 3rdparty/asmjit/src/asmjit/core/archtraits.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/assembler.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/assembler.cpp)18
-rw-r--r--3rdparty/asmjit/asmjit/core/assembler.h (renamed from 3rdparty/asmjit/src/asmjit/core/assembler.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/builder.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/builder.cpp)36
-rw-r--r--3rdparty/asmjit/asmjit/core/builder.h (renamed from 3rdparty/asmjit/src/asmjit/core/builder.h)28
-rw-r--r--3rdparty/asmjit/asmjit/core/builder_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/builder_p.h)4
-rw-r--r--3rdparty/asmjit/asmjit/core/codebuffer.h (renamed from 3rdparty/asmjit/src/asmjit/core/codebuffer.h)4
-rw-r--r--3rdparty/asmjit/asmjit/core/codeholder.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/codeholder.cpp)76
-rw-r--r--3rdparty/asmjit/asmjit/core/codeholder.h (renamed from 3rdparty/asmjit/src/asmjit/core/codeholder.h)37
-rw-r--r--3rdparty/asmjit/asmjit/core/codewriter.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/codewriter.cpp)13
-rw-r--r--3rdparty/asmjit/asmjit/core/codewriter_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/codewriter_p.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/compiler.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/compiler.cpp)20
-rw-r--r--3rdparty/asmjit/asmjit/core/compiler.h (renamed from 3rdparty/asmjit/src/asmjit/core/compiler.h)22
-rw-r--r--3rdparty/asmjit/asmjit/core/compilerdefs.h (renamed from 3rdparty/asmjit/src/asmjit/core/compilerdefs.h)10
-rw-r--r--3rdparty/asmjit/asmjit/core/constpool.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/constpool.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/core/constpool.h (renamed from 3rdparty/asmjit/src/asmjit/core/constpool.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/cpuinfo.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/cpuinfo.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/core/cpuinfo.h (renamed from 3rdparty/asmjit/src/asmjit/core/cpuinfo.h)10
-rw-r--r--3rdparty/asmjit/asmjit/core/emithelper.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/emithelper.cpp)12
-rw-r--r--3rdparty/asmjit/asmjit/core/emithelper_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/emithelper_p.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/emitter.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/emitter.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/core/emitter.h (renamed from 3rdparty/asmjit/src/asmjit/core/emitter.h)12
-rw-r--r--3rdparty/asmjit/asmjit/core/emitterutils.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/emitterutils.cpp)12
-rw-r--r--3rdparty/asmjit/asmjit/core/emitterutils_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/emitterutils_p.h)25
-rw-r--r--3rdparty/asmjit/asmjit/core/environment.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/environment.cpp)4
-rw-r--r--3rdparty/asmjit/asmjit/core/environment.h (renamed from 3rdparty/asmjit/src/asmjit/core/environment.h)2
-rw-r--r--3rdparty/asmjit/asmjit/core/errorhandler.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/errorhandler.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/core/errorhandler.h (renamed from 3rdparty/asmjit/src/asmjit/core/errorhandler.h)2
-rw-r--r--3rdparty/asmjit/asmjit/core/fixup.h (renamed from 3rdparty/asmjit/src/asmjit/core/fixup.h)2
-rw-r--r--3rdparty/asmjit/asmjit/core/formatter.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/formatter.cpp)24
-rw-r--r--3rdparty/asmjit/asmjit/core/formatter.h (renamed from 3rdparty/asmjit/src/asmjit/core/formatter.h)10
-rw-r--r--3rdparty/asmjit/asmjit/core/formatter_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/formatter_p.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/func.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/func.cpp)16
-rw-r--r--3rdparty/asmjit/asmjit/core/func.h (renamed from 3rdparty/asmjit/src/asmjit/core/func.h)10
-rw-r--r--3rdparty/asmjit/asmjit/core/funcargscontext.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/funcargscontext.cpp)4
-rw-r--r--3rdparty/asmjit/asmjit/core/funcargscontext_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/funcargscontext_p.h)12
-rw-r--r--3rdparty/asmjit/asmjit/core/globals.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/globals.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/core/globals.h (renamed from 3rdparty/asmjit/src/asmjit/core/globals.h)8
-rw-r--r--3rdparty/asmjit/asmjit/core/inst.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/inst.cpp)14
-rw-r--r--3rdparty/asmjit/asmjit/core/inst.h (renamed from 3rdparty/asmjit/src/asmjit/core/inst.h)12
-rw-r--r--3rdparty/asmjit/asmjit/core/instdb.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/instdb.cpp)4
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-rw-r--r--3rdparty/asmjit/asmjit/core/jitallocator.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/jitallocator.cpp)22
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-rw-r--r--3rdparty/asmjit/asmjit/core/string.h (renamed from 3rdparty/asmjit/src/asmjit/core/string.h)4
-rw-r--r--3rdparty/asmjit/asmjit/core/target.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/target.cpp)4
-rw-r--r--3rdparty/asmjit/asmjit/core/target.h (renamed from 3rdparty/asmjit/src/asmjit/core/target.h)6
-rw-r--r--3rdparty/asmjit/asmjit/core/type.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/type.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/core/type.h (renamed from 3rdparty/asmjit/src/asmjit/core/type.h)4
-rw-r--r--3rdparty/asmjit/asmjit/core/virtmem.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/virtmem.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/core/virtmem.h (renamed from 3rdparty/asmjit/src/asmjit/core/virtmem.h)6
-rw-r--r--3rdparty/asmjit/asmjit/host.h (renamed from 3rdparty/asmjit/src/asmjit/host.h)6
-rw-r--r--3rdparty/asmjit/asmjit/support/arena.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/arena.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/support/arena.h (renamed from 3rdparty/asmjit/src/asmjit/core/arena.h)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenabitset.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/arenabitset.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenabitset_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenabitset_p.h)12
-rw-r--r--3rdparty/asmjit/asmjit/support/arenahash.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/arenahash.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenahash.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenahash.h)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenalist.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/arenalist.cpp)6
-rw-r--r--3rdparty/asmjit/asmjit/support/arenalist.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenalist.h)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenapool.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenapool.h)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenastring.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenastring.h)10
-rw-r--r--3rdparty/asmjit/asmjit/support/arenatree.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/arenatree.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenatree.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenatree.h)8
-rw-r--r--3rdparty/asmjit/asmjit/support/arenavector.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/arenavector.cpp)109
-rw-r--r--3rdparty/asmjit/asmjit/support/arenavector.h (renamed from 3rdparty/asmjit/src/asmjit/core/arenavector.h)76
-rw-r--r--3rdparty/asmjit/asmjit/support/span.h (renamed from 3rdparty/asmjit/src/asmjit/core/span.h)104
-rw-r--r--3rdparty/asmjit/asmjit/support/support.cpp (renamed from 3rdparty/asmjit/src/asmjit/core/support.cpp)38
-rw-r--r--3rdparty/asmjit/asmjit/support/support.h (renamed from 3rdparty/asmjit/src/asmjit/core/support.h)243
-rw-r--r--3rdparty/asmjit/asmjit/support/support_p.h (renamed from 3rdparty/asmjit/src/asmjit/core/support_p.h)10
-rw-r--r--3rdparty/asmjit/asmjit/ujit.h (renamed from 3rdparty/asmjit/src/asmjit/ujit.h)14
-rw-r--r--3rdparty/asmjit/asmjit/ujit/ujitbase.h (renamed from 3rdparty/asmjit/src/asmjit/ujit/ujitbase.h)2
-rw-r--r--3rdparty/asmjit/asmjit/ujit/unicompiler.h (renamed from 3rdparty/asmjit/src/asmjit/ujit/unicompiler.h)8
-rw-r--r--3rdparty/asmjit/asmjit/ujit/unicompiler_a64.cpp (renamed from 3rdparty/asmjit/src/asmjit/ujit/unicompiler_a64.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/ujit/unicompiler_utils_p.h (renamed from 3rdparty/asmjit/src/asmjit/ujit/unicompiler_utils_p.h)4
-rw-r--r--3rdparty/asmjit/asmjit/ujit/unicompiler_x86.cpp (renamed from 3rdparty/asmjit/src/asmjit/ujit/unicompiler_x86.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/ujit/unicondition.h (renamed from 3rdparty/asmjit/src/asmjit/ujit/unicondition.h)4
-rw-r--r--3rdparty/asmjit/asmjit/ujit/uniop.h (renamed from 3rdparty/asmjit/src/asmjit/ujit/uniop.h)2
-rw-r--r--3rdparty/asmjit/asmjit/ujit/vecconsttable.cpp (renamed from 3rdparty/asmjit/src/asmjit/ujit/vecconsttable.cpp)4
-rw-r--r--3rdparty/asmjit/asmjit/ujit/vecconsttable.h (renamed from 3rdparty/asmjit/src/asmjit/ujit/vecconsttable.h)2
-rw-r--r--3rdparty/asmjit/asmjit/x86.h (renamed from 3rdparty/asmjit/src/asmjit/x86.h)20
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86archtraits_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86archtraits_p.h)6
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86assembler.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86assembler.cpp)80
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86assembler.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86assembler.h)6
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86builder.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86builder.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86builder.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86builder.h)6
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86compiler.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86compiler.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86compiler.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86compiler.h)8
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86emithelper.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86emithelper.cpp)22
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86emithelper_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86emithelper_p.h)14
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86emitter.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86emitter.h)8
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86formatter.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86formatter.cpp)20
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86formatter_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86formatter_p.h)8
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86func.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86func.cpp)8
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86func_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86func_p.h)2
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86globals.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86globals.h)4
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86instapi.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86instapi.cpp)20
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86instapi_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86instapi_p.h)9
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86instdb.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86instdb.cpp)18
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86instdb.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86instdb.h)4
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86instdb_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86instdb_p.h)4
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86opcode_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86opcode_p.h)2
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86operand.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86operand.cpp)10
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86operand.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86operand.h)10
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86rapass.cpp (renamed from 3rdparty/asmjit/src/asmjit/x86/x86rapass.cpp)24
-rw-r--r--3rdparty/asmjit/asmjit/x86/x86rapass_p.h (renamed from 3rdparty/asmjit/src/asmjit/x86/x86rapass_p.h)16
-rw-r--r--3rdparty/asmjit/configure.sh12
-rw-r--r--3rdparty/asmjit/configure_sanitizers.sh16
-rw-r--r--3rdparty/asmjit/db/LICENSE.md17
-rw-r--r--3rdparty/asmjit/db/README.md21
-rw-r--r--3rdparty/asmjit/db/aarch32.js987
-rw-r--r--3rdparty/asmjit/db/aarch64.js920
-rw-r--r--3rdparty/asmjit/db/base.js707
-rw-r--r--3rdparty/asmjit/db/exp.js760
-rw-r--r--3rdparty/asmjit/db/index.js11
-rw-r--r--3rdparty/asmjit/db/isa_aarch32.json2783
-rw-r--r--3rdparty/asmjit/db/isa_aarch64.json3820
-rw-r--r--3rdparty/asmjit/db/isa_aarch64_sme.json15
-rw-r--r--3rdparty/asmjit/db/isa_x86.json4244
-rw-r--r--3rdparty/asmjit/db/isa_x86.md145
-rw-r--r--3rdparty/asmjit/db/package.json29
-rw-r--r--3rdparty/asmjit/db/x86.js1273
-rw-r--r--3rdparty/asmjit/tools/enumgen.js2
-rw-r--r--3rdparty/asmjit/tools/tablegen-a64.js12
-rw-r--r--3rdparty/asmjit/tools/tablegen-x86.js10
222 files changed, 17653 insertions, 2042 deletions
diff --git a/3rdparty/asmjit/CMakeLists.txt b/3rdparty/asmjit/CMakeLists.txt
index 064b25536a1..a5aace5d632 100644
--- a/3rdparty/asmjit/CMakeLists.txt
+++ b/3rdparty/asmjit/CMakeLists.txt
@@ -1,10 +1,53 @@
# AsmJit
# ======
-# To consume asmjit as a dependency, use asmjit::asmjit alias.
+# AsmJit library provides a single alias that can use used to consume it as a dependency:
+#
+# `asmjit::asmjit`
+#
+# Depending on options, the alias would be either a static or shared library (depending on
+# `ASMJIT_STATIC=ON|OFF` options) or it would be an interface library if `ASMJIT_EMBED=ON`.
+#
+# NOTE: When `ASMJIT_EMBED=ON` AsmJit won't add any installation instructions of libraries
+# or header files. Embed is literally for users that want to consume AsmJit as source code
+# without creating an intermediate static library. C++ flags, which used by the consuming
+# target will then be used to compile the embedded AsmJit source code as well. This option
+# improves the control of how AsmJit is both compiled and consumed.
+#
+# Consuming AsmJit
+# ----------------
+#
+# The recommended scenario to consume AsmJit is to clone it to a directory where third
+# party libraries are placed (this can be done even if you use a package manager such as
+# vcpkg or conan to manage other dependencies). Usually, the directory is called '3rdparty'
+# and it resides in your project's root, but it's just a recommendation, not a convention.
+# In such case, consuming a cloned AsmJit from your own project would look like this:
+#
+# # == Configure AsmJit options ==
+# set(ASMJIT_EMBED ON or OFF) # AsmJit uses ASMJIT_EMBED=OFF by default.
+# set(ASMJIT_STATIC ON or OFF) # AsmJit uses ASMJIT_STATIC=OFF by default.
+# add_subdirectory(3rdparty/asmjit asmjit) # Adds AsmJit as a sub-project.
+#
+# # == Consume AsmJit as a CMake dependency ==
+# add_executable(test_app main.cpp) # Target executable having main.cpp
+# target_link_libraries(test_app asmjit::asmjit) # Adds AsmJit as a dependency to test_app.
+#
+# Developing & Testing AsmJit
+# ---------------------------
+#
+# There are sample configure scripts provided, which reside in project root. In general, to
+# develop AsmJit it must be configured with `ASMJIT_TEST=ON` to build AsmJit tests and they
+# have to pass. Here is a simple cmake invocation to build AsmJit with tests enabled:
+#
+# cmake . -B build/Debug -DCMAKE_BUILD_TYPE=Debug -DASMJIT_TEST=ON
+#
+# See <asmjit.com> for more details.
cmake_minimum_required(VERSION 3.24 FATAL_ERROR)
+# AsmJit - Project & Configuration
+# ================================
+
# Don't create a project if it was already created by another CMakeLists.txt. This makes
# it possible to support both add_subdirectory() and include() ways of using AsmJit as a
# dependency.
@@ -15,338 +58,55 @@ if (NOT CMAKE_PROJECT_NAME OR "${CMAKE_PROJECT_NAME}" STREQUAL "asmjit")
HOMEPAGE_URL "https://asmjit.com")
endif()
-include(CheckCXXCompilerFlag)
-include(CheckCXXSourceCompiles)
-include(GNUInstallDirs)
-
-# AsmJit - Configuration - Build
-# ==============================
-
-if (NOT DEFINED ASMJIT_TEST)
- set(ASMJIT_TEST FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_EMBED)
- set(ASMJIT_EMBED FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_STATIC)
- set(ASMJIT_STATIC ${ASMJIT_EMBED})
-endif()
-
-if (NOT DEFINED ASMJIT_SANITIZE)
- set(ASMJIT_SANITIZE FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_CUSTOM_FLAGS)
- set(ASMJIT_NO_CUSTOM_FLAGS FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_NATVIS)
- set(ASMJIT_NO_NATVIS FALSE)
-endif()
-
-# EMBED implies STATIC.
-if (ASMJIT_EMBED AND NOT ASMJIT_STATIC)
- set(ASMJIT_STATIC TRUE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_DEPRECATED)
- set(ASMJIT_NO_DEPRECATED FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_ABI_NAMESPACE)
- set(ASMJIT_NO_ABI_NAMESPACE FALSE)
-endif()
-
-# AsmJit - Configuration - Backend
-# ================================
-
-if (NOT DEFINED ASMJIT_NO_X86)
- set(ASMJIT_NO_X86 FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_AARCH64)
- set(ASMJIT_NO_AARCH64 FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_FOREIGN)
- set(ASMJIT_NO_FOREIGN FALSE)
-endif()
-
-# AsmJit - Configuration - Features
-# =================================
-
-if (NOT DEFINED ASMJIT_NO_SHM_OPEN)
- set(ASMJIT_NO_SHM_OPEN FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_JIT)
- set(ASMJIT_NO_JIT FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_TEXT)
- set(ASMJIT_NO_TEXT FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_LOGGING)
- set(ASMJIT_NO_LOGGING ${ASMJIT_NO_TEXT})
-endif()
-
-if (NOT DEFINED ASMJIT_NO_VALIDATION)
- set(ASMJIT_NO_VALIDATION FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_INTROSPECTION)
- set(ASMJIT_NO_INTROSPECTION FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_BUILDER)
- set(ASMJIT_NO_BUILDER FALSE)
-endif()
-
-if (NOT DEFINED ASMJIT_NO_COMPILER)
- if (ASMJIT_NO_BUILDER OR ASMJIT_NO_INTROSPECTION)
- set(ASMJIT_NO_COMPILER TRUE)
- else()
- set(ASMJIT_NO_COMPILER FALSE)
- endif()
-endif()
-
-if (NOT DEFINED ASMJIT_NO_UJIT)
- if (ASMJIT_NO_COMPILER)
- set(ASMJIT_NO_UJIT TRUE)
- else()
- set(ASMJIT_NO_UJIT FALSE)
- endif()
-endif()
-
-# AsmJit - Configuration - CMake Introspection
-# ============================================
-
-set(ASMJIT_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "Location of 'asmjit'")
-set(ASMJIT_TEST "${ASMJIT_TEST}" CACHE BOOL "Build 'asmjit' test applications")
-set(ASMJIT_EMBED "${ASMJIT_EMBED}" CACHE BOOL "Embed 'asmjit' library (no targets)")
-set(ASMJIT_STATIC "${ASMJIT_STATIC}" CACHE BOOL "Build 'asmjit' library as static")
-set(ASMJIT_SANITIZE "${ASMJIT_SANITIZE}" CACHE STRING "Build with sanitizers: 'address', 'undefined', etc...")
-set(ASMJIT_NO_NATVIS "${ASMJIT_NO_NATVIS}" CACHE BOOL "Disable natvis support (embedding asmjit.natvis in PDB)")
-set(ASMJIT_NO_CUSTOM_FLAGS "${ASMJIT_NO_CUSTOM_FLAGS}" CACHE BOOL "Disable extra compilation flags added by AsmJit to its targets")
-
-set(ASMJIT_NO_X86 "${ASMJIT_NO_X86}" CACHE BOOL "Disable X86/X64 backend")
-set(ASMJIT_NO_AARCH64 "${ASMJIT_NO_AARCH64}" CACHE BOOL "Disable AArch64 backend")
-set(ASMJIT_NO_FOREIGN "${ASMJIT_NO_FOREIGN}" CACHE BOOL "Disable all foreign architectures (enables only a target architecture)")
-
-set(ASMJIT_NO_DEPRECATED "${ASMJIT_NO_DEPRECATED}" CACHE BOOL "Disable deprecated API at build time")
-set(ASMJIT_NO_ABI_NAMESPACE "${ASMJIT_NO_ABI_NAMESPACE}" CACHE BOOL "Disable the use of ABI namespace (inline namespace in {asmjit} adding ABI version)")
-
-set(ASMJIT_NO_SHM_OPEN "${ASMJIT_NO_SHM_OPEN}" CACHE BOOL "Disable the use of shm_open() even on platforms where it's supported")
-set(ASMJIT_NO_JIT "${ASMJIT_NO_JIT}" CACHE BOOL "Disable VirtMem, JitAllocator, and JitRuntime at build time")
-set(ASMJIT_NO_TEXT "${ASMJIT_NO_TEXT}" CACHE BOOL "Disable textual representation of instructions, enums, cpu features, ...")
-set(ASMJIT_NO_LOGGING "${ASMJIT_NO_LOGGING}" CACHE BOOL "Disable logging features at build time")
-set(ASMJIT_NO_VALIDATION "${ASMJIT_NO_VALIDATION}" CACHE BOOL "Disable instruction validation API at build time")
-set(ASMJIT_NO_INTROSPECTION "${ASMJIT_NO_INTROSPECTION}" CACHE BOOL "Disable instruction introspection API at build time")
-set(ASMJIT_NO_BUILDER "${ASMJIT_NO_BUILDER}" CACHE BOOL "Disable Builder at build time")
-set(ASMJIT_NO_COMPILER "${ASMJIT_NO_COMPILER}" CACHE BOOL "Disable Compiler at build time")
-set(ASMJIT_NO_UJIT "${ASMJIT_NO_UJIT}" CACHE BOOL "Disable UniCompiler at build time")
-
-# AsmJit - Project
-# ================
-
-set(ASMJIT_INCLUDE_DIRS "${ASMJIT_DIR}/src") # Include directory is the same as source dir.
-set(ASMJIT_DEPS "") # AsmJit dependencies (libraries) for the linker.
-set(ASMJIT_LIBS "") # Dependencies of libs/apps that want to use AsmJit.
-set(ASMJIT_CFLAGS "") # Public compiler flags.
-set(ASMJIT_PRIVATE_CFLAGS "") # Private compiler flags independent of build type.
-set(ASMJIT_PRIVATE_CFLAGS_DBG "") # Private compiler flags used by debug builds.
-set(ASMJIT_PRIVATE_CFLAGS_REL "") # Private compiler flags used by release builds.
-set(ASMJIT_SANITIZE_CFLAGS "") # Compiler flags required by currently enabled sanitizers.
-set(ASMJIT_SANITIZE_LFLAGS "") # Linker flags required by currently enabled sanitizers.
-
-# AsmJit - Utilities
-# ==================
-
-function(asmjit_detect_cflags out)
- set(out_array ${${out}})
- foreach(flag ${ARGN})
- string(REGEX REPLACE "[+]" "x" flag_signature "${flag}")
- string(REGEX REPLACE "[-=:;/.\]" "_" flag_signature "${flag_signature}")
- check_cxx_compiler_flag(${flag} "__CxxFlag_${flag_signature}")
- if (${__CxxFlag_${flag_signature}})
- list(APPEND out_array "${flag}")
- endif()
- endforeach()
- set(${out} "${out_array}" PARENT_SCOPE)
-endfunction()
-
-# Support for various sanitizers provided by C/C++ compilers.
-function(asmjit_detect_sanitizers out)
- set(_out_array ${${out}})
- set(_flags "")
-
- foreach(_arg ${ARGN})
- string(REPLACE "," ";" _arg "${_arg}")
- list(APPEND _flags ${_arg})
- endforeach()
-
- foreach(_flag ${_flags})
- if (NOT "${_flag}" MATCHES "^-fsanitize=")
- SET(_flag "-fsanitize=${_flag}")
- endif()
-
- # Sanitizers also require link flags, see CMAKE_REQUIRED_FLAGS.
- set(CMAKE_REQUIRED_FLAGS "${_flag}")
- asmjit_detect_cflags(_out_array ${_flag})
- unset(CMAKE_REQUIRED_FLAGS)
- endforeach()
-
- set(${out} "${_out_array}" PARENT_SCOPE)
-endfunction()
-
-function(asmjit_addapp target target_type)
- set(single_val "")
- set(multi_val SOURCES LIBRARIES CFLAGS CFLAGS_DBG CFLAGS_REL)
- cmake_parse_arguments("X" "" "${single_val}" "${multi_val}" ${ARGN})
-
- if ("${target_type}" MATCHES "^(EXECUTABLE|TEST)$")
- add_executable(${target} ${X_SOURCES})
- else()
- add_library(${target} ${target_type} ${X_SOURCES})
- endif()
-
- set_target_properties(${target}
- PROPERTIES
- DEFINE_SYMBOL ""
- CXX_VISIBILITY_PRESET hidden)
- target_compile_options(${target} PRIVATE ${X_CFLAGS} ${ASMJIT_SANITIZE_CFLAGS} $<$<CONFIG:Debug>:${X_CFLAGS_DBG}> $<$<NOT:$<CONFIG:Debug>>:${X_CFLAGS_REL}>)
- target_compile_features(${target} PUBLIC cxx_std_17)
- target_link_options(${target} PRIVATE ${ASMJIT_PRIVATE_LFLAGS})
- target_link_libraries(${target} PRIVATE ${X_LIBRARIES})
-
- if ("${target_type}" STREQUAL "TEST")
- add_test(NAME ${target} COMMAND ${target})
- endif()
-endfunction()
-
-# AsmJit - Compiler Support
-# =========================
-
-# We will have to keep this most likely forever as some users may still be using it.
-set(ASMJIT_INCLUDE_DIR "${ASMJIT_INCLUDE_DIRS}")
-
-if (NOT ASMJIT_NO_CUSTOM_FLAGS)
- if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
- list(APPEND ASMJIT_PRIVATE_CFLAGS -W4) # [+] Warning level 4.
-
- list(APPEND ASMJIT_PRIVATE_CFLAGS -MP) # [+] Multi-Process Compilation.
- list(APPEND ASMJIT_PRIVATE_CFLAGS -GF) # [+] Eliminate duplicate strings.
- list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:__cplusplus) # [+] Conforming __cplusplus definition.
- list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:inline) # [+] Remove unreferenced COMDAT.
- list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:strictStrings) # [+] Strict const qualification of string literals.
- list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:threadSafeInit-) # [-] Thread-safe statics.
-
- list(APPEND ASMJIT_PRIVATE_CFLAGS_DBG -GS) # [+] Buffer security-check.
- list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -GS-) # [-] Buffer security-check.
- list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -O2) # [+] Favor speed over size.
- list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -Oi) # [+] Generate intrinsic functions.
- elseif ("${CMAKE_CXX_COMPILER_ID}" MATCHES "GNU|Clang")
- list(APPEND ASMJIT_PRIVATE_CFLAGS -Wall -Wextra -Wconversion) # [+] Add baseline warnings that can be used safely even with system headers.
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wdouble-promotion) # [+] Warn about double promotions.
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wduplicated-cond) # [+] Warn about duplicate conditions.
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wduplicated-branches) # [+] Warn about duplicate branches.
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wlogical-op) # [+] Warn about suspicious uses of logical operators in expressions.
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wlogical-not-parentheses) # [+] Warn about logical not used on the left hand side operand of a comparison.
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wrestrict)
-
- list(APPEND ASMJIT_PRIVATE_CFLAGS -fno-math-errno) # [-] Disable math functions setting errno (performance reasons).
- list(APPEND ASMJIT_PRIVATE_CFLAGS -fno-threadsafe-statics) # [-] Don't add guards when initializing statics (we don't need it).
- list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -O2) # [+] Compiling with -O2 in release mode is what we generally want.
- list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -fmerge-all-constants) # [+] We don't need unique address per constant (merging improves library size).
-
- # -fno-semantic-interposition is not available on apple - the compiler issues a warning, which is not detected.
- if (NOT APPLE)
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -fno-semantic-interposition)
- endif()
-
- if (NOT "${CMAKE_SYSTEM_NAME}" STREQUAL "iOS")
- asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS_REL -fno-enforce-eh-specs) # [-] Don't enforce termination if noexcept function throws.
- endif()
- endif()
-endif()
-
-# Support for sanitizers.
-if (ASMJIT_SANITIZE)
- asmjit_detect_sanitizers(ASMJIT_SANITIZE_CFLAGS ${ASMJIT_SANITIZE})
- if (ASMJIT_SANITIZE_CFLAGS)
- message("-- Enabling sanitizers: '${ASMJIT_SANITIZE_CFLAGS}'")
-
- # Linker must receive the same flags as the compiler when it comes to sanitizers.
- set(ASMJIT_SANITIZE_LFLAGS ${ASMJIT_SANITIZE_CFLAGS})
-
- # Don't omit frame pointer if sanitizers are enabled.
- if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
- list(APPEND ASMJIT_SANITIZE_CFLAGS -Oy-)
- else()
- list(APPEND ASMJIT_SANITIZE_CFLAGS -fno-omit-frame-pointer -g)
- endif()
-
- list(APPEND ASMJIT_PRIVATE_CFLAGS ${ASMJIT_SANITIZE_CFLAGS})
- list(APPEND ASMJIT_PRIVATE_LFLAGS ${ASMJIT_SANITIZE_LFLAGS})
+set(ASMJIT_SANITIZE "" CACHE STRING "Sanitizers to use (development)")
+set(ASMJIT_SANITIZE_OPTS "" CACHE STRING "Extra flags for sanitizers (development)")
+
+option(ASMJIT_EMBED "Embed 'asmjit' as an interface library (no static/shared library)" OFF)
+option(ASMJIT_STATIC "Build 'asmjit' as a static library (implied by ASMJIT_EMBED)" ${ASMJIT_EMBED})
+option(ASMJIT_TEST "Build 'asmjit' tests and benchmarks (development)" OFF)
+
+option(ASMJIT_NO_NATVIS "Disable natvis support (embedding asmjit.natvis in PDB)" OFF)
+option(ASMJIT_NO_CUSTOM_FLAGS "Disable extra compilation flags added by AsmJit to its targets" OFF)
+option(ASMJIT_NO_ABI_NAMESPACE "Disable the use of inline ABI namespace {asmjit::v...}" OFF)
+option(ASMJIT_NO_SHM_OPEN "Disable the use of shm_open() (some platforms have better options)" OFF)
+option(ASMJIT_NO_X86 "Disable X86/X64 backend" OFF)
+option(ASMJIT_NO_AARCH64 "Disable AArch64 backend" OFF)
+option(ASMJIT_NO_FOREIGN "Disable all foreign backends (enables only a backend that matches the target)" OFF)
+option(ASMJIT_NO_JIT "Disable VirtMem, JitAllocator, and JitRuntime at build time" OFF)
+option(ASMJIT_NO_TEXT "Disable textual representation of instructions, enums, cpu features, ..." OFF)
+option(ASMJIT_NO_LOGGING "Disable logging features (build feature)" ${ASMJIT_NO_TEXT})
+option(ASMJIT_NO_INTROSPECTION "Disable instruction validation and introspection API (build feature)" OFF)
+option(ASMJIT_NO_BUILDER "Disable AsmJit's Builder emitter (build feature)" OFF)
+
+if (NOT ASMJIT_NO_BUILDER AND NOT ASMJIT_NO_INTROSPECTION)
+ option(ASMJIT_NO_COMPILER "Disable AsmJit's Compiler emitter (build feature)" OFF)
+else()
+ if (NOT ASMJIT_NO_COMPILER)
+ unset(ASMJIT_NO_COMPILER CACHE)
endif()
+ option(ASMJIT_NO_COMPILER "Disable AsmJit's Compiler emitter (build feature)" ON)
endif()
-if (WIN32)
- # Dependency: nothing extra at the moment.
-elseif ("${CMAKE_SYSTEM_NAME}" STREQUAL "Android")
- # Dependency: libc is the only required library on Android as it also provides libthread.
- message("-- Dependency: adding libc (Android target detected)")
- list(APPEND ASMJIT_DEPS c)
-elseif ("${CMAKE_SYSTEM_NAME}" STREQUAL "Haiku")
- # Dependency: libroot is used by Haiku instead of libc, so link to libroot and libpthread.
- message("-- Dependency: adding libroot and libpthread (Haiku target detected)")
- list(APPEND ASMJIT_DEPS root pthread)
+if (NOT ASMJIT_NO_COMPILER)
+ option(ASMJIT_NO_UJIT "Disable AsmJit's UniCompiler backend (build feature)" OFF)
else()
- # Dependency: libc is always required.
- message("-- Dependency: adding libc (Linux, BSD, or other UNIX/POSIX environment)")
- list(APPEND ASMJIT_DEPS c)
-
- # Dependency: pthread (required so AsmJit can use pthread_lock).
- check_cxx_source_compiles("
- #include <pthread.h>
- int main() {
- pthread_mutex_t m;
- pthread_mutex_init(&m, nullptr);
- return pthread_mutex_destroy(&m);
- }
- " ASMJIT_LIBC_HAS_LIBPTHREAD)
- if (ASMJIT_LIBC_HAS_LIBPTHREAD)
- message("-- Dependency: libpthread provided by libc (not linking to libpthread)")
- else()
- message("-- Dependency: libpthread not provided by libc, linking to libpthread")
- list(APPEND ASMJIT_DEPS pthread)
- endif()
-
- # Dependency: shm_open (required so AsmJit can use shm_open on supported platforms).
- if ("${CMAKE_SYSTEM_NAME}" MATCHES "^(Linux|NetBSD)$" AND NOT ASMJIT_NO_SHM_OPEN)
- check_cxx_source_compiles("
- #include <sys/mman.h>
- int main() {
- const char file_name[1] {};
- return shm_open(file_name, 0, 0);
- }
- " ASMJIT_LIBC_HAS_LIBRT)
- if (ASMJIT_LIBC_HAS_LIBRT)
- message("-- Dependency: shm_open provided by libc (not linking to librt)")
- else()
- message("-- Dependency: shm_open not provided by libc, linking to librt")
- list(APPEND ASMJIT_DEPS rt)
- endif()
+ if (NOT ASMJIT_NO_UJIT)
+ unset(ASMJIT_NO_UJIT CACHE)
endif()
+ option(ASMJIT_NO_UJIT "Disable AsmJit's UniCompiler backend (build feature)" ON)
endif()
-set(ASMJIT_LIBS ${ASMJIT_DEPS})
-if (NOT ASMJIT_EMBED)
- list(INSERT ASMJIT_LIBS 0 asmjit)
-endif()
+# AsmJit - Build Definitions and Source Files
+# ===========================================
+
+set(ASMJIT_INCLUDE_DIRS "${CMAKE_CURRENT_LIST_DIR}") # AsmJit include directory is the same as <root> directory.
+set(ASMJIT_LIBS "") # AsmJit library dependencies for the linker.
+set(ASMJIT_CFLAGS "") # Public compiler flags.
+set(ASMJIT_PRIVATE_CFLAGS "") # Private compiler flags independent of build type.
+set(ASMJIT_PRIVATE_CFLAGS_DBG "") # Private compiler flags used by debug builds.
+set(ASMJIT_PRIVATE_CFLAGS_REL "") # Private compiler flags used by release builds.
+set(ASMJIT_SANITIZE_CFLAGS "") # Compiler flags required by currently enabled sanitizers.
+set(ASMJIT_SANITIZE_LFLAGS "") # Linker flags required by currently enabled sanitizers.
if (ASMJIT_EMBED)
set(ASMJIT_TARGET_TYPE "EMBED")
@@ -355,65 +115,17 @@ elseif (ASMJIT_STATIC)
else()
set(ASMJIT_TARGET_TYPE "SHARED")
endif()
+message(STATUS "[asmjit] == Configuring AsmJit ('ASMJIT_TARGET_TYPE=${ASMJIT_TARGET_TYPE}') ==")
-foreach(build_option # AsmJit build options.
- ASMJIT_STATIC
- ASMJIT_NO_DEPRECATED
- ASMJIT_NO_ABI_NAMESPACE
- # AsmJit backends selection.
- ASMJIT_NO_X86
- ASMJIT_NO_AARCH64
- ASMJIT_NO_FOREIGN
- # AsmJit features selection.
- ASMJIT_NO_SHM_OPEN
- ASMJIT_NO_JIT
- ASMJIT_NO_TEXT
- ASMJIT_NO_LOGGING
- ASMJIT_NO_INTROSPECTION
- ASMJIT_NO_VALIDATION
- ASMJIT_NO_BUILDER
- ASMJIT_NO_COMPILER
- ASMJIT_NO_UJIT)
- if (${build_option})
- List(APPEND ASMJIT_CFLAGS "-D${build_option}")
- List(APPEND ASMJIT_PRIVATE_CFLAGS "-D${build_option}")
- endif()
-endforeach()
-
-# AsmJit - Linker Support
-# =======================
-
-if (WIN32)
- if (CMAKE_LINKER MATCHES "link\\.exe" OR CMAKE_LINKER MATCHES "lld-link\\.exe")
- set(ASMJIT_LINKER_SUPPORTS_NATVIS TRUE)
- endif()
-endif()
-
-# AsmJit - Source
-# ===============
-
-set(ASMJIT_SRC_LIST
+set(ASMJIT_SRC
asmjit/asmjit.h
asmjit/asmjit-scope-begin.h
asmjit/asmjit-scope-end.h
+ asmjit/host.h
asmjit/core.h
asmjit/core/api-build_p.h
asmjit/core/api-config.h
- asmjit/core/arena.cpp
- asmjit/core/arena.h
- asmjit/core/arenabitset.cpp
- asmjit/core/arenabitset_p.h
- asmjit/core/arenahash.cpp
- asmjit/core/arenahash.h
- asmjit/core/arenalist.cpp
- asmjit/core/arenalist.h
- asmjit/core/arenapool.h
- asmjit/core/arenastring.h
- asmjit/core/arenatree.cpp
- asmjit/core/arenatree.h
- asmjit/core/arenavector.cpp
- asmjit/core/arenavector.h
asmjit/core/archtraits.cpp
asmjit/core/archtraits.h
asmjit/core/archcommons.h
@@ -478,13 +190,11 @@ set(ASMJIT_SRC_LIST
asmjit/core/ralocal_p.h
asmjit/core/rapass.cpp
asmjit/core/rapass_p.h
+ asmjit/core/rareg_p.h
asmjit/core/rastack.cpp
asmjit/core/rastack_p.h
- asmjit/core/span.h
asmjit/core/string.cpp
asmjit/core/string.h
- asmjit/core/support.cpp
- asmjit/core/support.h
asmjit/core/target.cpp
asmjit/core/target.h
asmjit/core/type.cpp
@@ -492,6 +202,25 @@ set(ASMJIT_SRC_LIST
asmjit/core/virtmem.cpp
asmjit/core/virtmem.h
+ asmjit/support/arena.cpp
+ asmjit/support/arena.h
+ asmjit/support/arenabitset.cpp
+ asmjit/support/arenabitset_p.h
+ asmjit/support/arenahash.cpp
+ asmjit/support/arenahash.h
+ asmjit/support/arenalist.cpp
+ asmjit/support/arenalist.h
+ asmjit/support/arenapool.h
+ asmjit/support/arenastring.h
+ asmjit/support/arenatree.cpp
+ asmjit/support/arenatree.h
+ asmjit/support/arenavector.cpp
+ asmjit/support/arenavector.h
+ asmjit/support/span.h
+ asmjit/support/support.cpp
+ asmjit/support/support.h
+ asmjit/support/support_p.h
+
asmjit/a64.h
asmjit/arm.h
asmjit/arm/armformatter.cpp
@@ -548,120 +277,357 @@ set(ASMJIT_SRC_LIST
asmjit/x86/x86rapass.cpp
asmjit/x86/x86rapass_p.h
+ asmjit/ujit.h
asmjit/ujit/ujitbase.h
asmjit/ujit/unicompiler.h
asmjit/ujit/unicompiler_a64.cpp
asmjit/ujit/unicompiler_x86.cpp
asmjit/ujit/unicompiler_utils_p.h
+ asmjit/ujit/unicondition.h
asmjit/ujit/uniop.h
asmjit/ujit/vecconsttable.cpp
asmjit/ujit/vecconsttable.h
)
-if (MSVC AND NOT ASMJIT_NO_NATVIS)
- list(APPEND ASMJIT_SRC_LIST asmjit.natvis)
+# AsmJit - CMake Utilities
+# ========================
+
+include(CheckCXXCompilerFlag)
+include(CheckCXXSourceCompiles)
+include(GNUInstallDirs)
+
+# Detects target architecture - since the code doesn't run it works also for cross-compilation.
+function(asmjit_detect_target_arch out)
+ set(${out} "unknown" PARENT_SCOPE)
+ foreach(target_arch "X86_64" "AARCH64" "X86" "AARCH32")
+ check_cxx_source_compiles("
+ #if defined(_M_X64) || defined(__x86_64__)
+ static int target_arch_is_X86_64() { return 1; }
+ #elif defined(_M_IX86) || defined(__X86__) || defined(__i386__)
+ static int target_arch_is_X86() { return 1; }
+ #elif defined(_M_ARM64) || defined(__arm64__) || defined(__aarch64__)
+ static int target_arch_is_AARCH64() { return 1; }
+ #elif defined(_M_ARM) || defined(_M_ARMT) || defined(__arm__) || defined(__thumb__) || defined(__thumb2__)
+ static int target_arch_is_AARCH32() { return 1; }
+ #endif
+ int main(void) { return target_arch_is_${target_arch}(); }" "${out}_${target_arch}")
+ if (${${out}_${target_arch}})
+ set(${out} "${target_arch}" PARENT_SCOPE)
+ return()
+ endif()
+ endforeach()
+endfunction()
+
+# Detects C++ compile flags and appends all detected ones to `out`.
+function(asmjit_detect_cflags out)
+ set(out_array ${${out}})
+ foreach(flag ${ARGN})
+ string(REGEX REPLACE "[+]" "x" flag_signature "${flag}")
+ string(REGEX REPLACE "[-=:;/.\]" "_" flag_signature "${flag_signature}")
+ check_cxx_compiler_flag(${flag} "__CxxFlag_${flag_signature}")
+ if (${__CxxFlag_${flag_signature}})
+ list(APPEND out_array "${flag}")
+ endif()
+ endforeach()
+ set(${out} "${out_array}" PARENT_SCOPE)
+endfunction()
+
+# Support for various sanitizers provided by C/C++ compilers.
+function(asmjit_detect_sanitizers out)
+ set(_out_array ${${out}})
+ set(_flags "")
+
+ foreach(_arg ${ARGN})
+ string(REPLACE "," ";" _arg "${_arg}")
+ list(APPEND _flags ${_arg})
+ endforeach()
+
+ foreach(_flag ${_flags})
+ if (NOT "${_flag}" MATCHES "^-fsanitize=")
+ SET(_flag "-fsanitize=${_flag}")
+ endif()
+
+ # Sanitizers also require link flags, see CMAKE_REQUIRED_FLAGS.
+ set(CMAKE_REQUIRED_FLAGS "${_flag}")
+ asmjit_detect_cflags(_out_array ${_flag})
+ unset(CMAKE_REQUIRED_FLAGS)
+ endforeach()
+
+ set(${out} "${_out_array}" PARENT_SCOPE)
+endfunction()
+
+function(asmjit_add_target target target_type)
+ set(single_val "")
+ set(multi_val SOURCES LIBRARIES CFLAGS CFLAGS_DBG CFLAGS_REL)
+ cmake_parse_arguments("X" "" "${single_val}" "${multi_val}" ${ARGN})
+
+ if ("${target_type}" MATCHES "^(EXECUTABLE|TEST)$")
+ add_executable(${target} ${X_SOURCES})
+ else()
+ add_library(${target} ${target_type} ${X_SOURCES})
+ endif()
+
+ set_target_properties(${target}
+ PROPERTIES
+ DEFINE_SYMBOL ""
+ CXX_VISIBILITY_PRESET hidden)
+ target_compile_options(${target} PRIVATE ${X_CFLAGS} ${ASMJIT_SANITIZE_CFLAGS} $<$<CONFIG:Debug>:${X_CFLAGS_DBG}> $<$<NOT:$<CONFIG:Debug>>:${X_CFLAGS_REL}>)
+ target_compile_features(${target} PUBLIC cxx_std_17)
+ target_link_options(${target} PRIVATE ${ASMJIT_PRIVATE_LFLAGS})
+ target_link_libraries(${target} PRIVATE ${X_LIBRARIES})
+
+ if ("${target_type}" STREQUAL "TEST")
+ add_test(NAME ${target} COMMAND ${target})
+ endif()
+endfunction()
+
+# AsmJit - Compiler Support
+# =========================
+
+if (NOT ASMJIT_EMBED)
+ if (NOT ASMJIT_NO_CUSTOM_FLAGS)
+ if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -W4) # [+] Warning level 4.
+
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -MP) # [+] Multi-Process Compilation.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -GF) # [+] Eliminate duplicate strings.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:__cplusplus) # [+] Conforming __cplusplus definition.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:inline) # [+] Remove unreferenced COMDAT.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:strictStrings) # [+] Strict const qualification of string literals.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -Zc:threadSafeInit-) # [-] Thread-safe statics.
+
+ list(APPEND ASMJIT_PRIVATE_CFLAGS_DBG -GS) # [+] Buffer security-check.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -GS-) # [-] Buffer security-check.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -O2) # [+] Favor speed over size.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -Oi) # [+] Generate intrinsic functions.
+ elseif ("${CMAKE_CXX_COMPILER_ID}" MATCHES "GNU|Clang")
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -Wall -Wextra -Wconversion) # [+] Add baseline warnings that can be used safely even with system headers.
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wdouble-promotion) # [+] Warn about double promotions.
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wduplicated-cond) # [+] Warn about duplicate conditions.
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wduplicated-branches) # [+] Warn about duplicate branches.
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wlogical-op) # [+] Warn about suspicious uses of logical operators in expressions.
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wlogical-not-parentheses) # [+] Warn about logical not used on the left hand side operand of a comparison.
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -Wrestrict)
+
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -fno-math-errno) # [-] Disable math functions setting errno (performance reasons).
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -fno-threadsafe-statics) # [-] Don't add guards when initializing statics (we don't need it).
+ list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -O2) # [+] Compiling with -O2 in release mode is what we generally want.
+ list(APPEND ASMJIT_PRIVATE_CFLAGS_REL -fmerge-all-constants) # [+] We don't need unique address per constant (merging improves library size).
+
+ # -fno-semantic-interposition is not available on apple - the compiler issues a warning, which is not detected.
+ if (NOT APPLE)
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS -fno-semantic-interposition)
+ endif()
+
+ if (NOT "${CMAKE_SYSTEM_NAME}" STREQUAL "iOS")
+ asmjit_detect_cflags(ASMJIT_PRIVATE_CFLAGS_REL -fno-enforce-eh-specs) # [-] Don't enforce termination if noexcept function throws.
+ endif()
+ endif()
+ endif()
+
+ # Support for sanitizers.
+ if (ASMJIT_SANITIZE)
+ asmjit_detect_sanitizers(ASMJIT_SANITIZE_CFLAGS ${ASMJIT_SANITIZE})
+ if (ASMJIT_SANITIZE_CFLAGS)
+ message(STATUS "[asmjit] Enabling sanitizers: '${ASMJIT_SANITIZE_CFLAGS}'")
+
+ # Linker must receive the same flags as the compiler when it comes to sanitizers.
+ set(ASMJIT_SANITIZE_LFLAGS ${ASMJIT_SANITIZE_CFLAGS})
+
+ # Don't omit frame pointer if sanitizers are enabled.
+ if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
+ list(APPEND ASMJIT_SANITIZE_CFLAGS -Oy-)
+ else()
+ list(APPEND ASMJIT_SANITIZE_CFLAGS -fno-omit-frame-pointer -g)
+ endif()
+
+ list(APPEND ASMJIT_PRIVATE_CFLAGS ${ASMJIT_SANITIZE_CFLAGS})
+ list(APPEND ASMJIT_PRIVATE_LFLAGS ${ASMJIT_SANITIZE_LFLAGS})
+ endif()
+ endif()
endif()
-set(ASMJIT_SRC "")
-foreach(src_file ${ASMJIT_SRC_LIST})
- set(src_file "${ASMJIT_DIR}/src/${src_file}")
- list(APPEND ASMJIT_SRC ${src_file})
+if ("${CMAKE_SYSTEM_NAME}" MATCHES "^Windows")
+ # Dependency: Windows target needs no extra dependencies, however, we have to check for .natvis support.
+ if(CMAKE_LINKER MATCHES "^(lld-link|link)\\.exe$")
+ set(ASMJIT_LINKER_SUPPORTS_NATVIS TRUE)
+ endif()
+elseif ("${CMAKE_SYSTEM_NAME}" STREQUAL "Android")
+ # Dependency: libc is the only required library on Android as it also provides libpthread.
+ message(STATUS "[asmjit] Adding 'libc' dependency (Android)")
+ list(APPEND ASMJIT_LIBS c)
+elseif ("${CMAKE_SYSTEM_NAME}" STREQUAL "Haiku")
+ # Dependency: libroot is used by Haiku instead of libc, so link to libroot and libpthread.
+ message(STATUS "[asmjit] Adding 'libroot' and 'libpthread' dependencies (Haiku)")
+ list(APPEND ASMJIT_LIBS root pthread)
+else()
+ # Dependency: libc is always required.
+ message(STATUS "[asmjit] Adding 'libc' dependency (Linux, BSD, or other UNIX/POSIX environment)")
+ list(APPEND ASMJIT_LIBS c)
+
+ # Dependency: pthread (required so AsmJit can use pthread_lock).
+ check_cxx_source_compiles("
+ #include <pthread.h>
+ int main() {
+ pthread_mutex_t m;
+ pthread_mutex_init(&m, nullptr);
+ return pthread_mutex_destroy(&m);
+ }
+ " ASMJIT_LIBC_HAS_LIBPTHREAD)
+ if (ASMJIT_LIBC_HAS_LIBPTHREAD)
+ message(STATUS "[asmjit] Library 'libpthread' provided by 'libc' (not linking to libpthread)")
+ else()
+ message(STATUS "[asmjit] Library 'libpthread' not provided by 'libc' (linking to libpthread)")
+ list(APPEND ASMJIT_LIBS pthread)
+ endif()
- if ("${src_file}" MATCHES "\\.natvis")
- if (ASMJIT_LINKER_SUPPORTS_NATVIS)
- list(APPEND ASMJIT_PRIVATE_LFLAGS "-natvis:${src_file}")
+ # Dependency: shm_open (required so AsmJit can use shm_open on supported platforms).
+ if ("${CMAKE_SYSTEM_NAME}" MATCHES "^(Linux|NetBSD)$" AND NOT ASMJIT_NO_SHM_OPEN)
+ check_cxx_source_compiles("
+ #include <sys/mman.h>
+ int main() {
+ const char file_name[1] {};
+ return shm_open(file_name, 0, 0);
+ }
+ " ASMJIT_LIBC_HAS_LIBRT)
+ if (ASMJIT_LIBC_HAS_LIBRT)
+ message(STATUS "[asmjit] Symbol 'shm_open' provided by libc (not linking to librt)")
+ else()
+ message(STATUS "[asmjit] Symbol 'shm_open' not provided by libc, linking to librt")
+ list(APPEND ASMJIT_LIBS rt)
endif()
endif()
-endforeach()
+endif()
-source_group(TREE "${ASMJIT_DIR}" FILES ${ASMJIT_SRC})
+if (ASMJIT_STATIC OR ASMJIT_EMBED)
+ list(APPEND ASMJIT_CFLAGS -DASMJIT_STATIC)
+endif()
-# AsmJit - Summary
-# ================
+if (ASMJIT_NO_SHM_OPEN)
+ list(APPEND ASMJIT_PRIVATE_CFLAGS -DASMJIT_NO_SHM_OPEN)
+endif()
-message("** AsmJit Summary **")
-message(" ASMJIT_DIR=${ASMJIT_DIR}")
-message(" ASMJIT_TEST=${ASMJIT_TEST}")
-message(" ASMJIT_TARGET_TYPE=${ASMJIT_TARGET_TYPE}")
-message(" ASMJIT_DEPS=${ASMJIT_DEPS}")
-message(" ASMJIT_LIBS=${ASMJIT_LIBS}")
-message(" ASMJIT_CFLAGS=${ASMJIT_CFLAGS}")
-message(" ASMJIT_PRIVATE_CFLAGS=${ASMJIT_PRIVATE_CFLAGS}")
-message(" ASMJIT_PRIVATE_CFLAGS_DBG=${ASMJIT_PRIVATE_CFLAGS_DBG}")
-message(" ASMJIT_PRIVATE_CFLAGS_REL=${ASMJIT_PRIVATE_CFLAGS_REL}")
+foreach(build_option ASMJIT_NO_X86
+ ASMJIT_NO_AARCH64
+ ASMJIT_NO_FOREIGN
+ ASMJIT_NO_ABI_NAMESPACE
+ ASMJIT_NO_JIT
+ ASMJIT_NO_TEXT
+ ASMJIT_NO_LOGGING
+ ASMJIT_NO_INTROSPECTION
+ ASMJIT_NO_BUILDER
+ ASMJIT_NO_COMPILER
+ ASMJIT_NO_UJIT)
+ if (${build_option})
+ list(APPEND ASMJIT_CFLAGS "-D${build_option}")
+ endif()
+endforeach()
+
+if (ASMJIT_LINKER_SUPPORTS_NATVIS AND NOT ASMJIT_NO_NATVIS)
+ list(APPEND ASMJIT_SRC asmjit/asmjit.natvis)
+ list(APPEND ASMJIT_PRIVATE_LFLAGS "-natvis:${CMAKE_CURRENT_LIST_DIR}/asmjit/asmjit.natvis")
+endif()
+
+source_group(TREE "${CMAKE_CURRENT_LIST_DIR}" FILES ${ASMJIT_SRC})
# AsmJit - Targets
# ================
-if (NOT ASMJIT_EMBED)
- # Add AsmJit target.
- asmjit_addapp(asmjit "${ASMJIT_TARGET_TYPE}"
+message(STATUS "[asmjit] Adding 'asmjit::asmjit' target ('ASMJIT_TARGET_TYPE=${ASMJIT_TARGET_TYPE}')")
+
+if (ASMJIT_EMBED)
+ add_library(asmjit_embed INTERFACE)
+ target_sources(asmjit_embed INTERFACE ${ASMJIT_SRC})
+ target_link_libraries(asmjit_embed INTERFACE ${ASMJIT_LIBS})
+ target_compile_options(asmjit_embed INTERFACE ${ASMJIT_CFLAGS})
+ target_include_directories(asmjit_embed BEFORE INTERFACE ${ASMJIT_INCLUDE_DIRS})
+ add_library(asmjit::asmjit ALIAS asmjit_embed)
+else()
+ foreach(v "ASMJIT_LIBS"
+ "ASMJIT_CFLAGS"
+ "ASMJIT_PRIVATE_CFLAGS"
+ "ASMJIT_PRIVATE_CFLAGS_DBG"
+ "ASMJIT_PRIVATE_CFLAGS_REL"
+ "ASMJIT_SANITIZE_CFLAGS"
+ "ASMJIT_SANITIZE_LFLAGS")
+ if (NOT "${${v}}" STREQUAL "")
+ message(" ${v}=${${v}}")
+ endif()
+ endforeach()
+
+ asmjit_add_target(asmjit "${ASMJIT_TARGET_TYPE}"
SOURCES ${ASMJIT_SRC}
- LIBRARIES ${ASMJIT_DEPS}
+ LIBRARIES ${ASMJIT_LIBS}
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
- target_compile_options(asmjit INTERFACE ${ASMJIT_CFLAGS})
- target_include_directories(asmjit BEFORE INTERFACE
- $<BUILD_INTERFACE:${ASMJIT_INCLUDE_DIRS}>
- $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
-
- # Create an asmjit::asmjit alias.
+ target_compile_options(asmjit PUBLIC ${ASMJIT_CFLAGS})
+ target_include_directories(asmjit BEFORE PUBLIC $<BUILD_INTERFACE:${ASMJIT_INCLUDE_DIRS}>
+ $<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
add_library(asmjit::asmjit ALIAS asmjit)
- # Add AsmJit install instructions (library and public headers).
+ # AsmJit - Install Instructions
+ # -----------------------------
+
if (NOT ASMJIT_NO_INSTALL)
+ message(STATUS "[asmjit] Enabling install support ('ASMJIT_NO_INSTALL=OFF')")
+
install(TARGETS asmjit
EXPORT asmjit-config
RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}"
ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}"
LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}"
INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}")
+
install(EXPORT asmjit-config
NAMESPACE asmjit::
DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/asmjit")
- foreach(_src_file ${ASMJIT_SRC_LIST})
+ foreach(_src_file ${ASMJIT_SRC})
if ("${_src_file}" MATCHES "\\.h$" AND NOT "${_src_file}" MATCHES "_p\\.h$")
get_filename_component(_src_dir ${_src_file} PATH)
- install(FILES "${ASMJIT_DIR}/src/${_src_file}" DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}/${_src_dir}")
+ install(FILES "${CMAKE_CURRENT_LIST_DIR}/${_src_file}" DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}/${_src_dir}")
endif()
endforeach()
endif()
- # Add AsmJit tests.
+ # AsmJit - Tests & Benchmarks
+ # ---------------------------
+
if (ASMJIT_TEST)
enable_testing()
+ message(STATUS "[asmjit] Enabling AsmJit tests ('ASMJIT_TEST=${ASMJIT_TEST}')")
# Special target that always uses embedded AsmJit.
- asmjit_addapp(asmjit_test_runner TEST
+ asmjit_add_target(asmjit_test_runner TEST
SOURCES ${ASMJIT_SRC}
- testing/tests/asmjit_test_runner.cpp
- testing/tests/broken.cpp
- testing/tests/broken.h
- LIBRARIES ${ASMJIT_DEPS}
- CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
+ asmjit-testing/tests/asmjit_test_runner.cpp
+ asmjit-testing/tests/broken.cpp
+ asmjit-testing/tests/broken.h
+ LIBRARIES ${ASMJIT_LIBS}
+ CFLAGS ${ASMJIT_CFLAGS}
+ ${ASMJIT_PRIVATE_CFLAGS}
-DASMJIT_TEST
-DASMJIT_STATIC
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
target_include_directories(asmjit_test_runner BEFORE PRIVATE ${ASMJIT_INCLUDE_DIRS})
- asmjit_addapp(asmjit_test_assembler TEST
- SOURCES testing/tests/asmjit_test_assembler.cpp
- testing/tests/asmjit_test_assembler.h
- testing/tests/asmjit_test_assembler_a64.cpp
- testing/tests/asmjit_test_assembler_x64.cpp
- testing/tests/asmjit_test_assembler_x86.cpp
+ asmjit_add_target(asmjit_test_assembler TEST
+ SOURCES asmjit-testing/tests/asmjit_test_assembler.cpp
+ asmjit-testing/tests/asmjit_test_assembler.h
+ asmjit-testing/tests/asmjit_test_assembler_a64.cpp
+ asmjit-testing/tests/asmjit_test_assembler_x64.cpp
+ asmjit-testing/tests/asmjit_test_assembler_x86.cpp
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
foreach(app asmjit_test_environment asmjit_test_emitters asmjit_test_x86_sections)
- asmjit_addapp(${app} TEST
- SOURCES testing/tests/${app}.cpp
+ asmjit_add_target(${app} TEST
+ SOURCES asmjit-testing/tests/${app}.cpp
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
@@ -669,8 +635,8 @@ if (NOT ASMJIT_EMBED)
endforeach()
if (NOT ASMJIT_NO_INTROSPECTION)
- asmjit_addapp(asmjit_test_instinfo TEST
- SOURCES testing/tests/asmjit_test_instinfo.cpp
+ asmjit_add_target(asmjit_test_instinfo TEST
+ SOURCES asmjit-testing/tests/asmjit_test_instinfo.cpp
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
@@ -682,45 +648,30 @@ if (NOT ASMJIT_EMBED)
# Some compilers don't like passing -msse2 for 64-bit targets, and some compilers targeting non-x86
# would pass "-msse2" compile flag check, but with a warning not detected by CMake. Thus, verify that
# our target is really 32-bit X86 and only use -msse2 or -arch:SSE2 flags when necessary.
- set(ASMJIT_SSE2_CFLAGS "")
-
- check_cxx_source_compiles("
- #if defined(_M_X64) || defined(__x86_64__)
- // Skip...
- #elif defined(_M_IX86) || defined(__X86__) || defined(__i386__)
- int target_arch_is_x86() { return 1; }
- #endif
- int main() { return target_arch_is_x86(); }
- " ASMJIT_TARGET_ARCH_X86)
-
- check_cxx_source_compiles("
- #if defined(_M_X64) || defined(__x86_64__)
- int target_arch_is_x86_64() { return 1; }
- #endif
- int main() { return target_arch_is_x86_64(); }
- " ASMJIT_TARGET_ARCH_X86_64)
+ asmjit_detect_target_arch(ASMJIT_TARGET_ARCH)
+ set(ASMJIT_SSE2_CFLAGS "")
if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC" OR "x${CMAKE_CXX_COMPILER_FRONTEND_VARIANT}" STREQUAL "xMSVC")
- if (ASMJIT_TARGET_ARCH_X86)
+ if (ASMJIT_TARGET_ARCH STREQUAL "X86")
asmjit_detect_cflags(ASMJIT_SSE2_CFLAGS -arch:SSE2)
endif()
- if (ASMJIT_TARGET_ARCH_X86 OR ASMJIT_TARGET_ARCH_X86_64)
+ if (ASMJIT_TARGET_ARCH MATCHES "^(X86|X86_64)$")
asmjit_detect_cflags(ASMJIT_AVX2FMA_CFLAGS -arch:AVX2)
endif()
else()
- if (ASMJIT_TARGET_ARCH_X86)
+ if (ASMJIT_TARGET_ARCH STREQUAL "X86")
asmjit_detect_cflags(ASMJIT_SSE2_CFLAGS -msse2)
endif()
- if (ASMJIT_TARGET_ARCH_X86 OR ASMJIT_TARGET_ARCH_X86_64)
+ if (ASMJIT_TARGET_ARCH MATCHES "^(X86|X86_64)$")
asmjit_detect_cflags(ASMJIT_AVX2FMA_CFLAGS -mavx2 -mfma)
endif()
endif()
- asmjit_addapp(asmjit_test_compiler TEST
- SOURCES testing/tests/asmjit_test_compiler.cpp
- testing/tests/asmjit_test_compiler.h
- testing/tests/asmjit_test_compiler_a64.cpp
- testing/tests/asmjit_test_compiler_x86.cpp
+ asmjit_add_target(asmjit_test_compiler TEST
+ SOURCES asmjit-testing/tests/asmjit_test_compiler.cpp
+ asmjit-testing/tests/asmjit_test_compiler.h
+ asmjit-testing/tests/asmjit_test_compiler_a64.cpp
+ asmjit-testing/tests/asmjit_test_compiler_x86.cpp
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS} ${ASMJIT_SSE2_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
@@ -728,31 +679,31 @@ if (NOT ASMJIT_EMBED)
endif()
if (NOT ASMJIT_NO_UJIT)
- asmjit_addapp(asmjit_test_unicompiler TEST
- SOURCES testing/tests/asmjit_test_unicompiler.cpp
- testing/tests/asmjit_test_unicompiler_sse2.cpp
- testing/tests/asmjit_test_unicompiler_avx2fma.cpp
- testing/tests/broken.cpp
+ asmjit_add_target(asmjit_test_unicompiler TEST
+ SOURCES asmjit-testing/tests/asmjit_test_unicompiler.cpp
+ asmjit-testing/tests/asmjit_test_unicompiler_sse2.cpp
+ asmjit-testing/tests/asmjit_test_unicompiler_avx2fma.cpp
+ asmjit-testing/tests/broken.cpp
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS} ${ASMJIT_SSE2_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
- set_property(SOURCE testing/tests/asmjit_test_unicompiler_avx2fma.cpp APPEND PROPERTY COMPILE_OPTIONS ${ASMJIT_AVX2FMA_CFLAGS})
+ set_property(SOURCE asmjit-testing/tests/asmjit_test_unicompiler_avx2fma.cpp APPEND PROPERTY COMPILE_OPTIONS ${ASMJIT_AVX2FMA_CFLAGS})
endif()
- asmjit_addapp(asmjit_bench_codegen EXECUTABLE
- SOURCES testing/bench/asmjit_bench_codegen.cpp
- testing/bench/asmjit_bench_codegen_a64.cpp
- testing/bench/asmjit_bench_codegen_x86.cpp
- SOURCES testing/bench/asmjit_bench_codegen.h
+ asmjit_add_target(asmjit_bench_codegen EXECUTABLE
+ SOURCES asmjit-testing/bench/asmjit_bench_codegen.cpp
+ asmjit-testing/bench/asmjit_bench_codegen_a64.cpp
+ asmjit-testing/bench/asmjit_bench_codegen_x86.cpp
+ SOURCES asmjit-testing/bench/asmjit_bench_codegen.h
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL})
foreach(app asmjit_bench_overhead asmjit_bench_regalloc)
- asmjit_addapp(${app} TEST
- SOURCES testing/bench/${app}.cpp
+ asmjit_add_target(${app} TEST
+ SOURCES asmjit-testing/bench/${app}.cpp
LIBRARIES asmjit::asmjit
CFLAGS ${ASMJIT_PRIVATE_CFLAGS}
CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG}
@@ -761,3 +712,5 @@ if (NOT ASMJIT_EMBED)
endif()
endif()
+
+message(STATUS "[asmjit] == Configuring done ==")
diff --git a/3rdparty/asmjit/CMakePresets.json b/3rdparty/asmjit/CMakePresets.json
new file mode 100644
index 00000000000..862e718ed89
--- /dev/null
+++ b/3rdparty/asmjit/CMakePresets.json
@@ -0,0 +1,53 @@
+{
+ "version": 10,
+ "configurePresets": [
+ {
+ "name": "conf-base",
+ "hidden": true,
+ "description": "${presetName}",
+ "binaryDir": "${sourceDir}/build/${presetName}",
+ "cacheVariables": { "CMAKE_EXPORT_COMPILE_COMMANDS": "ON" }
+ },
+
+ {
+ "name": "conf-debug",
+ "hidden": true,
+ "inherits": "conf-base",
+ "cacheVariables": { "CMAKE_BUILD_TYPE": "Debug" }
+ },
+
+ {
+ "name": "conf-release",
+ "hidden": true,
+ "inherits": "conf-base",
+ "cacheVariables": { "CMAKE_BUILD_TYPE": "Release", "CMAKE_INTERPROCEDURAL_OPTIMIZATION": "ON" }
+ },
+
+ { "name": "conf-test" , "hidden": true, "cacheVariables": { "ASMJIT_TEST": "ON" } },
+ { "name": "conf-static" , "hidden": true, "cacheVariables": { "ASMJIT_STATIC": "ON" } },
+ { "name": "conf-shared" , "hidden": true, "cacheVariables": { "ASMJIT_STATIC": "OFF" } },
+ { "name": "conf-asan" , "hidden": true, "cacheVariables": { "ASMJIT_SANITIZE": "address" } },
+ { "name": "conf-msan" , "hidden": true, "cacheVariables": { "ASMJIT_SANITIZE": "memory" } },
+ { "name": "conf-tsan" , "hidden": true, "cacheVariables": { "ASMJIT_SANITIZE": "thread" } },
+ { "name": "conf-ubsan" , "hidden": true, "cacheVariables": { "ASMJIT_SANITIZE": "undefined" } },
+ { "name": "conf-32" , "hidden": true, "environment": { "CFLAGS": "-m32", "CXXFLAGS": "-m32" } },
+ { "name": "conf-avx2" , "hidden": true, "environment": { "CXXFLAGS": "-mavx2 -mbmi -mbmi2" } },
+
+ { "name": "debug" , "inherits": ["conf-debug", "conf-test", "conf-static"] },
+ { "name": "debug-asan" , "inherits": ["conf-debug", "conf-test", "conf-static", "conf-asan"] },
+ { "name": "debug-msan" , "inherits": ["conf-debug", "conf-test", "conf-static", "conf-msan"] },
+ { "name": "debug-ubsan" , "inherits": ["conf-debug", "conf-test", "conf-static", "conf-ubsan"] },
+ { "name": "debug-32" , "inherits": ["conf-debug", "conf-test", "conf-static", "conf-32"] },
+ { "name": "debug-shared" , "inherits": ["conf-debug", "conf-test", "conf-shared"] },
+ { "name": "debug-shared-32" , "inherits": ["conf-debug", "conf-test", "conf-shared", "conf-32"] },
+
+ { "name": "release" , "inherits": ["conf-release", "conf-test", "conf-static"] },
+ { "name": "release-avx2" , "inherits": ["conf-release", "conf-test", "conf-static", "conf-avx2"] },
+ { "name": "release-asan" , "inherits": ["conf-release", "conf-test", "conf-static", "conf-asan"] },
+ { "name": "release-msan" , "inherits": ["conf-release", "conf-test", "conf-static", "conf-msan"] },
+ { "name": "release-ubsan" , "inherits": ["conf-release", "conf-test", "conf-static", "conf-ubsan"] },
+ { "name": "release-32" , "inherits": ["conf-release", "conf-test", "conf-static", "conf-32"] },
+ { "name": "release-shared" , "inherits": ["conf-release", "conf-test", "conf-shared"] },
+ { "name": "release-shared-32", "inherits": ["conf-release", "conf-test", "conf-shared", "conf-32"] }
+ ]
+}
diff --git a/3rdparty/asmjit/CONTRIBUTING.md b/3rdparty/asmjit/CONTRIBUTING.md
index 54f5047b223..7c33cc036f4 100644
--- a/3rdparty/asmjit/CONTRIBUTING.md
+++ b/3rdparty/asmjit/CONTRIBUTING.md
@@ -10,7 +10,7 @@
### Asking questions
- * We prefer GitHub issues to be used for reporting bugs or feature requests, but it's still okay to ask questions there as well. However, please consider joining our [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im) to ask questions; it has an active community that can quickly respond.
+ * We prefer GitHub issues to be used for reporting bugs or feature requests, but it's still okay to ask questions there as well. However, please consider joining our [Public Chat](https://app.element.io/#/room/#asmjit:matrix.org) to ask questions; it has an active community that can quickly respond.
### Suggesting feature requests
@@ -26,7 +26,7 @@
### Suggesting a website content enhancement
- * [AsmJit's website](https://asmjit.com) is also generated, but not from public sources at the moment. If you did find an issue on the website you can either use contact information on the [support page](https://asmjit.com/support.html) or to discuss the change on our [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im). Alternatively, opening a regular issue is also okay.
+ * [AsmJit's website](https://asmjit.com) is also generated, but not from public sources at the moment. If you did find an issue on the website you can either use contact information on the [support page](https://asmjit.com/support.html) or to discuss the change on our [Public Chat](https://app.element.io/#/room/#asmjit:matrix.org). Alternatively, opening a regular issue is also okay.
## Coding Style & Consistency
@@ -37,42 +37,44 @@
* Initially, AsmJit coding style was based on Google C++ Style Guide, but it has diverged from it.
- * Include guards use `<PATH_TO_SRC>_H_INCLUDED` format.
+ * Include guards use `ASMJIT_<...PATH...>_H_INCLUDED` format.
* `asmjit` namespace must be open by `ASMJIT_BEGIN_NAMESPACE` and closed by `ASMJIT_END_NAMESPACE`
* `asmjit::xxx` (backend specific) nested namespace must be open by `ASMJIT_BEGIN_SUB_NAMESPACE(xxx)` and closed by `ASMJIT_END_SUB_NAMESPACE`.
- * Opening bracket is on the same line, like `struct Something {`, `if (condition) {`, etc...
+ * Opening brackets are on the same line, like `struct Something {`, `if (condition) {`, etc...
* The code uses a soft limit of 120 characters per line (including documentation), but it's not enforced and it's okay to use more when it makes sense (for example defining tables, etc...).
- * Since AsmJit doesn't use Exceptions nor RTTI the code cannot use containers provided by the C++ standard library. In general, we try to only use a bare minimum from the C++ standard library to make it viable to use AsmJit even in C code bases where JIT complier is implemented in C++ ([Erlang](https://www.erlang.org/) can be seen as a great example).
+ * Since AsmJit doesn't use Exceptions nor RTTI the code cannot use containers provided by the C++ standard library. In general, we try to only use a bare minimum from the C++ standard library to make it viable to use AsmJit even in C code bases where JIT compiler is implemented in C++ ([Erlang](https://www.erlang.org/) can be seen as a great example).
+
+ * Please don't bring your own coding style preferences into the code base.
## Testing
* AsmJit uses a minimalist unit testing framework to write unit tests to avoid third-party dependencies.
- * At the moment tests are in the same file as the implementation and are only compiled when `ASMJIT_TEST` macro is defined.
+ * At the moment tests are in the same file as the implementation and are only compiled when `ASMJIT_TEST` macro is defined (will change in the future).
* Use `-DASMJIT_TEST=1` when invoking [CMake](https://cmake.org/) to compile AsmJit tests.
- * Unit tests are compiled to a single `asmjit_test_unit[.exe]` executable.
+ * Unit tests are compiled to a single `asmjit_test_runner[.exe]` executable.
* Other tests have their own executables based on what is tested.
- * Always add assembler tests when adding new instructions, see [asmjit_test_assembler_x64.cpp](./test/asmjit_test_assembler_x64.cpp) and [asmjit_test_assembler_a64.cpp](./test/asmjit_test_assembler_a64.cpp) for more details.
+ * Always add assembler tests when adding new instructions, see [asmjit_test_assembler_x64.cpp](./asmjit-testing/tests/asmjit_test_assembler_x64.cpp) and [asmjit_test_assembler_a64.cpp](./asmjit-testing/tests/asmjit_test_assembler_a64.cpp) for more details.
## Pull Request Messages
+ * If a change breaks ABI it must start with `[abi]` - this prefix has a precedence over anything else.
+
* If a change fixes a bug the message should should start with `[bug]`.
* If a change fixes or enhances documentation it should start with `[doc]`.
* If a change fixes or enhances our CI it should start with `[ci]`.
- * If a change breaks ABI it must start with `[abi]`.
-
* Otherwise there is no suggested prefix.
## ABI Changes
diff --git a/3rdparty/asmjit/README.md b/3rdparty/asmjit/README.md
index fb03e75e3a1..5920eab1906 100644
--- a/3rdparty/asmjit/README.md
+++ b/3rdparty/asmjit/README.md
@@ -5,7 +5,7 @@ AsmJit is a library for low-latency machine code generation written in C++.
* [Official Home Page (asmjit.com)](https://asmjit.com)
* [Official Repository (asmjit/asmjit)](https://github.com/asmjit/asmjit)
- * [Public Chat Channel](https://app.gitter.im/#/room/#asmjit:gitter.im)
+ * [Public Chat Channel](https://app.element.io/#/room/#asmjit:matrix.org)
* [Zlib License](./LICENSE.md)
See [asmjit.com](https://asmjit.com) page for more details, examples, and documentation.
@@ -13,36 +13,37 @@ See [asmjit.com](https://asmjit.com) page for more details, examples, and docume
Project Organization
--------------------
- * **`/`** - Project root
- * **src** - Source code
- * **asmjit** - Source code and headers (always point include path in here)
- * **core** - Core API, backend independent except relocations
- * **arm** - ARM specific API, designed to be common for both AArch32 and AArch64
- * **a64** - AArch64 specific API, used only by AArch64 backends
- * **x86** - X86 specific API, used only by X86 and X64 backends
- * **ujit** - Universal JIT API
- * **testing** - Unit tests, integration tests, and benchmarks (don't embed in your project)
- * **commons** - Common utilities shared between tests and benchmarks
- * **bench** - Benchmarks
- * **tests** - Unit tests and integration tests
- * **tools** - Tools used to re-regenerate generated files (instruction DB, enum strings)
+ * **`/`** - Project root - project files and scripts, `include` path points here
+ * **asmjit** - AsmJit source code and headers
+ * **core** - Core API, backend independent except relocations
+ * **support** - Support classes and functions
+ * **arm** - ARM specific API, designed to be common for both AArch32 and AArch64
+ * **a64** - AArch64 specific API, used only by AArch64 backends
+ * **x86** - X86 specific API, used only by X86 and X64 backends
+ * **ujit** - Universal JIT API
+ * **asmjit-testing** - Unit tests, integration tests, and benchmarks (don't embed in your project)
+ * **commons** - Common utilities shared between tests and benchmarks
+ * **bench** - Benchmarks
+ * **tests** - Unit tests and integration tests
+ * **db** - Instruction database
+ * **tools** - Tools used to re-regenerate generated files (instruction DB, enum strings)
Roadmap
-------
* See [Roadmap](https://asmjit.com/roadmap.html) page for more details
-Contributing
-------------
-
- * See [CONTRIBUTING](./CONTRIBUTING.md) page for more details
-
Documentation
-------------
* [Documentation Index](https://asmjit.com/doc/index.html)
* [Build Instructions](https://asmjit.com/doc/group__asmjit__build.html) (includes [CMake Integration](https://asmjit.com/doc/group__asmjit__build.html#cmake_integration))
+Contributing Guidelines
+-----------------------
+
+ * See [CONTRIBUTING](./CONTRIBUTING.md) page for more details
+
Development & Testing
---------------------
@@ -55,18 +56,18 @@ Breaking the API is sometimes inevitable, what to do?
* See [Breaking Changes Guide](https://asmjit.com/doc/group__asmjit__breaking__changes.html), which is now part of AsmJit documentation
* See asmjit tests, they always compile and provide implementation of many use-cases:
- * [asmjit_test_emitters.cpp](./testing/tests/asmjit_test_emitters.cpp) - Tests that demonstrate the purpose of emitters
- * [asmjit_test_assembler_x86.cpp](./testing/tests/asmjit_test_assembler_x86.cpp) - Tests targeting AsmJit's Assembler (x86/x64)
- * [asmjit_test_compiler_x86.cpp](./testing/tests/asmjit_test_compiler_x86.cpp) - Tests targeting AsmJit's Compiler (x86/x64)
- * [asmjit_test_instinfo.cpp](./testing/tests/asmjit_test_instinfo.cpp) - Tests that query instruction information
- * [asmjit_test_x86_sections.cpp](./testing/tests/asmjit_test_x86_sections.cpp) - Multiple sections test
- * Visit our [Gitter Chat](https://app.gitter.im/#/room/#asmjit:gitter.im) if you need a quick help
-
-Support
--------
+ * [asmjit_test_emitters.cpp](./asmjit-testing/tests/asmjit_test_emitters.cpp) - Tests that demonstrate the purpose of emitters
+ * [asmjit_test_assembler_x86.cpp](./asmjit-testing/tests/asmjit_test_assembler_x86.cpp) - Tests targeting AsmJit's Assembler (x86/x64)
+ * [asmjit_test_compiler_x86.cpp](./asmjit-testing/tests/asmjit_test_compiler_x86.cpp) - Tests targeting AsmJit's Compiler (x86/x64)
+ * [asmjit_test_instinfo.cpp](./asmjit-testing/tests/asmjit_test_instinfo.cpp) - Tests that query instruction information
+ * [asmjit_test_x86_sections.cpp](./asmjit-testing/tests/asmjit_test_x86_sections.cpp) - Multiple sections test
+ * Visit our [Public Chat](https://app.element.io/#/room/#asmjit:matrix.org) if you need a quick help
+
+Support & Funding
+-----------------
* AsmJit project has both community and commercial support, see [AsmJit's Support Page](https://asmjit.com/support.html)
- * Organizations that rely on AsmJit should support the development!
+ * If you use this software commercially, please see the [Funding Page](https://kobalicek.com/funding.html) and support the development
Notable Donors List:
diff --git a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen.cpp b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen.cpp
index 3f4933a2902..89e71a30848 100644
--- a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen.cpp
+++ b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen.cpp
@@ -4,13 +4,14 @@
// SPDX-License-Identifier: Zlib
#include <asmjit/core.h>
+
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/commons/cmdline.h>
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "../commons/asmjitutils.h"
-#include "../commons/cmdline.h"
-
using namespace asmjit;
static void print_app_info() noexcept {
diff --git a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen.h b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen.h
index 9df289cea11..ae6b372dc29 100644
--- a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen.h
+++ b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen.h
@@ -8,8 +8,8 @@
#include <asmjit/core.h>
-#include "../commons/asmjitutils.h"
-#include "../commons/performancetimer.h"
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/commons/performancetimer.h>
namespace asmjit_perf_utils {
diff --git a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen_a64.cpp b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen_a64.cpp
index a49db191018..7bb85356b93 100644
--- a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen_a64.cpp
+++ b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen_a64.cpp
@@ -8,12 +8,12 @@
#if !defined(ASMJIT_NO_AARCH64)
#include <asmjit/a64.h>
+#include <asmjit-testing/bench/asmjit_bench_codegen.h>
+
#include <limits>
#include <stdio.h>
#include <string.h>
-#include "asmjit_bench_codegen.h"
-
using namespace asmjit;
// Generates a long sequence of GP instructions.
diff --git a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen_x86.cpp b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen_x86.cpp
index 06209311d1e..586420bd06a 100644
--- a/3rdparty/asmjit/testing/bench/asmjit_bench_codegen_x86.cpp
+++ b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_codegen_x86.cpp
@@ -8,13 +8,13 @@
#if !defined(ASMJIT_NO_X86)
#include <asmjit/x86.h>
+#include <asmjit-testing/bench/asmjit_bench_codegen.h>
+#include <asmjit-testing/tests/asmjit_test_misc.h>
+
#include <limits>
#include <stdio.h>
#include <string.h>
-#include "asmjit_bench_codegen.h"
-#include "../tests/asmjit_test_misc.h"
-
using namespace asmjit;
enum class InstForm {
diff --git a/3rdparty/asmjit/testing/bench/asmjit_bench_overhead.cpp b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_overhead.cpp
index a964c30c4dd..94ef13774af 100644
--- a/3rdparty/asmjit/testing/bench/asmjit_bench_overhead.cpp
+++ b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_overhead.cpp
@@ -1,9 +1,10 @@
-#include <stdint.h>
#include <asmjit/host.h>
-#include "../commons/asmjitutils.h"
-#include "../commons/cmdline.h"
-#include "../commons/performancetimer.h"
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/commons/cmdline.h>
+#include <asmjit-testing/commons/performancetimer.h>
+
+#include <stdint.h>
using namespace asmjit;
@@ -19,12 +20,15 @@ static void print_app_info(size_t n) noexcept {
printf("This benchmark was designed to benchmark the cost of initialization and\n"
"reset (or reinitialization) of CodeHolder and Emitters; and the cost of\n"
"moving a minimal assembled function to executable memory. Each output line\n"
- "uses \"<Test> [Func] [Finalize] [RT]\" format, with the following meaning:\n"
+ "provides the following columns:\n"
"\n"
" - <Test> - test case name - either 'CodeHolder' only or an emitter\n"
- " - [Func] - function was assembled\n"
- " - [Finalize] - function was finalized (Builder/Compiler)\n"
- " - [RT] - function was added to JitRuntime and then removed from it\n"
+ " - Strategy - reusability strategy - whether init/reset or reinit is used\n"
+ " - Reuse Only - no code generation, no use of emitter except for init/reuse\n"
+ " - Func - function was assembled\n"
+ " - RA - function was compiled (registers allocated) (Compiler)\n"
+ " - Asm - function was finalized & serialized (Builder/Compiler)\n"
+ " - RT - function was added to JitRuntime and then removed from it\n"
"\n"
"Essentially the output provides an insight into the cost of reusing\n"
"CodeHolder and other emitters, and the cost of assembling, finalizing,\n"
@@ -36,6 +40,24 @@ static void print_app_info(size_t n) noexcept {
printf("\n");
}
+enum class AssemblerOp {
+ kNone,
+ kRT
+};
+
+enum class BuilderOp {
+ kNone,
+ kFinalize,
+ kFinalize_RT
+};
+
+enum class CompilerOp {
+ kNone,
+ kCompile,
+ kFinalize,
+ kFinalize_RT
+};
+
#if !defined(ASMJIT_NO_JIT)
class MyErrorHandler : public ErrorHandler {
@@ -126,7 +148,7 @@ static inline void bench_assembler(InitStrategy strategy, size_t count) {
}
}
-template<typename AssemblerT>
+template<typename AssemblerT, AssemblerOp op>
static inline void bench_assembler_func(InitStrategy strategy, size_t count) {
JitRuntime rt;
CodeHolder code;
@@ -139,40 +161,13 @@ static inline void bench_assembler_func(InitStrategy strategy, size_t count) {
code.set_error_handler(&eh);
code.attach(&a);
emit_raw_func(a);
- code.reset();
- }
- }
- else {
- code.init(rt.environment());
- code.set_error_handler(&eh);
- code.attach(&a);
-
- for (size_t i = 0; i < count; i++) {
- code.reinit();
- emit_raw_func(a);
- }
- }
-}
-
-template<typename AssemblerT>
-static inline void bench_assembler_func_rt(InitStrategy strategy, size_t count) {
- JitRuntime rt;
- CodeHolder code;
- AssemblerT a;
- MyErrorHandler eh;
- using Func = uint32_t(*)(void);
-
- if (strategy == InitStrategy::kInitReset) {
- for (size_t i = 0; i < count; i++) {
- code.init(rt.environment());
- code.set_error_handler(&eh);
- code.attach(&a);
- emit_raw_func(a);
-
- Func fn;
- rt.add(&fn, &code);
- rt.release(fn);
+ if constexpr (op == AssemblerOp::kRT) {
+ using Func = uint32_t(*)(void);
+ Func fn;
+ rt.add(&fn, &code);
+ rt.release(fn);
+ }
code.reset();
}
@@ -186,9 +181,12 @@ static inline void bench_assembler_func_rt(InitStrategy strategy, size_t count)
code.reinit();
emit_raw_func(a);
- Func fn;
- rt.add(&fn, &code);
- rt.release(fn);
+ if constexpr (op == AssemblerOp::kRT) {
+ using Func = uint32_t(*)(void);
+ Func fn;
+ rt.add(&fn, &code);
+ rt.release(fn);
+ }
}
}
}
@@ -221,8 +219,8 @@ static inline void bench_builder(InitStrategy strategy, size_t count) {
}
}
-template<typename BuilderT>
-static inline void bench_builder_func(InitStrategy strategy, size_t count, bool finalize) {
+template<typename BuilderT, BuilderOp op>
+static inline void bench_builder_func(InitStrategy strategy, size_t count) {
JitRuntime rt;
CodeHolder code;
BuilderT b;
@@ -235,9 +233,16 @@ static inline void bench_builder_func(InitStrategy strategy, size_t count, bool
code.attach(&b);
emit_raw_func(b);
- if (finalize) {
+ if constexpr (op >= BuilderOp::kFinalize) {
b.finalize();
+ if constexpr (op == BuilderOp::kFinalize_RT) {
+ using Func = uint32_t(*)(void);
+ Func fn;
+ rt.add(&fn, &code);
+ rt.release(fn);
+ }
}
+
code.reset();
}
}
@@ -250,53 +255,18 @@ static inline void bench_builder_func(InitStrategy strategy, size_t count, bool
code.reinit();
emit_raw_func(b);
- if (finalize) {
+ if constexpr (op >= BuilderOp::kFinalize) {
b.finalize();
+ if constexpr (op == BuilderOp::kFinalize_RT) {
+ using Func = uint32_t(*)(void);
+ Func fn;
+ rt.add(&fn, &code);
+ rt.release(fn);
+ }
}
}
}
}
-
-template<typename BuilderT>
-static inline void bench_builder_func_finalize_rt(InitStrategy strategy, size_t count) {
- JitRuntime rt;
- CodeHolder code;
- BuilderT b;
- MyErrorHandler eh;
-
- using Func = uint32_t(*)(void);
-
- if (strategy == InitStrategy::kInitReset) {
- for (size_t i = 0; i < count; i++) {
- code.init(rt.environment());
- code.set_error_handler(&eh);
- code.attach(&b);
- emit_raw_func(b);
- b.finalize();
-
- Func fn;
- rt.add(&fn, &code);
- rt.release(fn);
-
- code.reset();
- }
- }
- else {
- code.init(rt.environment());
- code.set_error_handler(&eh);
- code.attach(&b);
-
- for (size_t i = 0; i < count; i++) {
- code.reinit();
- emit_raw_func(b);
- b.finalize();
-
- Func fn;
- rt.add(&fn, &code);
- rt.release(fn);
- }
- }
-}
#endif // ASMJIT_HAS_HOST_BACKEND && !ASMJIT_NO_BUILDER
#if defined(ASMJIT_HAS_HOST_BACKEND) && !defined(ASMJIT_NO_COMPILER)
@@ -326,8 +296,8 @@ static inline void bench_compiler(InitStrategy strategy, size_t count) {
}
}
-template<typename CompilerT>
-static inline void bench_compiler_func(InitStrategy strategy, size_t count, bool finalize) {
+template<typename CompilerT, CompilerOp op>
+static inline void bench_compiler_func(InitStrategy strategy, size_t count) {
JitRuntime rt;
CodeHolder code;
CompilerT cc;
@@ -343,8 +313,17 @@ static inline void bench_compiler_func(InitStrategy strategy, size_t count, bool
compile_raw_func(cc);
cc.end_func();
- if (finalize) {
+ if constexpr (op == CompilerOp::kCompile) {
+ cc.run_passes();
+ }
+ else if constexpr (op >= CompilerOp::kFinalize) {
cc.finalize();
+ if constexpr (op == CompilerOp::kFinalize_RT) {
+ using Func = uint32_t(*)(void);
+ Func fn;
+ rt.add(&fn, &code);
+ rt.release(fn);
+ }
}
code.reset();
@@ -362,99 +341,70 @@ static inline void bench_compiler_func(InitStrategy strategy, size_t count, bool
compile_raw_func(cc);
cc.end_func();
- if (finalize) {
+ if constexpr (op == CompilerOp::kCompile) {
+ cc.run_passes();
+ }
+ else if constexpr (op >= CompilerOp::kFinalize) {
cc.finalize();
+ if constexpr (op == CompilerOp::kFinalize_RT) {
+ using Func = uint32_t(*)(void);
+ Func fn;
+ rt.add(&fn, &code);
+ rt.release(fn);
+ }
}
}
}
}
-
-template<typename CompilerT>
-static inline void bench_compiler_func_rt(InitStrategy strategy, size_t count) {
- JitRuntime rt;
- CodeHolder code;
- CompilerT cc;
- MyErrorHandler eh;
-
- using Func = uint32_t(*)(void);
-
- if (strategy == InitStrategy::kInitReset) {
- for (size_t i = 0; i < count; i++) {
- code.init(rt.environment());
- code.set_error_handler(&eh);
- code.attach(&cc);
-
- (void)cc.add_func(FuncSignature::build<uint32_t>());
- compile_raw_func(cc);
- cc.end_func();
- cc.finalize();
-
- Func fn;
- rt.add(&fn, &code);
- rt.release(fn);
-
- code.reset();
- }
- }
- else {
- code.init(rt.environment());
- code.set_error_handler(&eh);
- code.attach(&cc);
-
- for (size_t i = 0; i < count; i++) {
- code.reinit();
-
- (void)cc.add_func(FuncSignature::build<uint32_t>());
- compile_raw_func(cc);
- cc.end_func();
- cc.finalize();
-
- Func fn;
- rt.add(&fn, &code);
- rt.release(fn);
- }
- }
-}
#endif // ASMJIT_HAS_HOST_BACKEND && !ASMJIT_NO_COMPILER
template<typename Lambda>
-static inline void test_perf(const char* bench_name, InitStrategy strategy, size_t n, Lambda&& fn) {
+static inline void test_perf(const char* group, const char* params, InitStrategy strategy, size_t n, Lambda&& fn) {
PerformanceTimer timer;
- const char* strategy_name = strategy == InitStrategy::kInitReset ? "init/reset" : "reinit ";
+ const char* strategy_name = strategy == InitStrategy::kInitReset ? "init/reset" : "reinit";
timer.start();
fn(strategy, n);
timer.stop();
- printf("%-31s [%s]: %8.3f [ms]\n", bench_name, strategy_name, timer.duration());
+ printf("| %-10s | %-10s | %-23s| %8.1f [ms] |\n", group, strategy_name, params, timer.duration());
}
static inline void test_perf_all(InitStrategy strategy, size_t n) {
using IS = InitStrategy;
- test_perf("CodeHolder (Only)" , strategy, n, [](IS s, size_t n) { bench_codeholder(s, n); });
+ const char frame[] = "+------------+------------+------------------------+---------------+\n";
+ const char header[] = "| Group | Strategy | Features Used | Time [ms] |\n";
+
+ printf(frame);
+ printf(header);
+ printf(frame);
+
+ test_perf("CodeHolder", "Reuse Only" , strategy, n, [](IS s, size_t n) { bench_codeholder(s, n); });
#if defined(ASMJIT_HAS_HOST_BACKEND)
- test_perf("Assembler" , strategy, n, [](IS s, size_t n) { bench_assembler<host::Assembler>(s, n); });
- test_perf("Assembler + Func" , strategy, n, [](IS s, size_t n) { bench_assembler_func<host::Assembler>(s, n); });
- test_perf("Assembler + Func + RT" , strategy, n, [](IS s, size_t n) { bench_assembler_func_rt<host::Assembler>(s, n); });
+ test_perf("Assembler ", "Reuse Only" , strategy, n, [](IS s, size_t n) { bench_assembler<host::Assembler>(s, n); });
+ test_perf("Assembler ", "Func" , strategy, n, [](IS s, size_t n) { bench_assembler_func<host::Assembler, AssemblerOp::kNone>(s, n); });
+ test_perf("Assembler ", "Func + RT" , strategy, n, [](IS s, size_t n) { bench_assembler_func<host::Assembler, AssemblerOp::kRT>(s, n); });
#endif
#if defined(ASMJIT_HAS_HOST_BACKEND) && !defined(ASMJIT_NO_BUILDER)
- test_perf("Builder" , strategy, n, [](IS s, size_t n) { bench_builder<host::Builder>(s, n); });
- test_perf("Builder + Func" , strategy, n, [](IS s, size_t n) { bench_builder_func<host::Builder>(s, n, false); });
- test_perf("Builder + Func + Finalize" , strategy, n, [](IS s, size_t n) { bench_builder_func<host::Builder>(s, n, true); });
- test_perf("Builder + Func + Finalize + RT" , strategy, n, [](IS s, size_t n) { bench_builder_func_finalize_rt<host::Builder>(s, n); });
+ test_perf("Builder ", "Reuse Only" , strategy, n, [](IS s, size_t n) { bench_builder<host::Builder>(s, n); });
+ test_perf("Builder ", "Func" , strategy, n, [](IS s, size_t n) { bench_builder_func<host::Builder, BuilderOp::kNone>(s, n); });
+ test_perf("Builder ", "Func + Asm" , strategy, n, [](IS s, size_t n) { bench_builder_func<host::Builder, BuilderOp::kFinalize>(s, n); });
+ test_perf("Builder ", "Func + Asm + RT" , strategy, n, [](IS s, size_t n) { bench_builder_func<host::Builder, BuilderOp::kFinalize_RT>(s, n); });
#endif
#if defined(ASMJIT_HAS_HOST_BACKEND) && !defined(ASMJIT_NO_COMPILER)
- test_perf("Compiler" , strategy, n, [](IS s, size_t n) { bench_compiler<host::Compiler>(s, n); });
- test_perf("Compiler + Func" , strategy, n, [](IS s, size_t n) { bench_compiler_func<host::Compiler>(s, n, false); });
- test_perf("Compiler + Func + Finalize" , strategy, n, [](IS s, size_t n) { bench_compiler_func<host::Compiler>(s, n, true); });
-
- test_perf("Compiler + Func + Finalize + RT", strategy, n, [](IS s, size_t n) { bench_compiler_func_rt<host::Compiler>(s, n); });
+ test_perf("Compiler ", "Reuse Only" , strategy, n, [](IS s, size_t n) { bench_compiler<host::Compiler>(s, n); });
+ test_perf("Compiler ", "Func" , strategy, n, [](IS s, size_t n) { bench_compiler_func<host::Compiler, CompilerOp::kNone>(s, n); });
+ test_perf("Compiler ", "Func + RA" , strategy, n, [](IS s, size_t n) { bench_compiler_func<host::Compiler, CompilerOp::kCompile>(s, n); });
+ test_perf("Compiler ", "Func + RA + Asm" , strategy, n, [](IS s, size_t n) { bench_compiler_func<host::Compiler, CompilerOp::kFinalize>(s, n); });
+ test_perf("Compiler ", "Func + RA + Asm + RT", strategy, n, [](IS s, size_t n) { bench_compiler_func<host::Compiler, CompilerOp::kFinalize_RT>(s, n); });
#endif
+
+ printf(frame);
}
int main(int argc, char* argv[]) {
diff --git a/3rdparty/asmjit/testing/bench/asmjit_bench_regalloc.cpp b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_regalloc.cpp
index 32379cd01de..60c52c7c38b 100644
--- a/3rdparty/asmjit/testing/bench/asmjit_bench_regalloc.cpp
+++ b/3rdparty/asmjit/asmjit-testing/bench/asmjit_bench_regalloc.cpp
@@ -13,6 +13,14 @@
#include <asmjit/a64.h>
#endif // !ASMJIT_NO_AARCH64
+#include <asmjit-testing/commons/asmjitutils.h>
+
+#if !defined(ASMJIT_NO_COMPILER)
+ #include <asmjit-testing/commons/cmdline.h>
+ #include <asmjit-testing/commons/performancetimer.h>
+ #include <asmjit-testing/commons/random.h>
+#endif
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -20,14 +28,6 @@
#include <memory>
#include <vector>
-#include "../commons/asmjitutils.h"
-
-#if !defined(ASMJIT_NO_COMPILER)
- #include "../commons/cmdline.h"
- #include "../commons/performancetimer.h"
- #include "../commons/random.h"
-#endif
-
using namespace asmjit;
static void print_app_info() {
diff --git a/3rdparty/asmjit/testing/commons/asmjitutils.h b/3rdparty/asmjit/asmjit-testing/commons/asmjitutils.h
index 87c05c1589c..90d9d010dd2 100644
--- a/3rdparty/asmjit/testing/commons/asmjitutils.h
+++ b/3rdparty/asmjit/asmjit-testing/commons/asmjitutils.h
@@ -146,12 +146,6 @@ static void print_build_options() {
constexpr bool no_foreign = false;
#endif
-#if defined(ASMJIT_NO_DEPRECATED)
- constexpr bool no_deprecated = true;
-#else
- constexpr bool no_deprecated = false;
-#endif
-
#if defined(ASMJIT_NO_ABI_NAMESPACE)
constexpr bool no_abi_namespace = true;
#else
@@ -182,12 +176,6 @@ static void print_build_options() {
constexpr bool no_logging = false;
#endif
-#if defined(ASMJIT_NO_VALIDATION)
- constexpr bool no_validation = true;
-#else
- constexpr bool no_validation = false;
-#endif
-
#if defined(ASMJIT_NO_INTROSPECTION)
constexpr bool no_introspection = true;
#else
@@ -214,8 +202,8 @@ static void print_build_options() {
printf("Build Options:\n");
printf(" BUILD_TYPE : %s\n", asmjit_build_type());
- printf(" ASMJIT_NO_DEPRECATED : %s\n", stringify_build_definition(no_deprecated));
printf(" ASMJIT_NO_ABI_NAMESPACE: %s\n", stringify_build_definition(no_abi_namespace));
+ printf(" ASMJIT_NO_SHM_OPEN : %s\n", stringify_build_definition(no_shm_open));
printf("\n");
printf("Build Backends:\n");
@@ -225,11 +213,9 @@ static void print_build_options() {
printf("\n");
printf("Build Features:\n");
- printf(" ASMJIT_NO_SHM_OPEN : %s\n", stringify_build_definition(no_shm_open));
printf(" ASMJIT_NO_JIT : %s\n", stringify_build_definition(no_jit));
printf(" ASMJIT_NO_TEXT : %s\n", stringify_build_definition(no_text));
printf(" ASMJIT_NO_LOGGING : %s\n", stringify_build_definition(no_logging));
- printf(" ASMJIT_NO_VALIDATION : %s\n", stringify_build_definition(no_validation));
printf(" ASMJIT_NO_INTROSPECTION: %s\n", stringify_build_definition(no_introspection));
printf(" ASMJIT_NO_BUILDER : %s\n", stringify_build_definition(no_builder));
printf(" ASMJIT_NO_COMPILER : %s\n", stringify_build_definition(no_compiler));
diff --git a/3rdparty/asmjit/testing/commons/cmdline.h b/3rdparty/asmjit/asmjit-testing/commons/cmdline.h
index 571fc2058cb..571fc2058cb 100644
--- a/3rdparty/asmjit/testing/commons/cmdline.h
+++ b/3rdparty/asmjit/asmjit-testing/commons/cmdline.h
diff --git a/3rdparty/asmjit/testing/commons/performancetimer.h b/3rdparty/asmjit/asmjit-testing/commons/performancetimer.h
index 980ffabe039..8041498888f 100644
--- a/3rdparty/asmjit/testing/commons/performancetimer.h
+++ b/3rdparty/asmjit/asmjit-testing/commons/performancetimer.h
@@ -6,7 +6,6 @@
#ifndef PERFORMANCETIMER_H_INCLUDED
#define PERFORMANCETIMER_H_INCLUDED
-#include <asmjit/core.h>
#include <chrono>
class PerformanceTimer {
diff --git a/3rdparty/asmjit/testing/commons/random.h b/3rdparty/asmjit/asmjit-testing/commons/random.h
index 27f99f6afc0..27f99f6afc0 100644
--- a/3rdparty/asmjit/testing/commons/random.h
+++ b/3rdparty/asmjit/asmjit-testing/commons/random.h
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_assembler.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler.cpp
index 32dfd1e28ce..6e15697ab89 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_assembler.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler.cpp
@@ -4,15 +4,15 @@
// SPDX-License-Identifier: Zlib
#include <asmjit/core.h>
+
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/commons/cmdline.h>
+#include <asmjit-testing/tests/asmjit_test_assembler.h>
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "asmjit_test_assembler.h"
-
-#include "../commons/asmjitutils.h"
-#include "../commons/cmdline.h"
-
using namespace asmjit;
#if !defined(ASMJIT_NO_X86)
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_assembler.h b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler.h
index e507de54be6..f57b70617e1 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_assembler.h
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler.h
@@ -7,6 +7,7 @@
#define ASMJIT_TEST_ASSEMBLER_H_INCLUDED
#include <asmjit/core.h>
+
#include <stdio.h>
struct TestSettings {
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_assembler_a64.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_a64.cpp
index 7354291963d..15aa84fc59c 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_assembler_a64.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_a64.cpp
@@ -7,12 +7,13 @@
#if !defined(ASMJIT_NO_AARCH64)
#include <asmjit/a64.h>
+
+#include <asmjit-testing/tests/asmjit_test_assembler.h>
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "asmjit_test_assembler.h"
-
using namespace asmjit;
#define TEST_INSTRUCTION(OPCODE, ...) \
@@ -1906,6 +1907,10 @@ static void ASMJIT_NOINLINE test_aarch64_assembler_simd(AssemblerTester<a64::Ass
TEST_INSTRUCTION("01F4034F", fmov(v1.s4(), 0.5));
TEST_INSTRUCTION("01F4004F", fmov(v1.s4(), 2.0));
TEST_INSTRUCTION("01F4036F", fmov(v1.d2(), 0.5));
+ TEST_INSTRUCTION("00F4030F", fmov(v0.s2(), 0.5));
+ TEST_INSTRUCTION("00F4000F", fmov(v0.s2(), 2.0));
+ TEST_INSTRUCTION("00F4034F", fmov(v0.s4(), 0.5));
+ TEST_INSTRUCTION("00F4004F", fmov(v0.s4(), 2.0));
TEST_INSTRUCTION("01F4006F", fmov(v1.d2(), 2.0));
TEST_INSTRUCTION("4190C31F", fmsub(h1, h2, h3, h4));
TEST_INSTRUCTION("4190031F", fmsub(s1, s2, s3, s4));
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_assembler_x64.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_x64.cpp
index 7de00e25b47..0fa2345a08e 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_assembler_x64.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_x64.cpp
@@ -7,12 +7,13 @@
#if !defined(ASMJIT_NO_X86)
#include <asmjit/x86.h>
+
+#include <asmjit-testing/tests/asmjit_test_assembler.h>
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "asmjit_test_assembler.h"
-
using namespace asmjit;
#define TEST_INSTRUCTION(OPCODE, ...) \
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_assembler_x86.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_x86.cpp
index 0362060ea93..c273d17c400 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_assembler_x86.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_assembler_x86.cpp
@@ -7,12 +7,13 @@
#if !defined(ASMJIT_NO_X86)
#include <asmjit/x86.h>
+
+#include <asmjit-testing/tests/asmjit_test_assembler.h>
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "asmjit_test_assembler.h"
-
using namespace asmjit;
#define TEST_INSTRUCTION(OPCODE, ...) \
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_compiler.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler.cpp
index b5940b080c3..13765e0d73b 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_compiler.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler.cpp
@@ -15,11 +15,10 @@
#if !defined(ASMJIT_NO_COMPILER)
-#include "../commons/asmjitutils.h"
-#include "../commons/cmdline.h"
-#include "../commons/performancetimer.h"
-
-#include "asmjit_test_compiler.h"
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/commons/cmdline.h>
+#include <asmjit-testing/commons/performancetimer.h>
+#include <asmjit-testing/tests/asmjit_test_compiler.h>
#if !defined(ASMJIT_NO_X86)
#include <asmjit/x86.h>
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_compiler.h b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler.h
index 51d62a750ca..51d62a750ca 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_compiler.h
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler.h
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_compiler_a64.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler_a64.cpp
index 460999f0f15..d714f7e947c 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_compiler_a64.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler_a64.cpp
@@ -7,12 +7,13 @@
#if !defined(ASMJIT_NO_COMPILER) && !defined(ASMJIT_NO_AARCH64)
#include <asmjit/a64.h>
+
+#include <asmjit-testing/tests/asmjit_test_compiler.h>
+
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "asmjit_test_compiler.h"
-
using namespace asmjit;
// a64::Compiler - A64TestCase
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_compiler_x86.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler_x86.cpp
index 99cc492a771..b586a4bc9f8 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_compiler_x86.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_compiler_x86.cpp
@@ -7,6 +7,10 @@
#if !defined(ASMJIT_NO_X86) && !defined(ASMJIT_NO_COMPILER)
#include <asmjit/x86.h>
+
+#include <asmjit-testing/tests/asmjit_test_misc.h>
+#include <asmjit-testing/tests/asmjit_test_compiler.h>
+
#include <setjmp.h>
#include <stdio.h>
#include <stdlib.h>
@@ -17,9 +21,6 @@
#include <emmintrin.h>
#endif
-#include "asmjit_test_misc.h"
-#include "asmjit_test_compiler.h"
-
#ifdef _MSC_VER
// Interaction between '_setjmp' and C++ object destruction is non-portable.
#pragma warning(disable: 4611)
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_emitters.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_emitters.cpp
index 897436b7434..0386652e4aa 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_emitters.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_emitters.cpp
@@ -8,7 +8,6 @@
#include <string.h>
#include <asmjit/core.h>
-#include "../commons/asmjitutils.h"
#if ASMJIT_ARCH_X86 != 0
#include <asmjit/x86.h>
@@ -18,6 +17,8 @@
#include <asmjit/a64.h>
#endif
+#include <asmjit-testing/commons/asmjitutils.h>
+
using namespace asmjit;
static void print_app_info() noexcept {
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_environment.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_environment.cpp
index a3b86e1eedc..be39d51d503 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_environment.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_environment.cpp
@@ -13,7 +13,7 @@
#include <asmjit/a64.h>
#endif
-#include "../commons/asmjitutils.h"
+#include <asmjit-testing/commons/asmjitutils.h>
using namespace asmjit;
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_instinfo.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_instinfo.cpp
index 8c794c8cafe..a7c2924166a 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_instinfo.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_instinfo.cpp
@@ -11,7 +11,7 @@
#include <stdio.h>
-#include "../commons/asmjitutils.h"
+#include <asmjit-testing/commons/asmjitutils.h>
using namespace asmjit;
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_misc.h b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_misc.h
index 67ea6c7aaf7..67ea6c7aaf7 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_misc.h
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_misc.h
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_runner.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_runner.cpp
index ed831b42ac5..6e02b88cf2b 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_runner.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_runner.cpp
@@ -13,8 +13,8 @@
#include <asmjit/a64.h>
#endif
-#include "broken.h"
-#include "../commons/asmjitutils.h"
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/tests/broken.h>
#if !defined(ASMJIT_NO_COMPILER)
#include <asmjit/core/racfgblock_p.h>
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_unicompiler.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler.cpp
index 5d1fb6c6493..3ceba1af5e4 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_unicompiler.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler.cpp
@@ -5,13 +5,13 @@
#include <asmjit/ujit.h>
+#include <asmjit-testing/commons/asmjitutils.h>
+#include <asmjit-testing/commons/random.h>
+
#include <algorithm>
#include <cmath>
#include <limits>
-#include "../commons/asmjitutils.h"
-#include "../commons/random.h"
-
static void print_app_info() noexcept {
printf("AsmJit UniCompiler Test Suite v%u.%u.%u [Arch=%s] [Mode=%s]\n\n",
unsigned((ASMJIT_LIBRARY_VERSION >> 16) ),
@@ -24,7 +24,7 @@ static void print_app_info() noexcept {
#if !defined(ASMJIT_NO_UJIT) && !defined(ASMJIT_NO_JIT)
-#include "broken.h"
+#include <asmjit-testing/tests/broken.h>
namespace UniCompilerTests {
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_unicompiler_avx2fma.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler_avx2fma.cpp
index ed980394eab..ed980394eab 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_unicompiler_avx2fma.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler_avx2fma.cpp
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_unicompiler_sse2.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler_sse2.cpp
index fa49e6027df..fa49e6027df 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_unicompiler_sse2.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_unicompiler_sse2.cpp
diff --git a/3rdparty/asmjit/testing/tests/asmjit_test_x86_sections.cpp b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_x86_sections.cpp
index 2084ddb637a..2084ddb637a 100644
--- a/3rdparty/asmjit/testing/tests/asmjit_test_x86_sections.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/asmjit_test_x86_sections.cpp
diff --git a/3rdparty/asmjit/testing/tests/broken.cpp b/3rdparty/asmjit/asmjit-testing/tests/broken.cpp
index 34d4db6804b..34d4db6804b 100644
--- a/3rdparty/asmjit/testing/tests/broken.cpp
+++ b/3rdparty/asmjit/asmjit-testing/tests/broken.cpp
diff --git a/3rdparty/asmjit/testing/tests/broken.h b/3rdparty/asmjit/asmjit-testing/tests/broken.h
index cec5b92ac5e..cec5b92ac5e 100644
--- a/3rdparty/asmjit/testing/tests/broken.h
+++ b/3rdparty/asmjit/asmjit-testing/tests/broken.h
diff --git a/3rdparty/asmjit/src/asmjit/a64.h b/3rdparty/asmjit/asmjit/a64.h
index a2fd47b3fb5..01287897a56 100644
--- a/3rdparty/asmjit/src/asmjit/a64.h
+++ b/3rdparty/asmjit/asmjit/a64.h
@@ -39,17 +39,17 @@
//! - \ref arm::Shift - Shift operation and value.
//! - \ref arm::Utils - Utilities that can help during code generation for AArch32 and AArch64.
-#include "./arm.h"
+#include <asmjit/arm.h>
-#include "asmjit-scope-begin.h"
-#include "arm/a64assembler.h"
-#include "arm/a64builder.h"
-#include "arm/a64compiler.h"
-#include "arm/a64emitter.h"
-#include "arm/a64globals.h"
-#include "arm/a64instdb.h"
-#include "arm/a64operand.h"
-#include "asmjit-scope-end.h"
+#include <asmjit/asmjit-scope-begin.h>
+#include <asmjit/arm/a64assembler.h>
+#include <asmjit/arm/a64builder.h>
+#include <asmjit/arm/a64compiler.h>
+#include <asmjit/arm/a64emitter.h>
+#include <asmjit/arm/a64globals.h>
+#include <asmjit/arm/a64instdb.h>
+#include <asmjit/arm/a64operand.h>
+#include <asmjit/asmjit-scope-end.h>
#endif // ASMJIT_A64_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm.h b/3rdparty/asmjit/asmjit/arm.h
index a4cd5fa2814..af5d736c2cc 100644
--- a/3rdparty/asmjit/src/asmjit/arm.h
+++ b/3rdparty/asmjit/asmjit/arm.h
@@ -47,11 +47,11 @@
//! - \ref arm::Shift - Shift operation and value (both AArch32 and AArch64).
//! - \ref arm::Utils - Utilities that can help during code generation for AArch32 and AArch64.
-#include "core.h"
+#include <asmjit/core.h>
-#include "asmjit-scope-begin.h"
-#include "arm/armglobals.h"
-#include "arm/armutils.h"
-#include "asmjit-scope-end.h"
+#include <asmjit/asmjit-scope-begin.h>
+#include <asmjit/arm/armglobals.h>
+#include <asmjit/arm/armutils.h>
+#include <asmjit/asmjit-scope-end.h>
#endif // ASMJIT_ARM_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h b/3rdparty/asmjit/asmjit/arm/a64archtraits_p.h
index 9b279e0fcee..ce1e943b77b 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64archtraits_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64archtraits_p.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
#define ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/misc_p.h"
-#include "../core/type.h"
-#include "../arm/a64globals.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/core/type.h>
+#include <asmjit/arm/a64globals.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp b/3rdparty/asmjit/asmjit/arm/a64assembler.cpp
index a35c1ad3e3b..982da3d3298 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64assembler.cpp
@@ -3,22 +3,21 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64)
-#include "../core/codewriter_p.h"
-#include "../core/cpuinfo.h"
-#include "../core/emitterutils_p.h"
-#include "../core/formatter.h"
-#include "../core/logger.h"
-#include "../core/misc_p.h"
-#include "../core/support.h"
-
-#include "../arm/armformatter_p.h"
-#include "../arm/armutils.h"
-#include "../arm/a64assembler.h"
-#include "../arm/a64emithelper_p.h"
-#include "../arm/a64instdb_p.h"
+#include <asmjit/core/codewriter_p.h>
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/emitterutils_p.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/armformatter_p.h>
+#include <asmjit/arm/armutils.h>
+#include <asmjit/arm/a64assembler.h>
+#include <asmjit/arm/a64emithelper_p.h>
+#include <asmjit/arm/a64instdb_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -835,7 +834,7 @@ Error Assembler::_emit(InstId inst_id, const Operand_& o0, const Operand_& o1, c
goto Failed;
}
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
// Strict validation.
if (has_diagnostic_option(DiagnosticOptions::kValidateAssembler)) {
Operand_ op_array[Globals::kMaxOpCount];
@@ -3581,7 +3580,7 @@ Case_BaseLdurStur:
if (q > 1 || sz > 2)
goto InvalidInstruction;
- static const uint32_t sz_bits_table[3] = { B(11), B(0), B(29) };
+ static const uint32_t sz_bits_table[3] = { B(11), 0, B(29) };
opcode.reset(0b00001111000000001111010000000000);
opcode ^= sz_bits_table[sz];
opcode.add_imm(q, 30);
@@ -5129,11 +5128,12 @@ EmitOp_Rel:
if (rm_rel->is_imm()) {
uint64_t base_address = _code->base_address();
- uint64_t target_offset = rm_rel->as<Imm>().value_as<uint64_t>();
+ uint64_t section_offset = _section->offset();
+ uint64_t target_offset = rm_rel->as<Imm>().value_as<uint64_t>();
size_t code_offset = writer.offset_from(_buffer_data);
- if (base_address == Globals::kNoBaseAddress || _section->section_id() != 0) {
+ if (!EmitterUtils::is_absolute_location(base_address, section_offset)) {
// Create a new RelocEntry as we cannot calculate the offset right now.
RelocEntry* re;
err = _code->new_reloc_entry(Out(re), RelocType::kAbsToRel);
@@ -5148,7 +5148,7 @@ EmitOp_Rel:
goto EmitOp;
}
else {
- uint64_t pc = base_address + code_offset;
+ uint64_t pc = base_address + section_offset + code_offset;
if (offset_format.type() == OffsetType::kAArch64_ADRP) {
pc &= ~uint64_t(4096 - 1);
@@ -5168,7 +5168,7 @@ EmitOp_DispImm:
}
int64_t disp_imm64 = int64_t(offset_value) >> offset_format.imm_discard_lsb();
- if (!Support::is_encodable_offset_64(disp_imm64, offset_format.imm_bit_count())) {
+ if (!EmitterUtils::is_encodable_offset_64(disp_imm64, offset_format.imm_bit_count())) {
goto InvalidDisplacement;
}
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64assembler.h b/3rdparty/asmjit/asmjit/arm/a64assembler.h
index 44afdcb0052..d6723a88d8e 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64assembler.h
+++ b/3rdparty/asmjit/asmjit/arm/a64assembler.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_ARM_A64ASSEMBLER_H_INCLUDED
#define ASMJIT_ARM_A64ASSEMBLER_H_INCLUDED
-#include "../core/assembler.h"
-#include "../arm/a64emitter.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/arm/a64emitter.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64builder.cpp b/3rdparty/asmjit/asmjit/arm/a64builder.cpp
index fa13cc5b1be..470f66f4585 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64builder.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64builder.cpp
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64) && !defined(ASMJIT_NO_BUILDER)
-#include "../arm/a64assembler.h"
-#include "../arm/a64builder.h"
-#include "../arm/a64emithelper_p.h"
+#include <asmjit/arm/a64assembler.h>
+#include <asmjit/arm/a64builder.h>
+#include <asmjit/arm/a64emithelper_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64builder.h b/3rdparty/asmjit/asmjit/arm/a64builder.h
index c1545475eb5..c3708f971f9 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64builder.h
+++ b/3rdparty/asmjit/asmjit/arm/a64builder.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_ARM_A64BUILDER_H_INCLUDED
#define ASMJIT_ARM_A64BUILDER_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_BUILDER
-#include "../core/builder.h"
-#include "../arm/a64emitter.h"
+#include <asmjit/core/builder.h>
+#include <asmjit/arm/a64emitter.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp b/3rdparty/asmjit/asmjit/arm/a64compiler.cpp
index 858e1db8fbb..83157bb524a 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64compiler.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64compiler.cpp
@@ -3,13 +3,13 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64) && !defined(ASMJIT_NO_COMPILER)
-#include "../arm/a64assembler.h"
-#include "../arm/a64compiler.h"
-#include "../arm/a64emithelper_p.h"
-#include "../arm/a64rapass_p.h"
+#include <asmjit/arm/a64assembler.h>
+#include <asmjit/arm/a64compiler.h>
+#include <asmjit/arm/a64emithelper_p.h>
+#include <asmjit/arm/a64rapass_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64compiler.h b/3rdparty/asmjit/asmjit/arm/a64compiler.h
index 1d928c6d23c..8e5c8cdd3b0 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64compiler.h
+++ b/3rdparty/asmjit/asmjit/arm/a64compiler.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_ARM_A64COMPILER_H_INCLUDED
#define ASMJIT_ARM_A64COMPILER_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/compiler.h"
-#include "../core/type.h"
-#include "../arm/a64emitter.h"
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/type.h>
+#include <asmjit/arm/a64emitter.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -63,7 +63,7 @@ public:
//!
//! \note This is a convenience function alias of \ref new_gp32().
template<typename... Args>
- ASMJIT_INLINE_NODEBUG Gp new_gpw(Args&&... args) { return new_reg<Gp>(TypeId::kUIntPtr, std::forward<Args>(args)...); }
+ ASMJIT_INLINE_NODEBUG Gp new_gpw(Args&&... args) { return new_reg<Gp>(TypeId::kUInt32, std::forward<Args>(args)...); }
//! Creates a new 64-bit general purpose register.
//!
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp b/3rdparty/asmjit/asmjit/arm/a64emithelper.cpp
index 26b160279f4..3e4049c0a0d 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64emithelper.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64emithelper.cpp
@@ -3,18 +3,18 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64)
-#include "../core/formatter.h"
-#include "../core/funcargscontext_p.h"
-#include "../core/string.h"
-#include "../core/support.h"
-#include "../core/type.h"
-#include "../arm/a64emithelper_p.h"
-#include "../arm/a64formatter_p.h"
-#include "../arm/a64instapi_p.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/funcargscontext_p.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/a64emithelper_p.h>
+#include <asmjit/arm/a64formatter_p.h>
+#include <asmjit/arm/a64instapi_p.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -471,7 +471,7 @@ void init_emitter_funcs(BaseEmitter* emitter) {
emitter->_funcs.format_instruction = FormatterInternal::format_instruction;
#endif
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
emitter->_funcs.validate = InstInternal::validate;
#endif
}
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h b/3rdparty/asmjit/asmjit/arm/a64emithelper_p.h
index aad0e9021e3..1648a0c9922 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64emithelper_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64emithelper_p.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_ARM_A64EMITHELPER_P_H_INCLUDED
#define ASMJIT_ARM_A64EMITHELPER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
-#include "../core/emithelper_p.h"
-#include "../core/func.h"
-#include "../arm/a64emitter.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/emithelper_p.h>
+#include <asmjit/core/func.h>
+#include <asmjit/arm/a64emitter.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64emitter.h b/3rdparty/asmjit/asmjit/arm/a64emitter.h
index 34fe0922325..b511d04a2a9 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64emitter.h
+++ b/3rdparty/asmjit/asmjit/arm/a64emitter.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_ARM_A64EMITTER_H_INCLUDED
#define ASMJIT_ARM_A64EMITTER_H_INCLUDED
-#include "../core/emitter.h"
-#include "../core/support.h"
-#include "../arm/a64instdb.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/emitter.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/a64instdb.h>
+#include <asmjit/arm/a64operand.h>
// MSVC targeting AArch64 defines a lot of macros without underscores clashing
// with AArch64 instruction names. We have to workaround until it's fixed in SDK.
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp b/3rdparty/asmjit/asmjit/arm/a64formatter.cpp
index baed6613ee7..76fd7eb33ed 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64formatter.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64formatter.cpp
@@ -3,18 +3,18 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64) && !defined(ASMJIT_NO_LOGGING)
-#include "../core/misc_p.h"
-#include "../core/support.h"
-#include "../arm/a64formatter_p.h"
-#include "../arm/a64instapi_p.h"
-#include "../arm/a64instdb_p.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/misc_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/a64formatter_p.h>
+#include <asmjit/arm/a64instapi_p.h>
+#include <asmjit/arm/a64instdb_p.h>
+#include <asmjit/arm/a64operand.h>
#ifndef ASMJIT_NO_COMPILER
- #include "../core/compiler.h"
+ #include <asmjit/core/compiler.h>
#endif
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h b/3rdparty/asmjit/asmjit/arm/a64formatter_p.h
index 9b59f3da20e..39af75a67e9 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64formatter_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64formatter_p.h
@@ -6,14 +6,14 @@
#ifndef ASMJIT_ARM_A64FORMATTER_P_H_INCLUDED
#define ASMJIT_ARM_A64FORMATTER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_LOGGING
-#include "../core/formatter.h"
-#include "../core/span.h"
-#include "../core/string.h"
-#include "../arm/armformatter_p.h"
-#include "../arm/a64globals.h"
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/string.h>
+#include <asmjit/support/span.h>
+#include <asmjit/arm/armformatter_p.h>
+#include <asmjit/arm/a64globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64func.cpp b/3rdparty/asmjit/asmjit/arm/a64func.cpp
index a07321f355e..afa05a8e2d6 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64func.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64func.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64)
-#include "../arm/a64func_p.h"
-#include "../arm/a64operand.h"
+#include <asmjit/arm/a64func_p.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64func_p.h b/3rdparty/asmjit/asmjit/arm/a64func_p.h
index 907acbb7cbf..a322a48845d 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64func_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64func_p.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_ARM_A64FUNC_P_H_INCLUDED
#define ASMJIT_ARM_A64FUNC_P_H_INCLUDED
-#include "../core/func.h"
+#include <asmjit/core/func.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64globals.h b/3rdparty/asmjit/asmjit/arm/a64globals.h
index 5f22c1d0728..9abf069506e 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64globals.h
+++ b/3rdparty/asmjit/asmjit/arm/a64globals.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_ARM_A64GLOBALS_H_INCLUDED
#define ASMJIT_ARM_A64GLOBALS_H_INCLUDED
-#include "../arm/armglobals.h"
+#include <asmjit/arm/armglobals.h>
//! \namespace asmjit::a64
//! \ingroup asmjit_a64
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp b/3rdparty/asmjit/asmjit/arm/a64instapi.cpp
index 21d9bb98a5c..a7f3229c27b 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64instapi.cpp
@@ -3,15 +3,15 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64)
-#include "../core/cpuinfo.h"
-#include "../core/misc_p.h"
-#include "../core/support_p.h"
-#include "../arm/a64instapi_p.h"
-#include "../arm/a64instdb_p.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/support/support_p.h>
+#include <asmjit/arm/a64instapi_p.h>
+#include <asmjit/arm/a64instdb_p.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -50,13 +50,13 @@ InstId string_to_inst_id(const char* s, size_t len) noexcept {
// a64::InstInternal - Validate
// ============================
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
ASMJIT_FAVOR_SIZE Error validate(const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags) noexcept {
// TODO:
Support::maybe_unused(inst, operands, op_count, validation_flags);
return Error::kOk;
}
-#endif // !ASMJIT_NO_VALIDATION
+#endif // !ASMJIT_NO_INTROSPECTION
// a64::InstInternal - QueryRWInfo
// ===============================
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h b/3rdparty/asmjit/asmjit/arm/a64instapi_p.h
index 938d2be0572..90290a81ed0 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64instapi_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64instapi_p.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_ARM_A64INSTAPI_P_H_INCLUDED
#define ASMJIT_ARM_A64INSTAPI_P_H_INCLUDED
-#include "../core/inst.h"
-#include "../core/operand.h"
+#include <asmjit/core/inst.h>
+#include <asmjit/core/operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -22,11 +22,8 @@ Error ASMJIT_CDECL inst_id_to_string(InstId inst_id, InstStringifyOptions option
InstId ASMJIT_CDECL string_to_inst_id(const char* s, size_t len) noexcept;
#endif // !ASMJIT_NO_TEXT
-#ifndef ASMJIT_NO_VALIDATION
-Error ASMJIT_CDECL validate(const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags) noexcept;
-#endif // !ASMJIT_NO_VALIDATION
-
#ifndef ASMJIT_NO_INTROSPECTION
+Error ASMJIT_CDECL validate(const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags) noexcept;
Error ASMJIT_CDECL query_rw_info(const BaseInst& inst, const Operand_* operands, size_t op_count, InstRWInfo* out) noexcept;
Error ASMJIT_CDECL query_features(const BaseInst& inst, const Operand_* operands, size_t op_count, CpuFeatures* out) noexcept;
#endif // !ASMJIT_NO_INTROSPECTION
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp b/3rdparty/asmjit/asmjit/arm/a64instdb.cpp
index 3f33dcbe759..2ebb1eeeb07 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64instdb.cpp
@@ -3,13 +3,13 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64)
-#include "../core/codeholder.h"
-#include "../core/support.h"
-#include "../arm/a64instdb_p.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/codeholder.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/a64instdb_p.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instdb.h b/3rdparty/asmjit/asmjit/arm/a64instdb.h
index ac6ea0732d3..e044aca9a92 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64instdb.h
+++ b/3rdparty/asmjit/asmjit/arm/a64instdb.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_ARM_A64INSTDB_H_INCLUDED
#define ASMJIT_ARM_A64INSTDB_H_INCLUDED
-#include "../arm/a64globals.h"
+#include <asmjit/arm/a64globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64instdb_p.h b/3rdparty/asmjit/asmjit/arm/a64instdb_p.h
index 85f633e8d27..b4b45283aab 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64instdb_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64instdb_p.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_ARM_A64INSTDB_H_P_INCLUDED
#define ASMJIT_ARM_A64INSTDB_H_P_INCLUDED
-#include "../core/codeholder.h"
-#include "../core/instdb_p.h"
-#include "../arm/a64instdb.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/instdb_p.h>
+#include <asmjit/arm/a64instdb.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64operand.cpp b/3rdparty/asmjit/asmjit/arm/a64operand.cpp
index bd48969af9f..f1eddb55e5d 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64operand.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64operand.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64)
-#include "../core/misc_p.h"
-#include "../arm/a64operand.h"
+#include <asmjit/core/misc_p.h>
+#include <asmjit/arm/a64operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64operand.h b/3rdparty/asmjit/asmjit/arm/a64operand.h
index b84333bed41..ba5f98b8fcb 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64operand.h
+++ b/3rdparty/asmjit/asmjit/arm/a64operand.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_ARM_A64OPERAND_H_INCLUDED
#define ASMJIT_ARM_A64OPERAND_H_INCLUDED
-#include "../core/operand.h"
-#include "../arm/armglobals.h"
+#include <asmjit/core/operand.h>
+#include <asmjit/arm/armglobals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -651,24 +651,6 @@ public:
//! \}
};
-//! \name Shift Operation Construction
-//! \{
-
-//! Constructs a `LSL #value` shift (logical shift left).
-static ASMJIT_INLINE_CONSTEXPR Shift lsl(uint32_t value) noexcept { return Shift(ShiftOp::kLSL, value); }
-//! Constructs a `LSR #value` shift (logical shift right).
-static ASMJIT_INLINE_CONSTEXPR Shift lsr(uint32_t value) noexcept { return Shift(ShiftOp::kLSR, value); }
-//! Constructs a `ASR #value` shift (arithmetic shift right).
-static ASMJIT_INLINE_CONSTEXPR Shift asr(uint32_t value) noexcept { return Shift(ShiftOp::kASR, value); }
-//! Constructs a `ROR #value` shift (rotate right).
-static ASMJIT_INLINE_CONSTEXPR Shift ror(uint32_t value) noexcept { return Shift(ShiftOp::kROR, value); }
-//! Constructs a `RRX` shift (rotate with carry by 1).
-static ASMJIT_INLINE_CONSTEXPR Shift rrx() noexcept { return Shift(ShiftOp::kRRX, 0); }
-//! Constructs a `MSL #value` shift (logical shift left filling ones).
-static ASMJIT_INLINE_CONSTEXPR Shift msl(uint32_t value) noexcept { return Shift(ShiftOp::kMSL, value); }
-
-//! \}
-
#ifndef _DOXYGEN
namespace regs {
#endif
@@ -705,11 +687,11 @@ static ASMJIT_INLINE_CONSTEXPR Vec s(uint32_t id) noexcept { return Vec::make_v3
[[nodiscard]]
static ASMJIT_INLINE_CONSTEXPR Vec d(uint32_t id) noexcept { return Vec::make_v64(id); }
-//! Creates a 1282-bit V register operand.
+//! Creates a 128-bit Q register operand.
[[nodiscard]]
static ASMJIT_INLINE_CONSTEXPR Vec q(uint32_t id) noexcept { return Vec::make_v128(id); }
-//! Creates a 1282-bit V register operand.
+//! Creates a 128-bit V register operand.
[[nodiscard]]
static ASMJIT_INLINE_CONSTEXPR Vec v(uint32_t id) noexcept { return Vec::make_v128(id); }
@@ -989,6 +971,30 @@ using namespace regs;
//! \name Shift Operation Construction
//! \{
+//! Constructs a `LSL #value` shift (logical shift left).
+[[nodiscard]]
+static ASMJIT_INLINE_CONSTEXPR Shift lsl(uint32_t value) noexcept { return Shift(ShiftOp::kLSL, value); }
+
+//! Constructs a `LSR #value` shift (logical shift right).
+[[nodiscard]]
+static ASMJIT_INLINE_CONSTEXPR Shift lsr(uint32_t value) noexcept { return Shift(ShiftOp::kLSR, value); }
+
+//! Constructs a `ASR #value` shift (arithmetic shift right).
+[[nodiscard]]
+static ASMJIT_INLINE_CONSTEXPR Shift asr(uint32_t value) noexcept { return Shift(ShiftOp::kASR, value); }
+
+//! Constructs a `ROR #value` shift (rotate right).
+[[nodiscard]]
+static ASMJIT_INLINE_CONSTEXPR Shift ror(uint32_t value) noexcept { return Shift(ShiftOp::kROR, value); }
+
+//! Constructs a `RRX` shift (rotate with carry by 1).
+[[nodiscard]]
+static ASMJIT_INLINE_CONSTEXPR Shift rrx() noexcept { return Shift(ShiftOp::kRRX, 0); }
+
+//! Constructs a `MSL #value` shift (logical shift left filling ones).
+[[nodiscard]]
+static ASMJIT_INLINE_CONSTEXPR Shift msl(uint32_t value) noexcept { return Shift(ShiftOp::kMSL, value); }
+
//! Constructs a `UXTB #value` extend and shift (unsigned byte extend) (AArch64).
[[nodiscard]]
static ASMJIT_INLINE_CONSTEXPR Shift uxtb(uint32_t value) noexcept { return Shift(ShiftOp::kUXTB, value); }
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64rapass.cpp b/3rdparty/asmjit/asmjit/arm/a64rapass.cpp
index 3b684223586..9dbd00488d8 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64rapass.cpp
+++ b/3rdparty/asmjit/asmjit/arm/a64rapass.cpp
@@ -3,19 +3,19 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_AARCH64) && !defined(ASMJIT_NO_COMPILER)
-#include "../core/cpuinfo.h"
-#include "../core/formatter_p.h"
-#include "../core/support.h"
-#include "../core/type.h"
-#include "../arm/a64assembler.h"
-#include "../arm/a64compiler.h"
-#include "../arm/a64emithelper_p.h"
-#include "../arm/a64instapi_p.h"
-#include "../arm/a64instdb_p.h"
-#include "../arm/a64rapass_p.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/a64assembler.h>
+#include <asmjit/arm/a64compiler.h>
+#include <asmjit/arm/a64emithelper_p.h>
+#include <asmjit/arm/a64instapi_p.h>
+#include <asmjit/arm/a64instdb_p.h>
+#include <asmjit/arm/a64rapass_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
@@ -512,10 +512,10 @@ Error RACFGBuilder::on_invoke(InvokeNode* invoke_node, RAInstBuilder& ib) noexce
}
// Setup clobbered registers.
- ib._clobbered[0] = Support::lsb_mask<RegMask>(_pass._phys_reg_count[RegGroup(0)]) & ~fd.preserved_regs(RegGroup(0));
- ib._clobbered[1] = Support::lsb_mask<RegMask>(_pass._phys_reg_count[RegGroup(1)]) & ~fd.preserved_regs(RegGroup(1));
- ib._clobbered[2] = Support::lsb_mask<RegMask>(_pass._phys_reg_count[RegGroup(2)]) & ~fd.preserved_regs(RegGroup(2));
- ib._clobbered[3] = Support::lsb_mask<RegMask>(_pass._phys_reg_count[RegGroup(3)]) & ~fd.preserved_regs(RegGroup(3));
+ ib._clobbered[0] = Support::lsb_mask<RegMask>(_pass._phys_reg_count.get(RegGroup(0))) & ~fd.preserved_regs(RegGroup(0));
+ ib._clobbered[1] = Support::lsb_mask<RegMask>(_pass._phys_reg_count.get(RegGroup(1))) & ~fd.preserved_regs(RegGroup(1));
+ ib._clobbered[2] = Support::lsb_mask<RegMask>(_pass._phys_reg_count.get(RegGroup(2))) & ~fd.preserved_regs(RegGroup(2));
+ ib._clobbered[3] = Support::lsb_mask<RegMask>(_pass._phys_reg_count.get(RegGroup(3))) & ~fd.preserved_regs(RegGroup(3));
return Error::kOk;
}
diff --git a/3rdparty/asmjit/src/asmjit/arm/a64rapass_p.h b/3rdparty/asmjit/asmjit/arm/a64rapass_p.h
index 67149ca1ef0..dfab0c23644 100644
--- a/3rdparty/asmjit/src/asmjit/arm/a64rapass_p.h
+++ b/3rdparty/asmjit/asmjit/arm/a64rapass_p.h
@@ -6,16 +6,16 @@
#ifndef ASMJIT_ARM_A64RAPASS_P_H_INCLUDED
#define ASMJIT_ARM_A64RAPASS_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/compiler.h"
-#include "../core/racfgblock_p.h"
-#include "../core/racfgbuilder_p.h"
-#include "../core/rapass_p.h"
-#include "../arm/a64assembler.h"
-#include "../arm/a64compiler.h"
-#include "../arm/a64emithelper_p.h"
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/racfgblock_p.h>
+#include <asmjit/core/racfgbuilder_p.h>
+#include <asmjit/core/rapass_p.h>
+#include <asmjit/arm/a64assembler.h>
+#include <asmjit/arm/a64compiler.h>
+#include <asmjit/arm/a64emithelper_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(a64)
diff --git a/3rdparty/asmjit/src/asmjit/arm/armformatter.cpp b/3rdparty/asmjit/asmjit/arm/armformatter.cpp
index b6b8a37bcf3..5ad83ae6957 100644
--- a/3rdparty/asmjit/src/asmjit/arm/armformatter.cpp
+++ b/3rdparty/asmjit/asmjit/arm/armformatter.cpp
@@ -3,19 +3,19 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_LOGGING
-#include "../core/formatter_p.h"
-#include "../core/misc_p.h"
-#include "../core/support.h"
-#include "../arm/armformatter_p.h"
-#include "../arm/a64operand.h"
-#include "../arm/a64instapi_p.h"
-#include "../arm/a64instdb_p.h"
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/arm/armformatter_p.h>
+#include <asmjit/arm/a64operand.h>
+#include <asmjit/arm/a64instapi_p.h>
+#include <asmjit/arm/a64instdb_p.h>
#ifndef ASMJIT_NO_COMPILER
- #include "../core/compiler.h"
+ #include <asmjit/core/compiler.h>
#endif
ASMJIT_BEGIN_SUB_NAMESPACE(arm)
diff --git a/3rdparty/asmjit/src/asmjit/arm/armformatter_p.h b/3rdparty/asmjit/asmjit/arm/armformatter_p.h
index 1ba671ddf8f..ae9adfff938 100644
--- a/3rdparty/asmjit/src/asmjit/arm/armformatter_p.h
+++ b/3rdparty/asmjit/asmjit/arm/armformatter_p.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_ARM_ARMFORMATTER_P_H_INCLUDED
#define ASMJIT_ARM_ARMFORMATTER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_LOGGING
-#include "../core/formatter.h"
-#include "../core/string.h"
-#include "../arm/armglobals.h"
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/string.h>
+#include <asmjit/arm/armglobals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(arm)
diff --git a/3rdparty/asmjit/src/asmjit/arm/armglobals.h b/3rdparty/asmjit/asmjit/arm/armglobals.h
index e05ee74c07a..864c4f72cc3 100644
--- a/3rdparty/asmjit/src/asmjit/arm/armglobals.h
+++ b/3rdparty/asmjit/asmjit/arm/armglobals.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_ARM_ARMGLOBALS_H_INCLUDED
#define ASMJIT_ARM_ARMGLOBALS_H_INCLUDED
-#include "../core/archcommons.h"
-#include "../core/inst.h"
+#include <asmjit/core/archcommons.h>
+#include <asmjit/core/inst.h>
//! \namespace asmjit::arm
//! \ingroup asmjit_arm
diff --git a/3rdparty/asmjit/src/asmjit/arm/armutils.h b/3rdparty/asmjit/asmjit/arm/armutils.h
index f23cf454db6..bf0708dd115 100644
--- a/3rdparty/asmjit/src/asmjit/arm/armutils.h
+++ b/3rdparty/asmjit/asmjit/arm/armutils.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_ARM_ARMUTILS_H_INCLUDED
#define ASMJIT_ARM_ARMUTILS_H_INCLUDED
-#include "../core/support.h"
-#include "../arm/armglobals.h"
+#include <asmjit/support/support.h>
+#include <asmjit/arm/armglobals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(arm)
diff --git a/3rdparty/asmjit/src/asmjit/asmjit-scope-begin.h b/3rdparty/asmjit/asmjit/asmjit-scope-begin.h
index 78ba411f1d6..78ba411f1d6 100644
--- a/3rdparty/asmjit/src/asmjit/asmjit-scope-begin.h
+++ b/3rdparty/asmjit/asmjit/asmjit-scope-begin.h
diff --git a/3rdparty/asmjit/src/asmjit/asmjit-scope-end.h b/3rdparty/asmjit/asmjit/asmjit-scope-end.h
index b11ca2239f2..b11ca2239f2 100644
--- a/3rdparty/asmjit/src/asmjit/asmjit-scope-end.h
+++ b/3rdparty/asmjit/asmjit/asmjit-scope-end.h
diff --git a/3rdparty/asmjit/src/asmjit/asmjit.h b/3rdparty/asmjit/asmjit/asmjit.h
index b95350a3b6f..235d826796a 100644
--- a/3rdparty/asmjit/src/asmjit/asmjit.h
+++ b/3rdparty/asmjit/asmjit/asmjit.h
@@ -26,10 +26,10 @@
#pragma message("asmjit/asmjit.h is deprecated! Please use asmjit/[core|x86|a64|host].h instead.")
-#include "./core.h"
+#include <asmjit/core.h>
#ifndef ASMJIT_NO_X86
- #include "./x86.h"
+ #include <asmjit/x86.h>
#endif
#endif // ASMJIT_ASMJIT_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit.natvis b/3rdparty/asmjit/asmjit/asmjit.natvis
index c107c7f7aba..c107c7f7aba 100644
--- a/3rdparty/asmjit/src/asmjit.natvis
+++ b/3rdparty/asmjit/asmjit/asmjit.natvis
diff --git a/3rdparty/asmjit/src/asmjit/core.h b/3rdparty/asmjit/asmjit/core.h
index b1f5074106f..c26ddb83985 100644
--- a/3rdparty/asmjit/src/asmjit/core.h
+++ b/3rdparty/asmjit/asmjit/core.h
@@ -225,10 +225,6 @@ namespace asmjit {
//!
//! \section build_options Build Options
//!
-//! - \ref ASMJIT_NO_DEPRECATED - Disables deprecated API at compile time so it won't be available and the
-//! compilation will fail if there is attempt to use such API. This includes deprecated classes, namespaces,
-//! enumerations, and functions.
-//!
//! - \ref ASMJIT_NO_SHM_OPEN - Disables functionality that uses `shm_open()`.
//!
//! - \ref ASMJIT_NO_ABI_NAMESPACE - Disables inline ABI namespace within `asmjit` namespace. This is only provided
@@ -238,8 +234,8 @@ namespace asmjit {
//!
//! \section build_features Build Features
//!
-//! AsmJit builds by default all supported features, which includes all emitters, logging, instruction validation and
-//! introspection, and JIT memory allocation. Features can be disabled at compile time by using `ASMJIT_NO_...`
+//! AsmJit builds by default all supported features, which includes all emitters, logging, instruction validation
+//! and introspection, and JIT memory allocation. Features can be disabled at compile time by using `ASMJIT_NO_...`
//! definitions.
//! - \ref ASMJIT_NO_JIT - Disables JIT memory management and \ref JitRuntime.
//!
@@ -249,11 +245,9 @@ namespace asmjit {
//!
//! - \ref ASMJIT_NO_LOGGING - Disables \ref Logger and \ref Formatter.
//!
-//! - \ref ASMJIT_NO_VALIDATION - Disables validation API.
-//!
-//! - \ref ASMJIT_NO_INTROSPECTION - Disables instruction introspection API, must be used together with \ref
-//! ASMJIT_NO_COMPILER as \ref asmjit_compiler requires introspection for its liveness analysis and register
-//! allocation.
+//! - \ref ASMJIT_NO_INTROSPECTION - Disables instruction introspection and validation API, must be used together
+//! with \ref ASMJIT_NO_COMPILER as \ref asmjit_compiler requires introspection for its liveness analysis and
+//! register allocation.
//!
//! - \ref ASMJIT_NO_BUILDER - Disables \ref asmjit_builder functionality completely. This implies \ref
//! ASMJIT_NO_COMPILER as \ref asmjit_compiler cannot be used without \ref asmjit_builder.
@@ -1027,7 +1021,7 @@ namespace asmjit {
//! \section code_sections Code & Data Sections
//!
//! AsmJit allows to create multiple sections within the same \ref CodeHolder. A test-case
-//! [asmjit_test_x86_sections.cpp](https://github.com/asmjit/asmjit/blob/master/test/asmjit_test_x86_sections.cpp)
+//! [asmjit_test_x86_sections.cpp](https://github.com/asmjit/asmjit/blob/master/asmjit-testing/tests/asmjit_test_x86_sections.cpp)
//! can be used as a reference point although the following example should also provide a useful insight:
//!
//! ```
@@ -1866,7 +1860,7 @@ namespace asmjit {
//! instruction with operands must be given as some architectures like X86 may require different features for the
//! same instruction based on its operands.
//!
-//! - <a href="https://github.com/asmjit/asmjit/blob/master/test/asmjit_test_instinfo.cpp">asmjit_test_instinfo.cpp</a>
+//! - <a href="https://github.com/asmjit/asmjit/blob/master/asmjit-testing/tests/asmjit_test_instinfo.cpp">asmjit_test_instinfo.cpp</a>
//! can be also used as a reference about accessing instruction information.
//!
//! \section instruction_validation Instruction Validation
@@ -2281,43 +2275,46 @@ namespace asmjit {
} // {asmjit}
-#include "asmjit-scope-begin.h"
-#include "core/api-config.h"
-#include "core/archcommons.h"
-#include "core/archtraits.h"
-#include "core/arena.h"
-#include "core/arenahash.h"
-#include "core/arenalist.h"
-#include "core/arenapool.h"
-#include "core/arenastring.h"
-#include "core/arenatree.h"
-#include "core/arenavector.h"
-#include "core/assembler.h"
-#include "core/builder.h"
-#include "core/codebuffer.h"
-#include "core/codeholder.h"
-#include "core/compiler.h"
-#include "core/constpool.h"
-#include "core/cpuinfo.h"
-#include "core/emitter.h"
-#include "core/environment.h"
-#include "core/errorhandler.h"
-#include "core/fixup.h"
-#include "core/formatter.h"
-#include "core/func.h"
-#include "core/globals.h"
-#include "core/inst.h"
-#include "core/jitallocator.h"
-#include "core/jitruntime.h"
-#include "core/logger.h"
-#include "core/operand.h"
-#include "core/osutils.h"
-#include "core/span.h"
-#include "core/string.h"
-#include "core/support.h"
-#include "core/target.h"
-#include "core/type.h"
-#include "core/virtmem.h"
-#include "asmjit-scope-end.h"
+#include <asmjit/asmjit-scope-begin.h>
+
+#include <asmjit/core/api-config.h>
+#include <asmjit/core/archcommons.h>
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/builder.h>
+#include <asmjit/core/codebuffer.h>
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/constpool.h>
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/emitter.h>
+#include <asmjit/core/environment.h>
+#include <asmjit/core/errorhandler.h>
+#include <asmjit/core/fixup.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/func.h>
+#include <asmjit/core/globals.h>
+#include <asmjit/core/inst.h>
+#include <asmjit/core/jitallocator.h>
+#include <asmjit/core/jitruntime.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/osutils.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/target.h>
+#include <asmjit/core/type.h>
+#include <asmjit/core/virtmem.h>
+
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenahash.h>
+#include <asmjit/support/arenalist.h>
+#include <asmjit/support/arenapool.h>
+#include <asmjit/support/arenastring.h>
+#include <asmjit/support/arenatree.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/span.h>
+#include <asmjit/support/support.h>
+
+#include <asmjit/asmjit-scope-end.h>
#endif // ASMJIT_CORE_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/api-build_p.h b/3rdparty/asmjit/asmjit/core/api-build_p.h
index af56b64c9a9..2de68d25977 100644
--- a/3rdparty/asmjit/src/asmjit/core/api-build_p.h
+++ b/3rdparty/asmjit/asmjit/core/api-build_p.h
@@ -48,7 +48,7 @@
#endif
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#if !defined(ASMJIT_BUILD_DEBUG) && defined(__GNUC__) && !defined(__clang__)
#define ASMJIT_FAVOR_SIZE __attribute__((__optimize__("Os")))
@@ -68,7 +68,7 @@
// Include a unit testing package if this is a `asmjit_test_unit` build.
#if defined(ASMJIT_TEST)
- #include "../../../testing/tests/broken.h"
+ #include <asmjit-testing/tests/broken.h>
#endif
#endif // ASMJIT_CORE_API_BUILD_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/api-config.h b/3rdparty/asmjit/asmjit/core/api-config.h
index 203f9f8b43d..3444cb0739d 100644
--- a/3rdparty/asmjit/src/asmjit/core/api-config.h
+++ b/3rdparty/asmjit/asmjit/core/api-config.h
@@ -16,7 +16,7 @@
#define ASMJIT_LIBRARY_MAKE_VERSION(major, minor, patch) ((major << 16) | (minor << 8) | (patch))
//! AsmJit library version, see \ref ASMJIT_LIBRARY_MAKE_VERSION for a version format reference.
-#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 20, 0)
+#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 21, 0)
//! \def ASMJIT_ABI_NAMESPACE
//!
@@ -27,7 +27,7 @@
//! AsmJit default, which makes it possible to use multiple AsmJit libraries within a single project, totally
//! controlled by users. This is useful especially in cases in which some of such library comes from third party.
#if !defined(ASMJIT_ABI_NAMESPACE)
- #define ASMJIT_ABI_NAMESPACE v1_20
+ #define ASMJIT_ABI_NAMESPACE v1_21
#endif // !ASMJIT_ABI_NAMESPACE
//! \}
@@ -90,12 +90,6 @@
#define ASMJIT_BUILD_RELEASE
#undef ASMJIT_BUILD_RELEASE
-//! \def ASMJIT_NO_DEPRECATED
-//!
-//! Disables deprecated API at compile time (deprecated API won't be available).
-#define ASMJIT_NO_DEPRECATED
-#undef ASMJIT_NO_DEPRECATED
-
//! \def ASMJIT_NO_ABI_NAMESPACE
//!
//! Disables the use of an inline ABI namespace within asmjit namespace (the inline namespace is used as an ABI tag).
@@ -138,12 +132,6 @@
#define ASMJIT_NO_TEXT
#undef ASMJIT_NO_TEXT
-//! \def ASMJIT_NO_VALIDATION
-//!
-//! Disables instruction validation API.
-#define ASMJIT_NO_VALIDATION
-#undef ASMJIT_NO_VALIDATION
-
//! \def ASMJIT_NO_INTROSPECTION
//!
//! Disables instruction introspection API.
diff --git a/3rdparty/asmjit/src/asmjit/core/archcommons.h b/3rdparty/asmjit/asmjit/core/archcommons.h
index 8171eee275a..2ab5ca98771 100644
--- a/3rdparty/asmjit/src/asmjit/core/archcommons.h
+++ b/3rdparty/asmjit/asmjit/core/archcommons.h
@@ -10,7 +10,7 @@
// allows to be created from arm::Shift in a const-expr way, so the arm::Shift must be provided. So this header file
// provides everything architecture-specific that is used by the Core API.
-#include "../core/globals.h"
+#include <asmjit/core/globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(arm)
diff --git a/3rdparty/asmjit/src/asmjit/core/archtraits.cpp b/3rdparty/asmjit/asmjit/core/archtraits.cpp
index 51bf12c4b22..d4b3ec7e2e1 100644
--- a/3rdparty/asmjit/src/asmjit/core/archtraits.cpp
+++ b/3rdparty/asmjit/asmjit/core/archtraits.cpp
@@ -3,17 +3,17 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/archtraits.h"
-#include "../core/environment.h"
-#include "../core/misc_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/environment.h>
+#include <asmjit/core/misc_p.h>
#if !defined(ASMJIT_NO_X86)
- #include "../x86/x86archtraits_p.h"
+ #include <asmjit/x86/x86archtraits_p.h>
#endif
#if !defined(ASMJIT_NO_AARCH64)
- #include "../arm/a64archtraits_p.h"
+ #include <asmjit/arm/a64archtraits_p.h>
#endif
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/archtraits.h b/3rdparty/asmjit/asmjit/core/archtraits.h
index 877f32f6308..fc999753d94 100644
--- a/3rdparty/asmjit/src/asmjit/core/archtraits.h
+++ b/3rdparty/asmjit/asmjit/core/archtraits.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_ARCHTRAITS_H_INCLUDED
#define ASMJIT_CORE_ARCHTRAITS_H_INCLUDED
-#include "../core/operand.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/assembler.cpp b/3rdparty/asmjit/asmjit/core/assembler.cpp
index 3c90945e64d..37f270cc625 100644
--- a/3rdparty/asmjit/src/asmjit/core/assembler.cpp
+++ b/3rdparty/asmjit/asmjit/core/assembler.cpp
@@ -3,14 +3,14 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/assembler.h"
-#include "../core/codewriter_p.h"
-#include "../core/constpool.h"
-#include "../core/emitterutils_p.h"
-#include "../core/formatter.h"
-#include "../core/logger.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/codewriter_p.h>
+#include <asmjit/core/constpool.h>
+#include <asmjit/core/emitterutils_p.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -259,7 +259,7 @@ Error BaseAssembler::embed_label(const Label& label, size_t data_size) {
return report_error(make_error(Error::kNotInitialized));
}
- if (ASMJIT_UNLIKELY(is_label_valid(label))) {
+ if (ASMJIT_UNLIKELY(!is_label_valid(label))) {
return report_error(make_error(Error::kInvalidLabel));
}
diff --git a/3rdparty/asmjit/src/asmjit/core/assembler.h b/3rdparty/asmjit/asmjit/core/assembler.h
index 25cd9b3830d..021b325f9f5 100644
--- a/3rdparty/asmjit/src/asmjit/core/assembler.h
+++ b/3rdparty/asmjit/asmjit/core/assembler.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_ASSEMBLER_H_INCLUDED
#define ASMJIT_CORE_ASSEMBLER_H_INCLUDED
-#include "../core/codeholder.h"
-#include "../core/emitter.h"
-#include "../core/operand.h"
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/emitter.h>
+#include <asmjit/core/operand.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/builder.cpp b/3rdparty/asmjit/asmjit/core/builder.cpp
index acdc0b620be..8fba8a5fd1c 100644
--- a/3rdparty/asmjit/src/asmjit/core/builder.cpp
+++ b/3rdparty/asmjit/asmjit/core/builder.cpp
@@ -3,15 +3,15 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_BUILDER
-#include "../core/builder.h"
-#include "../core/emitterutils_p.h"
-#include "../core/errorhandler.h"
-#include "../core/formatter.h"
-#include "../core/logger.h"
-#include "../core/support.h"
+#include <asmjit/core/builder.h>
+#include <asmjit/core/emitterutils_p.h>
+#include <asmjit/core/errorhandler.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -34,7 +34,7 @@ public:
// BaseBuilder - Utilities
// =======================
-static void BaseBuilder_deletePasses(BaseBuilder* self) noexcept {
+static void BaseBuilder_delete_passes(BaseBuilder* self) noexcept {
for (Pass* pass : self->_passes) {
pass->~Pass();
}
@@ -50,7 +50,7 @@ BaseBuilder::BaseBuilder() noexcept
_pass_arena(64u * 1024u) {}
BaseBuilder::~BaseBuilder() noexcept {
- BaseBuilder_deletePasses(this);
+ BaseBuilder_delete_passes(this);
}
// BaseBuilder - Node Management
@@ -612,7 +612,7 @@ Error BaseBuilder::_emit(InstId inst_id, const Operand_& o0, const Operand_& o1,
return make_error(Error::kNotInitialized);
}
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
// Strict validation.
if (has_diagnostic_option(DiagnosticOptions::kValidateIntermediate)) {
Operand_ op_array[Globals::kMaxOpCount];
@@ -865,7 +865,7 @@ Error BaseBuilder::serialize_to(BaseEmitter* dst) {
// BaseBuilder - Events
// ====================
-static ASMJIT_INLINE void BaseBuilder_clearAll(BaseBuilder* self) noexcept {
+static ASMJIT_INLINE void BaseBuilder_clear_all(BaseBuilder* self) noexcept {
self->_section_nodes.reset();
self->_label_nodes.reset();
@@ -876,7 +876,7 @@ static ASMJIT_INLINE void BaseBuilder_clearAll(BaseBuilder* self) noexcept {
self->_node_list.reset();
}
-static ASMJIT_INLINE Error BaseBuilder_initSection(BaseBuilder* self) noexcept {
+static ASMJIT_INLINE Error BaseBuilder_init_section(BaseBuilder* self) noexcept {
SectionNode* initial_section;
ASMJIT_PROPAGATE(self->section_node_of(Out(initial_section), 0));
@@ -893,7 +893,7 @@ static ASMJIT_INLINE Error BaseBuilder_initSection(BaseBuilder* self) noexcept {
Error BaseBuilder::on_attach(CodeHolder& code) noexcept {
ASMJIT_PROPAGATE(Base::on_attach(code));
- Error err = BaseBuilder_initSection(this);
+ Error err = BaseBuilder_init_section(this);
if (ASMJIT_UNLIKELY(err != Error::kOk)) {
on_detach(code);
}
@@ -901,8 +901,8 @@ Error BaseBuilder::on_attach(CodeHolder& code) noexcept {
}
Error BaseBuilder::on_detach(CodeHolder& code) noexcept {
- BaseBuilder_deletePasses(this);
- BaseBuilder_clearAll(this);
+ BaseBuilder_delete_passes(this);
+ BaseBuilder_clear_all(this);
return Base::on_detach(code);
}
@@ -911,9 +911,9 @@ Error BaseBuilder::on_reinit(CodeHolder& code) noexcept {
// BaseEmitter::on_reinit() never fails.
(void)Base::on_reinit(code);
- BaseBuilder_deletePasses(this);
- BaseBuilder_clearAll(this);
- return BaseBuilder_initSection(this);
+ BaseBuilder_delete_passes(this);
+ BaseBuilder_clear_all(this);
+ return BaseBuilder_init_section(this);
}
// Pass - Construction & Destruction
diff --git a/3rdparty/asmjit/src/asmjit/core/builder.h b/3rdparty/asmjit/asmjit/core/builder.h
index 2e52edd832f..d65929db5b0 100644
--- a/3rdparty/asmjit/src/asmjit/core/builder.h
+++ b/3rdparty/asmjit/asmjit/core/builder.h
@@ -6,20 +6,20 @@
#ifndef ASMJIT_CORE_BUILDER_H_INCLUDED
#define ASMJIT_CORE_BUILDER_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_BUILDER
-#include "../core/arena.h"
-#include "../core/arenavector.h"
-#include "../core/assembler.h"
-#include "../core/codeholder.h"
-#include "../core/constpool.h"
-#include "../core/formatter.h"
-#include "../core/inst.h"
-#include "../core/operand.h"
-#include "../core/string.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/constpool.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/inst.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -1088,7 +1088,7 @@ public:
//! Returns the index of the given operand type `op_type`.
//!
//! \note If the operand type wa found, the value returned represents its index in \ref operands()
- //! array, otherwise \ref Globals::kNPos is returned to signalize that the operand was not found.
+ //! array, otherwise `SIZE_MAX` is returned to signalize that the operand was not found.
[[nodiscard]]
inline size_t index_of_op_type(OperandType op_type) const noexcept {
Span<const Operand> ops = operands();
@@ -1097,7 +1097,7 @@ public:
return i;
}
- return Globals::kNPos;
+ return SIZE_MAX;
}
//! A shortcut that calls `index_of_op_type(OperandType::kMem)`.
diff --git a/3rdparty/asmjit/src/asmjit/core/builder_p.h b/3rdparty/asmjit/asmjit/core/builder_p.h
index cb42e7b370d..131dadb5719 100644
--- a/3rdparty/asmjit/src/asmjit/core/builder_p.h
+++ b/3rdparty/asmjit/asmjit/core/builder_p.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_CORE_BUILDER_P_H_INCLUDED
#define ASMJIT_CORE_BUILDER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_BUILDER
-#include "../core/builder.h"
+#include <asmjit/core/builder.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/codebuffer.h b/3rdparty/asmjit/asmjit/core/codebuffer.h
index eedd06b1c9b..347bfa1e568 100644
--- a/3rdparty/asmjit/src/asmjit/core/codebuffer.h
+++ b/3rdparty/asmjit/asmjit/core/codebuffer.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_CORE_CODEBUFFER_H_INCLUDED
#define ASMJIT_CORE_CODEBUFFER_H_INCLUDED
-#include "../core/globals.h"
-#include "../core/support.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/codeholder.cpp b/3rdparty/asmjit/asmjit/core/codeholder.cpp
index 723cc4aa502..c628bf2f6f6 100644
--- a/3rdparty/asmjit/src/asmjit/core/codeholder.cpp
+++ b/3rdparty/asmjit/asmjit/core/codeholder.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/assembler.h"
-#include "../core/codewriter_p.h"
-#include "../core/logger.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/codewriter_p.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/support/support.h>
#include <algorithm>
#include <tuple>
@@ -32,7 +32,7 @@ static constexpr LabelEntry::ExtraData CodeHolder_make_shared_label_extra_data()
return extra_data;
}
-static constexpr LabelEntry::ExtraData CodeHolder_sharedLabelExtraData = CodeHolder_make_shared_label_extra_data();
+static constexpr LabelEntry::ExtraData CodeHolder_shared_label_extra_data = CodeHolder_make_shared_label_extra_data();
class ResolveFixupIterator {
public:
@@ -86,7 +86,7 @@ static ASMJIT_INLINE void Section_init_name(
section->_name.u32[3] = 0u;
}
-static ASMJIT_INLINE void Section_init_data(Section* section, uint32_t section_id, SectionFlags flags, uint32_t alignment, int order) noexcept {
+static ASMJIT_INLINE void Section_init_data(Section* section, uint32_t section_id, SectionFlags flags, uint32_t alignment, int order, uint64_t offset) noexcept {
section->_section_id = section_id;
// These two fields are not used by sections (see \ref LabelEntry for more details about why).
@@ -96,7 +96,7 @@ static ASMJIT_INLINE void Section_init_data(Section* section, uint32_t section_i
section->assign_flags(flags);
section->_alignment = alignment;
section->_order = order;
- section->_offset = 0;
+ section->_offset = offset;
section->_virtual_size = 0;
}
@@ -123,7 +123,7 @@ static ASMJIT_INLINE Error CodeHolder_init_section_storage(CodeHolder* self) noe
static ASMJIT_INLINE void CodeHolder_add_text_section(CodeHolder* self) noexcept {
Section* text_section = &self->_text_section;
- Section_init_data(text_section, 0u, SectionFlags::kExecutable | SectionFlags::kReadOnly | SectionFlags::kBuiltIn, 0u, 0);
+ Section_init_data(text_section, 0u, SectionFlags::kExecutable | SectionFlags::kReadOnly | SectionFlags::kBuiltIn, 0u, std::numeric_limits<int>::lowest(), 0);
Section_init_name(text_section, '.', 't', 'e', 'x', 't');
self->_sections.append_unchecked(text_section);
@@ -535,7 +535,7 @@ Error CodeHolder::new_section(Out<Section*> section_out, const char* name, size_
alignment = 1u;
}
- Section_init_data(section, section_id, flags, alignment, order);
+ Section_init_data(section, section_id, flags, alignment, order, Globals::kNoSectionOffset);
Section_init_buffer(section);
memcpy(section->_name.str, name, name_size);
@@ -692,7 +692,7 @@ Error CodeHolder::new_label_id(Out<uint32_t> label_id_out) noexcept {
}
else {
label_id_out = label_id;
- _label_entries.append_unchecked(LabelEntry{const_cast<LabelEntry::ExtraData*>(&CodeHolder_sharedLabelExtraData), uint64_t(0)});
+ _label_entries.append_unchecked(LabelEntry{const_cast<LabelEntry::ExtraData*>(&CodeHolder_shared_label_extra_data), uint64_t(0)});
return Error::kOk;
}
}
@@ -710,7 +710,7 @@ Error CodeHolder::new_named_label_id(Out<uint32_t> label_id_out, const char* nam
}
label_id_out = label_id;
- _label_entries.append_unchecked(LabelEntry{const_cast<LabelEntry::ExtraData*>(&CodeHolder_sharedLabelExtraData), uint64_t(0)});
+ _label_entries.append_unchecked(LabelEntry{const_cast<LabelEntry::ExtraData*>(&CodeHolder_shared_label_extra_data), uint64_t(0)});
return Error::kOk;
}
@@ -1099,14 +1099,14 @@ Error CodeHolder::flatten() noexcept {
}
// Now we know that we can assign offsets of all sections properly.
- Section* prev = nullptr;
offset = 0;
+ Section* prev = nullptr;
for (Section* section : _sections_by_order) {
uint64_t real_size = section->real_size();
if (real_size) {
offset = Support::align_up(offset, section->alignment());
}
- section->_offset = offset;
+ section->set_offset(offset);
// Make sure the previous section extends a bit to cover the alignment.
if (prev) {
@@ -1411,22 +1411,40 @@ UNIT(code_holder) {
EXPECT_EQ(strcmp(code.label_entry_of(label_id2).name(), "NamedLabel2"), 0);
EXPECT_EQ(code.label_id_by_name("NamedLabel2"), label_id2);
+ INFO("Verifying .text properties");
+ Section* section_text = code.text_section();
+ EXPECT_TRUE(section_text->has_offset());
+
INFO("Verifying section ordering");
- Section* section1;
- EXPECT_EQ(code.new_section(Out(section1), "high-priority", SIZE_MAX, SectionFlags::kNone, 1, -1), Error::kOk);
- EXPECT_EQ(code.sections()[1], section1);
- EXPECT_EQ(code.sections_by_order()[0], section1);
-
- Section* section0;
- EXPECT_EQ(code.new_section(Out(section0), "higher-priority", SIZE_MAX, SectionFlags::kNone, 1, -2), Error::kOk);
- EXPECT_EQ(code.sections()[2], section0);
- EXPECT_EQ(code.sections_by_order()[0], section0);
- EXPECT_EQ(code.sections_by_order()[1], section1);
-
- Section* section3;
- EXPECT_EQ(code.new_section(Out(section3), "low-priority", SIZE_MAX, SectionFlags::kNone, 1, 2), Error::kOk);
- EXPECT_EQ(code.sections()[3], section3);
- EXPECT_EQ(code.sections_by_order()[3], section3);
+ Section* section_a;
+ EXPECT_EQ(code.new_section(Out(section_a), "high-priority", SIZE_MAX, SectionFlags::kNone, 1, -1), Error::kOk);
+ EXPECT_EQ(code.sections()[0], section_text);
+ EXPECT_EQ(code.sections()[1], section_a);
+ EXPECT_EQ(code.sections_by_order()[0], section_text);
+ EXPECT_EQ(code.sections_by_order()[1], section_a);
+ EXPECT_FALSE(section_a->has_offset());
+
+ Section* section_b;
+ EXPECT_EQ(code.new_section(Out(section_b), "higher-priority", SIZE_MAX, SectionFlags::kNone, 1, -2), Error::kOk);
+ EXPECT_EQ(code.sections()[0], section_text);
+ EXPECT_EQ(code.sections()[1], section_a);
+ EXPECT_EQ(code.sections()[2], section_b);
+ EXPECT_EQ(code.sections_by_order()[0], section_text);
+ EXPECT_EQ(code.sections_by_order()[1], section_b);
+ EXPECT_EQ(code.sections_by_order()[2], section_a);
+ EXPECT_FALSE(section_b->has_offset());
+
+ Section* section_c;
+ EXPECT_EQ(code.new_section(Out(section_c), "low-priority", SIZE_MAX, SectionFlags::kNone, 1, 2), Error::kOk);
+ EXPECT_EQ(code.sections()[0], section_text);
+ EXPECT_EQ(code.sections()[1], section_a);
+ EXPECT_EQ(code.sections()[2], section_b);
+ EXPECT_EQ(code.sections()[3], section_c);
+ EXPECT_EQ(code.sections_by_order()[0], section_text);
+ EXPECT_EQ(code.sections_by_order()[1], section_b);
+ EXPECT_EQ(code.sections_by_order()[2], section_a);
+ EXPECT_EQ(code.sections_by_order()[3], section_c);
+ EXPECT_FALSE(section_c->has_offset());
}
#endif
diff --git a/3rdparty/asmjit/src/asmjit/core/codeholder.h b/3rdparty/asmjit/asmjit/core/codeholder.h
index 4e4605d05b5..f8dcfb7b52a 100644
--- a/3rdparty/asmjit/src/asmjit/core/codeholder.h
+++ b/3rdparty/asmjit/asmjit/core/codeholder.h
@@ -6,21 +6,21 @@
#ifndef ASMJIT_CORE_CODEHOLDER_H_INCLUDED
#define ASMJIT_CORE_CODEHOLDER_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/arena.h"
-#include "../core/arenahash.h"
-#include "../core/arenapool.h"
-#include "../core/arenastring.h"
-#include "../core/arenatree.h"
-#include "../core/arenavector.h"
-#include "../core/codebuffer.h"
-#include "../core/errorhandler.h"
-#include "../core/fixup.h"
-#include "../core/operand.h"
-#include "../core/span.h"
-#include "../core/string.h"
-#include "../core/support.h"
-#include "../core/target.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/codebuffer.h>
+#include <asmjit/core/errorhandler.h>
+#include <asmjit/core/fixup.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/target.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenahash.h>
+#include <asmjit/support/arenapool.h>
+#include <asmjit/support/arenastring.h>
+#include <asmjit/support/arenatree.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/span.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -294,8 +294,15 @@ public:
ASMJIT_INLINE_NODEBUG uint64_t offset() const noexcept { return _offset; }
//! Set the section offset.
+ //!
+ //! \note If the section's offset hasn't been assigned, the returned value would be \ref Globals::kNoSectionOffset.
ASMJIT_INLINE_NODEBUG void set_offset(uint64_t offset) noexcept { _offset = offset; }
+ //! Returns whether the section's offset has been already assigned.
+ //!
+ //! This is true for the first built-in .text section and for all sections that have been flattened.
+ ASMJIT_INLINE_NODEBUG bool has_offset() const noexcept { return _offset != Globals::kNoSectionOffset; }
+
//! Returns the virtual size of the section.
//!
//! Virtual size is initially zero and is never changed by AsmJit. It's normal if virtual size is smaller than
diff --git a/3rdparty/asmjit/src/asmjit/core/codewriter.cpp b/3rdparty/asmjit/asmjit/core/codewriter.cpp
index 8190252a8f5..7befce25d52 100644
--- a/3rdparty/asmjit/src/asmjit/core/codewriter.cpp
+++ b/3rdparty/asmjit/asmjit/core/codewriter.cpp
@@ -3,11 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/codeholder.h"
-#include "../core/codewriter_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/codewriter_p.h>
+#include <asmjit/core/emitterutils_p.h>
-#include "../arm/armutils.h"
+#include <asmjit/arm/armutils.h>
ASMJIT_BEGIN_NAMESPACE
@@ -65,7 +66,7 @@ bool CodeWriterUtils::encode_offset32(uint32_t* dst, int64_t offset64, const Off
}
value = uint32_t(int32_t(offset64));
- if (!Support::is_encodable_offset_32(int32_t(value), bit_count)) {
+ if (!EmitterUtils::is_encodable_offset_32(int32_t(value), bit_count)) {
return false;
}
}
@@ -228,7 +229,7 @@ bool CodeWriterUtils::encode_offset64(uint64_t* dst, int64_t offset64, const Off
offset64 >>= discard_lsb;
}
- if (!Support::is_encodable_offset_64(offset64, bit_count)) {
+ if (!EmitterUtils::is_encodable_offset_64(offset64, bit_count)) {
return false;
}
diff --git a/3rdparty/asmjit/src/asmjit/core/codewriter_p.h b/3rdparty/asmjit/asmjit/core/codewriter_p.h
index 392aea1b2b8..f05154e0665 100644
--- a/3rdparty/asmjit/src/asmjit/core/codewriter_p.h
+++ b/3rdparty/asmjit/asmjit/core/codewriter_p.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_CODEBUFFERWRITER_P_H_INCLUDED
#define ASMJIT_CORE_CODEBUFFERWRITER_P_H_INCLUDED
-#include "../core/assembler.h"
-#include "../core/codebuffer.h"
-#include "../core/support.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/codebuffer.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/compiler.cpp b/3rdparty/asmjit/asmjit/core/compiler.cpp
index 62f79b4aa49..eb12a037d4c 100644
--- a/3rdparty/asmjit/src/asmjit/core/compiler.cpp
+++ b/3rdparty/asmjit/asmjit/core/compiler.cpp
@@ -3,18 +3,18 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/assembler.h"
-#include "../core/builder_p.h"
-#include "../core/compiler.h"
-#include "../core/cpuinfo.h"
-#include "../core/logger.h"
-#include "../core/rapass_p.h"
-#include "../core/rastack_p.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/builder_p.h>
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/core/rapass_p.h>
+#include <asmjit/core/rastack_p.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/compiler.h b/3rdparty/asmjit/asmjit/core/compiler.h
index 6d18bd5ee4a..6e8a424fd3a 100644
--- a/3rdparty/asmjit/src/asmjit/core/compiler.h
+++ b/3rdparty/asmjit/asmjit/core/compiler.h
@@ -6,19 +6,19 @@
#ifndef ASMJIT_CORE_COMPILER_H_INCLUDED
#define ASMJIT_CORE_COMPILER_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/arena.h"
-#include "../core/arenavector.h"
-#include "../core/assembler.h"
-#include "../core/builder.h"
-#include "../core/constpool.h"
-#include "../core/compilerdefs.h"
-#include "../core/func.h"
-#include "../core/inst.h"
-#include "../core/operand.h"
-#include "../core/support.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/builder.h>
+#include <asmjit/core/constpool.h>
+#include <asmjit/core/compilerdefs.h>
+#include <asmjit/core/func.h>
+#include <asmjit/core/inst.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/compilerdefs.h b/3rdparty/asmjit/asmjit/core/compilerdefs.h
index e8e0d0b5946..5c41c89963c 100644
--- a/3rdparty/asmjit/src/asmjit/core/compilerdefs.h
+++ b/3rdparty/asmjit/asmjit/core/compilerdefs.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_COMPILERDEFS_H_INCLUDED
#define ASMJIT_CORE_COMPILERDEFS_H_INCLUDED
-#include "../core/api-config.h"
-#include "../core/arenastring.h"
-#include "../core/operand.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/api-config.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/arenastring.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/constpool.cpp b/3rdparty/asmjit/asmjit/core/constpool.cpp
index d83cfecc82b..c3fe9945348 100644
--- a/3rdparty/asmjit/src/asmjit/core/constpool.cpp
+++ b/3rdparty/asmjit/asmjit/core/constpool.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/constpool.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/constpool.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/constpool.h b/3rdparty/asmjit/asmjit/core/constpool.h
index 36f6e58f6f1..3b90941fadf 100644
--- a/3rdparty/asmjit/src/asmjit/core/constpool.h
+++ b/3rdparty/asmjit/asmjit/core/constpool.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_CONSTPOOL_H_INCLUDED
#define ASMJIT_CORE_CONSTPOOL_H_INCLUDED
-#include "../core/arena.h"
-#include "../core/arenatree.h"
-#include "../core/support.h"
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenatree.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/cpuinfo.cpp b/3rdparty/asmjit/asmjit/core/cpuinfo.cpp
index 2133a7d1a4d..5a9d839faf1 100644
--- a/3rdparty/asmjit/src/asmjit/core/cpuinfo.cpp
+++ b/3rdparty/asmjit/asmjit/core/cpuinfo.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/cpuinfo.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/support/support.h>
#include <atomic>
diff --git a/3rdparty/asmjit/src/asmjit/core/cpuinfo.h b/3rdparty/asmjit/asmjit/core/cpuinfo.h
index 6225a8c5219..921f351f625 100644
--- a/3rdparty/asmjit/src/asmjit/core/cpuinfo.h
+++ b/3rdparty/asmjit/asmjit/core/cpuinfo.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_CPUINFO_H_INCLUDED
#define ASMJIT_CORE_CPUINFO_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/environment.h"
-#include "../core/globals.h"
-#include "../core/string.h"
-#include "../core/support.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/environment.h>
+#include <asmjit/core/globals.h>
+#include <asmjit/core/string.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/emithelper.cpp b/3rdparty/asmjit/asmjit/core/emithelper.cpp
index 1805b710737..8765484c999 100644
--- a/3rdparty/asmjit/src/asmjit/core/emithelper.cpp
+++ b/3rdparty/asmjit/asmjit/core/emithelper.cpp
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/archtraits.h"
-#include "../core/emithelper_p.h"
-#include "../core/formatter.h"
-#include "../core/funcargscontext_p.h"
-#include "../core/radefs_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/emithelper_p.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/funcargscontext_p.h>
+#include <asmjit/core/radefs_p.h>
// Can be used for debugging...
// #define ASMJIT_DUMP_ARGS_ASSIGNMENT
diff --git a/3rdparty/asmjit/src/asmjit/core/emithelper_p.h b/3rdparty/asmjit/asmjit/core/emithelper_p.h
index 8e41566c4ae..2ebaea88f23 100644
--- a/3rdparty/asmjit/src/asmjit/core/emithelper_p.h
+++ b/3rdparty/asmjit/asmjit/core/emithelper_p.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_EMITHELPER_P_H_INCLUDED
#define ASMJIT_CORE_EMITHELPER_P_H_INCLUDED
-#include "../core/emitter.h"
-#include "../core/operand.h"
-#include "../core/type.h"
+#include <asmjit/core/emitter.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/emitter.cpp b/3rdparty/asmjit/asmjit/core/emitter.cpp
index 3a8ea0420b5..9c708cd0338 100644
--- a/3rdparty/asmjit/src/asmjit/core/emitter.cpp
+++ b/3rdparty/asmjit/asmjit/core/emitter.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/emitterutils_p.h"
-#include "../core/errorhandler.h"
-#include "../core/logger.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/emitterutils_p.h>
+#include <asmjit/core/errorhandler.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/emitter.h b/3rdparty/asmjit/asmjit/core/emitter.h
index e6bc2b33445..2c82912d0f9 100644
--- a/3rdparty/asmjit/src/asmjit/core/emitter.h
+++ b/3rdparty/asmjit/asmjit/core/emitter.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_CORE_EMITTER_H_INCLUDED
#define ASMJIT_CORE_EMITTER_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/codeholder.h"
-#include "../core/formatter.h"
-#include "../core/inst.h"
-#include "../core/operand.h"
-#include "../core/type.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/inst.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/emitterutils.cpp b/3rdparty/asmjit/asmjit/core/emitterutils.cpp
index ef9db4de8cb..85e6945c032 100644
--- a/3rdparty/asmjit/src/asmjit/core/emitterutils.cpp
+++ b/3rdparty/asmjit/asmjit/core/emitterutils.cpp
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/assembler.h"
-#include "../core/emitterutils_p.h"
-#include "../core/formatter_p.h"
-#include "../core/logger.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/emitterutils_p.h>
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/emitterutils_p.h b/3rdparty/asmjit/asmjit/core/emitterutils_p.h
index 27513a135e9..8386e887349 100644
--- a/3rdparty/asmjit/src/asmjit/core/emitterutils_p.h
+++ b/3rdparty/asmjit/asmjit/core/emitterutils_p.h
@@ -6,8 +6,10 @@
#ifndef ASMJIT_CORE_EMITTERUTILS_P_H_INCLUDED
#define ASMJIT_CORE_EMITTERUTILS_P_H_INCLUDED
-#include "../core/emitter.h"
-#include "../core/operand.h"
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/emitter.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -21,8 +23,6 @@ class FormatOptions;
//! Utilities used by various emitters, mostly Assembler implementations.
namespace EmitterUtils {
-//! Default paddings used by Emitter utils and Formatter.
-
static constexpr Operand no_ext[3] = { {}, {}, {} };
enum kOpIndex : uint32_t {
@@ -59,6 +59,23 @@ static ASMJIT_INLINE void op_array_from_emit_args(Operand_ dst[Globals::kMaxOpCo
dst[5].copy_from(op_ext[kOp5]);
}
+[[nodiscard]]
+static ASMJIT_INLINE_NODEBUG bool is_encodable_offset_32(int32_t offset, uint32_t num_bits) noexcept {
+ uint32_t n_rev = 32 - num_bits;
+ return Support::sar(Support::shl(offset, n_rev), n_rev) == offset;
+}
+
+[[nodiscard]]
+static ASMJIT_INLINE_NODEBUG bool is_encodable_offset_64(int64_t offset, uint32_t num_bits) noexcept {
+ uint32_t n_rev = 64 - num_bits;
+ return Support::sar(Support::shl(offset, n_rev), n_rev) == offset;
+}
+
+[[nodiscard]]
+static ASMJIT_INLINE_NODEBUG bool is_absolute_location(uint64_t base_address, uint64_t section_offset) noexcept {
+ return base_address != Globals::kNoBaseAddress && section_offset != Globals::kNoSectionOffset;
+}
+
#ifndef ASMJIT_NO_LOGGING
Error finish_formatted_line(String& sb, const FormatOptions& format_options, const uint8_t* bin_data, size_t bin_size, size_t offset_size, size_t imm_size, const char* comment) noexcept;
diff --git a/3rdparty/asmjit/src/asmjit/core/environment.cpp b/3rdparty/asmjit/asmjit/core/environment.cpp
index d5d3d38c986..fcc67f45db7 100644
--- a/3rdparty/asmjit/src/asmjit/core/environment.cpp
+++ b/3rdparty/asmjit/asmjit/core/environment.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/environment.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/environment.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/environment.h b/3rdparty/asmjit/asmjit/core/environment.h
index 4b872223915..84d45f6895d 100644
--- a/3rdparty/asmjit/src/asmjit/core/environment.h
+++ b/3rdparty/asmjit/asmjit/core/environment.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_CORE_ENVIRONMENT_H_INCLUDED
#define ASMJIT_CORE_ENVIRONMENT_H_INCLUDED
-#include "../core/archtraits.h"
+#include <asmjit/core/archtraits.h>
#if defined(__APPLE__)
#include <TargetConditionals.h>
diff --git a/3rdparty/asmjit/src/asmjit/core/errorhandler.cpp b/3rdparty/asmjit/asmjit/core/errorhandler.cpp
index c1f795fd688..1034212a035 100644
--- a/3rdparty/asmjit/src/asmjit/core/errorhandler.cpp
+++ b/3rdparty/asmjit/asmjit/core/errorhandler.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/errorhandler.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/errorhandler.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/errorhandler.h b/3rdparty/asmjit/asmjit/core/errorhandler.h
index 081bab72eab..085aa322b1e 100644
--- a/3rdparty/asmjit/src/asmjit/core/errorhandler.h
+++ b/3rdparty/asmjit/asmjit/core/errorhandler.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_CORE_ERRORHANDLER_H_INCLUDED
#define ASMJIT_CORE_ERRORHANDLER_H_INCLUDED
-#include "../core/globals.h"
+#include <asmjit/core/globals.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/fixup.h b/3rdparty/asmjit/asmjit/core/fixup.h
index 6dcfcf287a3..5533f2a9d91 100644
--- a/3rdparty/asmjit/src/asmjit/core/fixup.h
+++ b/3rdparty/asmjit/asmjit/core/fixup.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_CORE_FIXUP_H_INCLUDED
#define ASMJIT_CORE_FIXUP_H_INCLUDED
-#include "../core/globals.h"
+#include <asmjit/core/globals.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/formatter.cpp b/3rdparty/asmjit/asmjit/core/formatter.cpp
index c7168fee66e..8ad10a20de0 100644
--- a/3rdparty/asmjit/src/asmjit/core/formatter.cpp
+++ b/3rdparty/asmjit/asmjit/core/formatter.cpp
@@ -3,25 +3,25 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_LOGGING
-#include "../core/archtraits.h"
-#include "../core/builder.h"
-#include "../core/codeholder.h"
-#include "../core/compiler.h"
-#include "../core/emitter.h"
-#include "../core/formatter_p.h"
-#include "../core/string.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/builder.h>
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/emitter.h>
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
#if !defined(ASMJIT_NO_X86)
- #include "../x86/x86formatter_p.h"
+ #include <asmjit/x86/x86formatter_p.h>
#endif
#if !defined(ASMJIT_NO_AARCH64)
- #include "../arm/a64formatter_p.h"
+ #include <asmjit/arm/a64formatter_p.h>
#endif
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/formatter.h b/3rdparty/asmjit/asmjit/core/formatter.h
index f9a61200f1f..3d0dccac06d 100644
--- a/3rdparty/asmjit/src/asmjit/core/formatter.h
+++ b/3rdparty/asmjit/asmjit/core/formatter.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_FORMATTER_H_INCLUDED
#define ASMJIT_CORE_FORMATTER_H_INCLUDED
-#include "../core/globals.h"
-#include "../core/inst.h"
-#include "../core/span.h"
-#include "../core/string.h"
-#include "../core/support.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/core/inst.h>
+#include <asmjit/core/string.h>
+#include <asmjit/support/span.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/formatter_p.h b/3rdparty/asmjit/asmjit/core/formatter_p.h
index 77fc0ea3b75..495e8f9dfc5 100644
--- a/3rdparty/asmjit/src/asmjit/core/formatter_p.h
+++ b/3rdparty/asmjit/asmjit/core/formatter_p.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_FORMATTER_P_H_INCLUDED
#define ASMJIT_CORE_FORMATTER_P_H_INCLUDED
-#include "../core/compilerdefs.h"
-#include "../core/formatter.h"
-#include "../core/operand.h"
+#include <asmjit/core/compilerdefs.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/operand.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/func.cpp b/3rdparty/asmjit/asmjit/core/func.cpp
index 07dc8de0472..78c0eeb285b 100644
--- a/3rdparty/asmjit/src/asmjit/core/func.cpp
+++ b/3rdparty/asmjit/asmjit/core/func.cpp
@@ -3,19 +3,19 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/archtraits.h"
-#include "../core/func.h"
-#include "../core/operand.h"
-#include "../core/type.h"
-#include "../core/funcargscontext_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/func.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
+#include <asmjit/core/funcargscontext_p.h>
#if !defined(ASMJIT_NO_X86)
- #include "../x86/x86func_p.h"
+ #include <asmjit/x86/x86func_p.h>
#endif
#if !defined(ASMJIT_NO_AARCH64)
- #include "../arm/a64func_p.h"
+ #include <asmjit/arm/a64func_p.h>
#endif
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/func.h b/3rdparty/asmjit/asmjit/core/func.h
index 51d07fcb7e7..8a954173414 100644
--- a/3rdparty/asmjit/src/asmjit/core/func.h
+++ b/3rdparty/asmjit/asmjit/core/func.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_FUNC_H_INCLUDED
#define ASMJIT_CORE_FUNC_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/environment.h"
-#include "../core/operand.h"
-#include "../core/type.h"
-#include "../core/support.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/environment.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/funcargscontext.cpp b/3rdparty/asmjit/asmjit/core/funcargscontext.cpp
index d7d42f3d26d..c9948bc89e9 100644
--- a/3rdparty/asmjit/src/asmjit/core/funcargscontext.cpp
+++ b/3rdparty/asmjit/asmjit/core/funcargscontext.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/funcargscontext_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/funcargscontext_p.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/funcargscontext_p.h b/3rdparty/asmjit/asmjit/core/funcargscontext_p.h
index e83ebf016af..33c35e5e323 100644
--- a/3rdparty/asmjit/src/asmjit/core/funcargscontext_p.h
+++ b/3rdparty/asmjit/asmjit/core/funcargscontext_p.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_CORE_FUNCARGSCONTEXT_P_H_INCLUDED
#define ASMJIT_CORE_FUNCARGSCONTEXT_P_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/environment.h"
-#include "../core/func.h"
-#include "../core/operand.h"
-#include "../core/support.h"
-#include "../core/raconstraints_p.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/environment.h>
+#include <asmjit/core/func.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/raconstraints_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/globals.cpp b/3rdparty/asmjit/asmjit/core/globals.cpp
index 7ab14538560..ab7a4a50d63 100644
--- a/3rdparty/asmjit/src/asmjit/core/globals.cpp
+++ b/3rdparty/asmjit/asmjit/core/globals.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/globals.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/globals.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/globals.h b/3rdparty/asmjit/asmjit/core/globals.h
index 45d5c99faf7..056ce889cb7 100644
--- a/3rdparty/asmjit/src/asmjit/core/globals.h
+++ b/3rdparty/asmjit/asmjit/core/globals.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_CORE_GLOBALS_H_INCLUDED
#define ASMJIT_CORE_GLOBALS_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
ASMJIT_BEGIN_NAMESPACE
@@ -111,6 +111,9 @@ static constexpr uint32_t kInvalidId = 0xFFFFFFFFu;
//! Invalid base address.
static constexpr uint64_t kNoBaseAddress = ~uint64_t(0);
+//! Invalid section offset.
+static constexpr uint64_t kNoSectionOffset = ~uint64_t(0);
+
//! Number of virtual register groups.
static constexpr uint32_t kNumVirtGroups = 4;
@@ -122,9 +125,6 @@ static const constexpr Init_ Init {};
//! A decorator used to not initialize.
static const constexpr NoInit_ NoInit {};
-//! Invalid index, which means not in a string. Used by API that can match items in spans, vectors, etc...
-static constexpr size_t kNPos = ~size_t(0);
-
template<typename T>
static ASMJIT_INLINE_NODEBUG bool is_npos(const T& index) noexcept { return index == T(~T(0)); }
diff --git a/3rdparty/asmjit/src/asmjit/core/inst.cpp b/3rdparty/asmjit/asmjit/core/inst.cpp
index b538c514f75..3ed202b883d 100644
--- a/3rdparty/asmjit/src/asmjit/core/inst.cpp
+++ b/3rdparty/asmjit/asmjit/core/inst.cpp
@@ -3,16 +3,16 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/archtraits.h"
-#include "../core/inst.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/inst.h>
#if !defined(ASMJIT_NO_X86)
- #include "../x86/x86instapi_p.h"
+ #include <asmjit/x86/x86instapi_p.h>
#endif
#if !defined(ASMJIT_NO_AARCH64)
- #include "../arm/a64instapi_p.h"
+ #include <asmjit/arm/a64instapi_p.h>
#endif
ASMJIT_BEGIN_NAMESPACE
@@ -57,7 +57,7 @@ InstId InstAPI::string_to_inst_id(Arch arch, const char* s, size_t len) noexcept
// InstAPI - Validate
// ==================
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
Error InstAPI::validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags) noexcept {
#if !defined(ASMJIT_NO_X86)
if (Environment::is_family_x86(arch)) {
@@ -78,7 +78,7 @@ Error InstAPI::validate(Arch arch, const BaseInst& inst, const Operand_* operand
return make_error(Error::kInvalidArch);
}
-#endif // !ASMJIT_NO_VALIDATION
+#endif // !ASMJIT_NO_INTROSPECTION
// InstAPI - QueryRWInfo
// =====================
diff --git a/3rdparty/asmjit/src/asmjit/core/inst.h b/3rdparty/asmjit/asmjit/core/inst.h
index 200fcebf450..3968b24319b 100644
--- a/3rdparty/asmjit/src/asmjit/core/inst.h
+++ b/3rdparty/asmjit/asmjit/core/inst.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_CORE_INST_H_INCLUDED
#define ASMJIT_CORE_INST_H_INCLUDED
-#include "../core/cpuinfo.h"
-#include "../core/operand.h"
-#include "../core/string.h"
-#include "../core/support.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/string.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -903,13 +903,11 @@ ASMJIT_API Error inst_id_to_string(Arch arch, InstId inst_id, InstStringifyOptio
ASMJIT_API InstId string_to_inst_id(Arch arch, const char* s, size_t len) noexcept;
#endif // !ASMJIT_NO_TEXT
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
//! Validates the given instruction considering the given `validation_flags`.
[[nodiscard]]
ASMJIT_API Error validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags = ValidationFlags::kNone) noexcept;
-#endif // !ASMJIT_NO_VALIDATION
-#ifndef ASMJIT_NO_INTROSPECTION
//! Gets Read/Write information of the given instruction.
ASMJIT_API Error query_rw_info(Arch arch, const BaseInst& inst, const Operand_* operands, size_t op_count, InstRWInfo* out) noexcept;
diff --git a/3rdparty/asmjit/src/asmjit/core/instdb.cpp b/3rdparty/asmjit/asmjit/core/instdb.cpp
index b16b65c8f64..d085bce5934 100644
--- a/3rdparty/asmjit/src/asmjit/core/instdb.cpp
+++ b/3rdparty/asmjit/asmjit/core/instdb.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/instdb_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/instdb_p.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/instdb_p.h b/3rdparty/asmjit/asmjit/core/instdb_p.h
index 49b9af1efe4..326758fcdc7 100644
--- a/3rdparty/asmjit/src/asmjit/core/instdb_p.h
+++ b/3rdparty/asmjit/asmjit/core/instdb_p.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_CORE_INSTDB_P_H_INCLUDED
#define ASMJIT_CORE_INSTDB_P_H_INCLUDED
-#include "../core/inst.h"
-#include "../core/string.h"
+#include <asmjit/core/inst.h>
+#include <asmjit/core/string.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/jitallocator.cpp b/3rdparty/asmjit/asmjit/core/jitallocator.cpp
index c7f8e98c025..ad75ffd5046 100644
--- a/3rdparty/asmjit/src/asmjit/core/jitallocator.cpp
+++ b/3rdparty/asmjit/asmjit/core/jitallocator.cpp
@@ -3,21 +3,21 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_JIT
-#include "../core/archtraits.h"
-#include "../core/arena.h"
-#include "../core/arenalist.h"
-#include "../core/arenapool.h"
-#include "../core/arenatree.h"
-#include "../core/jitallocator.h"
-#include "../core/osutils_p.h"
-#include "../core/support.h"
-#include "../core/virtmem.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/jitallocator.h>
+#include <asmjit/core/osutils_p.h>
+#include <asmjit/core/virtmem.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenalist.h>
+#include <asmjit/support/arenapool.h>
+#include <asmjit/support/arenatree.h>
+#include <asmjit/support/support.h>
#if defined(ASMJIT_TEST)
-#include "../../../testing/commons/random.h"
+#include <asmjit-testing/commons/random.h>
#endif // ASMJIT_TEST
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/jitallocator.h b/3rdparty/asmjit/asmjit/core/jitallocator.h
index d68f0afe892..d1eb8f6bf64 100644
--- a/3rdparty/asmjit/src/asmjit/core/jitallocator.h
+++ b/3rdparty/asmjit/asmjit/core/jitallocator.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_CORE_JITALLOCATOR_H_INCLUDED
#define ASMJIT_CORE_JITALLOCATOR_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_JIT
-#include "../core/globals.h"
-#include "../core/support.h"
-#include "../core/virtmem.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/core/virtmem.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/jitruntime.cpp b/3rdparty/asmjit/asmjit/core/jitruntime.cpp
index b4ef0778dab..66b35794f90 100644
--- a/3rdparty/asmjit/src/asmjit/core/jitruntime.cpp
+++ b/3rdparty/asmjit/asmjit/core/jitruntime.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_JIT
-#include "../core/cpuinfo.h"
-#include "../core/jitruntime.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/jitruntime.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/jitruntime.h b/3rdparty/asmjit/asmjit/core/jitruntime.h
index b21d940efc4..cf401db6f35 100644
--- a/3rdparty/asmjit/src/asmjit/core/jitruntime.h
+++ b/3rdparty/asmjit/asmjit/core/jitruntime.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_CORE_JITRUNTIME_H_INCLUDED
#define ASMJIT_CORE_JITRUNTIME_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_JIT
-#include "../core/codeholder.h"
-#include "../core/jitallocator.h"
-#include "../core/target.h"
+#include <asmjit/core/codeholder.h>
+#include <asmjit/core/jitallocator.h>
+#include <asmjit/core/target.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/logger.cpp b/3rdparty/asmjit/asmjit/core/logger.cpp
index 705d9512687..df0b435bf90 100644
--- a/3rdparty/asmjit/src/asmjit/core/logger.cpp
+++ b/3rdparty/asmjit/asmjit/core/logger.cpp
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_LOGGING
-#include "../core/logger.h"
-#include "../core/string.h"
-#include "../core/support.h"
+#include <asmjit/core/logger.h>
+#include <asmjit/core/string.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/logger.h b/3rdparty/asmjit/asmjit/core/logger.h
index e2ef4a5e366..0f0e7331b55 100644
--- a/3rdparty/asmjit/src/asmjit/core/logger.h
+++ b/3rdparty/asmjit/asmjit/core/logger.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_LOGGING_H_INCLUDED
#define ASMJIT_CORE_LOGGING_H_INCLUDED
-#include "../core/inst.h"
-#include "../core/string.h"
-#include "../core/formatter.h"
+#include <asmjit/core/inst.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/formatter.h>
#ifndef ASMJIT_NO_LOGGING
diff --git a/3rdparty/asmjit/src/asmjit/core/misc_p.h b/3rdparty/asmjit/asmjit/core/misc_p.h
index 284b9eb493c..3c27e353f93 100644
--- a/3rdparty/asmjit/src/asmjit/core/misc_p.h
+++ b/3rdparty/asmjit/asmjit/core/misc_p.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_CORE_MISC_P_H_INCLUDED
#define ASMJIT_CORE_MISC_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/operand.cpp b/3rdparty/asmjit/asmjit/core/operand.cpp
index a3d0eae61cd..3773f37cd84 100644
--- a/3rdparty/asmjit/src/asmjit/core/operand.cpp
+++ b/3rdparty/asmjit/asmjit/core/operand.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/operand.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/operand.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/operand.h b/3rdparty/asmjit/asmjit/core/operand.h
index 43d23375427..f7e5e2a1314 100644
--- a/3rdparty/asmjit/src/asmjit/core/operand.h
+++ b/3rdparty/asmjit/asmjit/core/operand.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_OPERAND_H_INCLUDED
#define ASMJIT_CORE_OPERAND_H_INCLUDED
-#include "../core/archcommons.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/archcommons.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/osutils.cpp b/3rdparty/asmjit/asmjit/core/osutils.cpp
index 74d26751b22..68b5891710a 100644
--- a/3rdparty/asmjit/src/asmjit/core/osutils.cpp
+++ b/3rdparty/asmjit/asmjit/core/osutils.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/osutils_p.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/osutils_p.h>
+#include <asmjit/support/support.h>
#if !defined(_WIN32)
#include <fcntl.h>
diff --git a/3rdparty/asmjit/src/asmjit/core/osutils.h b/3rdparty/asmjit/asmjit/core/osutils.h
index 8e4fdebee7e..304e6c2152a 100644
--- a/3rdparty/asmjit/src/asmjit/core/osutils.h
+++ b/3rdparty/asmjit/asmjit/core/osutils.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_CORE_OSUTILS_H_INCLUDED
#define ASMJIT_CORE_OSUTILS_H_INCLUDED
-#include "../core/globals.h"
+#include <asmjit/core/globals.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/osutils_p.h b/3rdparty/asmjit/asmjit/core/osutils_p.h
index a752a95ca9c..3501b7a0610 100644
--- a/3rdparty/asmjit/src/asmjit/core/osutils_p.h
+++ b/3rdparty/asmjit/asmjit/core/osutils_p.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_CORE_OSUTILS_P_H_INCLUDED
#define ASMJIT_CORE_OSUTILS_P_H_INCLUDED
-#include "../core/osutils.h"
-#include "../core/string.h"
+#include <asmjit/core/osutils.h>
+#include <asmjit/core/string.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/raassignment_p.h b/3rdparty/asmjit/asmjit/core/raassignment_p.h
index 125d11e7a25..04e330dfa8d 100644
--- a/3rdparty/asmjit/src/asmjit/core/raassignment_p.h
+++ b/3rdparty/asmjit/asmjit/core/raassignment_p.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_RAASSIGNMENT_P_H_INCLUDED
#define ASMJIT_CORE_RAASSIGNMENT_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/radefs_p.h"
-#include "../core/rareg_p.h"
+#include <asmjit/core/radefs_p.h>
+#include <asmjit/core/rareg_p.h>
ASMJIT_BEGIN_NAMESPACE
@@ -142,8 +142,7 @@ public:
_layout.phys_index.build_indexes(phys_count);
_layout.phys_count = phys_count;
- _layout.phys_total = uint32_t(_layout.phys_index[RegGroup::kMaxVirt]) +
- uint32_t(_layout.phys_count[RegGroup::kMaxVirt]) ;
+ _layout.phys_total = _layout.phys_index.get(RegGroup::kMaxVirt) + _layout.phys_count.get(RegGroup::kMaxVirt);
_layout.work_count = uint32_t(work_regs.size());
_layout.work_regs = &work_regs;
}
@@ -337,7 +336,7 @@ public:
memset(_work_to_phys_map, uint8_t(Reg::kIdBad), WorkToPhysMap::size_of(_layout.work_count));
for (RegGroup group : Support::enumerate(RegGroup::kMaxVirt)) {
- uint32_t phys_base_index = _layout.phys_index[group];
+ uint32_t phys_base_index = _layout.phys_index.get(group);
Support::BitWordIterator<RegMask> it(_phys_to_work_map->assigned[group]);
while (it.has_next()) {
@@ -421,7 +420,7 @@ public:
// Verify PhysToWorkMap.
{
for (RegGroup group : Support::enumerate(RegGroup::kMaxVirt)) {
- uint32_t phys_count = _layout.phys_count[group];
+ uint32_t phys_count = _layout.phys_count.get(group);
for (uint32_t phys_id = 0; phys_id < phys_count; phys_id++) {
RAWorkId work_id = _phys_to_work_ids[group][phys_id];
if (work_id != kBadWorkId) {
diff --git a/3rdparty/asmjit/src/asmjit/core/racfgblock_p.h b/3rdparty/asmjit/asmjit/core/racfgblock_p.h
index 3a0ecfe3fce..a66ace2180c 100644
--- a/3rdparty/asmjit/src/asmjit/core/racfgblock_p.h
+++ b/3rdparty/asmjit/asmjit/core/racfgblock_p.h
@@ -6,14 +6,14 @@
#ifndef ASMJIT_CORE_RACFGBLOCK_P_H_INCLUDED
#define ASMJIT_CORE_RACFGBLOCK_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/arenabitset_p.h"
-#include "../core/arenavector.h"
-#include "../core/compilerdefs.h"
-#include "../core/raassignment_p.h"
-#include "../core/support_p.h"
+#include <asmjit/core/compilerdefs.h>
+#include <asmjit/core/raassignment_p.h>
+#include <asmjit/support/arenabitset_p.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/support_p.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/racfgbuilder_p.h b/3rdparty/asmjit/asmjit/core/racfgbuilder_p.h
index 54c5738bc45..ab6524c7246 100644
--- a/3rdparty/asmjit/src/asmjit/core/racfgbuilder_p.h
+++ b/3rdparty/asmjit/asmjit/core/racfgbuilder_p.h
@@ -6,13 +6,13 @@
#ifndef ASMJIT_CORE_RACFGBUILDER_P_H_INCLUDED
#define ASMJIT_CORE_RACFGBUILDER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/formatter.h"
-#include "../core/racfgblock_p.h"
-#include "../core/rainst_p.h"
-#include "../core/rapass_p.h"
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/racfgblock_p.h>
+#include <asmjit/core/rainst_p.h>
+#include <asmjit/core/rapass_p.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/raconstraints_p.h b/3rdparty/asmjit/asmjit/core/raconstraints_p.h
index 39596465f20..67fd87827d7 100644
--- a/3rdparty/asmjit/src/asmjit/core/raconstraints_p.h
+++ b/3rdparty/asmjit/asmjit/core/raconstraints_p.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_CORE_RACONSTRAINTS_P_H_INCLUDED
#define ASMJIT_CORE_RACONSTRAINTS_P_H_INCLUDED
-#include "../core/api-config.h"
-#include "../core/archtraits.h"
-#include "../core/operand.h"
-#include "../core/support.h"
+#include <asmjit/core/api-config.h>
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/radefs_p.h b/3rdparty/asmjit/asmjit/core/radefs_p.h
index 67a14ac0133..bcf232b7aab 100644
--- a/3rdparty/asmjit/src/asmjit/core/radefs_p.h
+++ b/3rdparty/asmjit/asmjit/core/radefs_p.h
@@ -6,19 +6,19 @@
#ifndef ASMJIT_CORE_RADEFS_P_H_INCLUDED
#define ASMJIT_CORE_RADEFS_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/archtraits.h"
-#include "../core/arena.h"
-#include "../core/arenabitset_p.h"
-#include "../core/arenavector.h"
-#include "../core/builder.h"
-#include "../core/compilerdefs.h"
-#include "../core/logger.h"
-#include "../core/operand.h"
-#include "../core/support.h"
-#include "../core/type.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/builder.h>
+#include <asmjit/core/compilerdefs.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenabitset_p.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -133,10 +133,7 @@ struct RARegCount {
//! \name Members
//! \{
- union {
- uint8_t _regs[4];
- uint32_t _packed;
- };
+ uint32_t _counters;
//! \}
@@ -144,7 +141,7 @@ struct RARegCount {
//! \{
//! Resets all counters to zero.
- ASMJIT_INLINE_NODEBUG void reset() noexcept { _packed = 0; }
+ ASMJIT_INLINE_NODEBUG void reset() noexcept { _counters = 0; }
//! \}
@@ -152,22 +149,10 @@ struct RARegCount {
//! \{
[[nodiscard]]
- inline uint8_t& operator[](RegGroup group) noexcept {
- ASMJIT_ASSERT(group <= RegGroup::kMaxVirt);
- return _regs[size_t(group)];
- }
-
- [[nodiscard]]
- inline const uint8_t& operator[](RegGroup group) const noexcept {
- ASMJIT_ASSERT(group <= RegGroup::kMaxVirt);
- return _regs[size_t(group)];
- }
-
- [[nodiscard]]
- ASMJIT_INLINE_NODEBUG bool operator==(const RARegCount& other) const noexcept { return _packed == other._packed; }
+ ASMJIT_INLINE_NODEBUG bool operator==(const RARegCount& other) const noexcept { return _counters == other._counters; }
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG bool operator!=(const RARegCount& other) const noexcept { return _packed != other._packed; }
+ ASMJIT_INLINE_NODEBUG bool operator!=(const RARegCount& other) const noexcept { return _counters != other._counters; }
//! \}
@@ -176,29 +161,29 @@ struct RARegCount {
//! Returns the count of registers by the given register `group`.
[[nodiscard]]
- inline uint32_t get(RegGroup group) const noexcept {
+ ASMJIT_INLINE uint32_t get(RegGroup group) const noexcept {
ASMJIT_ASSERT(group <= RegGroup::kMaxVirt);
- uint32_t shift = Support::byte_shift_in_struct(uint32_t(group));
- return (_packed >> shift) & uint32_t(0xFF);
+ uint32_t shift = uint32_t(group) * 8u;
+ return (_counters >> shift) & 0xFFu;
}
//! Sets the register count by a register `group`.
- inline void set(RegGroup group, uint32_t n) noexcept {
+ ASMJIT_INLINE void set(RegGroup group, uint32_t n) noexcept {
ASMJIT_ASSERT(group <= RegGroup::kMaxVirt);
- ASMJIT_ASSERT(n <= 0xFF);
+ ASMJIT_ASSERT(n <= 0xFFu);
- uint32_t shift = Support::byte_shift_in_struct(uint32_t(group));
- _packed = (_packed & ~uint32_t(0xFF << shift)) + (n << shift);
+ uint32_t shift = uint32_t(group) * 8u;
+ _counters = (_counters & ~uint32_t(0xFFu << shift)) + (n << shift);
}
//! Adds the register count by a register `group`.
- inline void add(RegGroup group, uint32_t n = 1) noexcept {
+ ASMJIT_INLINE void add(RegGroup group, uint32_t n = 1) noexcept {
ASMJIT_ASSERT(group <= RegGroup::kMaxVirt);
- ASMJIT_ASSERT(0xFF - uint32_t(_regs[size_t(group)]) >= n);
+ ASMJIT_ASSERT(get(group) + n <= 0xFFu);
- uint32_t shift = Support::byte_shift_in_struct(uint32_t(group));
- _packed += n << shift;
+ uint32_t shift = uint32_t(group) * 8u;
+ _counters += n << shift;
}
//! \}
@@ -208,13 +193,11 @@ struct RARegCount {
struct RARegIndex : public RARegCount {
//! Build register indexes based on the given `count` of registers.
ASMJIT_INLINE void build_indexes(const RARegCount& count) noexcept {
- uint32_t x = uint32_t(count._regs[0]);
- uint32_t y = uint32_t(count._regs[1]) + x;
- uint32_t z = uint32_t(count._regs[2]) + y;
+ ASMJIT_ASSERT(count.get(RegGroup(0)) + count.get(RegGroup(1)) <= 0xFFu);
+ ASMJIT_ASSERT(count.get(RegGroup(0)) + count.get(RegGroup(1)) + count.get(RegGroup(2)) <= 0xFFu);
- ASMJIT_ASSERT(y <= 0xFF);
- ASMJIT_ASSERT(z <= 0xFF);
- _packed = Support::bytepack32_4x8(0, x, y, z);
+ uint32_t i = count._counters;
+ _counters = (i + (i << 8u) + (i << 16)) << 8u;
}
};
diff --git a/3rdparty/asmjit/src/asmjit/core/rainst_p.h b/3rdparty/asmjit/asmjit/core/rainst_p.h
index 8ea1cd9c9ba..b6f08fd66d2 100644
--- a/3rdparty/asmjit/src/asmjit/core/rainst_p.h
+++ b/3rdparty/asmjit/asmjit/core/rainst_p.h
@@ -6,14 +6,14 @@
#ifndef ASMJIT_CORE_RAINST_P_H_INCLUDED
#define ASMJIT_CORE_RAINST_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/arena.h"
-#include "../core/compilerdefs.h"
-#include "../core/radefs_p.h"
-#include "../core/rareg_p.h"
-#include "../core/support_p.h"
+#include <asmjit/core/compilerdefs.h>
+#include <asmjit/core/radefs_p.h>
+#include <asmjit/core/rareg_p.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/support_p.h>
ASMJIT_BEGIN_NAMESPACE
@@ -123,7 +123,7 @@ public:
//! Returns count of tied registers of a given `group`.
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG uint32_t tied_count(RegGroup group) const noexcept { return _tied_count[group]; }
+ ASMJIT_INLINE_NODEBUG uint32_t tied_count(RegGroup group) const noexcept { return _tied_count.get(group); }
//! Returns `RATiedReg` at the given `index`.
[[nodiscard]]
diff --git a/3rdparty/asmjit/src/asmjit/core/ralocal.cpp b/3rdparty/asmjit/asmjit/core/ralocal.cpp
index 7c395c4c7a4..180aa5517e2 100644
--- a/3rdparty/asmjit/src/asmjit/core/ralocal.cpp
+++ b/3rdparty/asmjit/asmjit/core/ralocal.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/ralocal_p.h"
-#include "../core/support.h"
+#include <asmjit/core/ralocal_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/ralocal_p.h b/3rdparty/asmjit/asmjit/core/ralocal_p.h
index c9405db1b2b..3a8da4db29a 100644
--- a/3rdparty/asmjit/src/asmjit/core/ralocal_p.h
+++ b/3rdparty/asmjit/asmjit/core/ralocal_p.h
@@ -6,14 +6,14 @@
#ifndef ASMJIT_CORE_RALOCAL_P_H_INCLUDED
#define ASMJIT_CORE_RALOCAL_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/raassignment_p.h"
-#include "../core/radefs_p.h"
-#include "../core/rainst_p.h"
-#include "../core/rapass_p.h"
-#include "../core/support.h"
+#include <asmjit/core/raassignment_p.h>
+#include <asmjit/core/radefs_p.h>
+#include <asmjit/core/rainst_p.h>
+#include <asmjit/core/rapass_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -122,7 +122,7 @@ public:
ASMJIT_INLINE_NODEBUG uint32_t tied_count(RegGroup group) const noexcept { return _tied_count.get(group); }
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG bool is_group_used(RegGroup group) const noexcept { return _tied_count[group] != 0; }
+ ASMJIT_INLINE_NODEBUG bool is_group_used(RegGroup group) const noexcept { return _tied_count.get(group) != 0; }
//! \}
diff --git a/3rdparty/asmjit/src/asmjit/core/rapass.cpp b/3rdparty/asmjit/asmjit/core/rapass.cpp
index d7cec90d3b6..fda14d85972 100644
--- a/3rdparty/asmjit/src/asmjit/core/rapass.cpp
+++ b/3rdparty/asmjit/asmjit/core/rapass.cpp
@@ -3,15 +3,15 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/arenavector.h"
-#include "../core/formatter_p.h"
-#include "../core/ralocal_p.h"
-#include "../core/rapass_p.h"
-#include "../core/support_p.h"
-#include "../core/type.h"
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/ralocal_p.h>
+#include <asmjit/core/rapass_p.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/arenavector.h>
+#include <asmjit/support/support_p.h>
ASMJIT_BEGIN_NAMESPACE
@@ -1408,7 +1408,7 @@ Error BaseRAPass::run_global_allocator() noexcept {
ASMJIT_FAVOR_SPEED Error BaseRAPass::init_global_live_spans() noexcept {
for (RegGroup group : Support::enumerate(RegGroup::kMaxVirt)) {
- size_t phys_count = _phys_reg_count[group];
+ size_t phys_count = _phys_reg_count.get(group);
RALiveSpans* live_spans = nullptr;
if (phys_count) {
@@ -1448,7 +1448,7 @@ ASMJIT_FAVOR_SPEED Error BaseRAPass::bin_pack(RegGroup group) noexcept {
uint32_t(group));
#endif
- uint32_t phys_count = _phys_reg_count[group];
+ uint32_t phys_count = _phys_reg_count.get(group);
ArenaVector<RAWorkReg*> work_regs;
ArenaVector<RAConsecutiveReg> consecutive_regs;
@@ -1957,7 +1957,7 @@ Error BaseRAPass::block_entry_assigned(const PhysToWorkMap* phys_to_work_map) no
continue;
}
- uint32_t phys_base_index = _phys_reg_index[group];
+ uint32_t phys_base_index = _phys_reg_index.get(group);
Support::BitWordIterator<RegMask> it(phys_to_work_map->assigned[group]);
while (it.has_next()) {
diff --git a/3rdparty/asmjit/src/asmjit/core/rapass_p.h b/3rdparty/asmjit/asmjit/core/rapass_p.h
index 5d28275bd39..3e9e65c02e0 100644
--- a/3rdparty/asmjit/src/asmjit/core/rapass_p.h
+++ b/3rdparty/asmjit/asmjit/core/rapass_p.h
@@ -6,17 +6,17 @@
#ifndef ASMJIT_CORE_RAPASS_P_H_INCLUDED
#define ASMJIT_CORE_RAPASS_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/compiler.h"
-#include "../core/emithelper_p.h"
-#include "../core/raassignment_p.h"
-#include "../core/racfgblock_p.h"
-#include "../core/radefs_p.h"
-#include "../core/rainst_p.h"
-#include "../core/rastack_p.h"
-#include "../core/support_p.h"
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/emithelper_p.h>
+#include <asmjit/core/raassignment_p.h>
+#include <asmjit/core/racfgblock_p.h>
+#include <asmjit/core/radefs_p.h>
+#include <asmjit/core/rainst_p.h>
+#include <asmjit/core/rastack_p.h>
+#include <asmjit/support/support_p.h>
ASMJIT_BEGIN_NAMESPACE
@@ -350,13 +350,16 @@ public:
block->add_flags(RABlockFlags::kHasFixedRegs);
}
- RATiedReg& dst = ra_inst->_tied_regs[index[group]++];
+ RATiedReg& dst = ra_inst->_tied_regs[index.get(group)];
+ index.add(group);
+
dst = *tied_reg;
dst._flags &= flags_filter;
if (!tied_reg->is_duplicate()) {
dst._use_reg_mask &= ~ib._used[group];
}
+
}
node->set_pass_data<RAInst>(ra_inst);
@@ -486,12 +489,11 @@ public:
inline void _build_phys_index() noexcept {
_phys_reg_index.build_indexes(_phys_reg_count);
- _phys_reg_total = uint32_t(_phys_reg_index[RegGroup::kMaxVirt]) +
- uint32_t(_phys_reg_count[RegGroup::kMaxVirt]) ;
+ _phys_reg_total = _phys_reg_index.get(RegGroup::kMaxVirt) + _phys_reg_count.get(RegGroup::kMaxVirt);
}
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG uint32_t phys_reg_index(RegGroup group) const noexcept { return _phys_reg_index[group]; }
+ ASMJIT_INLINE_NODEBUG uint32_t phys_reg_index(RegGroup group) const noexcept { return _phys_reg_index.get(group); }
[[nodiscard]]
ASMJIT_INLINE_NODEBUG uint32_t phys_reg_total() const noexcept { return _phys_reg_total; }
diff --git a/3rdparty/asmjit/src/asmjit/core/rareg_p.h b/3rdparty/asmjit/asmjit/core/rareg_p.h
index 0f72edc0909..1ca95aee4a5 100644
--- a/3rdparty/asmjit/src/asmjit/core/rareg_p.h
+++ b/3rdparty/asmjit/asmjit/core/rareg_p.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_RAREG_P_H_INCLUDED
#define ASMJIT_CORE_RAREG_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/arenavector.h"
-#include "../core/radefs_p.h"
+#include <asmjit/core/radefs_p.h>
+#include <asmjit/support/arenavector.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/rastack.cpp b/3rdparty/asmjit/asmjit/core/rastack.cpp
index 85a49f9f928..da24e7094f1 100644
--- a/3rdparty/asmjit/src/asmjit/core/rastack.cpp
+++ b/3rdparty/asmjit/asmjit/core/rastack.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/rastack_p.h"
-#include "../core/support.h"
+#include <asmjit/core/rastack_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/rastack_p.h b/3rdparty/asmjit/asmjit/core/rastack_p.h
index 8619a8ded45..0e69588443e 100644
--- a/3rdparty/asmjit/src/asmjit/core/rastack_p.h
+++ b/3rdparty/asmjit/asmjit/core/rastack_p.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_CORE_RASTACK_P_H_INCLUDED
#define ASMJIT_CORE_RASTACK_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/radefs_p.h"
+#include <asmjit/core/radefs_p.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/string.cpp b/3rdparty/asmjit/asmjit/core/string.cpp
index d6c47b9fe74..f5eaaf4b0ac 100644
--- a/3rdparty/asmjit/src/asmjit/core/string.cpp
+++ b/3rdparty/asmjit/asmjit/core/string.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/string.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/string.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/string.h b/3rdparty/asmjit/asmjit/core/string.h
index a6ab533960b..135869a41eb 100644
--- a/3rdparty/asmjit/src/asmjit/core/string.h
+++ b/3rdparty/asmjit/asmjit/core/string.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_CORE_STRING_H_INCLUDED
#define ASMJIT_CORE_STRING_H_INCLUDED
-#include "../core/span.h"
-#include "../core/support.h"
+#include <asmjit/support/span.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/target.cpp b/3rdparty/asmjit/asmjit/core/target.cpp
index 59c6fc7fc02..d54401cda4e 100644
--- a/3rdparty/asmjit/src/asmjit/core/target.cpp
+++ b/3rdparty/asmjit/asmjit/core/target.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/target.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/target.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/target.h b/3rdparty/asmjit/asmjit/core/target.h
index 36cbef1b002..bb5cbe276e7 100644
--- a/3rdparty/asmjit/src/asmjit/core/target.h
+++ b/3rdparty/asmjit/asmjit/core/target.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_CORE_TARGET_H_INCLUDED
#define ASMJIT_CORE_TARGET_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/cpuinfo.h"
-#include "../core/func.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/func.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/type.cpp b/3rdparty/asmjit/asmjit/core/type.cpp
index 4db15a78620..6a0b8a4deb9 100644
--- a/3rdparty/asmjit/src/asmjit/core/type.cpp
+++ b/3rdparty/asmjit/asmjit/core/type.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/misc_p.h"
-#include "../core/type.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/core/type.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/type.h b/3rdparty/asmjit/asmjit/core/type.h
index 9224e29f6d7..518d9f668e4 100644
--- a/3rdparty/asmjit/src/asmjit/core/type.h
+++ b/3rdparty/asmjit/asmjit/core/type.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_CORE_TYPE_H_INCLUDED
#define ASMJIT_CORE_TYPE_H_INCLUDED
-#include "../core/globals.h"
-#include "../core/support.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/virtmem.cpp b/3rdparty/asmjit/asmjit/core/virtmem.cpp
index 3d6ef5be68e..37c7824edf7 100644
--- a/3rdparty/asmjit/src/asmjit/core/virtmem.cpp
+++ b/3rdparty/asmjit/asmjit/core/virtmem.cpp
@@ -3,13 +3,13 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#ifndef ASMJIT_NO_JIT
-#include "../core/osutils_p.h"
-#include "../core/string.h"
-#include "../core/support.h"
-#include "../core/virtmem.h"
+#include <asmjit/core/osutils_p.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/virtmem.h>
+#include <asmjit/support/support.h>
#if !defined(_WIN32)
#include <errno.h>
diff --git a/3rdparty/asmjit/src/asmjit/core/virtmem.h b/3rdparty/asmjit/asmjit/core/virtmem.h
index 846448a246d..c872bf89c83 100644
--- a/3rdparty/asmjit/src/asmjit/core/virtmem.h
+++ b/3rdparty/asmjit/asmjit/core/virtmem.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_CORE_VIRTMEM_H_INCLUDED
#define ASMJIT_CORE_VIRTMEM_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_JIT
-#include "../core/globals.h"
-#include "../core/support.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/host.h b/3rdparty/asmjit/asmjit/host.h
index 87fd71a40c8..36019795340 100644
--- a/3rdparty/asmjit/src/asmjit/host.h
+++ b/3rdparty/asmjit/asmjit/host.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_HOST_H_INCLUDED
#define ASMJIT_HOST_H_INCLUDED
-#include "core.h"
+#include <asmjit/core.h>
// Detect 'X86' or 'X86_64' host architectures.
#if ASMJIT_ARCH_X86 != 0 && !defined(ASMJIT_NO_X86)
-#include "x86.h"
+#include <asmjit/x86.h>
ASMJIT_BEGIN_NAMESPACE
namespace host { using namespace x86; }
@@ -22,7 +22,7 @@ ASMJIT_END_NAMESPACE
// Detect 'AArch64' host architecture.
#if ASMJIT_ARCH_ARM == 64 && !defined(ASMJIT_NO_AARCH64)
-#include "a64.h"
+#include <asmjit/a64.h>
ASMJIT_BEGIN_NAMESPACE
namespace host { using namespace a64; }
diff --git a/3rdparty/asmjit/src/asmjit/core/arena.cpp b/3rdparty/asmjit/asmjit/support/arena.cpp
index 12810d77a58..c9329cc6bdf 100644
--- a/3rdparty/asmjit/src/asmjit/core/arena.cpp
+++ b/3rdparty/asmjit/asmjit/support/arena.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/support.h"
-#include "../core/arena.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/arena.h b/3rdparty/asmjit/asmjit/support/arena.h
index 08e1ce74830..ec4a63a645a 100644
--- a/3rdparty/asmjit/src/asmjit/core/arena.h
+++ b/3rdparty/asmjit/asmjit/support/arena.h
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENA_H_INCLUDED
-#define ASMJIT_CORE_ARENA_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENA_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENA_H_INCLUDED
-#include "../core/support.h"
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -495,4 +495,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENA_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENA_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenabitset.cpp b/3rdparty/asmjit/asmjit/support/arenabitset.cpp
index 8aaa230ea8d..5bc11c83c10 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenabitset.cpp
+++ b/3rdparty/asmjit/asmjit/support/arenabitset.cpp
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/support.h"
-#include "../core/arena.h"
-#include "../core/arenabitset_p.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenabitset_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/arenabitset_p.h b/3rdparty/asmjit/asmjit/support/arenabitset_p.h
index 1061194e215..9b3dcd7cdd9 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenabitset_p.h
+++ b/3rdparty/asmjit/asmjit/support/arenabitset_p.h
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENABITSET_P_H_INCLUDED
-#define ASMJIT_CORE_ARENABITSET_P_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENABITSET_P_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENABITSET_P_H_INCLUDED
-#include "../core/arena.h"
-#include "../core/span.h"
-#include "../core/support.h"
+#include <asmjit/support/arena.h>
+#include <asmjit/support/span.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -433,4 +433,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENABITSET_P_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENABITSET_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenahash.cpp b/3rdparty/asmjit/asmjit/support/arenahash.cpp
index be32149eed4..e9c3736359e 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenahash.cpp
+++ b/3rdparty/asmjit/asmjit/support/arenahash.cpp
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/support.h"
-#include "../core/arena.h"
-#include "../core/arenahash.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenahash.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/arenahash.h b/3rdparty/asmjit/asmjit/support/arenahash.h
index 436123adde8..c6481ab0098 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenahash.h
+++ b/3rdparty/asmjit/asmjit/support/arenahash.h
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENAHASH_H_INCLUDED
-#define ASMJIT_CORE_ARENAHASH_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENAHASH_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENAHASH_H_INCLUDED
-#include "../core/arena.h"
+#include <asmjit/support/arena.h>
ASMJIT_BEGIN_NAMESPACE
@@ -195,4 +195,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENAHASH_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENAHASH_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenalist.cpp b/3rdparty/asmjit/asmjit/support/arenalist.cpp
index 97cd8924aa9..2fbed36ce0d 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenalist.cpp
+++ b/3rdparty/asmjit/asmjit/support/arenalist.cpp
@@ -3,9 +3,9 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/arena.h"
-#include "../core/arenalist.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenalist.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/arenalist.h b/3rdparty/asmjit/asmjit/support/arenalist.h
index efe194692bc..84d6107a026 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenalist.h
+++ b/3rdparty/asmjit/asmjit/support/arenalist.h
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENALIST_H_INCLUDED
-#define ASMJIT_CORE_ARENALIST_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENALIST_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENALIST_H_INCLUDED
-#include "../core/support.h"
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -218,4 +218,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENALIST_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENALIST_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenapool.h b/3rdparty/asmjit/asmjit/support/arenapool.h
index cb179c3ede2..398d3f03783 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenapool.h
+++ b/3rdparty/asmjit/asmjit/support/arenapool.h
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENAPOOL_H_INCLUDED
-#define ASMJIT_CORE_ARENAPOOL_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENAPOOL_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENAPOOL_H_INCLUDED
-#include "../core/support.h"
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -63,4 +63,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENAPOOL_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENAPOOL_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenastring.h b/3rdparty/asmjit/asmjit/support/arenastring.h
index bc90d6d715e..d424eb80e3c 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenastring.h
+++ b/3rdparty/asmjit/asmjit/support/arenastring.h
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENASTRING_H_INCLUDED
-#define ASMJIT_CORE_ARENASTRING_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENASTRING_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENASTRING_H_INCLUDED
-#include "../core/globals.h"
-#include "../core/arena.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/support/arena.h>
ASMJIT_BEGIN_NAMESPACE
@@ -120,4 +120,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENASTRING_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENASTRING_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenatree.cpp b/3rdparty/asmjit/asmjit/support/arenatree.cpp
index b37d182456c..90f24ff4b4d 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenatree.cpp
+++ b/3rdparty/asmjit/asmjit/support/arenatree.cpp
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/arena.h"
-#include "../core/arenatree.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenatree.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
diff --git a/3rdparty/asmjit/src/asmjit/core/arenatree.h b/3rdparty/asmjit/asmjit/support/arenatree.h
index a9a4d1f6c73..6cd5dba8423 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenatree.h
+++ b/3rdparty/asmjit/asmjit/support/arenatree.h
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENATREE_H_INCLUDED
-#define ASMJIT_CORE_ARENATREE_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENATREE_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENATREE_H_INCLUDED
-#include "../core/support.h"
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -404,4 +404,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENATREE_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENATREE_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/arenavector.cpp b/3rdparty/asmjit/asmjit/support/arenavector.cpp
index 4eb1a19261b..70d02229faf 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenavector.cpp
+++ b/3rdparty/asmjit/asmjit/support/arenavector.cpp
@@ -3,13 +3,36 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/support.h"
-#include "../core/arena.h"
-#include "../core/arenavector.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/support/arena.h>
+#include <asmjit/support/arenavector.h>
ASMJIT_BEGIN_NAMESPACE
+// ArenaVector - Item Size Helpers
+// ===============================
+
+template<typename ResultType, bool IsPowerOf2>
+static ASMJIT_INLINE_NODEBUG ResultType byte_size_from_item_count(size_t item_count, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
+ if constexpr (IsPowerOf2) {
+ return ResultType(item_count) << item_size.n;
+ }
+ else {
+ return ResultType(item_count) * item_size.n;
+ }
+}
+
+template<bool IsPowerOf2>
+static ASMJIT_INLINE_NODEBUG size_t item_count_from_byte_size(size_t byte_size, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
+ if constexpr (IsPowerOf2) {
+ return byte_size >> item_size.n;
+ }
+ else {
+ return byte_size / item_size.n;
+ }
+}
+
// ArenaVector - Memory Management
// ===============================
@@ -49,8 +72,8 @@ static ASMJIT_INLINE size_t ArenaVector_expand_byte_size(size_t byte_size) noexc
}
}
-template<typename ItemSize>
-static ASMJIT_NOINLINE Error ArenaVector_reserve_with_byte_size(ArenaVectorBase& self, Arena& arena, size_t byte_size, ItemSize item_size) noexcept {
+template<bool IsPowerOf2>
+static ASMJIT_NOINLINE Error ArenaVector_reserve_with_byte_size(ArenaVectorBase& self, Arena& arena, size_t byte_size, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
size_t allocated_size;
uint8_t* new_data = static_cast<uint8_t*>(arena.alloc_reusable(byte_size, Out(allocated_size)));
@@ -58,14 +81,14 @@ static ASMJIT_NOINLINE Error ArenaVector_reserve_with_byte_size(ArenaVectorBase&
return make_error(Error::kOutOfMemory);
}
- size_t allocated_capacity = Support::item_count_from_byte_size(allocated_size, item_size);
+ size_t allocated_capacity = item_count_from_byte_size(allocated_size, item_size);
void* old_data = self._data;
uint32_t size = self._size;
if (old_data) {
- memcpy(new_data, old_data, Support::byte_size_from_item_count(size, item_size));
- arena.free_reusable(old_data, Support::byte_size_from_item_count(self._capacity, item_size));
+ memcpy(new_data, old_data, byte_size_from_item_count<size_t>(size, item_size));
+ arena.free_reusable(old_data, byte_size_from_item_count<size_t>(self._capacity, item_size));
}
self._data = new_data;
@@ -97,11 +120,11 @@ static ASMJIT_INLINE bool ArenaVector_check_byte_size(uint64_t byte_size) noexce
}
}
-template<typename ItemSize>
-static ASMJIT_INLINE Error ArenaVector_reserve_fit(ArenaVectorBase& self, Arena& arena, size_t item_count, ItemSize item_size) noexcept {
+template<bool IsPowerOf2>
+static ASMJIT_INLINE Error ArenaVector_reserve_fit(ArenaVectorBase& self, Arena& arena, size_t item_count, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
size_t capacity = self._capacity;
size_t capacity_masked = capacity | Support::bool_as_mask<size_t>(!ArenaVector_is_valid_size(item_count));
- uint64_t byte_size = Support::byte_size_from_item_count<uint64_t>(item_count, item_size);
+ uint64_t byte_size = byte_size_from_item_count<uint64_t>(item_count, item_size);
if (ASMJIT_UNLIKELY(Support::bool_or(capacity_masked >= item_count, !ArenaVector_check_byte_size(byte_size)))) {
return capacity >= item_count ? Error::kOk : make_error(Error::kOutOfMemory);
@@ -110,11 +133,11 @@ static ASMJIT_INLINE Error ArenaVector_reserve_fit(ArenaVectorBase& self, Arena&
return ArenaVector_reserve_with_byte_size(self, arena, size_t(byte_size), item_size);
}
-template<typename ItemSize>
-static ASMJIT_INLINE Error ArenaVector_reserve_grow(ArenaVectorBase& self, Arena& arena, size_t item_count, ItemSize item_size) noexcept {
+template<bool IsPowerOf2>
+static ASMJIT_INLINE Error ArenaVector_reserve_grow(ArenaVectorBase& self, Arena& arena, size_t item_count, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
size_t capacity = self._capacity;
size_t capacity_masked = capacity | Support::bool_as_mask<size_t>(!ArenaVector_is_valid_size(item_count));
- uint64_t byte_size = Support::byte_size_from_item_count<uint64_t>(item_count, item_size);
+ uint64_t byte_size = byte_size_from_item_count<uint64_t>(item_count, item_size);
if (ASMJIT_UNLIKELY(Support::bool_or(capacity_masked >= item_count, !ArenaVector_check_byte_size(byte_size)))) {
return capacity >= item_count ? Error::kOk : make_error(Error::kOutOfMemory);
@@ -124,8 +147,8 @@ static ASMJIT_INLINE Error ArenaVector_reserve_grow(ArenaVectorBase& self, Arena
return ArenaVector_reserve_with_byte_size(self, arena, expanded_byte_size, item_size);
}
-template<typename ItemSize>
-static ASMJIT_INLINE Error ArenaVector_grow(ArenaVectorBase& self, Arena& arena, size_t n, ItemSize item_size) noexcept {
+template<bool IsPowerOf2>
+static ASMJIT_INLINE Error ArenaVector_grow(ArenaVectorBase& self, Arena& arena, size_t n, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
Support::FastUInt8 of {};
size_t after = Support::add_overflow<size_t>(self._size, n, &of);
@@ -136,8 +159,8 @@ static ASMJIT_INLINE Error ArenaVector_grow(ArenaVectorBase& self, Arena& arena,
return ArenaVector_reserve_grow(self, arena, after, item_size);
}
-template<typename ItemSize>
-static ASMJIT_INLINE Error ArenaVector_resize_fit(ArenaVectorBase& self, Arena& arena, size_t n, ItemSize item_size) noexcept {
+template<bool IsPowerOf2>
+static ASMJIT_INLINE Error ArenaVector_resize_fit(ArenaVectorBase& self, Arena& arena, size_t n, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
size_t size = self._size;
size_t capacity = self._capacity;
@@ -146,15 +169,15 @@ static ASMJIT_INLINE Error ArenaVector_resize_fit(ArenaVectorBase& self, Arena&
}
if (size < n) {
- memset(static_cast<uint8_t*>(self._data) + Support::byte_size_from_item_count(size, item_size), 0, Support::byte_size_from_item_count(n - size, item_size));
+ memset(static_cast<uint8_t*>(self._data) + byte_size_from_item_count<size_t>(size, item_size), 0, byte_size_from_item_count<size_t>(n - size, item_size));
}
self._size = uint32_t(n);
return Error::kOk;
}
-template<typename ItemSize>
-static ASMJIT_INLINE Error ArenaVector_resize_grow(ArenaVectorBase& self, Arena& arena, size_t n, ItemSize item_size) noexcept {
+template<bool IsPowerOf2>
+static ASMJIT_INLINE Error ArenaVector_resize_grow(ArenaVectorBase& self, Arena& arena, size_t n, ArenaVectorBase::ItemSize<IsPowerOf2> item_size) noexcept {
size_t size = self._size;
size_t capacity = self._capacity;
@@ -163,7 +186,7 @@ static ASMJIT_INLINE Error ArenaVector_resize_grow(ArenaVectorBase& self, Arena&
}
if (size < n) {
- memset(static_cast<uint8_t*>(self._data) + Support::byte_size_from_item_count(size, item_size), 0, Support::byte_size_from_item_count(n - size, item_size));
+ memset(static_cast<uint8_t*>(self._data) + byte_size_from_item_count<size_t>(size, item_size), 0, byte_size_from_item_count<size_t>(n - size, item_size));
}
self._size = uint32_t(n);
@@ -171,44 +194,44 @@ static ASMJIT_INLINE Error ArenaVector_resize_grow(ArenaVectorBase& self, Arena&
}
// Public API wrappers:
-Error ArenaVectorBase::_reserve_fit(Arena& arena, size_t n, Support::ByteSize item_size) noexcept {
- return ArenaVector_reserve_fit<Support::ByteSize>(*this, arena, n, item_size);
+Error ArenaVectorBase::_reserve_fit(Arena& arena, size_t n, ItemSize<false> item_size) noexcept {
+ return ArenaVector_reserve_fit(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_reserve_fit(Arena& arena, size_t n, Support::Log2Size item_size) noexcept {
- return ArenaVector_reserve_fit<Support::Log2Size>(*this, arena, n, item_size);
+Error ArenaVectorBase::_reserve_fit(Arena& arena, size_t n, ItemSize<true> item_size) noexcept {
+ return ArenaVector_reserve_fit(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_reserve_grow(Arena& arena, size_t n, Support::ByteSize item_size) noexcept {
- return ArenaVector_reserve_grow<Support::ByteSize>(*this, arena, n, item_size);
+Error ArenaVectorBase::_reserve_grow(Arena& arena, size_t n, ItemSize<false> item_size) noexcept {
+ return ArenaVector_reserve_grow(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_reserve_grow(Arena& arena, size_t n, Support::Log2Size item_size) noexcept {
- return ArenaVector_reserve_grow<Support::Log2Size>(*this, arena, n, item_size);
+Error ArenaVectorBase::_reserve_grow(Arena& arena, size_t n, ItemSize<true> item_size) noexcept {
+ return ArenaVector_reserve_grow(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_reserve_additional(Arena& arena, size_t n, Support::ByteSize item_size) noexcept {
- return ArenaVector_grow<Support::ByteSize>(*this, arena, n, item_size);
+Error ArenaVectorBase::_reserve_additional(Arena& arena, size_t n, ItemSize<false> item_size) noexcept {
+ return ArenaVector_grow(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_reserve_additional(Arena& arena, size_t n, Support::Log2Size item_size) noexcept {
- return ArenaVector_grow<Support::Log2Size>(*this, arena, n, item_size);
+Error ArenaVectorBase::_reserve_additional(Arena& arena, size_t n, ItemSize<true> item_size) noexcept {
+ return ArenaVector_grow(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_resize_fit(Arena& arena, size_t n, Support::ByteSize item_size) noexcept {
- return ArenaVector_resize_fit<Support::ByteSize>(*this, arena, n, item_size);
+Error ArenaVectorBase::_resize_fit(Arena& arena, size_t n, ItemSize<false> item_size) noexcept {
+ return ArenaVector_resize_fit(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_resize_fit(Arena& arena, size_t n, Support::Log2Size item_size) noexcept {
- return ArenaVector_resize_fit<Support::Log2Size>(*this, arena, n, item_size);
+Error ArenaVectorBase::_resize_fit(Arena& arena, size_t n, ItemSize<true> item_size) noexcept {
+ return ArenaVector_resize_fit(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_resize_grow(Arena& arena, size_t n, Support::ByteSize item_size) noexcept {
- return ArenaVector_resize_grow<Support::ByteSize>(*this, arena, n, item_size);
+Error ArenaVectorBase::_resize_grow(Arena& arena, size_t n, ItemSize<false> item_size) noexcept {
+ return ArenaVector_resize_grow(*this, arena, n, item_size);
}
-Error ArenaVectorBase::_resize_grow(Arena& arena, size_t n, Support::Log2Size item_size) noexcept {
- return ArenaVector_resize_grow<Support::Log2Size>(*this, arena, n, item_size);
+Error ArenaVectorBase::_resize_grow(Arena& arena, size_t n, ItemSize<true> item_size) noexcept {
+ return ArenaVector_resize_grow(*this, arena, n, item_size);
}
// ArenaVector - Tests
diff --git a/3rdparty/asmjit/src/asmjit/core/arenavector.h b/3rdparty/asmjit/asmjit/support/arenavector.h
index 114274d364c..f54269870d7 100644
--- a/3rdparty/asmjit/src/asmjit/core/arenavector.h
+++ b/3rdparty/asmjit/asmjit/support/arenavector.h
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_ARENAVECTOR_H_INCLUDED
-#define ASMJIT_CORE_ARENAVECTOR_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_ARENAVECTOR_H_INCLUDED
+#define ASMJIT_SUPPORT_ARENAVECTOR_H_INCLUDED
-#include "../core/arena.h"
-#include "../core/span.h"
-#include "../core/support.h"
+#include <asmjit/support/arena.h>
+#include <asmjit/support/span.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -20,6 +20,14 @@ class ArenaVectorBase {
public:
ASMJIT_NONCOPYABLE(ArenaVectorBase)
+ //! \name Item Size Detail
+ //! \{
+
+ template<bool IsPowerOf2>
+ struct ItemSize { uint32_t n; };
+
+ //! \}
+
//! \name Types (C++ compatibility)
//! \{
@@ -58,7 +66,7 @@ protected:
//! \name Internal
//! \{
- inline void _release(Arena& arena, uint32_t item_byte_size) noexcept {
+ ASMJIT_INLINE void _release(Arena& arena, uint32_t item_byte_size) noexcept {
if (_data != nullptr) {
arena.free_reusable(_data, _capacity * item_byte_size);
reset();
@@ -79,20 +87,20 @@ protected:
_capacity = capacity;
}
- ASMJIT_API Error _reserve_fit(Arena& arena, size_t n, Support::ByteSize byte_size) noexcept;
- ASMJIT_API Error _reserve_fit(Arena& arena, size_t n, Support::Log2Size log2_size) noexcept;
+ ASMJIT_API Error _reserve_fit(Arena& arena, size_t n, ItemSize<false> byte_size) noexcept;
+ ASMJIT_API Error _reserve_fit(Arena& arena, size_t n, ItemSize<true> log2_size) noexcept;
- ASMJIT_API Error _reserve_grow(Arena& arena, size_t n, Support::ByteSize byte_size) noexcept;
- ASMJIT_API Error _reserve_grow(Arena& arena, size_t n, Support::Log2Size log2_size) noexcept;
+ ASMJIT_API Error _reserve_grow(Arena& arena, size_t n, ItemSize<false> byte_size) noexcept;
+ ASMJIT_API Error _reserve_grow(Arena& arena, size_t n, ItemSize<true> log2_size) noexcept;
- ASMJIT_API Error _reserve_additional(Arena& arena, size_t n, Support::ByteSize byte_size) noexcept;
- ASMJIT_API Error _reserve_additional(Arena& arena, size_t n, Support::Log2Size log2_size) noexcept;
+ ASMJIT_API Error _reserve_additional(Arena& arena, size_t n, ItemSize<false> byte_size) noexcept;
+ ASMJIT_API Error _reserve_additional(Arena& arena, size_t n, ItemSize<true> log2_size) noexcept;
- ASMJIT_API Error _resize_fit(Arena& arena, size_t n, Support::ByteSize byte_size) noexcept;
- ASMJIT_API Error _resize_fit(Arena& arena, size_t n, Support::Log2Size log2_size) noexcept;
+ ASMJIT_API Error _resize_fit(Arena& arena, size_t n, ItemSize<false> byte_size) noexcept;
+ ASMJIT_API Error _resize_fit(Arena& arena, size_t n, ItemSize<true> log2_size) noexcept;
- ASMJIT_API Error _resize_grow(Arena& arena, size_t n, Support::ByteSize byte_size) noexcept;
- ASMJIT_API Error _resize_grow(Arena& arena, size_t n, Support::Log2Size log2_size) noexcept;
+ ASMJIT_API Error _resize_grow(Arena& arena, size_t n, ItemSize<false> byte_size) noexcept;
+ ASMJIT_API Error _resize_grow(Arena& arena, size_t n, ItemSize<true> log2_size) noexcept;
ASMJIT_INLINE_NODEBUG void _swap(ArenaVectorBase& other) noexcept {
std::swap(_data, other._data);
@@ -140,7 +148,7 @@ public:
}
//! Sets size of the vector to `n`. Used internally by some algorithms.
- inline void _set_size(size_t n) noexcept {
+ ASMJIT_INLINE void _set_size(size_t n) noexcept {
ASMJIT_ASSERT(n <= _capacity);
_size = uint32_t(n);
}
@@ -159,6 +167,14 @@ class ArenaVector : public ArenaVectorBase {
public:
ASMJIT_NONCOPYABLE(ArenaVector)
+ //! \name Item Size Detail
+ //! \{
+
+ static inline constexpr bool ItemSizeIsPowerOf2 = Support::is_power_of_2(sizeof(T));
+ static inline constexpr ItemSize<ItemSizeIsPowerOf2> item_size_ { ItemSizeIsPowerOf2 ? uint32_t(Support::ctz_t(sizeof(T))) : uint32_t(sizeof(T)) };
+
+ //! \}
+
//! \name Types (C++ compatibility)
//! \{
@@ -243,12 +259,12 @@ public:
//! Returns item at the given index `i` (const).
[[nodiscard]]
- inline const T& at(size_t i) const noexcept {
+ ASMJIT_INLINE const T& at(size_t i) const noexcept {
ASMJIT_ASSERT(i < _size);
return data()[i];
}
- inline void _set_end(T* p) noexcept {
+ ASMJIT_INLINE void _set_end(T* p) noexcept {
ASMJIT_ASSERT(p >= data() && p <= data() + _capacity);
_set_size(size_t(p - data()));
}
@@ -498,13 +514,13 @@ public:
return as_span().contains(std::forward<Value>(value));
}
- //! Returns the first index of the given `value` or `Globals::kNPos` if it wasn't found.
+ //! Returns the first index of the given `value` or `SIZE_MAX` if it wasn't found.
template<typename Value>
ASMJIT_INLINE size_t index_of(Value&& value) const noexcept {
return as_span().index_of(std::forward<Value>(value));
}
- //! Returns the last index of the given `value` or `Globals::kNPos` if it wasn't found.
+ //! Returns the last index of the given `value` or `SIZE_MAX` if it wasn't found.
template<typename Value>
ASMJIT_INLINE size_t last_index_of(Value&& value) const noexcept {
return as_span().index_of(std::forward<Value>(value));
@@ -517,23 +533,23 @@ public:
//! \{
ASMJIT_INLINE Error _reserve_fit(Arena& arena, size_t n) noexcept {
- return ArenaVectorBase::_reserve_fit(arena, n, Support::as_item_size<sizeof(T)>());
+ return ArenaVectorBase::_reserve_fit(arena, n, item_size_);
}
ASMJIT_INLINE Error _reserve_grow(Arena& arena, size_t n) noexcept {
- return ArenaVectorBase::_reserve_grow(arena, n, Support::as_item_size<sizeof(T)>());
+ return ArenaVectorBase::_reserve_grow(arena, n, item_size_);
}
ASMJIT_INLINE Error _resize_fit(Arena& arena, size_t n) noexcept {
- return ArenaVectorBase::_resize_fit(arena, n, Support::as_item_size<sizeof(T)>());
+ return ArenaVectorBase::_resize_fit(arena, n, item_size_);
}
ASMJIT_INLINE Error _resize_grow(Arena& arena, size_t n) noexcept {
- return ArenaVectorBase::_resize_grow(arena, n, Support::as_item_size<sizeof(T)>());
+ return ArenaVectorBase::_resize_grow(arena, n, item_size_);
}
ASMJIT_INLINE Error _reserve_additional(Arena& arena, size_t n) noexcept {
- return ArenaVectorBase::_reserve_additional(arena, n, Support::as_item_size<sizeof(T)>());
+ return ArenaVectorBase::_reserve_additional(arena, n, item_size_);
}
//! \}
@@ -557,7 +573,7 @@ public:
return _reserve_fit(arena, n);
}
else {
- return Error(Error::kOk);
+ return Error::kOk;
}
}
@@ -566,12 +582,12 @@ public:
//! If the vector is smaller than `n` the same growing calculations will be used as if `n` items were appended
//! to an empty vector, which means reserving additional space for more append operations that could follow.
[[nodiscard]]
- inline Error reserve_grow(Arena& arena, size_t n) noexcept {
+ ASMJIT_INLINE Error reserve_grow(Arena& arena, size_t n) noexcept {
if (ASMJIT_UNLIKELY(n > _capacity)) {
return _reserve_grow(arena, n);
}
else {
- return Error(Error::kOk);
+ return Error::kOk;
}
}
@@ -622,4 +638,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_ARENAVECTOR_H_INCLUDED
+#endif // ASMJIT_SUPPORT_ARENAVECTOR_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/span.h b/3rdparty/asmjit/asmjit/support/span.h
index d384794161c..140738a6cb7 100644
--- a/3rdparty/asmjit/src/asmjit/core/span.h
+++ b/3rdparty/asmjit/asmjit/support/span.h
@@ -3,10 +3,10 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_SPAN_H_INCLUDED
-#define ASMJIT_CORE_SPAN_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_SPAN_H_INCLUDED
+#define ASMJIT_SUPPORT_SPAN_H_INCLUDED
-#include "../core/globals.h"
+#include <asmjit/core/globals.h>
ASMJIT_BEGIN_NAMESPACE
@@ -27,37 +27,19 @@ public:
//! \name Overloaded Operators
//! \{
- ASMJIT_INLINE_NODEBUG bool operator==(const T* other) const noexcept { return ptr == other; }
- ASMJIT_INLINE_NODEBUG bool operator==(const SpanForwardIterator& other) const noexcept { return ptr == other.ptr; }
+ ASMJIT_INLINE_CONSTEXPR bool operator==(const T* other) const noexcept { return ptr == other; }
+ ASMJIT_INLINE_CONSTEXPR bool operator==(const SpanForwardIterator& other) const noexcept { return ptr == other.ptr; }
- ASMJIT_INLINE_NODEBUG bool operator!=(const T* other) const noexcept { return ptr != other; }
- ASMJIT_INLINE_NODEBUG bool operator!=(const SpanForwardIterator& other) const noexcept { return ptr != other.ptr; }
+ ASMJIT_INLINE_CONSTEXPR bool operator!=(const T* other) const noexcept { return ptr != other; }
+ ASMJIT_INLINE_CONSTEXPR bool operator!=(const SpanForwardIterator& other) const noexcept { return ptr != other.ptr; }
- ASMJIT_INLINE_NODEBUG SpanForwardIterator& operator++() noexcept { ptr++; return *this; }
- ASMJIT_INLINE_NODEBUG SpanForwardIterator& operator--() noexcept { ptr--; return *this; }
+ ASMJIT_INLINE_CONSTEXPR SpanForwardIterator& operator++() noexcept { ptr++; return *this; }
+ ASMJIT_INLINE_CONSTEXPR SpanForwardIterator operator++(int) noexcept { SpanForwardIterator prev(*this); ptr++; return prev; }
- ASMJIT_INLINE_NODEBUG SpanForwardIterator operator++(int) noexcept { SpanForwardIterator prev(*this); ptr++; return prev; }
- ASMJIT_INLINE_NODEBUG SpanForwardIterator operator--(int) noexcept { SpanForwardIterator prev(*this); ptr--; return prev; }
+ ASMJIT_INLINE_CONSTEXPR T& operator*() const noexcept { return *ptr; }
+ ASMJIT_INLINE_CONSTEXPR T* operator->() const noexcept { return ptr; }
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanForwardIterator operator+(const N& n) noexcept { return SpanForwardIterator(ptr += n); }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanForwardIterator operator-(const N& n) noexcept { return SpanForwardIterator(ptr -= n); }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanForwardIterator& operator+=(const N& n) noexcept { ptr += n; return *this; }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanForwardIterator& operator-=(const N& n) noexcept { ptr -= n; return *this; }
-
- ASMJIT_INLINE_CONSTEXPR T& operator*() const noexcept { return ptr[0]; }
- ASMJIT_INLINE_CONSTEXPR T* operator->() const noexcept { return &ptr[0]; }
-
- template<typename Index>
- ASMJIT_INLINE_NODEBUG T& operator[](const Index& n) noexcept { return *(ptr - n - 1); }
-
- ASMJIT_INLINE_NODEBUG operator T*() const noexcept { return ptr; }
+ ASMJIT_INLINE_CONSTEXPR operator T*() const noexcept { return ptr; }
//! \}
};
@@ -76,49 +58,19 @@ public:
//! \name Overloaded Operators
//! \{
- ASMJIT_INLINE_NODEBUG bool operator==(const T* other) const noexcept { return ptr == other; }
- ASMJIT_INLINE_NODEBUG bool operator==(const SpanReverseIterator& other) const noexcept { return ptr == other.ptr; }
-
- ASMJIT_INLINE_NODEBUG bool operator!=(const T* other) const noexcept { return ptr != other; }
- ASMJIT_INLINE_NODEBUG bool operator!=(const SpanReverseIterator& other) const noexcept { return ptr != other.ptr; }
-
- ASMJIT_INLINE_NODEBUG bool operator<(const T* other) const noexcept { return ptr < other; }
- ASMJIT_INLINE_NODEBUG bool operator<(const SpanReverseIterator& other) const noexcept { return ptr < other.ptr; }
+ ASMJIT_INLINE_CONSTEXPR bool operator==(const T* other) const noexcept { return ptr == other; }
+ ASMJIT_INLINE_CONSTEXPR bool operator==(const SpanReverseIterator& other) const noexcept { return ptr == other.ptr; }
- ASMJIT_INLINE_NODEBUG bool operator<=(const T* other) const noexcept { return ptr <= other; }
- ASMJIT_INLINE_NODEBUG bool operator<=(const SpanReverseIterator& other) const noexcept { return ptr <= other.ptr; }
+ ASMJIT_INLINE_CONSTEXPR bool operator!=(const T* other) const noexcept { return ptr != other; }
+ ASMJIT_INLINE_CONSTEXPR bool operator!=(const SpanReverseIterator& other) const noexcept { return ptr != other.ptr; }
- ASMJIT_INLINE_NODEBUG bool operator>(const T* other) const noexcept { return ptr > other; }
- ASMJIT_INLINE_NODEBUG bool operator>(const SpanReverseIterator& other) const noexcept { return ptr > other.ptr; }
-
- ASMJIT_INLINE_NODEBUG bool operator>=(const T* other) const noexcept { return ptr >= other; }
- ASMJIT_INLINE_NODEBUG bool operator>=(const SpanReverseIterator& other) const noexcept { return ptr >= other.ptr; }
-
- ASMJIT_INLINE_NODEBUG SpanReverseIterator& operator++() noexcept { ptr--; return *this; }
- ASMJIT_INLINE_NODEBUG SpanReverseIterator& operator--() noexcept { ptr++; return *this; }
-
- ASMJIT_INLINE_NODEBUG SpanReverseIterator operator++(int) noexcept { SpanReverseIterator prev(*this); ptr--; return prev; }
- ASMJIT_INLINE_NODEBUG SpanReverseIterator operator--(int) noexcept { SpanReverseIterator prev(*this); ptr++; return prev; }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanReverseIterator operator+(const N& n) noexcept { return SpanReverseIterator(ptr -= n); }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanReverseIterator operator-(const N& n) noexcept { return SpanReverseIterator(ptr += n); }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanReverseIterator& operator+=(const N& n) noexcept { ptr -= n; return *this; }
-
- template<typename N>
- ASMJIT_INLINE_NODEBUG SpanReverseIterator& operator-=(const N& n) noexcept { ptr += n; return *this; }
+ ASMJIT_INLINE_CONSTEXPR SpanReverseIterator& operator++() noexcept { ptr--; return *this; }
+ ASMJIT_INLINE_CONSTEXPR SpanReverseIterator operator++(int) noexcept { SpanReverseIterator prev(*this); ptr--; return prev; }
ASMJIT_INLINE_CONSTEXPR T& operator*() const noexcept { return ptr[-1]; }
ASMJIT_INLINE_CONSTEXPR T* operator->() const noexcept { return &ptr[-1]; }
- template<typename Index>
- ASMJIT_INLINE_NODEBUG T& operator[](const Index& n) noexcept { return *(ptr - n - 1); }
-
- ASMJIT_INLINE_NODEBUG operator T*() const noexcept { return &ptr[-1]; }
+ ASMJIT_INLINE_CONSTEXPR operator T*() const noexcept { return &ptr[-1]; }
//! \}
};
@@ -145,10 +97,10 @@ public:
//! \{
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG iterator begin() const noexcept { return iterator{_begin}; };
+ ASMJIT_INLINE_CONSTEXPR iterator begin() const noexcept { return iterator{_begin}; };
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG iterator end() const noexcept { return iterator{_end}; };
+ ASMJIT_INLINE_CONSTEXPR iterator end() const noexcept { return iterator{_end}; };
//! \}
};
@@ -175,10 +127,10 @@ public:
//! \{
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG iterator begin() const noexcept { return iterator{_end}; };
+ ASMJIT_INLINE_CONSTEXPR iterator begin() const noexcept { return iterator{_end}; };
[[nodiscard]]
- ASMJIT_INLINE_NODEBUG iterator end() const noexcept { return iterator{_begin}; };
+ ASMJIT_INLINE_CONSTEXPR iterator end() const noexcept { return iterator{_begin}; };
//! \}
};
@@ -334,7 +286,7 @@ struct Span {
return false;
}
- //! Returns the first index of the given `value` or `Globals::kNPos` if it wasn't found'.
+ //! Returns the first index of the given `value` or `SIZE_MAX` if it wasn't found'.
template<typename Value>
[[nodiscard]]
ASMJIT_INLINE size_t index_of(Value&& value) const noexcept {
@@ -346,16 +298,16 @@ struct Span {
}
}
- return Globals::kNPos;
+ return SIZE_MAX;
}
- //! Returns the last index of the given `value` or `Globals::kNPos` if it wasn't found.
+ //! Returns the last index of the given `value` or `SIZE_MAX` if it wasn't found.
template<typename Value>
[[nodiscard]]
ASMJIT_INLINE size_t last_index_of(Value&& value) const noexcept {
size_t i = _size;
- while (--i != Globals::kNPos) {
+ while (--i != SIZE_MAX) {
if (_data[i] == value) {
break;
}
@@ -382,4 +334,4 @@ struct Span {
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_SPAN_H_INCLUDED
+#endif // ASMJIT_SUPPORT_SPAN_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/support.cpp b/3rdparty/asmjit/asmjit/support/support.cpp
index fb734e6472c..07ed1e0f26c 100644
--- a/3rdparty/asmjit/src/asmjit/core/support.cpp
+++ b/3rdparty/asmjit/asmjit/support/support.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "../core/support.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -121,6 +121,40 @@ static void test_bit_utils() noexcept {
EXPECT_EQ(Support::lsb_mask<uint64_t>(i), expected_bits);
}
+ INFO("Support::fill_trailing_bits()");
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(0u)), uint8_t(0u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(1u)), uint8_t(1u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(2u)), uint8_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(3u)), uint8_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(4u)), uint8_t(7u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(0x80u)), uint8_t(0xFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(0xFEu)), uint8_t(0xFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint8_t(0xFFu)), uint8_t(0xFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(0u)), uint16_t(0u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(1u)), uint16_t(1u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(2u)), uint16_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(3u)), uint16_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(4u)), uint16_t(7u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(0x8000u)), uint16_t(0xFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(0xFFFEu)), uint16_t(0xFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint16_t(0xFFFFu)), uint16_t(0xFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(0u)), uint32_t(0u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(1u)), uint32_t(1u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(2u)), uint32_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(3u)), uint32_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(4u)), uint32_t(7u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(0x80000000u)), uint32_t(0xFFFFFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(0xFFFFFFFEu)), uint32_t(0xFFFFFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint32_t(0xFFFFFFFFu)), uint32_t(0xFFFFFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(0u)), uint64_t(0u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(1u)), uint64_t(1u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(2u)), uint64_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(3u)), uint64_t(3u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(4u)), uint64_t(7u));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(0x8000000000000000u)), uint64_t(0xFFFFFFFFFFFFFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(0xFFFFFFFFFFFFFFFEu)), uint64_t(0xFFFFFFFFFFFFFFFFu));
+ EXPECT_EQ(Support::fill_trailing_bits(uint64_t(0xFFFFFFFFFFFFFFFFu)), uint64_t(0xFFFFFFFFFFFFFFFFu));
+
INFO("Support::is_power_of_2()");
EXPECT_FALSE(Support::is_power_of_2(uint8_t(0)));
EXPECT_FALSE(Support::is_power_of_2(uint16_t(0)));
diff --git a/3rdparty/asmjit/src/asmjit/core/support.h b/3rdparty/asmjit/asmjit/support/support.h
index 3149ae1161d..1fc17119d9f 100644
--- a/3rdparty/asmjit/src/asmjit/core/support.h
+++ b/3rdparty/asmjit/asmjit/support/support.h
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_SUPPORT_H_INCLUDED
-#define ASMJIT_CORE_SUPPORT_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_SUPPORT_H_INCLUDED
+#define ASMJIT_SUPPORT_SUPPORT_H_INCLUDED
-#include "../core/globals.h"
-#include "../core/span.h"
+#include <asmjit/core/globals.h>
+#include <asmjit/support/span.h>
#if defined(_MSC_VER)
#include <intrin.h>
@@ -32,6 +32,13 @@ ASMJIT_BEGIN_NAMESPACE
//! here is considered internal and should not be used outside of AsmJit and related projects like AsmTK.
namespace Support {
+// Support - Maybe Unused
+// ======================
+
+//! Silences warnings about unused arguments or variables - more variables can be passed to `maybe_unused()` at once.
+template<typename... Args>
+static SUPPORT_INLINE_NODEBUG void maybe_unused(Args&&...) noexcept {}
+
// Support - Byte Order
// ====================
@@ -94,13 +101,6 @@ using FastUInt8 = uint8_t;
using FastUInt8 = uint32_t;
#endif
-// Support - Maybe Unused
-// ======================
-
-//! Silences warnings about unused arguments or variables - more variables can be passed to `maybe_unused()` at once.
-template<typename... Args>
-static SUPPORT_INLINE_NODEBUG void maybe_unused(Args&&...) noexcept {}
-
// Support - Min & Max
// ===================
@@ -254,12 +254,15 @@ SUPPORT_INLINE constexpr bool bool_and(Args&&... args) noexcept { return bool((.
template<typename... Args>
SUPPORT_INLINE constexpr bool bool_or(Args&&... args) noexcept { return bool((... | bool_as<unsigned>(args))); }
-// Support - Bit Constants
-// =======================
+// Support - Bit Size
+// ==================
template<typename T>
inline constexpr uint32_t bit_size_of = uint32_t(sizeof(T) * 8u);
+// Support - Bit Ones
+// ==================
+
template<typename T>
inline constexpr T bit_ones = T(~T(0));
@@ -665,18 +668,11 @@ SUPPORT_INLINE constexpr T bit_mask(const Index& idx, Args... args) noexcept { r
// Fills all trailing bits right of the given `value` from the first most significant bit set.
template<typename T>
[[nodiscard]]
-SUPPORT_INLINE constexpr T fill_trailing_bits(const T& value) noexcept {
- T v = as_basic_uint(value);
-
- v = v | (v >> 1);
- v = v | (v >> 2);
- v = v | (v >> 4);
-
- if constexpr (sizeof(T) > 1u) { v = v | (v >> 8); }
- if constexpr (sizeof(T) > 2u) { v = v | (v >> 16); }
- if constexpr (sizeof(T) > 4u) { v = v | (v >> 32); }
+SUPPORT_INLINE_NODEBUG T fill_trailing_bits(const T& value) noexcept {
+ auto v = as_basic_uint(value);
- return T(v);
+ uint32_t leading_count = clz(v | 1u);
+ return T(((bit_ones<decltype(v)> >> 1u) >> leading_count) | v);
}
// Support - Is LSB & Consecutive Mask
@@ -983,14 +979,14 @@ struct unaligned_uint;
template<> struct unaligned_uint<1> { typedef uint8_t type; };
-#if !defined(_MSC_VER)
-template<> struct unaligned_uint<2> { typedef uint16_t __attribute__((__may_alias__, __aligned__(1))) type; };
-template<> struct unaligned_uint<4> { typedef uint32_t __attribute__((__may_alias__, __aligned__(1))) type; };
-template<> struct unaligned_uint<8> { typedef uint64_t __attribute__((__may_alias__, __aligned__(1))) type; };
-#else
+#if defined(_MSC_VER)
template<> struct unaligned_uint<2> { typedef uint16_t __declspec(align(1)) type; };
template<> struct unaligned_uint<4> { typedef uint32_t __declspec(align(1)) type; };
template<> struct unaligned_uint<8> { typedef uint64_t __declspec(align(1)) type; };
+#elif defined(__GNUC__)
+template<> struct unaligned_uint<2> { typedef uint16_t __attribute__((__may_alias__, __aligned__(1))) type; };
+template<> struct unaligned_uint<4> { typedef uint32_t __attribute__((__may_alias__, __aligned__(1))) type; };
+template<> struct unaligned_uint<8> { typedef uint64_t __attribute__((__may_alias__, __aligned__(1))) type; };
#endif
template<size_t Size>
@@ -1176,45 +1172,6 @@ SUPPORT_INLINE_NODEBUG void storeu_u64_be(void* p, uint64_t x) noexcept { storeu
} // {anonymous}
-// Support - Is Encodable Offset
-// =============================
-
-[[nodiscard]]
-static bool SUPPORT_INLINE_NODEBUG is_encodable_offset_32(int32_t offset, uint32_t num_bits) noexcept {
- uint32_t n_rev = 32 - num_bits;
- return sar(shl(offset, n_rev), n_rev) == offset;
-}
-
-[[nodiscard]]
-static bool SUPPORT_INLINE_NODEBUG is_encodable_offset_64(int64_t offset, uint32_t num_bits) noexcept {
- uint32_t n_rev = 64 - num_bits;
- return sar(shl(offset, n_rev), n_rev) == offset;
-}
-
-// Support - BytePack & Unpack
-// ===========================
-
-//! Pack four 8-bit integer into a 32-bit integer as it is an array of `{b0,b1,b2,b3}`.
-[[nodiscard]]
-static SUPPORT_INLINE constexpr uint32_t bytepack32_4x8(uint32_t a, uint32_t b, uint32_t c, uint32_t d) noexcept {
- return (ByteOrder::kNative == ByteOrder::kLE)
- ? (a | (b << 8) | (c << 16) | (d << 24))
- : (d | (c << 8) | (b << 16) | (a << 24));
-}
-
-template<typename T>
-[[nodiscard]]
-static SUPPORT_INLINE constexpr uint32_t unpack_u32_at_0(T x) noexcept { return (ByteOrder::kNative == ByteOrder::kLE) ? uint32_t(uint64_t(x) & 0xFFFFFFFFu) : uint32_t(uint64_t(x) >> 32); }
-
-template<typename T>
-[[nodiscard]]
-static SUPPORT_INLINE constexpr uint32_t unpack_u32_at_1(T x) noexcept { return (ByteOrder::kNative == ByteOrder::kBE) ? uint32_t(uint64_t(x) & 0xFFFFFFFFu) : uint32_t(uint64_t(x) >> 32); }
-
-[[nodiscard]]
-static SUPPORT_INLINE_NODEBUG uint32_t byte_shift_in_struct(uint32_t index) noexcept {
- return (ByteOrder::kNative == ByteOrder::kLE) ? index * 8 : (uint32_t(sizeof(uint32_t)) - 1u - index) * 8;
-}
-
// Support - Enumerate
// ===================
@@ -1330,40 +1287,6 @@ static SUPPORT_INLINE int compare_string_views(const char* a_data, size_t a_size
return int(a_size) - int(b_size);
}
-// Support - Vector Helpers
-// ========================
-
-struct ByteSize { uint32_t n; };
-struct Log2Size { uint32_t n; };
-
-template<size_t kSize, bool kIsPowerOf2>
-struct ByteSizeOrLog2Size {
- using Size = ByteSize;
-
- static SUPPORT_INLINE constexpr Size get() noexcept { return ByteSize{kSize}; }
-};
-
-template<size_t kSize>
-struct ByteSizeOrLog2Size<kSize, true> {
- using Size = Log2Size;
-
- static SUPPORT_INLINE constexpr Size get() noexcept { return Log2Size{ctz_const<kSize>}; }
-};
-
-template<size_t kSize>
-static SUPPORT_INLINE constexpr typename ByteSizeOrLog2Size<kSize, Support::is_power_of_2(kSize)>::Size as_item_size() noexcept {
- return ByteSizeOrLog2Size<kSize, Support::is_power_of_2(kSize)>::get();
-}
-
-template<typename ResultType = size_t>
-static SUPPORT_INLINE_NODEBUG ResultType byte_size_from_item_count(size_t item_count, ByteSize item_size) noexcept { return ResultType(item_count) * item_size.n; }
-
-template<typename ResultType = size_t>
-static SUPPORT_INLINE_NODEBUG ResultType byte_size_from_item_count(size_t item_count, Log2Size item_size) noexcept { return ResultType(item_count) << item_size.n; }
-
-static SUPPORT_INLINE_NODEBUG size_t item_count_from_byte_size(size_t byte_size, ByteSize item_size) noexcept { return byte_size / item_size.n; }
-static SUPPORT_INLINE_NODEBUG size_t item_count_from_byte_size(size_t byte_size, Log2Size item_size) noexcept { return byte_size >> item_size.n; }
-
// Support - Operators
// ===================
@@ -1386,6 +1309,31 @@ struct Or {
};
//! \endcond
+// Support - BytePack & Unpack
+// ===========================
+
+//! Pack four 8-bit integer into a 32-bit integer as it is an array of `{b0,b1,b2,b3}`.
+[[nodiscard]]
+static SUPPORT_INLINE constexpr uint32_t bytepack32_4x8(uint32_t a, uint32_t b, uint32_t c, uint32_t d) noexcept {
+ return (ByteOrder::kNative == ByteOrder::kLE)
+ ? (a | (b << 8) | (c << 16) | (d << 24))
+ : (d | (c << 8) | (b << 16) | (a << 24));
+}
+
+template<typename T>
+[[nodiscard]]
+static SUPPORT_INLINE constexpr uint32_t unpack_u32_at_0(T x) noexcept {
+ constexpr uint32_t kShift = ByteOrder::kNative == ByteOrder::kLE ? 0 : 32;
+ return uint32_t((uint64_t(x) >> kShift) & 0xFFFFFFFFu);
+}
+
+template<typename T>
+[[nodiscard]]
+static SUPPORT_INLINE constexpr uint32_t unpack_u32_at_1(T x) noexcept {
+ constexpr uint32_t kShift = ByteOrder::kNative == ByteOrder::kLE ? 32 : 0;
+ return uint32_t((uint64_t(x) >> kShift) & 0xFFFFFFFFu);
+}
+
// Support - BitWordIterator
// =========================
@@ -1686,7 +1634,7 @@ struct Compare {
//! Insertion sort.
template<typename T, typename CompareT = Compare<SortOrder::kAscending>>
-static inline void insertion_sort(T* base, size_t size, const CompareT& cmp = CompareT()) noexcept {
+static SUPPORT_INLINE void insertion_sort(T* base, size_t size, const CompareT& cmp = CompareT()) noexcept {
for (T* pm = base + 1; pm < base + size; pm++) {
for (T* pl = pm; pl > base && cmp(pl[-1], pl[0]) > 0; pl--) {
std::swap(pl[-1], pl[0]);
@@ -1776,75 +1724,6 @@ static SUPPORT_INLINE_NODEBUG void sort(T* base, size_t size, const CompareT& cm
Internal::QSortImpl<T, CompareT>::sort(base, size, cmp);
}
-// Support - ReverseIterator
-// =========================
-
-//! Reverse iterator to avoid including `<iterator>` header for iteration over arrays, specialized for
-//! AsmJit use (noexcept by design).
-template<typename T>
-class ArrayReverseIterator {
-public:
- //! \name Members
- //! \{
-
- T* _ptr {};
-
- //! \}
-
- //! \name Construction & Destruction
- //! \{
-
- SUPPORT_INLINE constexpr ArrayReverseIterator() noexcept = default;
- SUPPORT_INLINE constexpr ArrayReverseIterator(const ArrayReverseIterator& other) noexcept = default;
- SUPPORT_INLINE constexpr ArrayReverseIterator(T* ptr) noexcept : _ptr(ptr) {}
-
- //! \}
-
- //! \name Overloaded Operators
- //! \{
-
- SUPPORT_INLINE_NODEBUG ArrayReverseIterator& operator=(const ArrayReverseIterator& other) noexcept = default;
-
- SUPPORT_INLINE_NODEBUG bool operator==(const T* other) const noexcept { return _ptr == other; }
- SUPPORT_INLINE_NODEBUG bool operator==(const ArrayReverseIterator& other) const noexcept { return _ptr == other._ptr; }
-
- SUPPORT_INLINE_NODEBUG bool operator!=(const T* other) const noexcept { return _ptr != other; }
- SUPPORT_INLINE_NODEBUG bool operator!=(const ArrayReverseIterator& other) const noexcept { return _ptr != other._ptr; }
-
- SUPPORT_INLINE_NODEBUG bool operator<(const T* other) const noexcept { return _ptr < other; }
- SUPPORT_INLINE_NODEBUG bool operator<(const ArrayReverseIterator& other) const noexcept { return _ptr < other._ptr; }
-
- SUPPORT_INLINE_NODEBUG bool operator<=(const T* other) const noexcept { return _ptr <= other; }
- SUPPORT_INLINE_NODEBUG bool operator<=(const ArrayReverseIterator& other) const noexcept { return _ptr <= other._ptr; }
-
- SUPPORT_INLINE_NODEBUG bool operator>(const T* other) const noexcept { return _ptr > other; }
- SUPPORT_INLINE_NODEBUG bool operator>(const ArrayReverseIterator& other) const noexcept { return _ptr > other._ptr; }
-
- SUPPORT_INLINE_NODEBUG bool operator>=(const T* other) const noexcept { return _ptr >= other; }
- SUPPORT_INLINE_NODEBUG bool operator>=(const ArrayReverseIterator& other) const noexcept { return _ptr >= other._ptr; }
-
- SUPPORT_INLINE_NODEBUG ArrayReverseIterator& operator++() noexcept { _ptr--; return *this; }
- SUPPORT_INLINE_NODEBUG ArrayReverseIterator& operator--() noexcept { _ptr++; return *this; }
-
- SUPPORT_INLINE_NODEBUG ArrayReverseIterator operator++(int) noexcept { ArrayReverseIterator prev(*this); _ptr--; return prev; }
- SUPPORT_INLINE_NODEBUG ArrayReverseIterator operator--(int) noexcept { ArrayReverseIterator prev(*this); _ptr++; return prev; }
-
- template<typename Diff> SUPPORT_INLINE_NODEBUG ArrayReverseIterator operator+(const Diff& n) noexcept { return ArrayReverseIterator(_ptr -= n); }
- template<typename Diff> SUPPORT_INLINE_NODEBUG ArrayReverseIterator operator-(const Diff& n) noexcept { return ArrayReverseIterator(_ptr += n); }
-
- template<typename Diff> SUPPORT_INLINE_NODEBUG ArrayReverseIterator& operator+=(const Diff& n) noexcept { _ptr -= n; return *this; }
- template<typename Diff> SUPPORT_INLINE_NODEBUG ArrayReverseIterator& operator-=(const Diff& n) noexcept { _ptr += n; return *this; }
-
- SUPPORT_INLINE constexpr T& operator*() const noexcept { return _ptr[-1]; }
- SUPPORT_INLINE constexpr T* operator->() const noexcept { return &_ptr[-1]; }
-
- template<typename Diff> SUPPORT_INLINE_NODEBUG T& operator[](const Diff& n) noexcept { return *(_ptr - n - 1); }
-
- SUPPORT_INLINE_NODEBUG operator T*() const noexcept { return _ptr; }
-
- //! \}
-};
-
// Support - Array
// ===============
@@ -1881,18 +1760,18 @@ struct Array {
//! \{
template<typename Index>
- inline T& operator[](const Index& index) noexcept {
+ SUPPORT_INLINE T& operator[](const Index& index) noexcept {
SUPPORT_ASSERT(as_std_uint(index) < N);
return _data[as_std_uint(index)];
}
template<typename Index>
- inline const T& operator[](const Index& index) const noexcept {
+ SUPPORT_INLINE const T& operator[](const Index& index) const noexcept {
SUPPORT_ASSERT(as_std_uint(index) < N);
return _data[as_std_uint(index)];
}
- constexpr inline bool operator==(const Array& other) const noexcept {
+ SUPPORT_INLINE constexpr bool operator==(const Array& other) const noexcept {
for (size_t i = 0; i < N; i++) {
if (_data[i] != other._data[i]) {
return false;
@@ -1960,33 +1839,33 @@ struct Array {
SUPPORT_INLINE Span<T> as_span() noexcept { return Span<T>(_data, N); }
SUPPORT_INLINE Span<const T> as_span() const noexcept { return Span<const T>(_data, N); }
- inline void swap(Array& other) noexcept {
+ SUPPORT_INLINE void swap(Array& other) noexcept {
for (size_t i = 0; i < N; i++) {
std::swap(_data[i], other._data[i]);
}
}
- inline void fill(const T& value) noexcept {
+ SUPPORT_INLINE void fill(const T& value) noexcept {
for (size_t i = 0; i < N; i++) {
_data[i] = value;
}
}
- inline void copy_from(const Array& other) noexcept {
+ SUPPORT_INLINE void copy_from(const Array& other) noexcept {
for (size_t i = 0; i < N; i++) {
_data[i] = other._data[i];
}
}
template<typename Operator>
- inline void combine(const Array& other) noexcept {
+ SUPPORT_INLINE void combine(const Array& other) noexcept {
for (size_t i = 0; i < N; i++) {
_data[i] = Operator::op(_data[i], other._data[i]);
}
}
template<typename Operator>
- inline T aggregate(T initial_value = T()) const noexcept {
+ SUPPORT_INLINE T aggregate(T initial_value = T()) const noexcept {
T value = initial_value;
for (size_t i = 0; i < N; i++) {
value = Operator::op(value, _data[i]);
@@ -1995,7 +1874,7 @@ struct Array {
}
template<typename Fn>
- inline void for_each(Fn&& fn) noexcept {
+ SUPPORT_INLINE void for_each(Fn&& fn) noexcept {
for (size_t i = 0; i < N; i++) {
fn(_data[i]);
}
@@ -2016,4 +1895,4 @@ struct Array {
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_SUPPORT_H_INCLUDED
+#endif // ASMJIT_SUPPORT_SUPPORT_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/core/support_p.h b/3rdparty/asmjit/asmjit/support/support_p.h
index 54087cfb4d8..6e196d4370b 100644
--- a/3rdparty/asmjit/src/asmjit/core/support_p.h
+++ b/3rdparty/asmjit/asmjit/support/support_p.h
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#ifndef ASMJIT_CORE_SUPPORT_P_H_INCLUDED
-#define ASMJIT_CORE_SUPPORT_P_H_INCLUDED
+#ifndef ASMJIT_SUPPORT_SUPPORT_P_H_INCLUDED
+#define ASMJIT_SUPPORT_SUPPORT_P_H_INCLUDED
-#include "../core/arenabitset_p.h"
-#include "../core/support.h"
+#include <asmjit/support/arenabitset_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_NAMESPACE
@@ -252,4 +252,4 @@ public:
ASMJIT_END_NAMESPACE
-#endif // ASMJIT_CORE_SUPPORT_P_H_INCLUDED
+#endif // ASMJIT_SUPPORT_SUPPORT_P_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/ujit.h b/3rdparty/asmjit/asmjit/ujit.h
index 78c1082cc67..4e972982bef 100644
--- a/3rdparty/asmjit/src/asmjit/ujit.h
+++ b/3rdparty/asmjit/asmjit/ujit.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_UJIT_H_INCLUDED
#define ASMJIT_UJIT_H_INCLUDED
-#include "asmjit-scope-begin.h"
-#include "ujit/ujitbase.h"
-#include "ujit/unicompiler.h"
-#include "ujit/unicondition.h"
-#include "ujit/uniop.h"
-#include "ujit/vecconsttable.h"
-#include "asmjit-scope-end.h"
+#include <asmjit/asmjit-scope-begin.h>
+#include <asmjit/ujit/ujitbase.h>
+#include <asmjit/ujit/unicompiler.h>
+#include <asmjit/ujit/unicondition.h>
+#include <asmjit/ujit/uniop.h>
+#include <asmjit/ujit/vecconsttable.h>
+#include <asmjit/asmjit-scope-end.h>
#endif // ASMJIT_UJIT_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/ujit/ujitbase.h b/3rdparty/asmjit/asmjit/ujit/ujitbase.h
index ecc72cb4db0..2bbef3cfa03 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/ujitbase.h
+++ b/3rdparty/asmjit/asmjit/ujit/ujitbase.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_UJIT_JITBASE_P_H_INCLUDED
#define ASMJIT_UJIT_JITBASE_P_H_INCLUDED
-#include "../host.h"
+#include <asmjit/host.h>
#if !defined(ASMJIT_NO_UJIT) && !defined(ASMJIT_HAS_HOST_BACKEND)
#pragma message("ASMJIT_NO_UJIT wasn't defined, however, no backends were found! (ASMJIT_HAS_HOST_BACKEND not defined)")
diff --git a/3rdparty/asmjit/src/asmjit/ujit/unicompiler.h b/3rdparty/asmjit/asmjit/ujit/unicompiler.h
index 3c9b52bfdef..651e2ac5d89 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/unicompiler.h
+++ b/3rdparty/asmjit/asmjit/ujit/unicompiler.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_UJIT_UNICOMPILER_H_INCLUDED
#define ASMJIT_UJIT_UNICOMPILER_H_INCLUDED
-#include "ujitbase.h"
-#include "uniop.h"
-#include "vecconsttable.h"
+#include <asmjit/ujit/ujitbase.h>
+#include <asmjit/ujit/uniop.h>
+#include <asmjit/ujit/vecconsttable.h>
#if !defined(ASMJIT_NO_UJIT)
@@ -761,7 +761,7 @@ public:
template<typename RegT, typename... Args>
[[nodiscard]]
ASMJIT_INLINE RegT new_reg(TypeId type_id, Args&&... args) noexcept {
- return cc->new_similar_reg<RegT>(type_id, std::forward<Args>(args)...);
+ return cc->new_reg<RegT>(type_id, std::forward<Args>(args)...);
}
//! Wraps `BackendCompiler::new_similar_reg(ref, args...)`.
diff --git a/3rdparty/asmjit/src/asmjit/ujit/unicompiler_a64.cpp b/3rdparty/asmjit/asmjit/ujit/unicompiler_a64.cpp
index 42c39ad315f..8411119195a 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/unicompiler_a64.cpp
+++ b/3rdparty/asmjit/asmjit/ujit/unicompiler_a64.cpp
@@ -3,14 +3,14 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "ujitbase.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/ujit/ujitbase.h>
#if defined(ASMJIT_UJIT_AARCH64)
-#include "unicompiler.h"
-#include "unicompiler_utils_p.h"
-#include "unicondition.h"
+#include <asmjit/ujit/unicompiler.h>
+#include <asmjit/ujit/unicompiler_utils_p.h>
+#include <asmjit/ujit/unicondition.h>
ASMJIT_BEGIN_SUB_NAMESPACE(ujit)
diff --git a/3rdparty/asmjit/src/asmjit/ujit/unicompiler_utils_p.h b/3rdparty/asmjit/asmjit/ujit/unicompiler_utils_p.h
index b01cc1c7cfd..01fe3cbb1ff 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/unicompiler_utils_p.h
+++ b/3rdparty/asmjit/asmjit/ujit/unicompiler_utils_p.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_UJIT_UNICOMPILER_UTILS_P_H_INCLUDED
#define ASMJIT_UJIT_UNICOMPILER_UTILS_P_H_INCLUDED
-#include "ujitbase.h"
+#include <asmjit/ujit/ujitbase.h>
#if !defined(ASMJIT_NO_UJIT)
-#include "uniop.h"
+#include <asmjit/ujit/uniop.h>
ASMJIT_BEGIN_SUB_NAMESPACE(ujit)
diff --git a/3rdparty/asmjit/src/asmjit/ujit/unicompiler_x86.cpp b/3rdparty/asmjit/asmjit/ujit/unicompiler_x86.cpp
index ae4412e48fb..18556062a7e 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/unicompiler_x86.cpp
+++ b/3rdparty/asmjit/asmjit/ujit/unicompiler_x86.cpp
@@ -3,14 +3,14 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "ujitbase.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/ujit/ujitbase.h>
#if defined(ASMJIT_UJIT_X86)
-#include "unicompiler.h"
-#include "unicompiler_utils_p.h"
-#include "unicondition.h"
+#include <asmjit/ujit/unicompiler.h>
+#include <asmjit/ujit/unicompiler_utils_p.h>
+#include <asmjit/ujit/unicondition.h>
ASMJIT_BEGIN_SUB_NAMESPACE(ujit)
diff --git a/3rdparty/asmjit/src/asmjit/ujit/unicondition.h b/3rdparty/asmjit/asmjit/ujit/unicondition.h
index 3e6ee817fec..f110b3a4260 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/unicondition.h
+++ b/3rdparty/asmjit/asmjit/ujit/unicondition.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_UJIT_UNICONDITION_H_INCLUDED
#define ASMJIT_UJIT_UNICONDITION_H_INCLUDED
-#include "ujitbase.h"
-#include "uniop.h"
+#include <asmjit/ujit/ujitbase.h>
+#include <asmjit/ujit/uniop.h>
#if !defined(ASMJIT_NO_UJIT)
diff --git a/3rdparty/asmjit/src/asmjit/ujit/uniop.h b/3rdparty/asmjit/asmjit/ujit/uniop.h
index 63935bfb902..af27583c78e 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/uniop.h
+++ b/3rdparty/asmjit/asmjit/ujit/uniop.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_UJIT_UNIOP_H_INCLUDED
#define ASMJIT_UJIT_UNIOP_H_INCLUDED
-#include "ujitbase.h"
+#include <asmjit/ujit/ujitbase.h>
#if !defined(ASMJIT_NO_UJIT)
diff --git a/3rdparty/asmjit/src/asmjit/ujit/vecconsttable.cpp b/3rdparty/asmjit/asmjit/ujit/vecconsttable.cpp
index 1e3fc5ee400..1bfe508ea63 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/vecconsttable.cpp
+++ b/3rdparty/asmjit/asmjit/ujit/vecconsttable.cpp
@@ -3,8 +3,8 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
-#include "vecconsttable.h"
+#include <asmjit/core/api-build_p.h>
+#include <asmjit/ujit/vecconsttable.h>
#if !defined(ASMJIT_NO_UJIT)
diff --git a/3rdparty/asmjit/src/asmjit/ujit/vecconsttable.h b/3rdparty/asmjit/asmjit/ujit/vecconsttable.h
index b0779ff4544..76682761b6d 100644
--- a/3rdparty/asmjit/src/asmjit/ujit/vecconsttable.h
+++ b/3rdparty/asmjit/asmjit/ujit/vecconsttable.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_UJIT_VECCONSTTABLE_H_INCLUDED
#define ASMJIT_UJIT_VECCONSTTABLE_H_INCLUDED
-#include "../core/globals.h"
+#include <asmjit/core/globals.h>
#if !defined(ASMJIT_NO_UJIT)
diff --git a/3rdparty/asmjit/src/asmjit/x86.h b/3rdparty/asmjit/asmjit/x86.h
index 9a8ceb81eec..db6c46bc717 100644
--- a/3rdparty/asmjit/src/asmjit/x86.h
+++ b/3rdparty/asmjit/asmjit/x86.h
@@ -69,16 +69,16 @@
//! - \ref x86::VReduceImm - `REDUCE[PD|PS|SD|SS]` predicate (AVX512+).
//! - \ref x86::TLogImm - `VPTERNLOG[D|Q]` predicate and operations (AVX512+).
-#include "core.h"
+#include <asmjit/core.h>
-#include "asmjit-scope-begin.h"
-#include "x86/x86assembler.h"
-#include "x86/x86builder.h"
-#include "x86/x86compiler.h"
-#include "x86/x86emitter.h"
-#include "x86/x86globals.h"
-#include "x86/x86instdb.h"
-#include "x86/x86operand.h"
-#include "asmjit-scope-end.h"
+#include <asmjit/asmjit-scope-begin.h>
+#include <asmjit/x86/x86assembler.h>
+#include <asmjit/x86/x86builder.h>
+#include <asmjit/x86/x86compiler.h>
+#include <asmjit/x86/x86emitter.h>
+#include <asmjit/x86/x86globals.h>
+#include <asmjit/x86/x86instdb.h>
+#include <asmjit/x86/x86operand.h>
+#include <asmjit/asmjit-scope-end.h>
#endif // ASMJIT_X86_H_INCLUDED
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86archtraits_p.h b/3rdparty/asmjit/asmjit/x86/x86archtraits_p.h
index dee87e4aa15..80d00c28531 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86archtraits_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86archtraits_p.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_X86_X86ARCHTRAITS_P_H_INCLUDED
#define ASMJIT_X86_X86ARCHTRAITS_P_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/misc_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86assembler.cpp b/3rdparty/asmjit/asmjit/x86/x86assembler.cpp
index e6516289561..6b9c1a4a183 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86assembler.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86assembler.cpp
@@ -3,23 +3,23 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86)
-#include "../core/assembler.h"
-#include "../core/codewriter_p.h"
-#include "../core/cpuinfo.h"
-#include "../core/emitterutils_p.h"
-#include "../core/formatter.h"
-#include "../core/logger.h"
-#include "../core/misc_p.h"
-#include "../core/support.h"
-#include "../x86/x86assembler.h"
-#include "../x86/x86emithelper_p.h"
-#include "../x86/x86instapi_p.h"
-#include "../x86/x86instdb_p.h"
-#include "../x86/x86formatter_p.h"
-#include "../x86/x86opcode_p.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/core/codewriter_p.h>
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/emitterutils_p.h>
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/logger.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/x86/x86assembler.h>
+#include <asmjit/x86/x86emithelper_p.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/x86/x86instdb_p.h>
+#include <asmjit/x86/x86formatter_p.h>
+#include <asmjit/x86/x86opcode_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -511,13 +511,15 @@ static ASMJIT_INLINE bool x86_should_use_movabs(Assembler* self, X86BufferWriter
int64_t addr_value = rm_rel.offset();
uint64_t base_address = self->code()->base_address();
+ uint64_t section_offset = self->_section->offset();
// If the address type is default, it means to basically check whether relative addressing is possible. However,
- // this is only possible when the base address is known - relative encoding uses RIP+N it has to be calculated.
- if (rm_rel.addr_type() == Mem::AddrType::kDefault && base_address != Globals::kNoBaseAddress && !rm_rel.has_segment()) {
+ // this is only possible when the base address is known as relative encoding uses RIP+N.
+ if (rm_rel.addr_type() == Mem::AddrType::kDefault && !rm_rel.has_segment() &&
+ EmitterUtils::is_absolute_location(base_address, section_offset)) {
uint32_t instruction_size = x86_get_movabs_inst_size_64bit(register_size, options, rm_rel);
uint64_t virtual_offset = uint64_t(writer.offset_from(self->_buffer_data));
- uint64_t rip64 = base_address + self->_section->offset() + virtual_offset + instruction_size;
+ uint64_t rip64 = base_address + section_offset + virtual_offset + instruction_size;
uint64_t rel64 = uint64_t(addr_value) - rip64;
if (Support::is_int_n<32>(int64_t(rel64))) {
@@ -620,7 +622,7 @@ ASMJIT_FAVOR_SPEED Error Assembler::_emit(InstId inst_id, const Operand_& o0, co
goto Failed;
}
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
// Strict validation.
if (has_diagnostic_option(DiagnosticOptions::kValidateAssembler)) {
Operand_ op_array[Globals::kMaxOpCount];
@@ -4146,12 +4148,14 @@ EmitModSib:
else {
bool is_offset_int32 = rm_rel->as<Mem>().offset_hi32() == (rel_offset >> 31);
bool is_offset_uint32 = rm_rel->as<Mem>().offset_hi32() == 0;
+
uint64_t base_address = code()->base_address();
+ uint64_t section_offset = _section->offset();
// If relative addressing was not explicitly set then we can try to guess. By guessing we check some
// properties of the memory operand and try to base the decision on the segment prefix and the address type.
if (addr_type == Mem::AddrType::kDefault) {
- if (base_address == Globals::kNoBaseAddress) {
+ if (EmitterUtils::is_absolute_location(base_address, section_offset)) {
// Prefer absolute addressing mode if the offset is 32-bit.
addr_type = is_offset_int32 || is_offset_uint32 ? Mem::AddrType::kAbs : Mem::AddrType::kRel;
}
@@ -4169,7 +4173,7 @@ EmitModSib:
uint32_t kModRel32Size = 5;
uint64_t virtual_offset = uint64_t(writer.offset_from(_buffer_data)) + imm_size + kModRel32Size;
- if (base_address == Globals::kNoBaseAddress || _section->section_id() != 0) {
+ if (!EmitterUtils::is_absolute_location(base_address, section_offset)) {
// Create a new RelocEntry as we cannot calculate the offset right now.
err = _code->new_reloc_entry(Out(re), RelocType::kAbsToRel);
if (ASMJIT_UNLIKELY(err != Error::kOk))
@@ -4188,7 +4192,7 @@ EmitModSib:
goto EmitDone;
}
else {
- uint64_t rip64 = base_address + _section->offset() + virtual_offset;
+ uint64_t rip64 = base_address + section_offset + virtual_offset;
uint64_t rel64 = uint64_t(rm_rel->as<Mem>().offset()) - rip64;
if (Support::is_int_n<32>(int64_t(rel64))) {
@@ -4855,12 +4859,13 @@ EmitJmpCall:
if (rm_rel->is_imm()) {
uint64_t base_address = code()->base_address();
+ uint64_t section_offset = _section->offset();
uint64_t jump_address = rm_rel->as<Imm>().value_as<uint64_t>();
// If the base-address is known calculate a relative displacement and check if it fits in 32 bits (which is
// always true in 32-bit mode). Emit relative displacement as it was a bound label if all checks are ok.
- if (base_address != Globals::kNoBaseAddress) {
- uint64_t rel64 = jump_address - (ip + base_address) - inst32_size;
+ if (EmitterUtils::is_absolute_location(base_address, section_offset)) {
+ uint64_t rel64 = jump_address - (ip + base_address + section_offset) - inst32_size;
if (Environment::is_32bit(arch()) || Support::is_int_n<32>(int64_t(rel64))) {
rel32 = uint32_t(rel64 & 0xFFFFFFFFu);
goto EmitJmpCallRel;
@@ -4868,14 +4873,16 @@ EmitJmpCall:
else {
// Relative displacement exceeds 32-bits - relocator can only insert trampoline for jmp/call, but not
// for jcc/jecxz.
- if (ASMJIT_UNLIKELY(!is_jmp_or_call(inst_id)))
+ if (ASMJIT_UNLIKELY(!is_jmp_or_call(inst_id))) {
goto InvalidDisplacement;
+ }
}
}
err = _code->new_reloc_entry(Out(re), RelocType::kAbsToRel);
- if (ASMJIT_UNLIKELY(err != Error::kOk))
+ if (ASMJIT_UNLIKELY(err != Error::kOk)) {
goto Failed;
+ }
re->_source_offset = offset();
re->_source_section_id = _section->section_id();
@@ -4886,28 +4893,30 @@ EmitJmpCall:
// but allows to patch the instruction to use MOD/M and to point to a memory where the final 64-bit address
// is stored.
if (Environment::is_64bit(arch()) && is_jmp_or_call(inst_id)) {
- if (!rex)
+ if (!rex) {
writer.emit8(kX86ByteRex);
+ }
err = _code->add_address_to_address_table(jump_address);
- if (ASMJIT_UNLIKELY(err != Error::kOk))
+ if (ASMJIT_UNLIKELY(err != Error::kOk)) {
goto Failed;
+ }
re->_reloc_type = RelocType::kX64AddressEntry;
}
writer.emit8_if(0x0F, (opcode & Opcode::kMM_Mask) != 0); // Emit 0F prefix.
- writer.emit8(opcode.v); // Emit opcode.
+ writer.emit8(opcode.v); // Emit opcode.
writer.emit8_if(encode_mod(3, op_reg, 0), op_reg != 0); // Emit MOD.
re->_format.reset_to_simple_value(OffsetType::kSignedOffset, 4);
re->_format.set_leading_and_trailing_size(writer.offset_from(_buffer_ptr), imm_size);
writer.emit32u_le(0); // Emit DISP32.
}
else {
- writer.emit8(opcode8); // Emit opcode.
+ writer.emit8(opcode8); // Emit opcode.
re->_format.reset_to_simple_value(OffsetType::kSignedOffset, 1);
re->_format.set_leading_and_trailing_size(writer.offset_from(_buffer_ptr), imm_size);
- writer.emit8(0); // Emit DISP8 (zero).
+ writer.emit8(0); // Emit DISP8 (zero).
}
goto EmitDone;
}
@@ -4920,17 +4929,18 @@ EmitJmpCall:
EmitJmpCallRel:
if (Support::is_int_n<8>(int32_t(rel32 + inst32_size - inst8_size)) && opcode8 && !Support::test(options, InstOptions::kLongForm)) {
options |= InstOptions::kShortForm;
- writer.emit8(opcode8); // Emit opcode
- writer.emit8(rel32 + inst32_size - inst8_size); // Emit DISP8.
+ writer.emit8(opcode8); // Emit opcode
+ writer.emit8(rel32 + inst32_size - inst8_size); // Emit DISP8.
goto EmitDone;
}
else {
- if (ASMJIT_UNLIKELY(!opcode.v || Support::test(options, InstOptions::kShortForm)))
+ if (ASMJIT_UNLIKELY(!opcode.v || Support::test(options, InstOptions::kShortForm))) {
goto InvalidDisplacement;
+ }
options &= ~InstOptions::kShortForm;
writer.emit8_if(0x0F, (opcode & Opcode::kMM_Mask) != 0); // Emit 0x0F prefix.
- writer.emit8(opcode.v); // Emit Opcode.
+ writer.emit8(opcode.v); // Emit Opcode.
writer.emit8_if(encode_mod(3, op_reg, 0), op_reg != 0); // Emit MOD.
writer.emit32u_le(rel32); // Emit DISP32.
goto EmitDone;
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86assembler.h b/3rdparty/asmjit/asmjit/x86/x86assembler.h
index e53b676f394..98e0862fa9f 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86assembler.h
+++ b/3rdparty/asmjit/asmjit/x86/x86assembler.h
@@ -6,9 +6,9 @@
#ifndef ASMJIT_X86_X86ASSEMBLER_H_INCLUDED
#define ASMJIT_X86_X86ASSEMBLER_H_INCLUDED
-#include "../core/assembler.h"
-#include "../x86/x86emitter.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/assembler.h>
+#include <asmjit/x86/x86emitter.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86builder.cpp b/3rdparty/asmjit/asmjit/x86/x86builder.cpp
index b5023fb8bfd..d7df46593ec 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86builder.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86builder.cpp
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86) && !defined(ASMJIT_NO_BUILDER)
-#include "../x86/x86assembler.h"
-#include "../x86/x86builder.h"
-#include "../x86/x86emithelper_p.h"
+#include <asmjit/x86/x86assembler.h>
+#include <asmjit/x86/x86builder.h>
+#include <asmjit/x86/x86emithelper_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86builder.h b/3rdparty/asmjit/asmjit/x86/x86builder.h
index 71fae5a15be..985e3a116f6 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86builder.h
+++ b/3rdparty/asmjit/asmjit/x86/x86builder.h
@@ -6,11 +6,11 @@
#ifndef ASMJIT_X86_X86BUILDER_H_INCLUDED
#define ASMJIT_X86_X86BUILDER_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_BUILDER
-#include "../core/builder.h"
-#include "../x86/x86emitter.h"
+#include <asmjit/core/builder.h>
+#include <asmjit/x86/x86emitter.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86compiler.cpp b/3rdparty/asmjit/asmjit/x86/x86compiler.cpp
index 0bf419061f8..bf8fb54ff57 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86compiler.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86compiler.cpp
@@ -3,13 +3,13 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86) && !defined(ASMJIT_NO_COMPILER)
-#include "../x86/x86assembler.h"
-#include "../x86/x86compiler.h"
-#include "../x86/x86instapi_p.h"
-#include "../x86/x86rapass_p.h"
+#include <asmjit/x86/x86assembler.h>
+#include <asmjit/x86/x86compiler.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/x86/x86rapass_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86compiler.h b/3rdparty/asmjit/asmjit/x86/x86compiler.h
index 245dfef9e53..c65f785da95 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86compiler.h
+++ b/3rdparty/asmjit/asmjit/x86/x86compiler.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_X86_X86COMPILER_H_INCLUDED
#define ASMJIT_X86_X86COMPILER_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/compiler.h"
-#include "../core/type.h"
-#include "../x86/x86emitter.h"
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/type.h>
+#include <asmjit/x86/x86emitter.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86emithelper.cpp b/3rdparty/asmjit/asmjit/x86/x86emithelper.cpp
index e1b8ba366fa..bb22fa41f79 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86emithelper.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86emithelper.cpp
@@ -3,19 +3,19 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86)
-#include "../core/formatter.h"
-#include "../core/funcargscontext_p.h"
-#include "../core/string.h"
-#include "../core/support.h"
-#include "../core/type.h"
-#include "../core/radefs_p.h"
-#include "../x86/x86emithelper_p.h"
-#include "../x86/x86emitter.h"
-#include "../x86/x86formatter_p.h"
-#include "../x86/x86instapi_p.h"
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/funcargscontext_p.h>
+#include <asmjit/core/string.h>
+#include <asmjit/core/type.h>
+#include <asmjit/core/radefs_p.h>
+#include <asmjit/x86/x86emithelper_p.h>
+#include <asmjit/x86/x86emitter.h>
+#include <asmjit/x86/x86formatter_p.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/support/support.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86emithelper_p.h b/3rdparty/asmjit/asmjit/x86/x86emithelper_p.h
index fb70858e46e..ac3f1b7ebc4 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86emithelper_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86emithelper_p.h
@@ -6,13 +6,13 @@
#ifndef ASMJIT_X86_X86EMITHELPER_P_H_INCLUDED
#define ASMJIT_X86_X86EMITHELPER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
-#include "../core/emithelper_p.h"
-#include "../core/func.h"
-#include "../x86/x86emitter.h"
-#include "../x86/x86instapi_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/emithelper_p.h>
+#include <asmjit/core/func.h>
+#include <asmjit/x86/x86emitter.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -106,7 +106,7 @@ public:
void init_emitter_funcs(BaseEmitter* emitter) noexcept;
static ASMJIT_INLINE void update_emitter_funcs(BaseEmitter* emitter) noexcept {
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
emitter->_funcs.validate = emitter->is_32bit() ? InstInternal::validate_x86 : InstInternal::validate_x64;
#else
Support::maybe_unused(emitter);
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86emitter.h b/3rdparty/asmjit/asmjit/x86/x86emitter.h
index 1c018afda9e..dafc961e5f1 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86emitter.h
+++ b/3rdparty/asmjit/asmjit/x86/x86emitter.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_X86_X86EMITTER_H_INCLUDED
#define ASMJIT_X86_X86EMITTER_H_INCLUDED
-#include "../core/emitter.h"
-#include "../core/support.h"
-#include "../x86/x86globals.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/emitter.h>
+#include <asmjit/support/support.h>
+#include <asmjit/x86/x86globals.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86formatter.cpp b/3rdparty/asmjit/asmjit/x86/x86formatter.cpp
index 39c554c8531..eeb13f8e605 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86formatter.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86formatter.cpp
@@ -3,20 +3,20 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86) && !defined(ASMJIT_NO_LOGGING)
-#include "../core/cpuinfo.h"
-#include "../core/formatter_p.h"
-#include "../core/misc_p.h"
-#include "../core/support.h"
-#include "../x86/x86formatter_p.h"
-#include "../x86/x86instapi_p.h"
-#include "../x86/x86instdb_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/x86/x86formatter_p.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/x86/x86instdb_p.h>
+#include <asmjit/x86/x86operand.h>
#ifndef ASMJIT_NO_COMPILER
- #include "../core/compiler.h"
+ #include <asmjit/core/compiler.h>
#endif
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86formatter_p.h b/3rdparty/asmjit/asmjit/x86/x86formatter_p.h
index 360a9b60f71..b014ea3202a 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86formatter_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86formatter_p.h
@@ -6,12 +6,12 @@
#ifndef ASMJIT_X86_X86FORMATTER_P_H_INCLUDED
#define ASMJIT_X86_X86FORMATTER_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_LOGGING
-#include "../core/formatter.h"
-#include "../core/string.h"
-#include "../x86/x86globals.h"
+#include <asmjit/core/formatter.h>
+#include <asmjit/core/string.h>
+#include <asmjit/x86/x86globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86func.cpp b/3rdparty/asmjit/asmjit/x86/x86func.cpp
index d8893a357e6..8de3f861cf8 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86func.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86func.cpp
@@ -3,12 +3,12 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86)
-#include "../x86/x86func_p.h"
-#include "../x86/x86emithelper_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/x86/x86func_p.h>
+#include <asmjit/x86/x86emithelper_p.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86func_p.h b/3rdparty/asmjit/asmjit/x86/x86func_p.h
index c3e7985e275..1249dafe55b 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86func_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86func_p.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_X86_X86FUNC_P_H_INCLUDED
#define ASMJIT_X86_X86FUNC_P_H_INCLUDED
-#include "../core/func.h"
+#include <asmjit/core/func.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86globals.h b/3rdparty/asmjit/asmjit/x86/x86globals.h
index 8de56202ccb..07c459f872c 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86globals.h
+++ b/3rdparty/asmjit/asmjit/x86/x86globals.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_X86_X86GLOBALS_H_INCLUDED
#define ASMJIT_X86_X86GLOBALS_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/inst.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/inst.h>
//! \namespace asmjit::x86
//! \ingroup asmjit_x86
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86instapi.cpp b/3rdparty/asmjit/asmjit/x86/x86instapi.cpp
index 8642e535274..29757bcc556 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86instapi.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86instapi.cpp
@@ -3,16 +3,16 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86)
-#include "../core/cpuinfo.h"
-#include "../core/instdb_p.h"
-#include "../core/misc_p.h"
-#include "../x86/x86instapi_p.h"
-#include "../x86/x86instdb_p.h"
-#include "../x86/x86opcode_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/instdb_p.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/x86/x86instdb_p.h>
+#include <asmjit/x86/x86opcode_p.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -59,7 +59,7 @@ InstId string_to_inst_id(const char* s, size_t len) noexcept {
// x86::InstInternal - Validate
// ============================
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
struct X86ValidationData {
//! Allowed registers by \ref RegType.
RegMask allowed_reg_mask[uint32_t(RegType::kMaxValue) + 1];
@@ -738,7 +738,7 @@ Error validate_x64(const BaseInst& inst, const Operand_* operands, size_t op_cou
return validate(InstDB::Mode::kX64, inst, operands, op_count, validation_flags);
}
-#endif // !ASMJIT_NO_VALIDATION
+#endif // !ASMJIT_NO_INTROSPECTION
// x86::InstInternal - QueryRWInfo
// ===============================
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86instapi_p.h b/3rdparty/asmjit/asmjit/x86/x86instapi_p.h
index cda40009081..6c1d072952e 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86instapi_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86instapi_p.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_X86_X86INSTAPI_P_H_INCLUDED
#define ASMJIT_X86_X86INSTAPI_P_H_INCLUDED
-#include "../core/inst.h"
-#include "../core/operand.h"
+#include <asmjit/core/inst.h>
+#include <asmjit/core/operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -22,12 +22,9 @@ Error ASMJIT_CDECL inst_id_to_string(InstId inst_id, InstStringifyOptions option
InstId ASMJIT_CDECL string_to_inst_id(const char* s, size_t len) noexcept;
#endif // !ASMJIT_NO_TEXT
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
Error ASMJIT_CDECL validate_x86(const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags) noexcept;
Error ASMJIT_CDECL validate_x64(const BaseInst& inst, const Operand_* operands, size_t op_count, ValidationFlags validation_flags) noexcept;
-#endif // !ASMJIT_NO_VALIDATION
-
-#ifndef ASMJIT_NO_INTROSPECTION
Error ASMJIT_CDECL query_rw_info(Arch arch, const BaseInst& inst, const Operand_* operands, size_t op_count, InstRWInfo* out) noexcept;
Error ASMJIT_CDECL query_features(Arch arch, const BaseInst& inst, const Operand_* operands, size_t op_count, CpuFeatures* out) noexcept;
#endif // !ASMJIT_NO_INTROSPECTION
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86instdb.cpp b/3rdparty/asmjit/asmjit/x86/x86instdb.cpp
index d48b77e4e10..238d6f6edc6 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86instdb.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86instdb.cpp
@@ -3,15 +3,15 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86)
-#include "../core/cpuinfo.h"
-#include "../core/misc_p.h"
-#include "../core/support.h"
-#include "../x86/x86instdb_p.h"
-#include "../x86/x86opcode_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/misc_p.h>
+#include <asmjit/support/support.h>
+#include <asmjit/x86/x86instdb_p.h>
+#include <asmjit/x86/x86opcode_p.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -4696,7 +4696,7 @@ const uint32_t InstDB::alias_index_to_inst_id_table[] = {
// x86::InstDB - InstSignature & OpSignature
// =========================================
-#ifndef ASMJIT_NO_VALIDATION
+#ifndef ASMJIT_NO_INTROSPECTION
// ${InstSignatureTable:Begin}
// ------------------- Automatically generated, do not edit -------------------
#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \
@@ -5496,7 +5496,7 @@ const InstDB::OpSignature InstDB::_op_signature_table[] = {
#undef ROW
// ----------------------------------------------------------------------------
// ${InstSignatureTable:End}
-#endif // !ASMJIT_NO_VALIDATION
+#endif // !ASMJIT_NO_INTROSPECTION
// x86::InstInternal - QueryRWInfo
// ===============================
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86instdb.h b/3rdparty/asmjit/asmjit/x86/x86instdb.h
index ff920469957..34f51a12186 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86instdb.h
+++ b/3rdparty/asmjit/asmjit/x86/x86instdb.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_X86_X86INSTDB_H_INCLUDED
#define ASMJIT_X86_X86INSTDB_H_INCLUDED
-#include "../core/span.h"
-#include "../x86/x86globals.h"
+#include <asmjit/support/span.h>
+#include <asmjit/x86/x86globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86instdb_p.h b/3rdparty/asmjit/asmjit/x86/x86instdb_p.h
index e9536cedd0a..43aa4523e9b 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86instdb_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86instdb_p.h
@@ -6,8 +6,8 @@
#ifndef ASMJIT_X86_X86INSTDB_P_H_INCLUDED
#define ASMJIT_X86_X86INSTDB_P_H_INCLUDED
-#include "../core/instdb_p.h"
-#include "../x86/x86instdb.h"
+#include <asmjit/core/instdb_p.h>
+#include <asmjit/x86/x86instdb.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86opcode_p.h b/3rdparty/asmjit/asmjit/x86/x86opcode_p.h
index 80cb3a144ef..511f70271b4 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86opcode_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86opcode_p.h
@@ -6,7 +6,7 @@
#ifndef ASMJIT_X86_X86OPCODE_P_H_INCLUDED
#define ASMJIT_X86_X86OPCODE_P_H_INCLUDED
-#include "../x86/x86globals.h"
+#include <asmjit/x86/x86globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86operand.cpp b/3rdparty/asmjit/asmjit/x86/x86operand.cpp
index 1d5f2760e5a..9a29406ad62 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86operand.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86operand.cpp
@@ -3,11 +3,11 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86)
-#include "../core/misc_p.h"
-#include "../x86/x86operand.h"
+#include <asmjit/core/misc_p.h>
+#include <asmjit/x86/x86operand.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -141,6 +141,10 @@ UNIT(x86_operand) {
EXPECT_EQ(zmm7.ymm(), ymm7);
EXPECT_EQ(zmm7.zmm(), zmm7);
+ EXPECT_EQ(xmm4.half(), xmm4);
+ EXPECT_EQ(ymm4.half(), xmm4);
+ EXPECT_EQ(zmm4.half(), ymm4);
+
INFO("Checking x86::Mm register properties");
EXPECT_TRUE(Mm().is_reg());
EXPECT_TRUE(mm2.is_reg());
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86operand.h b/3rdparty/asmjit/asmjit/x86/x86operand.h
index 52f4703b7bc..8725d8b7476 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86operand.h
+++ b/3rdparty/asmjit/asmjit/x86/x86operand.h
@@ -6,10 +6,10 @@
#ifndef ASMJIT_X86_X86OPERAND_H_INCLUDED
#define ASMJIT_X86_X86OPERAND_H_INCLUDED
-#include "../core/archtraits.h"
-#include "../core/operand.h"
-#include "../core/type.h"
-#include "../x86/x86globals.h"
+#include <asmjit/core/archtraits.h>
+#include <asmjit/core/operand.h>
+#include <asmjit/core/type.h>
+#include <asmjit/x86/x86globals.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -237,7 +237,7 @@ class Vec : public UniVec {
//! was ZMM, or XMM for whatever else input.
[[nodiscard]]
ASMJIT_INLINE_CONSTEXPR Vec half() const noexcept {
- return Vec(is_vec512() ? signature_of_t<RegType::kVec256>() : signature_of_t<RegType::kVec512>(), id());
+ return Vec(is_vec512() ? signature_of_t<RegType::kVec256>() : signature_of_t<RegType::kVec128>(), id());
}
//! \}
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86rapass.cpp b/3rdparty/asmjit/asmjit/x86/x86rapass.cpp
index 151b1f0efd0..7110b45bbb6 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86rapass.cpp
+++ b/3rdparty/asmjit/asmjit/x86/x86rapass.cpp
@@ -3,19 +3,19 @@
// See <asmjit/core.h> or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
-#include "../core/api-build_p.h"
+#include <asmjit/core/api-build_p.h>
#if !defined(ASMJIT_NO_X86) && !defined(ASMJIT_NO_COMPILER)
-#include "../core/cpuinfo.h"
-#include "../core/formatter_p.h"
-#include "../core/support.h"
-#include "../core/type.h"
-#include "../x86/x86assembler.h"
-#include "../x86/x86compiler.h"
-#include "../x86/x86instapi_p.h"
-#include "../x86/x86instdb_p.h"
-#include "../x86/x86emithelper_p.h"
-#include "../x86/x86rapass_p.h"
+#include <asmjit/core/cpuinfo.h>
+#include <asmjit/core/formatter_p.h>
+#include <asmjit/core/type.h>
+#include <asmjit/support/support.h>
+#include <asmjit/x86/x86assembler.h>
+#include <asmjit/x86/x86compiler.h>
+#include <asmjit/x86/x86instapi_p.h>
+#include <asmjit/x86/x86instdb_p.h>
+#include <asmjit/x86/x86emithelper_p.h>
+#include <asmjit/x86/x86rapass_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
@@ -785,7 +785,7 @@ Error RACFGBuilder::on_invoke(InvokeNode* invoke_node, RAInstBuilder& ib) noexce
// Setup clobbered registers.
for (RegGroup group : Support::enumerate(RegGroup::kMaxVirt)) {
- ib._clobbered[group] = Support::lsb_mask<RegMask>(_pass._phys_reg_count[group]) & ~fd.preserved_regs(group);
+ ib._clobbered[group] = Support::lsb_mask<RegMask>(_pass._phys_reg_count.get(group)) & ~fd.preserved_regs(group);
}
return Error::kOk;
diff --git a/3rdparty/asmjit/src/asmjit/x86/x86rapass_p.h b/3rdparty/asmjit/asmjit/x86/x86rapass_p.h
index 610f0a1bfc5..4dd1d5fa661 100644
--- a/3rdparty/asmjit/src/asmjit/x86/x86rapass_p.h
+++ b/3rdparty/asmjit/asmjit/x86/x86rapass_p.h
@@ -6,16 +6,16 @@
#ifndef ASMJIT_X86_X86RAPASS_P_H_INCLUDED
#define ASMJIT_X86_X86RAPASS_P_H_INCLUDED
-#include "../core/api-config.h"
+#include <asmjit/core/api-config.h>
#ifndef ASMJIT_NO_COMPILER
-#include "../core/compiler.h"
-#include "../core/racfgblock_p.h"
-#include "../core/racfgbuilder_p.h"
-#include "../core/rapass_p.h"
-#include "../x86/x86assembler.h"
-#include "../x86/x86compiler.h"
-#include "../x86/x86emithelper_p.h"
+#include <asmjit/core/compiler.h>
+#include <asmjit/core/racfgblock_p.h>
+#include <asmjit/core/racfgbuilder_p.h>
+#include <asmjit/core/rapass_p.h>
+#include <asmjit/x86/x86assembler.h>
+#include <asmjit/x86/x86compiler.h>
+#include <asmjit/x86/x86emithelper_p.h>
ASMJIT_BEGIN_SUB_NAMESPACE(x86)
diff --git a/3rdparty/asmjit/configure.sh b/3rdparty/asmjit/configure.sh
index 659d6dc8c72..3f9b1d6b88b 100644
--- a/3rdparty/asmjit/configure.sh
+++ b/3rdparty/asmjit/configure.sh
@@ -1,11 +1,9 @@
-#!/bin/sh
+#!/bin/bash
-BUILD_OPTIONS="-DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DASMJIT_TEST=1"
-
-echo "== [Configuring Build - Debug] =="
-eval cmake . -B build/Debug -DCMAKE_BUILD_TYPE=Debug ${BUILD_OPTIONS} "$@"
+echo "== [configure debug] =="
+cmake --preset debug "$@"
echo ""
-echo "== [Configuring Build - Release] =="
-eval cmake . -B build/Release -DCMAKE_BUILD_TYPE=Release ${BUILD_OPTIONS} "$@"
+echo "== [configure release] =="
+cmake --preset release "$@"
echo ""
diff --git a/3rdparty/asmjit/configure_sanitizers.sh b/3rdparty/asmjit/configure_sanitizers.sh
index 2634bcdf57e..defd80f959e 100644
--- a/3rdparty/asmjit/configure_sanitizers.sh
+++ b/3rdparty/asmjit/configure_sanitizers.sh
@@ -1,15 +1,13 @@
-#!/bin/sh
+#!/bin/bash
-BUILD_OPTIONS="-DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DASMJIT_TEST=1"
-
-echo "== [Configuring Build - Release_ASAN] =="
-eval cmake . -B build/Release_ASAN ${BUILD_OPTIONS} -DCMAKE_BUILD_TYPE=Release -DASMJIT_SANITIZE=address "$@"
+echo "== [configure release-asan] =="
+cmake --preset release-asan "$@"
echo ""
-echo "== [Configuring Build - Release_MSAN] =="
-eval cmake . -B build/Release_MSAN ${BUILD_OPTIONS} -DCMAKE_BUILD_TYPE=Release -DASMJIT_SANITIZE=memory "$@"
+echo "== [configure release-msan] =="
+cmake --preset release-msan "$@"
echo ""
-echo "== [Configuring Build - Release_UBSAN] =="
-eval cmake . -B build/Release_UBSAN ${BUILD_OPTIONS} -DCMAKE_BUILD_TYPE=Release -DASMJIT_SANITIZE=undefined "$@"
+echo "== [configure release-ubsan] =="
+cmake --preset release-ubsan "$@"
echo ""
diff --git a/3rdparty/asmjit/db/LICENSE.md b/3rdparty/asmjit/db/LICENSE.md
new file mode 100644
index 00000000000..e01395cd5cf
--- /dev/null
+++ b/3rdparty/asmjit/db/LICENSE.md
@@ -0,0 +1,17 @@
+Copyright (c) 2008-2025 The AsmJit Authors
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, subject to the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not
+ claim that you wrote the original software. If you use this software
+ in a product, an acknowledgment in the product documentation would be
+ appreciated but is not required.
+2. Altered source versions must be plainly marked as such, and must not be
+ misrepresented as being the original software.
+3. This notice may not be removed or altered from any source distribution.
diff --git a/3rdparty/asmjit/db/README.md b/3rdparty/asmjit/db/README.md
new file mode 100644
index 00000000000..faddd94822d
--- /dev/null
+++ b/3rdparty/asmjit/db/README.md
@@ -0,0 +1,21 @@
+AsmJit Instruction Database
+---------------------------
+
+This is a database of instructions that is used by AsmJit to generate its internal database and also assembler implementations. This project started initially as AsmDB, but was merged to AsmJit later to make the maintenance easier. The database was created in a way so that each instruction definition would only need a single line in JSON data file. The data is then processed by architecture specific data readers that make the data canonical and ready for processing.
+
+AsmJit database provides the following ISAs:
+
+ * `isa_x86.json` - provides X86 instruction data (both 32-bit and 64-bit)
+ * `isa_aarch32.json` - provides AArch32 instruction data (A32/T16/T32 encoding)
+ * `isa_aarch64.json` - provides AArch64 instruction data (A64 encoding)
+ * `isa_aarch64_sme.json` - provides AArch64 SME instruction data (work-in-progress)
+
+To Be Documented
+----------------
+
+This project will be refactored and documented in the future.
+
+License
+-------
+
+AsmJit database is licensed under [Zlib License](./LICENSE.md)
diff --git a/3rdparty/asmjit/db/aarch32.js b/3rdparty/asmjit/db/aarch32.js
new file mode 100644
index 00000000000..6f9d61651e0
--- /dev/null
+++ b/3rdparty/asmjit/db/aarch32.js
@@ -0,0 +1,987 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See <asmjit/core.h> or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+(function($scope, $as) {
+"use strict";
+
+function FAIL(msg) { throw new Error("[AArch32] " + msg); }
+
+// Import
+// ======
+
+const base = $scope.base ? $scope.base : require("./base.js");
+const exp = $scope.exp ? $scope.exp : require("./exp.js")
+
+const dict = base.dict;
+const NONE = base.NONE;
+const Parsing = base.Parsing;
+const MapUtils = base.MapUtils;
+
+// Export
+// ======
+
+const arm = $scope[$as] = dict();
+
+// Database
+// ========
+
+arm.dbName = "isa_aarch32.json";
+
+// asmdb.aarch32.Utils
+// ===================
+
+// Can be used to assign the number of bits each part of the opcode occupies.
+// NOTE: THUMB instructions that use halfword must always specify the width
+// of all registers as many instructions accept only LO (r0..r7) registers.
+const FieldInfo = {
+ "P" : { "bits": 1 },
+ "U" : { "bits": 1 },
+ "W" : { "bits": 1 },
+ "S" : { "bits": 1 },
+ "R" : { "bits": 1 },
+ "H" : { "bits": 1 },
+ "isFp32": { "bits": 1 },
+ "F" : { "bits": 1 },
+ "align" : { "bits": 2 },
+ "ja" : { "bits": 1 },
+ "jb" : { "bits": 1 },
+ "op" : { "bits": 1 }, // TODO: This should be fixed.
+ "sz" : { "bits": 2 },
+ "sop" : { "bits": 2 },
+ "cond" : { "bits": 4 },
+ "cmode" : { "bits": 4 },
+ "Cn" : { "bits": 4 },
+ "Cm" : { "bits": 4 },
+
+ "Rd" : { "bits": 4, "read": false, "write": true },
+ "Rd2" : { "bits": 4, "read": false, "write": true },
+ "RdLo" : { "bits": 4, "read": false, "write": true },
+ "RdHi" : { "bits": 4, "read": false, "write": true },
+ "RdList": { "bits": 4, "read": false, "write": true , "list": true },
+ "Rx" : { "bits": 4, "read": true , "write": true },
+ "RxLo" : { "bits": 4, "read": true , "write": true },
+ "RxHi" : { "bits": 4, "read": true , "write": true },
+ "Rn" : { "bits": 4, "read": true , "write": false },
+ "Rm" : { "bits": 4, "read": true , "write": false },
+ "Ra" : { "bits": 4, "read": true , "write": false },
+ "Rs" : { "bits": 4, "read": true , "write": false },
+ "Rs2" : { "bits": 4, "read": true , "write": false },
+ "RsList": { "bits": 4, "read": true , "write": false , "list": true },
+
+ "Sd" : { "bits": 4, "read": false, "write": true },
+ "Sd2" : { "bits": 4, "read": false, "write": true },
+ "SdList": { "bits": 4, "read": false, "write": true , "list": true },
+ "Sx" : { "bits": 4, "read": true , "write": true },
+ "Sn" : { "bits": 4, "read": true , "write": false },
+ "Sm" : { "bits": 4, "read": true , "write": false },
+ "Ss" : { "bits": 4, "read": true , "write": false },
+ "Ss2" : { "bits": 4, "read": true , "write": false },
+ "SsList": { "bits": 4, "read": true , "write": false , "list": true },
+
+ "Dd" : { "bits": 4, "read": false, "write": true },
+ "Dd2" : { "bits": 4, "read": false, "write": true },
+ "Dd3" : { "bits": 4, "read": false, "write": true },
+ "Dd4" : { "bits": 4, "read": false, "write": true },
+ "DdList": { "bits": 4, "read": false, "write": true , "list": true },
+ "Dx" : { "bits": 4, "read": true , "write": true },
+ "Dx2" : { "bits": 4, "read": true , "write": true },
+ "Dn" : { "bits": 4, "read": true , "write": false },
+ "Dn2" : { "bits": 4, "read": true , "write": false },
+ "Dn3" : { "bits": 4, "read": true , "write": false },
+ "Dn4" : { "bits": 4, "read": true , "write": false },
+ "Dm" : { "bits": 4, "read": true , "write": false },
+ "Ds" : { "bits": 4, "read": true , "write": false },
+ "Ds2" : { "bits": 4, "read": true , "write": false },
+ "Ds3" : { "bits": 4, "read": true , "write": false },
+ "Ds4" : { "bits": 4, "read": true , "write": false },
+ "DsList": { "bits": 4, "read": true , "write": false , "list": true },
+
+ "Vd" : { "bits": 4, "read": false, "write": true },
+ "Vd2" : { "bits": 4, "read": false, "write": true },
+ "Vd3" : { "bits": 4, "read": false, "write": true },
+ "Vd4" : { "bits": 4, "read": false, "write": true },
+ "Vx" : { "bits": 4, "read": true , "write": true },
+ "Vx2" : { "bits": 4, "read": true , "write": true },
+ "Vn" : { "bits": 4, "read": true , "write": false },
+ "Vm" : { "bits": 4, "read": true , "write": false },
+ "Vs" : { "bits": 4, "read": true , "write": false },
+ "Vs2" : { "bits": 4, "read": true , "write": false },
+};
+
+arm.FieldInfo = FieldInfo;
+
+// ARM utilities.
+class Utils {
+ static splitInstructionSignature(s) {
+ const names = s.match(/^[\w\|]+/)[0];
+ s = s.substring(names.length);
+
+ const opOffset = s.indexOf(" ")
+ const suffix = s.substring(0, opOffset).trim();
+ const operands = opOffset === -1 ? "" : s.substring(opOffset + 1).trim();
+
+ return {
+ names: names.split("|").map((base)=>{ return base + suffix}),
+ operands: operands
+ }
+ }
+
+ static parseShiftOp(s) {
+ const m = s.match(/^(sop|lsl_or_asr|lsl|lsr|asr|ror|rrx) /);
+ return m ? m[1] : "";
+ }
+
+ static parseDtArray(s) {
+ const out = [];
+ if (!s) return out;
+
+ const arr = s.split("|");
+ let i;
+
+ // First expand anything between X-Y, for example s8-32 would be expanded to [s8, s16, s32].
+ for (i = 0; i < arr.length; i++) {
+ const v = arr[i];
+
+ if (v.indexOf("-") !== -1) {
+ const m = /^([A-Za-z]+)?(\d+)-(\d+)$/.exec(v);
+ if (!m)
+ FAIL(`Couldn't parse '${s}' data-type`);
+
+ let type = m[1] || "";
+ let size = parseInt(m[2], 10);
+ let last = parseInt(m[3], 10);
+
+ if (!Utils.checkDtSize(size) || !Utils.checkDtSize(last))
+ FAIL(`Invalid dt width in '${s}'`);
+
+ do {
+ out.push(type + String(size));
+ size <<= 1;
+ } while (size <= last);
+ }
+ else {
+ out.push(v);
+ }
+ }
+
+ // Now expand 'x' to 's' and 'u'.
+ i = 0;
+ while (i < out.length) {
+ const v = out[i];
+ if (v.startsWith("x")) {
+ out.splice(i, 1, "s" + v.substr(1), "u" + v.substr(1));
+ i += 2;
+ }
+ else {
+ i++;
+ }
+ }
+
+ return out;
+ }
+
+ static checkDtSize(x) {
+ return x === 8 || x === 16 || x === 32 || x === 64;
+ }
+}
+arm.Utils = Utils;
+
+function normalizeNumber(n) {
+ return n < 0 ? 0x100000000 + n : n;
+}
+
+function decomposeOperand(s) {
+ const elementSuffix = "[#i]";
+ let element = null;
+ let consecutive = 0;
+ let userRegList = false;
+
+ if (s.endsWith("^")) {
+ userRegList = true;
+ s = s.substring(0, s.length - 1);
+ }
+
+ if (s.endsWith(elementSuffix)) {
+ element = "#i";
+ s = s.substring(0, s.length - elementSuffix.length);
+ }
+
+ if (s.endsWith("++")) {
+ consecutive = 2;
+ s = s.substr(0, s.length - 2);
+ }
+ else if (s.endsWith("+")) {
+ consecutive = 1;
+ s = s.substr(0, s.length - 1);
+ }
+
+ let m = s.match(/==|\!=|>=|<=|\*/);
+ let restrict = false;
+
+ if (m) {
+ restrict = s.substr(m.index);
+ s = s.substr(0, m.index);
+ }
+
+ return {
+ data : s,
+ element : element,
+ restrict: restrict,
+ consecutive: consecutive,
+ userRegList: true
+ };
+}
+
+function splitOpcodeFields(s) {
+ const arr = s.split("|");
+ const out = [];
+
+ for (let i = 0; i < arr.length; i++) {
+ const val = arr[i];
+ if (/^[0-1A-Z]{2,}$/.test(val))
+ out.push.apply(out, val.match(/([0-1]+)|[A-Z]/g));
+ else
+ out.push(val);
+ }
+
+ return out.map((field) => { return field.trim(); });
+}
+
+// asmdb.aarch32.Operand
+// =====================
+
+// ARM operand.
+class Operand extends base.Operand {
+ constructor(def) {
+ super();
+ this.data = def;
+ }
+
+ hasMemModes() {
+ return Object.keys(this.memModes).length !== 0;
+ }
+
+ get name() {
+ switch (this.type) {
+ case "reg": return this.reg;
+ case "mem": return this.mem;
+ case "imm": return this.imm;
+ case "rel": return this.rel;
+ default : return "";
+ }
+ }
+
+ get scale() {
+ if (this.restrict && this.restrict.startsWith("*"))
+ return parseInt(this.restrict.substr(1), 10);
+ else
+ return 0;
+ }
+
+ isRelative() {
+ if (this.type === "imm")
+ return this.name === "relA" || this.name === "relS" || this.name === "relZ";
+ else
+ return false;
+ }
+}
+arm.Operand = Operand;
+
+// asmdb.aarch32.Instruction
+// =========================
+
+function patternFromOperand(key) {
+ return key;
+ // return key.replace(/\b(?:[RVDS](?:d|s|n|m|x|x2))\b/, "R");
+}
+
+// Rewrite a memory operand expression (either base or index) to a simplified one, which is okay
+// to be generated as C++ expression. In general, we want to simplify != to a more favorable code.
+function simplifyMemoryExpression(e) {
+ if (e.type === "binary" && e.op === "!=" && e.right.type === "var") {
+ // Rewrite A != PC to A < PC
+ if (e.right.name === "PC") { e.op = "<"; }
+
+ // Rewrite A != HI to A < 8
+ if (e.right.name === "HI") { e.op = "<"; e.right = exp.Imm(8); }
+
+ // Rewrite A != XX to A < SP || A == LR
+ if (e.right.name === "XX") {
+ return exp.Or(exp.Lt(e.left, exp.Var("SP")),
+ exp.Eq(e.left.clone(), exp.Var("LR")));
+ }
+ }
+
+ return e;
+}
+
+// ARM instruction.
+class Instruction extends base.Instruction {
+ constructor(db, data) {
+ super(db, data);
+ // name, operands, encoding, opcode, metadata
+
+ const encoding = Object.hasOwn(data, "a32") ? "a32" :
+ Object.hasOwn(data, "t32") ? "t32" :
+ Object.hasOwn(data, "t16") ? "t16" : "";
+
+ this.name = data.name;
+ this.it = dict(); // THUMB's 'it' flags.
+ this.apsr = dict();
+ this.fpcsr = dict();
+ this.calc = dict(); // Calculations required to generate opcode.
+ this.immCond = []; // Immediate value conditions (array of conditions).
+
+ this.s = null; // Instruction S flag (null, true, or false).
+ this.dt = []; // Instruction <dt> field (first data-type).
+ this.dt2 = []; // Instruction <dt2> field (second data-type).
+
+ this.availableFrom = ""; // Instruction supported by from ARMv???.
+ this.availableUntil = ""; // Instruction supported by until ARMv???.
+
+ this._assignOperands(data.operands);
+ this._assignEncoding(encoding.toUpperCase());
+ this._assignOpcode(data[encoding]);
+
+ for (let k in data) {
+ if (k === "name" || k == encoding || k === "operands")
+ continue;
+ this._assignAttribute(k, data[k]);
+ }
+
+ this._updateOperandsInfo();
+ this._postProcess();
+ }
+
+ _assignAttribute(key, value) {
+ switch (key) {
+ case "it":
+ for (let it of value.split(" "))
+ this.it[it.trim()] = true;
+ break;
+
+ case "apsr":
+ case "fpcsr":
+ this._assignAttributeKeyValue(key, value);
+ break;
+
+ case "imm":
+ this.imm = exp.parse(value);
+ break;
+
+ case "calc":
+ for (let calcKey in value)
+ this.calc[calcKey] = exp.parse(value[calcKey]);
+ break;
+
+ default:
+ super._assignAttribute(key, value);
+ }
+ }
+
+ _assignAttributeKeyValue(name, content) {
+ const attributes = content.trim().split(/[ ]+/);
+
+ for (let i = 0; i < attributes.length; i++) {
+ const attr = attributes[i].trim();
+ if (!attr)
+ continue;
+
+ const eq = attr.indexOf("=");
+ let key = eq === -1 ? attr : attr.substr(0, eq);
+ let val = eq === -1 ? true : attr.substr(eq + 1);
+
+ // If the key contains "|" it's a definition of multiple attributes.
+ if (key.indexOf("|") !== -1) {
+ const dot = key.indexOf(".");
+
+ const base = dot === -1 ? "" : key.substr(0, dot + 1);
+ const keys = (dot === -1 ? key : key.substr(dot + 1)).split("|");
+
+ for (let j = 0; j < keys.length; j++)
+ this[name][base + keys[j]] = val;
+ }
+ else {
+ this[name][key] = val;
+ }
+ }
+ }
+
+ _assignEncoding(s) {
+ this.arch = s === "T16" || s === "T32" ? "THUMB" : "ARM";
+ this.encoding = s;
+ }
+
+ _assignOperands(s) {
+ if (!s) return;
+
+ // Split into individual operands and push them to `operands`.
+ const arr = base.Parsing.splitOperands(s);
+ for (let i = 0; i < arr.length; i++) {
+ let def = arr[i];
+ const op = new Operand(def);
+
+ const consecutive = def.match(/(\d+)x\{(.*)\}([+][+]?)/);
+ if (consecutive)
+ def = consecutive[2];
+
+ op.sign = false;
+ op.element = null;
+ op.shiftOp = "";
+ op.shiftImm = null;
+
+ // Handle {optional} attribute.
+ if (Parsing.isOptional(def)) {
+ op.optional = true;
+ def = Parsing.clearOptional(def);
+ }
+
+ // Handle commutativity <-> symbol.
+ if (Parsing.isCommutative(def)) {
+ op.commutative = true;
+ def = Parsing.clearCommutative(def);
+ }
+
+ // Handle shift operation.
+ let shiftOp = Utils.parseShiftOp(def);
+ if (shiftOp) {
+ op.shiftOp = shiftOp;
+ def = def.substring(shiftOp.length + 1);
+ }
+
+ if (def.startsWith("[")) {
+ op.type = "mem";
+ op.memModes = dict();
+
+ op.base = null;
+ op.index = null;
+ op.offset = null;
+
+ let mem = def;
+ let didHaveMemMode = false;
+
+ for (;;) {
+ if (mem.endsWith("!")) {
+ op.memModes.preIndex = true;
+ mem = mem.substring(0, mem.length - 1);
+
+ didHaveMemMode = true;
+ break;
+ }
+
+ if (mem.endsWith("@")) {
+ op.memModes.postIndex = true;
+ mem = mem.substring(0, mem.length - 1);
+
+ didHaveMemMode = true;
+ break;
+ }
+
+ if (mem.endsWith("{!}")) {
+ op.memModes.offset = true;
+ op.memModes.preIndex = true;
+ mem = mem.substring(0, mem.length - 3);
+
+ didHaveMemMode = true;
+ continue;
+ }
+
+ if (mem.endsWith("{@}")) {
+ op.memModes.offset = true;
+ op.memModes.postIndex = true;
+ mem = mem.substring(0, mem.length - 3);
+
+ didHaveMemMode = true;
+ continue;
+ }
+
+ break;
+ }
+
+ if (!mem.endsWith("]"))
+ FAIL(`Unknown memory operand '${mem}' in '${def}'`);
+
+ let parts = mem.substring(1, mem.length - 1).split(",").map(function(s) { return s.trim() });
+ for (let i = 0; i < parts.length; i++) {
+ const part = parts[i];
+
+ const m = part.match(/^\{(lsl|sop)\s+#(\w+)\}$/);
+ if (m) {
+ op.shiftOp = m[1];
+ op.shiftImm = m[2];
+ continue;
+ }
+
+ if (i === 0) {
+ op.base = dict();
+ op.base.field = part;
+ op.base.exp = null;
+
+ const m = part.match(/^([A-Za-z]\w*)/);
+ if (m.length < part.length) {
+ op.base.exp = simplifyMemoryExpression(exp.parse(part));
+ op.base.field = m[1];
+ }
+ }
+ else if (part.startsWith("#")) {
+ let p = part.substring(1);
+ let u = "1";
+ let alwaysNegative = false;
+
+ let offExp = null;
+ let offMul = 1;
+
+ if (p.startsWith("+/-")) {
+ u = "U";
+ p = p.substring(3);
+ }
+
+ if (p.startsWith("-")) {
+ alwaysNegative = false;
+ p = p.substring(1);
+ }
+
+ const expMatch = p.match(/^([A-Za-z]\w*)==/);
+ if (expMatch) {
+ offExp = exp.parse(p);
+ p = p.substr(0, expMatch[1].length);
+ }
+
+ const mulMatch = p.match(/\s*\*\s*(\d+)$/);
+ if (mulMatch) {
+ offMul = parseInt(mulMatch[1]);
+ p = p.substr(0, mulMatch.index);
+ }
+
+ op.offset = dict();
+ op.offset.field = p;
+ op.offset.u = u;
+ op.offset.exp = offExp;
+ op.offset.mul = offMul;
+ op.offset.negative = alwaysNegative;
+ }
+ else {
+ let p = part;
+ let u = "1";
+
+ if (p.startsWith("+/-")) {
+ u = "U";
+ p = p.substring(3);
+ }
+
+ op.index = dict();
+ op.index.field = p;
+ op.index.u = u;
+
+ const m = p.match(/^([A-Za-z]\w*)/);
+ if (m.length < p.length) {
+ op.index.exp = simplifyMemoryExpression(exp.parse(p));
+ op.index.field = m[1];
+ }
+ }
+ }
+
+ if (!op.hasMemModes() && (op.offset || op.index))
+ op.memModes.offset = true;
+
+ op.mem = mem;
+ }
+ else if (def.startsWith("#")) {
+ const obj = decomposeOperand(def);
+ const imm = obj.data;
+
+ op.type = "imm";
+ op.imm = imm.substring(1); // Immediate operand name.
+ op.immSize = 0; // Immediate size in bits.
+ op.restrict = obj.restrict; // Immediate condition.
+ }
+ else {
+ const obj = decomposeOperand(def);
+ const reg = obj.data;
+
+ const type = reg.substr(0, 1).toLowerCase();
+ const info = FieldInfo[reg];
+
+ if (!info)
+ FAIL(`Unknown register operand '${reg}' in '${def}'`);
+
+ op.type = info.list ? "reg-list" : "reg";
+ op.reg = reg; // Register name (as specified in manual).
+ op.regType = type; // Register type.
+ op.regList = !!info.list; // Register list.
+ op.read = info.read; // Register access (read).
+ op.write = info.write; // Register access (write).
+ op.element = obj.element; // Register element[] access.
+ op.restrict = obj.restrict; // Register condition.
+ op.consecutive = obj.consecutive;
+ }
+
+ this.operands.push(op);
+
+ if (consecutive) {
+ const count = parseInt(consecutive[1]);
+ for (let n = 2; n <= count; n++) {
+ const def = consecutive[3].replace(op.reg, op.reg + n);
+ const opN = new Operand(def);
+ opN.type = "reg";
+ opN.reg = op.reg + n;
+ opN.regType = op.regType;
+ opN.read = op.read;
+ opN.write = op.write;
+ opN.element = op.element;
+ opN.consecutive = consecutive[3].length;
+ this.operands.push(opN);
+ }
+ }
+ }
+ }
+
+ _assignOpcode(s) {
+ this.opcodeString = s;
+
+ let opcodeIndex = 0;
+ let opcodeValue = 0;
+
+ let patternMap = {};
+
+ // Split opcode into its fields.
+ const arr = splitOpcodeFields(s);
+ const dup = dict();
+
+ const fields = this.fields;
+ const pattern = [];
+
+ const fieldMap = Object.create(null);
+ for (let field of arr) {
+ fieldMap[field] = true;
+ }
+
+ for (let i = arr.length - 1; i >= 0; i--) {
+ let key = arr[i];
+ let m;
+
+ if (/^[0-1]+$/.test(key)) {
+ // This part of the opcode is RAW bits, they contribute to the `opcodeValue`.
+ opcodeValue |= parseInt(key, 2) << opcodeIndex;
+ opcodeIndex += key.length;
+ pattern.unshift("_".repeat(key.length));
+ }
+ else {
+ pattern.unshift(patternFromOperand(key));
+ patternMap[patternFromOperand(key)] = true;
+
+ let size = 0;
+ let mask = 0;
+ let bits = 0;
+ let from = -1;
+
+ let lbit = key.startsWith("'");
+ let hbit = key.endsWith("'");
+
+ if ((m = key.match(/\[\s*(\d+)\s*\:\s*(\d+)\s*\]$/))) {
+ const a = parseInt(m[1], 10);
+ const b = parseInt(m[2], 10);
+ if (a < b)
+ FAIL(`Invalid bit range '${key}' in opcode '${s}'`);
+ from = b;
+ size = a - b + 1;
+ mask = ((1 << size) - 1) << b;
+ key = key.substr(0, m.index).trim();
+ }
+ else if ((m = key.match(/\[\s*(\d+)\s*\]$/))) {
+ from = parseInt(m[1], 10);
+ size = 1;
+ mask = 1 << from;
+ key = key.substr(0, m.index).trim();
+ }
+ else if ((m = key.match(/\:\s*(\d+)$/))) {
+ size = parseInt(m[1], 10);
+ bits = size;
+ key = key.substr(0, m.index).trim();
+ }
+ else {
+ const key_ = key;
+
+ if (lbit || hbit) {
+ from = 0;
+
+ if (lbit && hbit)
+ FAIL(`Couldn't recognize the format of '${key}' in opcode '${s}'`);
+
+ if (lbit) {
+ key = key.substring(1);
+ }
+
+ if (hbit) {
+ key = key.substring(0, key.length - 1);
+ from = 4;
+ }
+
+ size = 1;
+ }
+ else if (FieldInfo[key]) {
+ // Sizes of some standard fields can be assigned automatically.
+ size = FieldInfo[key].bits;
+ bits = size;
+
+ if (fieldMap["'" + key])
+ from = 1;
+ }
+ else if (key.length === 1) {
+ // Sizes of one-letter fields (like 'U', 'F', etc...) is 1 if not specified.
+ size = 1;
+ bits = 1;
+ }
+ else {
+ FAIL(`Couldn't recognize the size of '${key}' in opcode '${s}'`);
+ }
+
+ if (dup[key_] === true) {
+ bits = 0;
+ lbit = 0;
+ hbit = 0;
+ }
+ else {
+ dup[key_] = true;
+ }
+ }
+
+ let field = fields[key];
+ if (!field) {
+ field = {
+ index: opcodeIndex,
+ values: [],
+ bits: 0,
+ mask: 0,
+ lbit: 0,
+ hbit: 0 // Only 1 if a single quote (') was used.
+ }
+ fields[key] = field;
+ }
+
+ if (from === -1)
+ from = field.bits;
+
+ field.mask |= mask;
+ field.bits += bits;
+ field.lbit += lbit;
+ field.hbit += hbit;
+ field.values.push({
+ index: opcodeIndex,
+ from: from,
+ size: size
+ });
+
+ opcodeIndex += size;
+ }
+ }
+
+ for (let i = 0; i < pattern.length; i++)
+ if (pattern[i] === 'U')
+ pattern[i] = "_";
+
+ // Normalize all fields.
+ for (let key in fields) {
+ const field = fields[key];
+
+ // There should be either number of bits or mask, there shouldn't be both.
+ if (!field.bits && !field.mask)
+ FAIL(`Part '${key}' of opcode '${s}' contains neither size nor mask`);
+
+ if (field.bits && field.mask)
+ FAIL(`Part '${key}' of opcode '${s}' contains both size and mask`);
+
+ if (field.bits)
+ field.mask = ((1 << field.bits) - 1);
+ else if (field.mask)
+ field.bits = 32 - Math.clz32(field.mask);
+
+ // Handle field that used single-quote.
+ if (field.lbit) {
+ field.mask = (field.mask << 1) | 0x1;
+ field.bits++;
+ }
+
+ if (field.hbit) {
+ field.mask |= 1 << field.bits;
+ field.bits++;
+ }
+
+ const op = this.operandByName(key);
+ if (op && op.isImm())
+ op.immSize = field.bits;
+ }
+
+ // Check if the opcode value has the correct number of bits (either 16 or 32).
+ if (opcodeIndex !== 16 && opcodeIndex !== 32)
+ FAIL(`The number of bits '${opcodeIndex}' used by the opcode '${s}' doesn't match 16 or 32`);
+ this.opcodeValue = normalizeNumber(opcodeValue);
+ }
+
+ _assignSpecificAttribute(key, value) {
+ // Support ARMv?+ and ARMv?- attributes.
+ if (/^ARM\w+[+-]$/.test(key)) {
+ const armv = key.substr(0, key.length - 1);
+ const sign = key.substr(key.length - 1);
+
+ if (sign === "+")
+ this.availableFrom = armv;
+ else
+ this.availableUntil = armv;
+ return true;
+ }
+
+ switch (key) {
+ case "it": {
+ const values = String(value).split("|");
+ for (let i = 0; i < values.length; i++) {
+ const value = values[i];
+ switch (value) {
+ case "in" : this.it.IN = true; break;
+ case "out" : this.it.OUT = true; break;
+ case "any" : this.it.IN = true;
+ this.it.OUT = true; break;
+ case "last": this.it.LAST = true; break;
+ case "def" : this.it.DEF = true; break;
+ default:
+ this.report(`${this.name}: Unhandled IT value '${value}'`);
+ }
+ }
+ return true;
+ }
+ }
+
+ return false;
+ }
+
+ // ARM instruction name could consist of name and optional type information
+ // specified as <dt> and <dt2> in ARM manuals. We parse this information and
+ // store it to `dt` and `dt2` fields. In addition, we also recognize the `S`
+ // suffix (uppercase) of the instruction and mark it as `S` instruction. After
+ // that the name is normalized to be lowercased.
+ //
+ // This functionality requires all the instruction data to be already set-up.
+ _postProcess() {
+ let s = this.name;
+
+ // Parse <dt> and <dt2> fields.
+ if (s.indexOf(".") !== -1) {
+ const parts = s.split(".");
+ this.name = parts[0];
+
+ if (parts.length > 3)
+ FAIL(`Couldn't recognize name attributes of '${s}'`);
+
+ for (let i = 1; i < parts.length; i++) {
+ const dt = Utils.parseDtArray(parts[i]);
+ if (i === 1)
+ this.dt = dt;
+ else
+ this.dt2 = dt;
+ }
+ }
+
+ // Recognize "S" suffix.
+ if (this.name.endsWith("S")) {
+ this.name = this.name.substr(0, this.name.length - 1) + "s";
+ this.s = true;
+ }
+
+ this.dt.sort();
+ }
+
+ operandByName(name) {
+ const operands = this.operands;
+ for (let i = 0; i < operands.length; i++) {
+ const op = operands[i];
+ if (op.name === name)
+ return op;
+ }
+ return null;
+ }
+}
+arm.Instruction = Instruction;
+
+// asmdb.aarch32.ISA
+// =================
+
+function mergeGroupData(data, group) {
+ for (let k in group) {
+ switch (k) {
+ case "group":
+ case "data":
+ break;
+
+ case "ext":
+ data[k] = (data[k] ? data[k] + " " : "") + group[k];
+ break;
+
+ default:
+ if (data[k] === undefined)
+ data[k] = group[k]
+ break;
+ }
+ }
+}
+
+class ISA extends base.ISA {
+ constructor(data) {
+ super(data);
+ this.addData(data || NONE);
+ }
+
+ _addInstructions(groups) {
+ for (let group of groups) {
+ for (let inst of group.data) {
+ const sgn = Utils.splitInstructionSignature(inst.inst);
+ const data = MapUtils.cloneExcept(inst, { "inst": true });
+
+ mergeGroupData(data, group)
+
+ for (let j = 0; j < sgn.names.length; j++) {
+ data.name = sgn.names[j];
+ data.operands = sgn.operands;
+ if (j > 0)
+ data.aliasOf = sgn.names[0];
+ this._addInstruction(new Instruction(this, data));
+ }
+ }
+ }
+
+ return this;
+ }
+/*
+ _addInstructions(instructions) {
+ for (let i = 0; i < instructions.length; i++) {
+ const obj = instructions[i];
+ const sgn = obj.inst;
+ const sep = sgn.indexOf(" ");
+
+ const names = (sep !== -1 ? sgn.substring(0, sep) : sgn).trim().split("/");
+ const operands = sep !== -1 ? sgn.substring(sep + 1) : "";
+
+ const encoding = Object.hasOwn(obj, "a32") ? "a32" :
+ Object.hasOwn(obj, "t32") ? "t32" :
+ Object.hasOwn(obj, "t16") ? "t16" : "";
+
+ if (!encoding)
+ FAIL(`Instruction ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`);
+
+ for (let j = 0; j < names.length; j++) {
+ const inst = new Instruction(this, names[j], operands, encoding.toUpperCase(), obj[encoding], obj);
+ if (j > 0)
+ inst.aliasOf = names[0];
+ this._addInstruction(inst);
+ }
+ }
+
+ return this;
+ }
+*/
+}
+arm.ISA = ISA;
+
+}).apply(this, typeof module === "object" && module && module.exports
+ ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "aarch32"]);
diff --git a/3rdparty/asmjit/db/aarch64.js b/3rdparty/asmjit/db/aarch64.js
new file mode 100644
index 00000000000..af3b623c1af
--- /dev/null
+++ b/3rdparty/asmjit/db/aarch64.js
@@ -0,0 +1,920 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See <asmjit/core.h> or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+(function($scope, $as) {
+"use strict";
+
+function FAIL(msg) { throw new Error("[AArch64] " + msg); }
+
+// Import
+// ======
+
+const base = $scope.base ? $scope.base : require("./base.js");
+const exp = $scope.exp ? $scope.exp : require("./exp.js")
+
+const dict = base.dict;
+const NONE = base.NONE;
+const Parsing = base.Parsing;
+const MapUtils = base.MapUtils;
+
+// Export
+// ======
+
+const arm = $scope[$as] = dict();
+
+// Database
+// ========
+
+arm.dbName = "isa_aarch64.json";
+
+// asmdb.aarch64.Utils
+// ===================
+
+// Can be used to assign the number of bits each part of the opcode occupies.
+// NOTE: THUMB instructions that use halfword must always specify the width
+// of all registers as many instructions accept only LO (r0..r7) registers.
+const FieldInfo = {
+ "P" : { "bits": 1 },
+ "U" : { "bits": 1 },
+ "W" : { "bits": 1 },
+ "S" : { "bits": 1 },
+ "R" : { "bits": 1 },
+ "H" : { "bits": 1 },
+ "F" : { "bits": 1 },
+ "post" : { "bits": 1 },
+ "!post" : { "bits": 1 },
+ "op" : { "bits": 1 }, // TODO: This should be fixed.
+ "s" : { "bits": 1 },
+ "sz" : { "bits": 2 },
+ "msz" : { "bits": 2 },
+ "sop" : { "bits": 2 },
+ "cond" : { "bits": 4 },
+ "nzcv" : { "bits": 4 },
+ "cmode" : { "bits": 4 },
+ "CRn" : { "bits": 4 },
+ "CRm" : { "bits": 4 },
+
+ "Rx" : { "bits": 5, "read": true , "write": true },
+ "Rx2" : { "bits": 5, "read": true , "write": true },
+ "Rdn" : { "bits": 5, "read": true , "write": true },
+ "Rd" : { "bits": 5, "read": false, "write": true },
+ "Rd2" : { "bits": 5, "read": false, "write": true },
+ "Rs" : { "bits": 5, "read": true , "write": false },
+ "Rs2" : { "bits": 5, "read": true , "write": false },
+ "Rn" : { "bits": 5, "read": true , "write": false },
+ "Rm" : { "bits": 5, "read": true , "write": false },
+ "Ra" : { "bits": 5, "read": true , "write": false },
+ "Rt" : { "bits": 5, "read": true , "write": false },
+ "Rt2" : { "bits": 5, "read": true , "write": false },
+
+ "Wx" : { "bits": 5, "read": true , "write": true },
+ "Wx2" : { "bits": 5, "read": true , "write": true },
+ "Wdn" : { "bits": 5, "read": true , "write": true },
+ "Wd" : { "bits": 5, "read": false, "write": true },
+ "Wd2" : { "bits": 5, "read": false, "write": true },
+ "Ws" : { "bits": 5, "read": true , "write": false },
+ "Ws2" : { "bits": 5, "read": true , "write": false },
+ "Wn" : { "bits": 5, "read": true , "write": false },
+ "Wm" : { "bits": 5, "read": true , "write": false },
+ "Wa" : { "bits": 5, "read": true , "write": false },
+ "Wt" : { "bits": 5, "read": true , "write": false },
+ "Wt2" : { "bits": 5, "read": true , "write": false },
+
+ "Xx" : { "bits": 5, "read": true , "write": true },
+ "Xx2" : { "bits": 5, "read": true , "write": true },
+ "Xdn" : { "bits": 5, "read": true , "write": true },
+ "Xd" : { "bits": 5, "read": false, "write": true },
+ "Xd2" : { "bits": 5, "read": false, "write": true },
+ "Xs" : { "bits": 5, "read": true , "write": false },
+ "Xs2" : { "bits": 5, "read": true , "write": false },
+ "Xn" : { "bits": 5, "read": true , "write": false },
+ "Xm" : { "bits": 5, "read": true , "write": false },
+ "Xa" : { "bits": 5, "read": true , "write": false },
+ "Xt" : { "bits": 5, "read": true , "write": false },
+ "Xt2" : { "bits": 5, "read": true , "write": false },
+
+ "Bx" : { "bits": 5, "read": true , "write": true },
+ "Bx2" : { "bits": 5, "read": true , "write": true },
+ "Bdn" : { "bits": 5, "read": true , "write": true },
+ "Bd" : { "bits": 5, "read": false, "write": true },
+ "Bd2" : { "bits": 5, "read": false, "write": true },
+ "Bs" : { "bits": 5, "read": true , "write": false },
+ "Bs2" : { "bits": 5, "read": true , "write": false },
+ "Bn" : { "bits": 5, "read": true , "write": false },
+ "Bm" : { "bits": 5, "read": true , "write": false },
+ "Ba" : { "bits": 5, "read": true , "write": false },
+
+ "Hx" : { "bits": 5, "read": true , "write": true },
+ "Hx2" : { "bits": 5, "read": true , "write": true },
+ "Hdn" : { "bits": 5, "read": true , "write": true },
+ "Hd" : { "bits": 5, "read": false, "write": true },
+ "Hd2" : { "bits": 5, "read": false, "write": true },
+ "Hs" : { "bits": 5, "read": true , "write": false },
+ "Hs2" : { "bits": 5, "read": true , "write": false },
+ "Hn" : { "bits": 5, "read": true , "write": false },
+ "Hm" : { "bits": 5, "read": true , "write": false },
+ "Ha" : { "bits": 5, "read": true , "write": false },
+
+ "Sx" : { "bits": 5, "read": true , "write": true },
+ "Sx2" : { "bits": 5, "read": true , "write": true },
+ "Sdn" : { "bits": 5, "read": true , "write": true },
+ "Sd" : { "bits": 5, "read": false, "write": true },
+ "Sd2" : { "bits": 5, "read": false, "write": true },
+ "Ss" : { "bits": 5, "read": true , "write": false },
+ "Ss2" : { "bits": 5, "read": true , "write": false },
+ "Sn" : { "bits": 5, "read": true , "write": false },
+ "Sm" : { "bits": 5, "read": true , "write": false },
+ "Sa" : { "bits": 5, "read": true , "write": false },
+
+ "Dx" : { "bits": 5, "read": true , "write": true },
+ "Dx2" : { "bits": 5, "read": true , "write": true },
+ "Ddn" : { "bits": 5, "read": true , "write": true },
+ "Dd" : { "bits": 5, "read": false, "write": true },
+ "Dd2" : { "bits": 5, "read": false, "write": true },
+ "Ds" : { "bits": 5, "read": true , "write": false },
+ "Ds2" : { "bits": 5, "read": true , "write": false },
+ "Dn" : { "bits": 5, "read": true , "write": false },
+ "Dn2" : { "bits": 5, "read": true , "write": false },
+ "Dm" : { "bits": 5, "read": true , "write": false },
+ "Da" : { "bits": 5, "read": true , "write": false },
+
+ "Qx" : { "bits": 5, "read": true , "write": true },
+ "Qx2" : { "bits": 5, "read": true , "write": true },
+ "Qdn" : { "bits": 5, "read": true , "write": true },
+ "Qd" : { "bits": 5, "read": false, "write": true },
+ "Qd2" : { "bits": 5, "read": false, "write": true },
+ "Qs" : { "bits": 5, "read": true , "write": false },
+ "Qs2" : { "bits": 5, "read": true , "write": false },
+ "Qn" : { "bits": 5, "read": true , "write": false },
+ "Qn2" : { "bits": 5, "read": true , "write": false },
+ "Qm" : { "bits": 5, "read": true , "write": false },
+ "Qa" : { "bits": 5, "read": true , "write": false },
+
+ "Vx" : { "bits": 5, "read": true , "write": true },
+ "Vx2" : { "bits": 5, "read": true , "write": true },
+ "Vdn" : { "bits": 5, "read": true , "write": true },
+ "Vd" : { "bits": 5, "read": false, "write": true },
+ "Vd2" : { "bits": 5, "read": false, "write": true },
+ "Vs" : { "bits": 5, "read": true , "write": false },
+ "Vs2" : { "bits": 5, "read": true , "write": false },
+ "Vn" : { "bits": 5, "read": true , "write": false },
+ "Vm" : { "bits": 5, "read": true , "write": false },
+ "Va" : { "bits": 5, "read": true , "write": false },
+
+ "Zx" : { "bits": 5, "read": true , "write": true },
+ "Zx2" : { "bits": 5, "read": true , "write": true },
+ "Zda" : { "bits": 5, "read": true , "write": true },
+ "Zdn" : { "bits": 5, "read": true , "write": true },
+ "Zdn2" : { "bits": 5, "read": true , "write": true },
+ "Zd" : { "bits": 5, "read": false, "write": true },
+ "Zd2" : { "bits": 5, "read": false, "write": true },
+ "Zs" : { "bits": 5, "read": true , "write": false },
+ "Zs2" : { "bits": 5, "read": true , "write": false },
+ "Zn" : { "bits": 5, "read": true , "write": false },
+ "Zm" : { "bits": 5, "read": true , "write": false },
+ "Zk" : { "bits": 5, "read": true , "write": false },
+ "Za" : { "bits": 5, "read": true , "write": false },
+
+ "Pdn" : { "bits": 4, "read": true , "write": true },
+ "Pdm" : { "bits": 4, "read": true , "write": true },
+ "Pd" : { "bits": 4, "read": false, "write": true },
+ "Ps" : { "bits": 4, "read": true , "write": false },
+ "Pn" : { "bits": 4, "read": true , "write": false },
+ "Pm" : { "bits": 4, "read": true , "write": false },
+ "Pg" : { "bits": 4, "read": true , "write": false }
+};
+
+arm.FieldInfo = FieldInfo;
+
+// AArch64 utilities.
+class Utils {
+ static splitInstructionSignature(s) {
+ const names = s.match(/^[\w\|]+/)[0];
+ s = s.substring(names.length);
+
+ const opOffset = s.indexOf(" ")
+ const suffix = s.substring(0, opOffset).trim();
+ const operands = opOffset === -1 ? "" : s.substring(opOffset + 1).trim();
+
+ return {
+ names: names.split("|").map((base)=>{ return base + suffix}),
+ operands: operands
+ }
+ }
+
+ static parseShiftOrExtendOp(s) {
+ const space = s.indexOf(" ");
+ if (space === -1)
+ return "";
+
+ const ops = s.substring(0, space).trim();
+ for (let op of ops.split("|"))
+ if (!/^(sop|extend|lsl|lsr|asr|uxtw|sxtw|sxtx|mul)$/.test(op))
+ return "";
+
+ return ops;
+ }
+}
+arm.Utils = Utils;
+
+function normalizeNumber(n) {
+ return n < 0 ? 0x100000000 + n : n;
+}
+
+function decomposeOperand(s) {
+ let type = null;
+ let element = null;
+ let consecutive = 0;
+ let maskType = "";
+
+ const elementM = s.match(/\[#(\w+)\]$/);
+ if (elementM) {
+ element = elementM[1];
+ s = s.substring(0, s.length - elementM[0].length);
+ }
+
+ const typeM = s.match(/\.(\w+)$/);
+ if (typeM) {
+ type = typeM[1];
+ s = s.substring(0, s.length - typeM[0].length);
+ }
+
+ const maskM = s.match(/\/(M|Z|MZ)$/);
+ if (maskM) {
+ maskType = maskM[1];
+ s = s.substring(0, s.length - maskM[0].length);
+ }
+
+ if (s.endsWith("++")) {
+ consecutive = 2;
+ s = s.substring(0, s.length - 2);
+ }
+ else if (s.endsWith("+")) {
+ consecutive = 1;
+ s = s.substring(0, s.length - 1);
+ }
+
+ let m = s.match(/==|\!=|>=|<=|\*/);
+ let restrict = false;
+
+ if (m) {
+ restrict = s.substring(m.index);
+ s = s.substring(0, m.index);
+ }
+
+ return {
+ data : s,
+ maskType : maskType,
+ type : type,
+ element : element,
+ restrict : restrict,
+ consecutive: consecutive
+ };
+}
+
+function splitOpcodeFields(s) {
+ const arr = s.split("|");
+ const out = [];
+
+ for (let i = 0; i < arr.length; i++) {
+ const val = arr[i];
+ if (/^[0-1A-Z]{2,}$/.test(val))
+ out.push.apply(out, val.match(/([0-1]+)|[A-Z]/g));
+ else
+ out.push(val);
+ }
+
+ return out.map((field)=>{return field.trim(); });
+}
+
+// asmdb.aarch64.Operand
+// =====================
+
+// ARM operand.
+class Operand extends base.Operand {
+ constructor(def) {
+ super();
+ this.data = def;
+
+ // Register.
+ this.sp = ""; // GP register stack access: ["", "WSP" or "SP"].
+ this.mask = ""; // Masking specifier.
+ }
+
+ hasMemModes() {
+ return Object.keys(this.memModes).length !== 0;
+ }
+
+ get name() {
+ switch (this.type) {
+ case "reg": return this.reg;
+ case "mem": return this.mem;
+ case "imm": return this.imm;
+ case "rel": return this.rel;
+ default : return "";
+ }
+ }
+
+ get scale() {
+ if (this.restrict && this.restrict.startsWith("*"))
+ return parseInt(this.restrict.substring(1), 10);
+ else
+ return 0;
+ }
+}
+arm.Operand = Operand;
+
+// asmdb.aarch64.Instruction
+// =========================
+
+function patternFromOperand(key) { return key; }
+
+// ARM instruction.
+class Instruction extends base.Instruction {
+ constructor(db, data) {
+ super(db, data);
+
+ this.name = data.name;
+ this.it = dict(); // THUMB's 'it' flags.
+ this.apsr = dict();
+ this.fpcsr = dict();
+ this.calc = dict(); // Calculations required to generate opcode.
+ this.immCond = []; // Immediate value conditions (array of conditions).
+
+ this._assignOperands(data.operands);
+ this._assignOpcode(data.op);
+
+ for (let k in data) {
+ if (k === "name" || k == "op" || k === "operands")
+ continue;
+ this._assignAttribute(k, data[k]);
+ }
+
+ this._updateOperandsInfo();
+ this._postProcess();
+ }
+
+ _assignAttribute(key, value) {
+ switch (key) {
+ case "it":
+ for (let it of value.split(" "))
+ this.it[it.trim()] = true;
+ break;
+
+ case "apsr":
+ case "fpcsr":
+ this._assignAttributeKeyValue(key, value);
+ break;
+
+ case "imm":
+ this.imm = exp.parse(value);
+ break;
+
+ case "calc":
+ for (let calcKey in value)
+ this.calc[calcKey] = exp.parse(value[calcKey]);
+ break;
+
+ default:
+ super._assignAttribute(key, value);
+ }
+ }
+
+ _assignAttributeKeyValue(name, content) {
+ const attributes = content.trim().split(/[ ]+/);
+
+ for (let i = 0; i < attributes.length; i++) {
+ const attr = attributes[i].trim();
+ if (!attr)
+ continue;
+
+ const eq = attr.indexOf("=");
+ let key = eq === -1 ? attr : attr.substring(0, eq);
+ let val = eq === -1 ? true : attr.substring(eq + 1);
+
+ // If the key contains "|" it's a definition of multiple attributes.
+ if (key.indexOf("|") !== -1) {
+ const dot = key.indexOf(".");
+
+ const base = dot === -1 ? "" : key.substring(0, dot + 1);
+ const keys = (dot === -1 ? key : key.substring(dot + 1)).split("|");
+
+ for (let j = 0; j < keys.length; j++)
+ this[name][base + keys[j]] = val;
+ }
+ else {
+ this[name][key] = val;
+ }
+ }
+ }
+
+ _assignOperands(s) {
+ if (!s) return;
+
+ // Split into individual operands and push them to `operands`.
+ const arr = base.Parsing.splitOperands(s);
+ for (let i = 0; i < arr.length; i++) {
+ let def = arr[i].trim();
+ const op = new Operand(def);
+
+ const sp = def.match(/^(\w+)\|(SP|WSP)$/);
+ if (sp) {
+ def = sp[1];
+ op.sp = sp[2];
+ }
+
+ const consecutive = def.match(/(\d+)x\{(.*)\}([+]?[+]?)/);
+ if (consecutive)
+ def = consecutive[2];
+
+ op.sign = false;
+ op.element = null;
+ op.shiftOp = "";
+ op.shiftImm = null;
+ op.shiftCond = "";
+
+ // Handle {optional} attribute.
+ if (Parsing.isOptional(def)) {
+ op.optional = true;
+ def = Parsing.clearOptional(def);
+ }
+
+ // Handle commutativity <-> symbol.
+ if (Parsing.isCommutative(def)) {
+ op.commutative = true;
+ def = Parsing.clearCommutative(def);
+ }
+
+ // Handle shift operation.
+ let shiftOp = Utils.parseShiftOrExtendOp(def);
+ if (shiftOp) {
+ op.shiftOp = shiftOp;
+ def = def.substring(shiftOp.length + 1);
+ }
+
+ if (def.startsWith("[")) {
+ op.type = "mem";
+ op.memModes = dict();
+
+ op.base = null;
+ op.index = null;
+ op.offset = null;
+
+ let mem = def;
+ let didHaveMemMode = false;
+
+ for (;;) {
+ if (mem.endsWith("!")) {
+ op.memModes.preIndex = true;
+ mem = mem.substring(0, mem.length - 1);
+
+ didHaveMemMode = true;
+ break;
+ }
+
+ if (mem.endsWith("@")) {
+ op.memModes.postIndex = true;
+ mem = mem.substring(0, mem.length - 1);
+
+ didHaveMemMode = true;
+ break;
+ }
+
+ if (mem.endsWith("{!}")) {
+ op.memModes.offset = true;
+ op.memModes.preIndex = true;
+ mem = mem.substring(0, mem.length - 3);
+
+ didHaveMemMode = true;
+ continue;
+ }
+
+ if (mem.endsWith("{@}")) {
+ op.memModes.offset = true;
+ op.memModes.postIndex = true;
+ mem = mem.substring(0, mem.length - 3);
+
+ didHaveMemMode = true;
+ continue;
+ }
+
+ break;
+ }
+
+ if (!mem.endsWith("]"))
+ FAIL(`Unknown memory operand '${mem}' in '${def}'`);
+
+ let parts = mem.substring(1, mem.length - 1).split(",").map(function(s) { return s.trim() });
+ for (let i = 0; i < parts.length; i++) {
+ const part = parts[i];
+
+ const m = part.match(/^\{(([a-z]+)(\|[a-z]+)*)\s+#(\w+)\s*(\*\s*\d+\s*)?\}$/);
+ if (m) {
+ op.shiftOp = m[1];
+ op.shiftImm = m[2];
+ if (m[3])
+ op.shiftCond = m[3]
+ continue;
+ }
+
+ if (i === 0) {
+ op.base = dict();
+ op.base.field = part;
+ op.base.exp = null;
+
+ const m = part.match(/^([A-Za-z]\w*(?:\.\w+)?)/);
+ if (m && m[1].length < part.length) {
+ op.base.exp = exp.parse(part);
+ op.base.field = m[1];
+ }
+ }
+ else if (part.startsWith("#")) {
+ let p = part.substring(1);
+ let u = "1";
+
+ let offExp = null;
+ let offMul = 1;
+
+ if (p.startsWith("+/-")) {
+ u = "U";
+ p = p.substring(3);
+ }
+
+ const expMatch = p.match(/^([A-Za-z]\w*)==/);
+ if (expMatch) {
+ offExp = exp.parse(p);
+ p = p.substring(0, expMatch[1].length);
+ }
+
+ const mulMatch = p.match(/\s*\*\s*(\d+)$/);
+ if (mulMatch) {
+ offMul = parseInt(mulMatch[1]);
+ p = p.substring(0, mulMatch.index);
+ }
+
+ op.offset = dict();
+ op.offset.field = p;
+ op.offset.u = u;
+ op.offset.exp = offExp;
+ op.offset.mul = offMul;
+ }
+ else {
+ let p = part;
+ let u = "1";
+
+ if (p.startsWith("+/-")) {
+ u = "U";
+ p = p.substring(3);
+ }
+
+ op.index = dict();
+ op.index.field = p;
+ op.index.u = u;
+
+ const m = p.match(/^([A-Za-z\|]\w*(?:\.\w+)?)/);
+ if (m && m[1].length < p.length) {
+ op.index.exp = exp.parse(p);
+ op.index.field = m[1];
+ }
+ }
+ }
+
+ if (!op.hasMemModes() && (op.offset || op.index))
+ op.memModes.offset = true;
+
+ op.mem = mem;
+ }
+ else if (def.startsWith("#")) {
+ const obj = decomposeOperand(def);
+ const imm = obj.data;
+
+ op.type = "imm";
+ op.imm = imm.substring(1); // Immediate operand name.
+ op.immSize = 0; // Immediate size in bits.
+ op.restrict = obj.restrict; // Immediate condition.
+ }
+ else {
+ // Some instructions use Reg! to specify that the register increments.
+ if (def.endsWith("!")) {
+ def = def.substring(0, def.length - 1)
+ op.regInc = true
+ }
+
+ const obj = decomposeOperand(def);
+ const reg = obj.data;
+
+ const type = reg.substring(0, 1).toLowerCase();
+ const info = FieldInfo[reg];
+
+ if (!info)
+ FAIL(`Unknown register operand '${reg}' in '${def}'`);
+
+ op.type = info.list ? "reg-list" : "reg";
+ op.reg = reg; // Register name (as specified in manual).
+ op.regType = type; // Register type.
+ op.regList = !!info.list; // Register list.
+ op.maskType = obj.maskType; // Mask type.
+ op.elementType = obj.type // Element type or t, ta, tb.
+ op.read = info.read; // Register access (read).
+ op.write = info.write; // Register access (write).
+ op.element = obj.element; // Register element[] access.
+ op.restrict = obj.restrict; // Register condition.
+ op.consecutive = obj.consecutive;
+ }
+
+ this.operands.push(op);
+
+ if (consecutive) {
+ const count = parseInt(consecutive[1]);
+ for (let n = 2; n <= count; n++) {
+ const def = consecutive[3].replace(op.reg, op.reg + n);
+ const opN = new Operand(def);
+ opN.type = "reg";
+ opN.reg = op.reg + n;
+ opN.regType = op.regType;
+ opN.read = op.read;
+ opN.write = op.write;
+ opN.element = op.element;
+ opN.consecutive = consecutive[3].length;
+ opN.artificial = true;
+ this.operands.push(opN);
+ }
+ }
+ }
+ }
+
+ _assignOpcode(s) {
+ this.opcodeString = s;
+
+ let opcodeIndex = 0;
+ let opcodeValue = 0;
+
+ let patternMap = {};
+
+ // Split opcode into its fields.
+ const arr = splitOpcodeFields(s);
+ const dup = dict();
+
+ const fields = this.fields;
+ const pattern = [];
+
+ const fieldMap = Object.create(null);
+ for (let field of arr) {
+ fieldMap[field] = true;
+ }
+
+ for (let i = arr.length - 1; i >= 0; i--) {
+ let key = arr[i].trim();
+ let m;
+
+ if (/^[0-1]+$/.test(key)) {
+ // This part of the opcode is RAW bits, they contribute to the `opcodeValue`.
+ opcodeValue |= parseInt(key, 2) << opcodeIndex;
+ opcodeIndex += key.length;
+ pattern.unshift("_".repeat(key.length));
+ }
+ else {
+ pattern.unshift(patternFromOperand(key));
+ patternMap[patternFromOperand(key)] = true;
+
+ let size = 0;
+ let mask = 0;
+ let bits = 0;
+ let from = -1;
+
+ let lbit = key.startsWith("'");
+ let hbit = key.endsWith("'");
+
+ if ((m = key.match(/\[\s*(\d+)\s*\:\s*(\d+)\s*\]$/))) {
+ const a = parseInt(m[1], 10);
+ const b = parseInt(m[2], 10);
+ if (a < b)
+ FAIL(`Invalid bit range '${key}' in opcode '${s}'`);
+ from = b;
+ size = a - b + 1;
+ mask = ((1 << size) - 1) << b;
+ key = key.substring(0, m.index).trim();
+ }
+ else if ((m = key.match(/\[\s*(\d+)\s*\]$/))) {
+ from = parseInt(m[1], 10);
+ size = 1;
+ mask = 1 << from;
+ key = key.substring(0, m.index).trim();
+ }
+ else if ((m = key.match(/\:\s*(\d+)$/))) {
+ size = parseInt(m[1], 10);
+ bits = size;
+ key = key.substring(0, m.index).trim();
+ }
+ else {
+ const key_ = key;
+
+ if (lbit || hbit) {
+ from = 0;
+
+ if (lbit && hbit)
+ FAIL(`Couldn't recognize the format of '${key}' in opcode '${s}'`);
+
+ if (lbit) {
+ key = key.substring(1);
+ }
+
+ if (hbit) {
+ key = key.substring(0, key.length - 1);
+ from = 4;
+ }
+
+ size = 1;
+ }
+ else if (FieldInfo[key]) {
+ // Sizes of some standard fields can be assigned automatically.
+ size = FieldInfo[key].bits;
+ bits = size;
+
+ if (fieldMap["'" + key])
+ from = 1;
+ }
+ else if (key.length === 1) {
+ // Sizes of one-letter fields (like 'U', 'F', etc...) is 1 if not specified.
+ size = 1;
+ bits = 1;
+ }
+ else {
+ FAIL(`Couldn't recognize the size of '${key}' in opcode '${s}'`);
+ }
+
+ if (dup[key_] === true) {
+ bits = 0;
+ lbit = 0;
+ hbit = 0;
+ }
+ else {
+ dup[key_] = true;
+ }
+ }
+
+ let field = fields[key];
+ if (!field) {
+ field = {
+ index: opcodeIndex,
+ values: [],
+ bits: 0,
+ mask: 0,
+ lbit: 0,
+ hbit: 0 // Only 1 if a single quote (') was used.
+ }
+ fields[key] = field;
+ }
+
+ if (from === -1)
+ from = field.bits;
+
+ field.mask |= mask;
+ field.bits += bits;
+ field.lbit += lbit;
+ field.hbit += hbit;
+ field.values.push({
+ index: opcodeIndex,
+ from: from,
+ size: size
+ });
+
+ opcodeIndex += size;
+ }
+ }
+
+ for (let i = 0; i < pattern.length; i++)
+ if (pattern[i] === 'U')
+ pattern[i] = "_";
+
+ // Normalize all fields.
+ for (let key in fields) {
+ const field = fields[key];
+
+ // There should be either number of bits or mask, there shouldn't be both.
+ if (!field.bits && !field.mask)
+ FAIL(`Part '${key}' of opcode '${s}' contains neither size nor mask`);
+
+ if (field.bits && field.mask)
+ FAIL(`Part '${key}' of opcode '${s}' contains both size and mask`);
+
+ if (field.bits)
+ field.mask = ((1 << field.bits) - 1);
+ else if (field.mask)
+ field.bits = 32 - Math.clz32(field.mask);
+
+ // Handle field that used single-quote.
+ if (field.lbit) {
+ field.mask = (field.mask << 1) | 0x1;
+ field.bits++;
+ }
+
+ if (field.hbit) {
+ field.mask |= 1 << field.bits;
+ field.bits++;
+ }
+
+ const op = this.operandByName(key);
+ if (op && op.isImm())
+ op.immSize = field.bits;
+ }
+
+ // Check if the opcode value has the correct number of bits.
+ if (opcodeIndex !== 32)
+ FAIL(`The number of bits '${opcodeIndex}' used by the opcode '${s}' doesn't match 32`);
+ this.opcodeValue = normalizeNumber(opcodeValue);
+ }
+
+ _assignSpecificAttribute(key, value) {
+ switch (key) {
+ case "it": {
+ const values = String(value).split("|");
+ for (let i = 0; i < values.length; i++) {
+ const value = values[i];
+ switch (value) {
+ case "in" : this.it.IN = true; break;
+ case "out" : this.it.OUT = true; break;
+ case "any" : this.it.IN = true;
+ this.it.OUT = true; break;
+ case "last": this.it.LAST = true; break;
+ case "def" : this.it.DEF = true; break;
+ default:
+ this.report(`${this.name}: Unhandled IT value '${value}'`);
+ }
+ }
+ return true;
+ }
+ }
+
+ return false;
+ }
+
+ _postProcess() {}
+
+ operandByName(name) {
+ const operands = this.operands;
+ for (let i = 0; i < operands.length; i++) {
+ const op = operands[i];
+ if (op.name === name)
+ return op;
+ }
+ return null;
+ }
+}
+arm.Instruction = Instruction;
+
+// asmdb.aarch64.ISA
+// =================
+
+function mergeGroupData(data, group) {
+ for (let k in group) {
+ switch (k) {
+ case "group":
+ case "data":
+ break;
+
+ case "ext":
+ data[k] = (data[k] ? data[k] + " " : "") + group[k];
+ break;
+
+ default:
+ if (data[k] === undefined)
+ data[k] = group[k]
+ break;
+ }
+ }
+}
+
+class ISA extends base.ISA {
+ constructor(data) {
+ super(data);
+ this.addData(data || NONE);
+ }
+
+ _addInstructions(groups) {
+ for (let group of groups) {
+ for (let instructions of group.data) {
+ const sgn = Utils.splitInstructionSignature(instructions.inst);
+ const data = MapUtils.cloneExcept(instructions, { "inst": true });
+
+ mergeGroupData(data, group)
+
+ for (let j = 0; j < sgn.names.length; j++) {
+ data.name = sgn.names[j];
+ data.operands = sgn.operands;
+ if (j > 0)
+ data.aliasOf = sgn.names[0];
+ this._addInstruction(new Instruction(this, data));
+ }
+ }
+ }
+
+ return this;
+ }
+}
+arm.ISA = ISA;
+
+}).apply(this, typeof module === "object" && module && module.exports
+ ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "aarch64"]);
diff --git a/3rdparty/asmjit/db/base.js b/3rdparty/asmjit/db/base.js
new file mode 100644
index 00000000000..38bec54819c
--- /dev/null
+++ b/3rdparty/asmjit/db/base.js
@@ -0,0 +1,707 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See <asmjit/core.h> or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+(function($scope, $as) {
+"use strict";
+
+function FAIL(msg) { throw new Error("[BASE] " + msg); }
+
+const exp = $scope.exp ? $scope.exp : require("./exp.js");
+
+// Export.
+const base = $scope[$as] = Object.create(null);
+
+base.exp = exp;
+
+function dict(src) {
+ const dst = Object.create(null);
+ if (src)
+ Object.assign(dst, src);
+ return dst;
+}
+base.dict = dict;
+const NONE = base.NONE = Object.freeze(dict());
+
+// asmdb.base.Symbols
+// ==================
+
+const Symbols = Object.freeze({
+ Commutative: '~'
+});
+base.Symbols = Symbols;
+
+// asmdb.base.Parsing
+// ==================
+
+// Namespace that provides functions related to text parsing.
+const Parsing = {
+ // Get whether the string `s` representing an operand is <implicit>.
+ isImplicit: function(s) { return s.startsWith("<") && s.endsWith(">"); },
+
+ // Clear <implicit> attribute from the given operand string `s`.
+ clearImplicit: function(s) { return s.substring(1, s.length - 1); },
+
+ // Get whether the string `s` representing an operand is {optional}.
+ isOptional: function(s) { return s.startsWith("{") && s.endsWith("}"); },
+
+ // Clear {optional} attribute from the given operand string `s`.
+ clearOptional: function(s) { return s.substring(1, s.length - 1); },
+
+ // Get whether the string `s` representing an operand specifies commutativity.
+ isCommutative: function(s) { return s.length > 0 && s.charAt(0) === Symbols.Commutative; },
+
+ // Clear commutative attribute from the given operand string `s`.
+ clearCommutative: function(s) { return s.substring(1); },
+
+ // Matches a closing bracket in string `s` starting `from` the given index.
+ // It behaves like `s.indexOf()`, but uses a counter and skips all nested
+ // matches.
+ matchClosingChar: function(s, from) {
+ const len = s.length;
+ const opening = s.charCodeAt(from);
+ const closing = opening === 40 ? 31 : // ().
+ opening === 60 ? 62 : // <>.
+ opening === 91 ? 93 : // [].
+ opening === 123 ? 125 : 0; // {}.
+
+ let i = from;
+ let pending = 1;
+ do {
+ if (++i >= len)
+ break;
+
+ const c = s.charCodeAt(i);
+ pending += Number(c === opening);
+ pending -= Number(c === closing);
+ } while (pending);
+
+ return i;
+ },
+
+ // Split instruction operands into an array containing each operand as a
+ // trimmed string. This function is similar to `s.split(",")`, however,
+ // it matches brackets inside the operands and won't just blindly split
+ // the string based on "," token. If operand contains metadata or it's
+ // an address it would still be split correctly.
+ splitOperands: function(s) {
+ const result = [];
+
+ s = s.trim();
+ if (!s)
+ return result;
+
+ let start = 0;
+ let i = 0;
+ let c = "";
+
+ for (;;) {
+ if (i === s.length || (c = s[i]) === ",") {
+ const op = s.substring(start, i).trim();
+ if (!op)
+ FAIL(`Found empty operand in '${s}'`);
+
+ result.push(op);
+ if (i === s.length)
+ return result;
+
+ start = ++i;
+ continue;
+ }
+
+ if ((c === "<" || c === ">") && i != start) {
+ i++;
+ continue;
+ }
+
+ if (c === "[" || c === "{" || c === "(" || c === "<")
+ i = base.Parsing.matchClosingChar(s, i);
+ else
+ i++;
+ }
+ }
+}
+base.Parsing = Parsing;
+
+// asmdb.base.MapUtils
+// ===================
+
+class MapUtils {
+ static cloneExcept(map, except) {
+ if (typeof except === "string") {
+ const key = except;
+ except = Object.create(null);
+ except[key] = true;
+ }
+
+ const out = Object.create(null);
+ for (let k in map) {
+ if (k in except)
+ continue
+ out[k] = map[k];
+ }
+ return out;
+ }
+
+ static mapFromArray(array) {
+ const out = Object.create(null);
+ for (let k of array) {
+ out[k] = true;
+ }
+ return out;
+ }
+};
+base.MapUtils = MapUtils;
+
+// asmdb.base.Operand
+// ==================
+
+const OperandFlags = Object.freeze({
+ Optional : 0x00000001,
+ Implicit : 0x00000002,
+ Commutative: 0x00000004,
+ ZExt : 0x00000008,
+ ReadAccess : 0x00000010,
+ WriteAccess: 0x00000020
+});
+base.OperandFlags = OperandFlags;
+
+class Operand {
+ constructor() {
+ this.type = ""; // Type of the operand ("reg", "reg-list", "mem", "reg/mem", "imm", "rel").
+ this.data = ""; // The operand's data (possibly processed).
+ this.flags = 0;
+
+ this.reg = ""; // Register operand's definition.
+ this.mem = ""; // Memory operand's definition.
+ this.imm = 0; // Immediate operand's size.
+ this.rel = 0; // Relative displacement operand's size.
+
+ this.restrict = ""; // Operand is restricted (specific register or immediate value).
+ this.read = false; // True if the operand is a read-op from reg/mem.
+ this.write = false; // True if the operand is a write-op to reg/mem.
+
+ this.regType = ""; // Register operand's type.
+ this.regIndexRel = 0; // Register index is relative to the previous register operand index (0 if not).
+ this.memSize = -1; // Memory operand's size.
+ this.immSign = ""; // Immediate sign (any / signed / unsigned).
+ this.immValue = null; // Immediate value - `null` or `1` (only used by shift/rotate instructions).
+
+ this.rwxIndex = -1; // Read/Write (RWX) index.
+ this.rwxWidth = -1; // Read/Write (RWX) width.
+ }
+
+ _getFlag(flag) {
+ return (this.flags & flag) != 0;
+ }
+
+ _setFlag(flag, value) {
+ this.flags = (this.flags & ~flag) | (value ? flag : 0);
+ return this;
+ }
+
+ get optional() { return this._getFlag(OperandFlags.Optional); }
+ set optional(value) { this._setFlag(OperandFlags.Optional, value); }
+
+ get implicit() { return this._getFlag(OperandFlags.Implicit); }
+ set implicit(value) { this._setFlag(OperandFlags.Implicit, value); }
+
+ get commutative() { return this._getFlag(OperandFlags.Commutative); }
+ set commutative(value) { this._setFlag(OperandFlags.Commutative, value); }
+
+ get zext() { return this._getFlag(OperandFlags.ZExt); }
+ set zext(value) { this._setFlag(OperandFlags.ZExt, value); }
+
+ toString() { return this.data; }
+
+ isReg() { return !!this.reg && this.type !== "reg-list"; }
+ isMem() { return !!this.mem; }
+ isImm() { return !!this.imm; }
+ isRel() { return !!this.rel; }
+
+ isRegMem() { return this.reg && this.mem; }
+ isRegOrMem() { return !!this.reg || !!this.mem; }
+
+ isRegList() { return this.type === "reg-list" }
+ isPartialOp() { return false; }
+}
+base.Operand = Operand;
+
+// asmdb.base.Instruction
+// ======================
+
+// Defines interface and properties that each architecture dependent instruction
+// must provide even if that particular architecture doesn't use that feature(s).
+class Instruction {
+ constructor(db) {
+ Object.defineProperty(this, "db", { value: db });
+
+ this.name = ""; // Instruction name.
+ this.arch = "ANY"; // Architecture.
+ this.encoding = ""; // Encoding type.
+ this.operands = []; // Instruction operands.
+
+ this.implicit = 0; // Indexes of all implicit operands (registers / memory).
+ this.commutative = 0; // Indexes of all commutative operands.
+
+ this.opcodeString = ""; // Instruction opcode as specified in manual.
+ this.opcodeValue = 0; // Instruction opcode as number (arch dependent).
+ this.fields = dict(); // Information about each opcode field (arch dependent).
+ this.operations = dict(); // Operations the instruction performs.
+
+ this.io = dict(); // Instruction input / output (CPU flags, states, and other registers).
+ this.ext = dict(); // ISA extensions required by the instruction.
+ this.category = dict(); // Instruction categories.
+
+ this.specialRegs = dict(); // Information about read/write to special registers.
+
+ this.alt = false; // This is an alternative form, not needed to create a signature.
+ this.volatile = false; // Instruction is volatile and should not be reordered.
+ this.control = "none"; // Control flow type (none by default).
+ this.privilege = ""; // Privilege-level required to execute the instruction.
+ this.aliasOf = ""; // Instruction is an alias of another instruction
+ }
+
+ get extArray() {
+ const out = Object.keys(this.ext);
+ out.sort();
+ return out;
+ }
+
+ get operandCount() {
+ return this.operands.length;
+ }
+
+ get minimumOperandCount() {
+ const count = this.operands.length;
+ for (let i = 0; i < count; i++) {
+ if (this.operands[i].optional) {
+ return i;
+ }
+ }
+ return count
+ }
+
+ _assignAttribute(key, value) {
+ switch (key) {
+ case "ext":
+ case "io":
+ case "category":
+ return this._combineAttribute(key, value);
+
+ default:
+ if (typeof this[key] === undefined)
+ FAIL(`Cannot assign ${key}=${value}`);
+ this[key] = value;
+ break;
+ }
+ }
+
+ _combineAttribute(key, value) {
+ if (typeof value === "string")
+ value = value.split(" ");
+
+ if (Array.isArray(value)) {
+ for (let v of value) {
+ let pKeys = v;
+ let pValue = true;
+
+ const i = v.indexOf("=");
+ if (i !== -1) {
+ pValue = v.substring(i + 1);
+ pKeys = v.substring(0, i).trim();
+ }
+
+ for (let pk of pKeys.trim().split("|").map(function(s) { return s.trim(); })) {
+ this[key][pk] = pValue;
+ }
+ }
+ }
+ else {
+ for (let k in value)
+ this[key][k] = value[k];
+ }
+ }
+
+ _updateOperandsInfo() {
+ this.implicit = 0;
+ this.commutative = 0;
+
+ for (let i = 0; i < this.operands.length; i++) {
+ const op = this.operands[i];
+
+ if (op.implicit) this.implicit |= (1 << i);
+ if (op.commutative) this.commutative |= (1 << i);
+ }
+ }
+
+ isAlias() { return !!this.aliasOf; }
+ isCommutative() { return this.commutative !== 0; }
+
+ hasImplicit() { return this.implicit !== 0; }
+
+ hasAttribute(name, matchValue) {
+ const value = this[name];
+ if (value === undefined)
+ return false;
+
+ if (matchValue === undefined)
+ return true;
+
+ return value === matchValue;
+ }
+
+ report(msg) {
+ console.log(`${this}: ${msg}`);
+ }
+
+ toString() {
+ return `${this.name} ${this.operands.join(", ")}`;
+ }
+}
+base.Instruction = Instruction;
+
+// asmdb.base.InstructionGroup
+// ===========================
+
+// Instruction group is simply array of function that has some additional
+// functionality.
+class InstructionGroup extends Array {
+ constructor() {
+ super();
+
+ if (arguments.length === 1) {
+ const a = arguments[0];
+ if (Array.isArray(a)) {
+ for (let i = 0; i < a.length; i++)
+ this.push(a[i]);
+ }
+ }
+ }
+
+ unionCpuFeatures(name) {
+ const result = dict();
+ for (let i = 0; i < this.length; i++) {
+ const instruction = this[i];
+ const features = instruction.ext;
+ for (let k in features)
+ result[k] = features[k];
+ }
+ return result;
+ }
+
+ checkAttribute(key, value) {
+ let n = 0;
+ for (let i = 0; i < this.length; i++)
+ n += Number(this[i][key] === value);
+ return n;
+ }
+}
+base.InstructionGroup = InstructionGroup;
+
+const EmptyInstructionGroup = Object.freeze(new InstructionGroup());
+
+// asmdb.base.ISA
+// ==============
+
+class ISA {
+ constructor() {
+ this._instructions = null; // Instruction array (contains all instructions).
+ this._instructionNames = null; // Instruction names (sorted), regenerated when needed.
+ this._instructionMap = dict(); // Instruction name to `Instruction[]` mapping.
+ this._aliases = dict(); // Instruction aliases.
+ this._aliasMap = dict(); // Instruction aliases.
+ this._cpuLevels = dict(); // Architecture versions.
+ this._extensions = dict(); // Architecture extensions.
+ this._attributes = dict(); // Instruction attributes.
+ this._specialRegs = dict(); // Special registers.
+ this._shortcuts = dict(); // Shortcuts used by instructions metadata.
+ this.stats = {
+ instructions : 0, // Number of all instructions.
+ groups: 0 // Number of grouped instructions (having unique name).
+ };
+ }
+
+ get instructions() {
+ let array = this._instructions;
+ if (array === null) {
+ array = [];
+ const map = this.instructionMap;
+ const names = this.instructionNames;
+ for (let i = 0; i < names.length; i++)
+ array.push.apply(array, map[names[i]]);
+ this._instructions = array;
+ }
+ return array;
+ }
+
+ get instructionNames() {
+ let names = this._instructionNames;
+ if (names === null) {
+ names = Object.keys(this._instructionMap);
+ names.sort();
+ this._instructionNames = names;
+ }
+ return names;
+ }
+
+ get instructionMap() { return this._instructionMap; }
+ get aliases() { return this._aliasMap; }
+ get cpuLevels() { return this._cpuLevels; }
+ get extensions() { return this._extensions; }
+ get attributes() { return this._attributes; }
+ get specialRegs() { return this._specialRegs; }
+ get shortcuts() { return this._shortcuts; }
+
+ query(args, copy) {
+ if (typeof args !== "object" || !args || Array.isArray(args))
+ return this._queryByName(args, copy);
+
+ const filter = args.filter;
+ if (filter)
+ copy = false;
+
+ let result = this._queryByName(args.name, copy);
+ if (filter)
+ result = result.filter(filter, args.filterThis);
+
+ return result;
+ }
+
+ aliasData(name) {
+ return this._aliases[name] || null;
+ }
+
+ _queryByName(name, copy) {
+ let result = EmptyInstructionGroup;
+ const map = this._instructionMap;
+
+ if (typeof name === "string") {
+ const instructions = map[name];
+ if (instructions) result = instructions;
+ return copy ? result.slice() : result;
+ }
+
+ if (Array.isArray(name)) {
+ const names = name;
+ for (let i = 0; i < names.length; i++) {
+ const instructions = map[names[i]];
+ if (!instructions) continue;
+
+ if (result === EmptyInstructionGroup)
+ result = new InstructionGroup();
+
+ for (let j = 0; j < instructions.length; j++)
+ result.push(instructions[j]);
+ }
+ return result;
+ }
+
+ result = this.instructions;
+ return copy ? result.slice() : result;
+ }
+
+ forEachGroup(cb, thisArg) {
+ const map = this._instructionMap;
+ const names = this.instructionNames;
+
+ for (let i = 0; i < names.length; i++) {
+ const name = names[i];
+ cb.call(thisArg, name, map[name]);
+ }
+
+ return this;
+ }
+
+ addData(data) {
+ if (typeof data !== "object" || !data)
+ FAIL("ISA.addData(): data argument must be object");
+
+ if (data.cpuLevels) this._addCpuLevels(data.cpuLevels);
+ if (data.specialRegs) this._addSpecialRegs(data.specialRegs);
+ if (data.shortcuts) this._addShortcuts(data.shortcuts);
+ if (data.instructions) this._addInstructions(data.instructions);
+ if (data.aliases) this._addAliases(data.aliases);
+ if (data.postproc) this._postProc(data.postproc);
+ }
+
+ _postProc(groups) {
+ for (let group of groups) {
+ for (let iRule of group.instructions) {
+ const names = iRule.name.split(" ");
+ for (let name of names) {
+ const instructions = this._instructionMap[name];
+ if (!instructions)
+ FAIL(`Instruction ${name} referenced by '${group.group}' group doesn't exist`);
+
+ for (let k in iRule) {
+ if (k === "name" || k === "data")
+ continue;
+ for (let instruction of instructions) {
+ instruction._assignAttribute(k, iRule[k]);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ _addCpuLevels(items) {
+ if (!Array.isArray(items))
+ FAIL("Property 'cpuLevels' must be array");
+
+ for (let i = 0; i < items.length; i++) {
+ const item = items[i];
+ const name = item.name;
+
+ const obj = {
+ name: name
+ };
+
+ this._cpuLevels[name] = obj;
+ }
+ }
+
+ _addExtensions(items) {
+ if (!Array.isArray(items))
+ FAIL("Property 'extensions' must be array");
+
+ for (let i = 0; i < items.length; i++) {
+ const item = items[i];
+ const name = item.name;
+
+ const obj = {
+ name: name,
+ from: item.from || ""
+ };
+
+ this._extensions[name] = obj;
+ }
+ }
+
+ _addAttributes(items) {
+ if (!Array.isArray(items))
+ FAIL("Property 'attributes' must be array");
+
+ for (let i = 0; i < items.length; i++) {
+ const item = items[i];
+ const name = item.name;
+ const type = item.type;
+
+ if (!/^(?:flag|string|string\[\])$/.test(type))
+ FAIL(`Unknown attribute type '${type}'`);
+
+ const obj = {
+ name: name,
+ type: type,
+ doc : item.doc || ""
+ };
+
+ this._attributes[name] = obj;
+ }
+ }
+
+ _addSpecialRegs(items) {
+ if (!Array.isArray(items))
+ FAIL("Property 'specialRegs' must be array");
+
+ for (let i = 0; i < items.length; i++) {
+ const item = items[i];
+ const name = item.name;
+
+ const obj = {
+ name : name,
+ group: item.group || name,
+ doc : item.doc || ""
+ };
+
+ this._specialRegs[name] = obj;
+ }
+ }
+
+ _addShortcuts(items) {
+ if (!Array.isArray(items))
+ FAIL("Property 'shortcuts' must be array");
+
+ for (let i = 0; i < items.length; i++) {
+ const item = items[i];
+ const name = item.name;
+ const expand = item.expand;
+
+ if (!name || !expand)
+ FAIL("Shortcut must contain 'name' and 'expand' properties");
+
+ const obj = {
+ name : name,
+ expand: expand,
+ doc : item.doc || ""
+ };
+
+ this._shortcuts[name] = obj;
+ }
+ }
+
+ _addInstructions(instructions) {
+ FAIL("ISA._addInstructions() must be reimplemented");
+ }
+
+ _addInstruction(instruction) {
+ let group;
+
+ if (Object.hasOwn(this._instructionMap, instruction.name)) {
+ group = this._instructionMap[instruction.name];
+ }
+ else {
+ group = new InstructionGroup();
+ this._instructionNames = null;
+ this._instructionMap[instruction.name] = group;
+ this.stats.groups++;
+ }
+
+ if (instruction.aliasOf) {
+ this._addAlias(instruction.name, instruction.aliasOf);
+ }
+
+ group.push(instruction);
+ this.stats.instructions++;
+ this._instructions = null;
+
+ return this;
+ }
+
+ // Add aliases from instruction database - aliases must be an object where each key is a non-aliased instruction.
+ _addAliases(aliases) {
+ for (let instructionName in aliases) {
+ const data = aliases[instructionName];
+ for (let aliasName of data.aliases) {
+ this._addAlias(instructionName, aliasName, data.format || "");
+ }
+ }
+ }
+
+ _addAlias(instructionName, aliasName, aliasFormat) {
+ const group = this._instructionMap[instructionName];
+ if (!group) {
+ FAIL(`Instruction ${instructionName} doesn't exist when processing alias (${aliasName})`);
+ }
+
+ let alias = this._aliases[instructionName];
+ if (!alias) {
+ alias = dict({
+ primaryName: instructionName,
+ aliasNames: [],
+ format: ""
+ });
+ this._aliases[instructionName] = alias;
+ }
+
+ this._aliasMap[aliasName] = instructionName;
+ alias.aliasNames.push(aliasName);
+ alias.format = aliasFormat || "";
+ }
+}
+base.ISA = ISA;
+
+}).apply(this, typeof module === "object" && module && module.exports
+ ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "base"]);
diff --git a/3rdparty/asmjit/db/exp.js b/3rdparty/asmjit/db/exp.js
new file mode 100644
index 00000000000..32674b78762
--- /dev/null
+++ b/3rdparty/asmjit/db/exp.js
@@ -0,0 +1,760 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See <asmjit/core.h> or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+(function($scope, $as) {
+"use strict";
+
+// Supported Operators
+// -------------------
+
+const kUnaryOperators = {
+ "-": {prec: 3, rtl : 1, emit: "-@1" },
+ "~": {prec: 3, rtl : 1, emit: "~@1" },
+ "!": {prec: 3, rtl : 1, emit: "!@1" }
+};
+
+const kBinaryOperators = {
+ "*" : { prec: 5, rtl : 0, emit: "@1 * @2" },
+ "/" : { prec: 5, rtl : 0, emit: "@1 / @2" },
+ "%" : { prec: 5, rtl : 0, emit: "@1 % @2" },
+ "+" : { prec: 6, rtl : 0, emit: "@1 + @2" },
+ "-" : { prec: 6, rtl : 0, emit: "@1 - @2" },
+ ">>": { prec: 7, rtl : 0, emit: "@1 >> @2" },
+ "<<": { prec: 7, rtl : 0, emit: "@1 << @2" },
+ "<" : { prec: 9, rtl : 0, emit: "@1 < @2" },
+ ">" : { prec: 9, rtl : 0, emit: "@1 > @2" },
+ "<=": { prec: 9, rtl : 0, emit: "@1 <= @2" },
+ ">=": { prec: 9, rtl : 0, emit: "@1 >= @2" },
+ "==": { prec:10, rtl : 0, emit: "@1 == @2" },
+ "!=": { prec:10, rtl : 0, emit: "@1 != @2" },
+ "&" : { prec:11, rtl : 0, emit: "@1 & @2" },
+ "^" : { prec:12, rtl : 0, emit: "@1 ^ @2" },
+ "|" : { prec:13, rtl : 0, emit: "@1 | @2" },
+ "&&": { prec:14, rtl : 0, emit: "@1 && @2" },
+ "||": { prec:15, rtl : 0, emit: "@1 || @2" },
+ "?" : { prec:16, rtl : 0, emit: "@1 ? @2" },
+ ":" : { prec:16, rtl : 0, emit: "@1 : @2" }
+};
+
+const kMaxOperatorLen = 4;
+
+function rightAssociate(info, bPrec) {
+ return info.prec > bPrec || (info.prec === bPrec && info.rtl);
+}
+
+// Expression Error
+// ----------------
+
+// Contains `message` and `position` members. If the `position` is not `-1` then it is
+// a zero-based index, which points to a first character of the token near the error.
+class ExpressionError extends Error {
+ constructor(message, position) {
+ super(message);
+ this.name = "ExpressionError";
+ this.message = message;
+ this.position = position != null ? position : -1;
+ }
+}
+
+function throwTokenizerError(token) {
+ throw new ExpressionError(`Unexpected token '${token.data}'`, token.position);
+}
+
+function throwExpressionError(message, position) {
+ throw new ExpressionError(message, position);
+}
+
+// Expression Tree
+// ---------------
+
+function mustEnclose(node) {
+ return node.isUnary() ? node.child.isOperator() : node.isBinary() ? true : false;
+}
+
+class ExpNode {
+ constructor(type) { this.type = type; }
+
+ isImm() { return this.type === "imm"; }
+ isVar() { return this.type === "var"; }
+ isCall() { return this.type === "call"; }
+ isUnary() { return this.type === "unary"; }
+ isBinary() { return this.type === "binary"; }
+ isOperator() { return this.type === "unary" || this.type === "binary"; }
+
+ info() { return null; }
+ clone() { throw new Error("ExpNode.clone() must be overridden"); }
+ evaluate(ctx) { throw new Error("ExpNode.evaluate() must be overridden"); }
+ toString(ctx) { throw new Error("ExpNode.toString() must be overridden"); }
+}
+
+class ImmNode extends ExpNode {
+ constructor(imm) {
+ super("imm");
+ this.imm = imm || 0;
+ }
+
+ clone() { return new ImmNode(this.imm); }
+ evaluate(ctx) { return this.imm; }
+ toString(ctx) { return ctx ? ctx.stringifyImmediate(this.imm) : String(this.imm); }
+}
+
+class VarNode extends ExpNode {
+ constructor(name) {
+ super("var");
+ this.name = name || "";
+ }
+
+ clone() { return new VarNode(this.name); }
+ evaluate(ctx) { return ctx.variable(this.name); }
+ toString(ctx) { return ctx ? ctx.stringifyVariable(this.name) : String(this.name); }
+}
+
+class CallNode extends ExpNode {
+ constructor(name, args) {
+ super("call");
+ this.name = name || "";
+ this.args = args || [];
+ }
+
+ clone() {
+ return new CallNode(this.name, this.args.map(function(arg) { return arg.clone(); }));
+ }
+
+ evaluate(ctx) {
+ const evaluatedArgs = this.args.map(function(arg) { return arg.evaluate(ctx); });
+ return ctx.function(this.name, evaluatedArgs);
+ }
+
+ toString(ctx) {
+ if (this.name === "$bit") {
+ return `((${this.args[0]} >> ${this.args[1]}) & 1)`;
+ }
+ else {
+ let argsCode = this.args.map(function(arg) { return arg.toString(ctx); }).join(", ");
+ if (ctx)
+ return `${ctx.stringifyFunction(this.name)}(${argsCode})`;
+ else
+ return `${this.name}(${argsCode})`;
+ }
+ }
+}
+
+class UnaryNode extends ExpNode {
+ constructor(op, child) {
+ if (!Object.hasOwn(kUnaryOperators, op))
+ throw new Error(`Invalid unary operator '${op}`);
+
+ super("unary");
+ this.op = op;
+ this.child = child || null;
+ }
+
+ info() {
+ return kUnaryOperators[this.op];
+ }
+
+ clone() {
+ return new UnaryNode(this.op, this.left ? this.left.clone() : null);
+ }
+
+ evaluate(ctx) {
+ const val = this.child.evaluate(ctx);
+ switch (this.op) {
+ case "-": return (-val);
+ case "~": return (~val);
+ case "!": return (val ? 0 : 1);
+ default : return ctx.unary(this.op, val);
+ }
+ }
+
+ toString(ctx) {
+ return this.info().emit.replace(/@1/g, () => {
+ const node = this.child;
+ const code = node.toString(ctx);
+ return mustEnclose(node) ? `(${code})` : code;
+ });
+ }
+}
+
+class BinaryNode extends ExpNode {
+ constructor(op, left, right) {
+ if (!Object.hasOwn(kBinaryOperators, op))
+ throw new Error(`Invalid binary operator '${op}`);
+
+ super("binary");
+ this.op = op || "";
+ this.left = left || null;
+ this.right = right || null;
+ }
+
+ info() {
+ return kBinaryOperators[this.op];
+ }
+
+ clone() {
+ return new BinaryNode(this.op, this.left ? this.left.clone() : null, this.right ? this.right.clone() : null);
+ }
+
+ evaluate(ctx) {
+ const left = this.left.evaluate(ctx);
+ const right = this.right.evaluate(ctx);
+
+ switch (this.op) {
+ case "-" : return left - right;
+ case "+" : return left + right;
+ case "*" : return left * right;
+ case "/" : return (left / right)|0;
+ case "%" : return (left % right)|0;
+ case "&" : return left & right;
+ case "|" : return left | right;
+ case "^" : return left ^ right;
+ case "<<": return left << right;
+ case ">>": return left >> right;
+ case "==": return left == right ? 1 : 0;
+ case "!=": return left != right ? 1 : 0;
+ case "<" : return left < right ? 1 : 0;
+ case "<=": return left <= right ? 1 : 0;
+ case ">" : return left > right ? 1 : 0;
+ case ">=": return left >= right ? 1 : 0;
+ case "&&": return left && right ? 1 : 0;
+ case "||": return left || right ? 1 : 0;
+ default : return ctx.binary(this.op, left, right);
+ }
+ }
+
+ toString(ctx) {
+ return this.info().emit.replace(/@[1-2]/g, (p) => {
+ const node = p === "@1" ? this.left : this.right;
+ const code = node.toString(ctx);
+ return mustEnclose(node) ? `(${code})` : code;
+ });
+ }
+}
+
+function Imm(imm) { return new ImmNode(imm); }
+function Var(name) { return new VarNode(name); }
+function Call(name, args) { return new CallNode(name, args); }
+function Unary(op, child) { return new UnaryNode(op, child); }
+function Binary(op, left, right) { return new BinaryNode(op, left, right); }
+
+function Negate(child) { return Unary("-", child); }
+function BitNot(child) { return Unary("~", child); }
+
+function Add(left, right) { return Binary("+", left, right); }
+function Sub(left, right) { return Binary("-", left, right); }
+function Mul(left, right) { return Binary("*", left, right); }
+function Div(left, right) { return Binary("/", left, right); }
+function Mod(left, right) { return Binary("%", left, right); }
+function Shl(left, right) { return Binary("<<", left, right); }
+function Shr(left, right) { return Binary(">>", left, right); }
+function BitAnd(left, right) { return Binary("&", left, right); }
+function BitOr(left, right) { return Binary("|", left, right); }
+function BitXor(left, right) { return Binary("^", left, right); }
+function Eq(left, right) { return Binary("==", left, right); }
+function Ne(left, right) { return Binary("!=", left, right); }
+function Lt(left, right) { return Binary("<", left, right); }
+function Le(left, right) { return Binary("<=", left, right); }
+function Gt(left, right) { return Binary(">", left, right); }
+function Ge(left, right) { return Binary(">=", left, right); }
+function And(left, right) { return Binary("&&", left, right); }
+function Or(left, right) { return Binary("||", left, right); }
+
+
+
+// Expression Tokenizer
+// --------------------
+
+const kCharNone = 0; // '_' - Character category - Invalid or <end>.
+const kCharSpace = 1; // 'S' - Character category - Space.
+const kCharAlpha = 2; // 'A' - Character category - Alpha [A-Za-z_].
+const kCharDigit = 3; // 'D' - Character category - Digit [0-9].
+const kCharPunct = 4; // '$' - Character category - Punctuation.
+
+const Category = (function(_, S, A, D, $) {
+ const Table = [
+ _,_,_,_,_,_,_,_,_,S,S,S,S,S,_,_, // 000-015 |......... ..|
+ _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, // 016-031 |................|
+ S,$,$,$,$,$,$,$,$,$,$,$,$,$,$,$, // 032-047 | !"#$%&'()*+,-./|
+ D,D,D,D,D,D,D,D,D,D,$,$,$,$,$,$, // 048-063 |0123456789:;<=>?|
+ $,A,A,A,A,A,A,A,A,A,A,A,A,A,A,A, // 064-079 |@ABCDEFGHIJKLMNO|
+ A,A,A,A,A,A,A,A,A,A,A,$,$,$,$,A, // 080-095 |PQRSTUVWXYZ[\]^_|
+ $,A,A,A,A,A,A,A,A,A,A,A,A,A,A,A, // 096-111 |`abcdefghijklmno|
+ A,A,A,A,A,A,A,A,A,A,A,$,$,$,$,_, // 112-127 |pqrstuvwxyz{|}~ |
+ _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, // 128-143 |................|
+ _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_ // 144-159 |................|
+ ];
+ const kTableLength = Table.length;
+
+ return function(c) {
+ if (c < kTableLength)
+ return Table[c];
+ return kCharNone;
+ };
+})(kCharNone, kCharSpace, kCharAlpha, kCharDigit, kCharPunct);
+
+const kTokenNone = 0;
+const kTokenPunct = 1;
+const kTokenIdent = 2;
+const kTokenValue = 3;
+
+function newToken(type, position, data, value) {
+ return {
+ type : type, // Token type, see `kToken...`.
+ position: position, // Token position in expression's source.
+ data : data, // Token data (content) as string.
+ value : value // Token value (only if the token is a value).
+ };
+}
+const NoToken = newToken(kTokenNone, -1, "<end>", null);
+
+// Must be reset before it can be used, use `RegExp.lastIndex`.
+const reNumValue = /(?:(?:\d*\.\d+|\d+)(?:[E|e][+|-]?\d+)?)/g;
+
+function parseHex(source, from) {
+ let i = from;
+ let number = 0;
+
+ while (i < source.length) {
+ let c = source.charCodeAt(i);
+ let n = 0;
+
+ if (c >= '0'.charCodeAt(0) && c <= '9'.charCodeAt(0)) {
+ n = c - '0'.charCodeAt(0);
+ }
+ else if (c >= 'a'.charCodeAt(0) && c <= 'f'.charCodeAt(0)) {
+ n = c - 'a'.charCodeAt(0) + 10;
+ }
+ else if (c >= 'A'.charCodeAt(0) && c <= 'F'.charCodeAt(0)) {
+ n = c - 'A'.charCodeAt(0) + 10;
+ }
+ else if (c >= 'g'.charCodeAt(0) && c <= 'z'.charCodeAt(0) || c >= 'g'.charCodeAt(0) && c <= 'Z'.charCodeAt(0)) {
+ throwExpressionError(`Invalid hex number 0x${source.substring(from, i + 1)}`);
+ }
+ else {
+ break;
+ }
+
+ number = (number << 4) | n;
+ i++;
+ }
+
+ if (i === from)
+ throwExpressionError(`Invalid number starting with 0x`);
+
+ return {
+ number: number,
+ end: i
+ };
+}
+
+function tokenize(source) {
+ const len = source.length;
+ const tokens = [];
+
+ let i = 0, j = 0; // Current index in `source` and temporary.
+ let start = 0; // Current token start position.
+ let data = ""; // Current token data (content) as string.
+ let c, cat; // Current character code and category.
+
+ while (i < len) {
+ c = source.charCodeAt(i);
+ cat = Category(c);
+
+ if (cat === kCharSpace) {
+ i++;
+ }
+ else if (cat === kCharDigit) {
+ const n = tokens.length - 1;
+
+ // Hex number.
+ if (c === '0'.charCodeAt(0) && i + 1 < len && source.charCodeAt(i + 1) === 'x'.charCodeAt(0)) {
+ const status = parseHex(source, i + 2);
+ tokens.push(newToken(kTokenValue, i, source.substring(i, status.end), status.number));
+ i = status.end;
+ }
+ else {
+ if (n >= 0 && tokens[n].data === "." && source[i - 1] === ".") {
+ tokens.length = n;
+ i--;
+ }
+
+ reNumValue.lastIndex = i;
+ data = reNumValue.exec(source)[0];
+
+ tokens.push(newToken(kTokenValue, i, data, parseFloat(data)));
+ i += data.length;
+ }
+ }
+ else if (cat === kCharAlpha) {
+ start = i;
+ while (++i < len && ((cat = Category(source.charCodeAt(i))) === kCharAlpha || cat === kCharDigit))
+ continue;
+
+ data = source.substring(start, i);
+ tokens.push(newToken(kTokenIdent, start, data, null));
+ }
+ else if (cat === kCharPunct) {
+ start = i;
+ while (++i < len && Category(source.charCodeAt(i)) === kCharPunct)
+ continue;
+
+ data = source.substring(start, i);
+ do {
+ for (j = Math.min(i - start, kMaxOperatorLen); j > 0; j--) {
+ const part = source.substr(start, j);
+ if (Object.hasOwn(kUnaryOperators, part) || Object.hasOwn(kBinaryOperators, part) || j === 1) {
+ tokens.push(newToken(kTokenPunct, start, part, null));
+ start += j;
+ break;
+ }
+ }
+ } while (start < i);
+ }
+ else {
+ throwExpressionError(`Unrecognized character '0x${c.toString(16)}'`, i);
+ }
+ }
+
+ return tokens;
+}
+
+// Expression Parser
+// -----------------
+
+class Parser {
+ constructor(tokens) {
+ this.tokens = tokens;
+ this.tIndex = 0;
+ }
+
+ peek() { return this.tIndex < this.tokens.length ? this.tokens[this.tIndex ] : NoToken; }
+ next() { return this.tIndex < this.tokens.length ? this.tokens[this.tIndex++] : NoToken; }
+ skip() { this.tIndex++; return this; }
+ back(token) { this.tIndex -= +(token !== NoToken); return this; }
+
+ parse() {
+ // The root expression cannot be empty.
+ let token = this.peek();
+ if (token === NoToken)
+ throwExpressionError("Expression cannot be empty", 0);
+
+ const exp = this.parseExpression();
+
+ // The root expression must reach the end of the input.
+ token = this.peek();
+ if (token !== NoToken)
+ throwTokenizerError(token);
+
+ return exp;
+ }
+
+ parseExpression() {
+ const stack = [];
+ let value = null;
+ let token = null;
+
+ for (;;) {
+ // The only case of value not being `null` is after ternary-if. In that
+ // case the value was already parsed so we want to skip this section.
+ if (value === null) {
+ let unaryFirst = null;
+ let unaryLast = null;
+
+ token = this.next();
+
+ // Parse a possible unary operator(s).
+ if (token.type === kTokenPunct) {
+ do {
+ const opName = token.data;
+ const opInfo = kUnaryOperators[opName];
+
+ if (!opInfo)
+ break;
+
+ const node = Unary(opName);
+ if (unaryLast)
+ unaryLast.child = node;
+ else
+ unaryFirst = node;
+
+ unaryLast = node;
+ token = this.next();
+ } while (token.type === kTokenPunct);
+ }
+
+ // Parse a value, variable, function call, or nested expression.
+ if (token.type === kTokenValue) {
+ value = Imm(token.value);
+ }
+ else if (token.type === kTokenIdent) {
+ const name = token.data;
+ const after = this.peek();
+
+ if (after.data === "(")
+ value = this.parseCall(token.data);
+ else if (after.data === "[")
+ value = this.parseBitAccess(token.data);
+ else
+ value = Var(name);
+ }
+ else if (token.data === "(") {
+ value = this.parseExpression();
+ token = this.next();
+
+ if (token.data !== ")")
+ throwTokenizerError(token);
+ }
+ else {
+ throwTokenizerError(token);
+ }
+
+ // Replace the value with the top-level unary operator, if parsed.
+ if (unaryFirst) {
+ unaryLast.child = value;
+ value = unaryFirst;
+ }
+ }
+
+ // Parse a possible binary operator - the loop must repeat, if present.
+ token = this.peek();
+ if (token.type === kTokenPunct && Object.hasOwn(kBinaryOperators, token.data)) {
+ const opName = token.data;
+ if (opName === ":")
+ break;
+
+ // Consume the token.
+ this.skip();
+
+ const bNode = Binary(opName, null, null);
+
+ if (!stack.length) {
+ bNode.left = value;
+ stack.push(bNode);
+ }
+ else {
+ let aNode = stack.pop();
+ let aPrec = aNode.info().prec;
+ let bPrec = bNode.info().prec;
+
+ if (aPrec > bPrec) {
+ aNode.right = bNode;
+ bNode.left = value;
+ stack.push(aNode, bNode);
+ }
+ else {
+ aNode.right = value;
+
+ // Advance to the top-most op that has less/equal precedence than `bPrec`.
+ while (stack.length) {
+ if (rightAssociate(aNode.info(), bPrec))
+ break;
+ aNode = stack.pop();
+ }
+
+ if (!stack.length && !rightAssociate(aNode.info(), bPrec)) {
+ bNode.left = aNode;
+ stack.push(bNode);
+ }
+ else {
+ const tmp = aNode.right;
+ aNode.right = bNode;
+ bNode.left = tmp;
+ stack.push(aNode, bNode);
+ }
+ }
+ }
+
+ // Parse "<cond> {ternary-if} <taken> {ternary-else} <not-taken>".
+ if (opName === "?") {
+ const ternLeft = this.parseExpression();
+ const ternTok = this.next();
+
+ if (ternTok.data !== ":")
+ throwExpressionError(`Unterminated ternary if '${token.data}'`, token.position);
+
+ const ternRight = this.parseExpression();
+ value = Binary(opName, info, ternLeft, ternRight);
+ }
+ else {
+ value = null;
+ }
+
+ continue;
+ }
+
+ break;
+ }
+
+ if (value === null)
+ throwExpressionError("Invalid expression");
+
+ if (stack.length !== 0) {
+ stack[stack.length - 1].right = value;
+ value = stack[0];
+ }
+
+ return value;
+ }
+
+ parseCall(name) {
+ const args = [];
+
+ let token = this.next();
+ if (token.data !== "(")
+ throwTokenizerError(token);
+
+ for (;;) {
+ token = this.peek();
+ if (token.data === ")")
+ break;
+
+ if (args.length !== 0) {
+ if (token.data !== ",")
+ throwTokenizerError(token);
+ this.skip();
+ }
+
+ args.push(this.parseExpression());
+ }
+
+ this.skip();
+ return Call(name, args);
+ }
+
+ parseBitAccess(name) {
+ let token = this.next();
+ if (token.data !== "[")
+ throwTokenizerError(token);
+
+ token = this.next();
+ if (token.type != kTokenValue)
+ throwTokenizerError(token);
+
+ const index = token.value;
+
+ token = this.next();
+ if (token.data !== "]")
+ throwTokenizerError(token);
+
+ return Call("$bit", [Var(name), index]);
+ }
+}
+
+function parse(source) {
+ const tokens = tokenize(source);
+ return new Parser(tokens).parse();
+}
+
+// Expression Visitors
+// -------------------
+
+class Visitor {
+ visit(node) {
+ switch (node.type) {
+ case "imm":
+ case "var": {
+ break;
+ }
+
+ case "call": {
+ for (let arg of node.args)
+ this.visit(arg);
+ break;
+ }
+
+ case "unary": {
+ if (node.child)
+ this.visit(node.child);
+ break;
+ }
+
+ case "binary": {
+ if (node.left)
+ this.visit(node.left);
+ if (node.right)
+ this.visit(node.right);
+ break;
+ }
+
+ default: {
+ throw new Error(`Visitor.visit(): Unknown node type '${node.type}'`);
+ }
+ }
+ }
+}
+
+class Collector extends Visitor {
+ constructor(nodeType, dst) {
+ super();
+ this.dict = dst || Object.create(null);
+ this.nodeType = nodeType;
+ }
+
+ visit(node) {
+ if (node.type === this.nodeType) {
+ if (Object.hasOwn(this.dict, node.name))
+ this.dict[node.name]++;
+ else
+ this.dict[node.name] = 1;
+ }
+
+ super.visit(node);
+ }
+}
+
+function collectVars(node, dst) {
+ const collector = new Collector("var", dst);
+ collector.visit(node)
+ return collector.dict;
+}
+
+function collectCalls(node, dst) {
+ const collector = new Collector("call", dst);
+ collector.visit(node)
+ return collector.dict;
+}
+
+// Exports
+// -------
+
+$scope[$as] = {
+ Imm: Imm,
+ Var: Var,
+ Call: Call,
+ Unary: Unary,
+ Binary: Binary,
+
+ Negate: Negate,
+ BitNot: BitNot,
+
+ Add: Add,
+ Sub: Sub,
+ Mul: Mul,
+ Div: Div,
+ Mod: Mod,
+ Shl: Shl,
+ Shr: Shr,
+ BitAnd: BitAnd,
+ BitOr: BitOr,
+ BitXor: BitXor,
+ Eq: Eq,
+ Ne: Ne,
+ Lt: Lt,
+ Le: Le,
+ Gt: Gt,
+ Ge: Ge,
+ And: And,
+ Or: Or,
+
+ Visitor: Visitor,
+ ExpressionError: ExpressionError,
+
+ parse: parse,
+ collectVars: collectVars,
+ collectCalls: collectCalls
+};
+
+}).apply(this, typeof module === "object" && module && module.exports
+ ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "exp"]);
diff --git a/3rdparty/asmjit/db/index.js b/3rdparty/asmjit/db/index.js
new file mode 100644
index 00000000000..bf55e6f94b0
--- /dev/null
+++ b/3rdparty/asmjit/db/index.js
@@ -0,0 +1,11 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See <asmjit/core.h> or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+"use strict";
+
+exports.base = require("./base.js");
+exports.aarch32 = require("./aarch32.js");
+exports.aarch64 = require("./aarch64.js");
+exports.x86 = require("./x86.js");
diff --git a/3rdparty/asmjit/db/isa_aarch32.json b/3rdparty/asmjit/db/isa_aarch32.json
new file mode 100644
index 00000000000..2e53010054d
--- /dev/null
+++ b/3rdparty/asmjit/db/isa_aarch32.json
@@ -0,0 +1,2783 @@
+{
+ "instructions": [
+ {"category": "GP", "data": [
+ {"inst": "adc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0101|0|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "C=R"},
+ {"inst": "adc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0101|0|Rn|Rd|n:5|sop:2|0|Rm" , "io": "C=R"},
+ {"inst": "adc Rd, Rn, #immA" , "a32": "cond|001|0101|0|Rn|Rd|imm:12" , "io": "C=R"},
+ {"inst": "adcS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0101|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "adcS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0101|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "adcS Rd!=PC, Rn, #immA" , "a32": "cond|001|0101|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "add Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0100|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "add Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0100|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "add Rd, Rn!=PC, #immA" , "a32": "cond|001|0100|0|Rn|Rd|imm:12"},
+ {"inst": "addS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0100|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0100|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=PC, Rn, #immA" , "a32": "cond|001|0100|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adr Rd, #relA" , "a32": "cond|001|0PN0|0|1111|Rd|relA:12"},
+ {"inst": "and Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0000|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "and Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0000|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "and Rd, Rn, #immA" , "a32": "cond|001|0000|0|Rn|Rd|imm:12"},
+ {"inst": "andS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0000|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "andS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0000|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "andS Rd!=PC, Rn, #immA" , "a32": "cond|001|0000|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "asr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0101|Rn"},
+ {"inst": "asr Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|100|Rn"},
+ {"inst": "asrS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0101|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "asrS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|100|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "b #relS*4" , "a32": "cond|101|0|relS:24"},
+ {"inst": "bfc Rd!=PC, #lsb, #width" , "a32": "cond|011|1110|msb:5|Rd|lsb:5|001|1111" , "imm": "BfcBfiImm(lsb, width)"},
+ {"inst": "bfi Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1110|msb:5|Rd|lsb:5|001|Rn" , "imm": "BfcBfiImm(lsb, width)"},
+ {"inst": "bic Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1110|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "bic Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|1110|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "bic Rd, Rn, #immA" , "a32": "cond|001|1110|0|Rn|Rd|imm:12"},
+ {"inst": "bicS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1110|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "bicS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|1110|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "bicS Rd!=PC, Rn, #immA" , "a32": "cond|001|1110|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "bkpt #immZ" , "a32": "cond|000|1001|0|immZ:12|0111|immZ:4"},
+ {"inst": "bl #relS*4" , "a32": "cond|101|1|relS:24"},
+ {"inst": "blx Rm!=PC" , "a32": "cond|000|1001|0|1111|1111|1111|0011|Rm"},
+ {"inst": "blx #relS*2" , "a32": "1111|101|relS[0]|relS[24:1]" },
+ {"inst": "bx Rm" , "a32": "cond|000|1001|0|1111|1111|1111|0001|Rm"},
+ {"inst": "bxj Rm!=PC" , "a32": "cond|000|1001|0|1111|1111|1111|0010|Rm"},
+ {"inst": "clz Rd!=PC, Rn!=PC" , "a32": "cond|000|1011|0|1111|Rd|1111|0001|Rn"},
+ {"inst": "cmn Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1011|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Rn, Rm, {sop #n}" , "a32": "cond|000|1011|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Rn, #immA" , "a32": "cond|001|1011|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1010|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn, Rm, {sop #n}" , "a32": "cond|000|1010|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn, #immA" , "a32": "cond|001|1010|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cps #immZ" , "a32": "1111|000|1000|0|0010|0000|000|000|0|immZ:5"},
+ {"inst": "cpsid #aif" , "a32": "1111|000|1000|0|1100|0000|000|aif:3|0|00000"},
+ {"inst": "cpsid #aif, #immZ" , "a32": "1111|000|1000|0|1110|0000|000|aif:3|0|immZ:5"},
+ {"inst": "cpsie #aif" , "a32": "1111|000|1000|0|1000|0000|000|aif:3|0|00000"},
+ {"inst": "cpsie #aif, #immZ" , "a32": "1111|000|1000|0|1010|0000|000|aif:3|0|immZ:5"},
+ {"inst": "eor Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0001|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "eor Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0001|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "eor Rd, Rn, #immA" , "a32": "cond|001|0001|0|Rn|Rd|imm:12"},
+ {"inst": "eorS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0001|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "eorS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0001|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "eorS Rd!=PC, Rn, #immA" , "a32": "cond|001|0001|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "eret" , "a32": "cond|000|1011|0|0000|0000|0000|0110|1110"},
+ {"inst": "hlt #immZ" , "a32": "1110|000|1000|0|immZ:12|0111|immZ:4"},
+ {"inst": "hvc #immZ" , "a32": "cond|000|1010|0|immZ:12|0111|immZ:4"},
+ {"inst": "ldmda [Rn!=PC]{!}, RdList" , "a32": "cond|100|000W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmdb [Rn!=PC]{!}, RdList" , "a32": "cond|100|100W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmia [Rn!=PC]{!}, RdList" , "a32": "cond|100|010W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmib [Rn!=PC]{!}, RdList" , "a32": "cond|100|110W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmda [Rn!=PC], RdList^" , "a32": "cond|100|0010|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmdb [Rn!=PC], RdList^" , "a32": "cond|100|1010|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmia [Rn!=PC], RdList^" , "a32": "cond|100|0110|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldmib [Rn!=PC], RdList^" , "a32": "cond|100|1110|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "ldr Rd, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU0W|1|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "ldr Rd, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU0W|1|Rn|Rd|off:12"},
+ {"inst": "ldr Rd, [Rn==PC, #+/-off]" , "a32": "cond|010|1U00|1|Rn|Rd|off:12"},
+ {"inst": "ldrb Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU1W|1|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "ldrb Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU1W|1|Rn|Rd|off:12"},
+ {"inst": "ldrb Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|1U10|1|Rn|Rd|off:12"},
+ {"inst": "ldrbt Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U11|1|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "ldrbt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U11|1|Rn|Rd|off:12"},
+ {"inst": "ldrd Rd<=13, Rd2+, [Rn!=PC, +/-Rm]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rd|0000|1101|Rm"},
+ {"inst": "ldrd Rd<=13, Rd2+, [Rn!=PC, #+/-off]{!}" , "a32": "cond|000|PU1W|0|Rn|Rd|off:4|1101|off:4"},
+ {"inst": "ldrd Rd<=13, Rd2+, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rd|off:4|1101|off:4"},
+ {"inst": "ldrex Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1111|1001|1111"},
+ {"inst": "ldrexb Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1111|1001|1111"},
+ {"inst": "ldrexd Rd<=13, Rd2+, [Rn!=PC]" , "a32": "cond|000|1101|1|Rn|Rd|1111|1001|1111"},
+ {"inst": "ldrexh Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1111|1001|1111"},
+ {"inst": "ldrh Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1011|Rm"},
+ {"inst": "ldrh Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1011|off:4"},
+ {"inst": "ldrh Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1011|off:4"},
+ {"inst": "ldrht Rd!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1011|Rm"},
+ {"inst": "ldrht Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1011|off:4"},
+ {"inst": "ldrsb Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1101|Rm"},
+ {"inst": "ldrsb Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1101|off:4"},
+ {"inst": "ldrsb Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1101|off:4"},
+ {"inst": "ldrsbt Rd!=PC, [Rn!=PC, +/-Rm]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1101|Rm"},
+ {"inst": "ldrsbt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1101|off:4"},
+ {"inst": "ldrsh Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1111|Rm"},
+ {"inst": "ldrsh Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1111|off:4"},
+ {"inst": "ldrsh Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1111|off:4"},
+ {"inst": "ldrsht Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1111|off:4"},
+ {"inst": "ldrsht Rd!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1111|Rm"},
+ {"inst": "ldrt Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U01|1|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "ldrt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U01|1|Rn|Rd|off:12"},
+ {"inst": "lsl Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|000|Rn"},
+ {"inst": "lsl Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0001|Rn"},
+ {"inst": "lslS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|000|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "lslS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0001|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "lsr Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|010|Rn"},
+ {"inst": "lsr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0011|Rn"},
+ {"inst": "lsrS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|010|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "lsrS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0011|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "mcr #CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "a32": "cond|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4"},
+ {"inst": "mcr2 #CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "a32": "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4"},
+ {"inst": "mcrr #CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "a32": "cond|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4"},
+ {"inst": "mcrr2 #CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "a32": "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4"},
+ {"inst": "mla Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0001|0|Rd|Ra|Rm|1001|Rn"},
+ {"inst": "mlaS Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0001|1|Rd|Ra|Rm|1001|Rn" , "io": "N=W Z=W"},
+ {"inst": "mls Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0011|0|Rd|Ra|Rm|1001|Rn"},
+ {"inst": "mov Rd, Rn, sop Rs" , "a32": "cond|000|1101|0|0000|Rd|Rs|0|sop:2|1|Rn"},
+ {"inst": "mov Rd, Rn, {sop #n}" , "a32": "cond|000|1101|0|0000|Rd|n:5|sop:2|0|Rn"},
+ {"inst": "mov Rd, #immA" , "a32": "cond|001|1101|0|0000|Rd|imm:12"},
+ {"inst": "movS Rd!=PC, Rn, sop Rs" , "a32": "cond|000|1101|1|0000|Rd|Rs|0|sop:2|1|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=PC, Rn, {sop #n}" , "a32": "cond|000|1101|1|0000|Rd|n:5|sop:2|0|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=PC, #immA" , "a32": "cond|001|1101|1|0000|Rd|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "movt Rx!=PC, #immZ" , "a32": "cond|001|1010|0|immZ:4|Rx|immZ:12"},
+ {"inst": "movw Rd!=PC, #immZ" , "a32": "cond|001|1000|0|immZ:4|Rd|immZ:12"},
+ {"inst": "mrc #CP, #op1, Rd!=PC, Cn, Cm, {#op2}" , "a32": "cond|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4"},
+ {"inst": "mrc2 #CP, #op1, Rd!=PC, Cn, Cm, {#op2}" , "a32": "1111|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4"},
+ {"inst": "mrrc #CP, #op1, Rd!=PC, Rd2!=Rd, Cm" , "a32": "cond|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4"},
+ {"inst": "mrrc2 #CP, #op1, Rd!=PC, Rd2!=Rd, Cm" , "a32": "1111|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4"},
+ {"inst": "mrs Rd!=PC, #APSR" , "a32": "cond|000|10|APSR:1|0|0|1111|Rd|0000|0000|0000"},
+ {"inst": "msr #APSR, Rn!=PC" , "a32": "cond|000|1001|0|APSR:2|00|1111|0000|0000|Rn"},
+ {"inst": "msr #APSR, #immA" , "a32": "cond|001|1001|0|APSR:2|00|1111|imm:12"},
+ {"inst": "mul Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0000|0|Rd|0000|Rm|1001|Rn"},
+ {"inst": "mulS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0000|1|Rd|0000|Rm|1001|Rn" , "io": "N=W Z=W"},
+ {"inst": "mvn Rd!=PC, Rn!=PC, sop Rs!=PC" , "a32": "cond|000|1111|0|0000|Rd|Rs|0|sop:2|1|Rn"},
+ {"inst": "mvn Rd, Rn, {sop #n}" , "a32": "cond|000|1111|0|0000|Rd|n:5|sop:2|0|Rn"},
+ {"inst": "mvn Rd, #immA" , "a32": "cond|001|1111|0|0000|Rd|imm:12"},
+ {"inst": "mvnS Rd!=PC, Rn!=PC, sop Rs!=PC" , "a32": "cond|000|1111|1|0000|Rd|Rs|0|sop:2|1|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "mvnS Rd!=PC, Rn, {sop #n}" , "a32": "cond|000|1111|1|0000|Rd|n:5|sop:2|0|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "mvnS Rd!=PC, #immA" , "a32": "cond|001|1111|1|0000|Rd|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "nop" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0000"},
+ {"inst": "orr Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1100|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "orr Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|1100|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "orr Rd, Rn, #immA" , "a32": "cond|001|1100|0|Rn|Rd|imm:12"},
+ {"inst": "orrS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1100|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "orrS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|1100|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "orrS Rd!=PC, Rn, #immA" , "a32": "cond|001|1100|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "pkhbt Rd!=PC, Rn!=PC, Rm!=PC, {lsl #n}" , "a32": "cond|011|0100|0|Rn|Rd|n:5|0|01|Rm"},
+ {"inst": "pkhtb Rd!=PC, Rn!=PC, Rm!=PC, {asr #n}" , "a32": "cond|011|0100|0|Rn|Rd|n:5|1|01|Rm"},
+ {"inst": "pld [Rn!=PC, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|1U10|1|Rn|1111|n:5|sop:2|0|Rm"},
+ {"inst": "pld [Rn, #+/-off]" , "a32": "1111|010|1U10|1|Rn|1111|off:12"},
+ {"inst": "pop Rd!=SP" , "a32": "cond|010|0100|1|1101|Rd|0000|0000|0100"},
+ {"inst": "pop RdList" , "a32": "cond|100|0101|1|1101|immMask:16" , "imm": "GpListImm(RdList)"},
+ {"inst": "push Rs!=SP" , "a32": "cond|010|1001|0|1101|Rs|0000|0000|0100"},
+ {"inst": "push RsList" , "a32": "cond|100|1001|0|1101|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "qadd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
+ {"inst": "qadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0001|Rm"},
+ {"inst": "qadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|1001|Rm"},
+ {"inst": "qasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0011|Rm"},
+ {"inst": "qdadd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
+ {"inst": "qdsub Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
+ {"inst": "qsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0101|Rm"},
+ {"inst": "qsub Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"},
+ {"inst": "qsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0111|Rm"},
+ {"inst": "qsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|1111|Rm"},
+ {"inst": "rbit Rd!=PC, Rn!=PC" , "a32": "cond|011|0111|1|1111|Rd|1111|0011|Rn"},
+ {"inst": "rev Rd!=PC, Rn!=PC" , "a32": "cond|011|0101|1|1111|Rd|1111|0011|Rn"},
+ {"inst": "rev16 Rd!=PC, Rn!=PC" , "a32": "cond|011|0101|1|1111|Rd|1111|1011|Rn"},
+ {"inst": "revsh Rd!=PC, Rn!=PC" , "a32": "cond|011|0111|1|1111|Rd|1111|1011|Rn"},
+ {"inst": "rfeda [Rn!=PC]{!}" , "a32": "1111|100|000|W|1|Rn|0000|1010|0000|0000"},
+ {"inst": "rfedb [Rn!=PC]{!}" , "a32": "1111|100|100|W|1|Rn|0000|1010|0000|0000"},
+ {"inst": "rfeia [Rn!=PC]{!}" , "a32": "1111|100|010|W|1|Rn|0000|1010|0000|0000"},
+ {"inst": "rfeib [Rn!=PC]{!}" , "a32": "1111|100|110|W|1|Rn|0000|1010|0000|0000"},
+ {"inst": "ror Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|110|Rn"},
+ {"inst": "ror Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0111|Rn"},
+ {"inst": "rorS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|110|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "rorS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0111|Rn" , "io": "N=W Z=W C=W"},
+ {"inst": "rsb Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0011|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "rsb Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0011|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "rsb Rd, Rn, #immA" , "a32": "cond|001|0011|0|Rn|Rd|imm:12"},
+ {"inst": "rsbS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0011|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rsbS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0011|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rsbS Rd!=PC, Rn, #immA" , "a32": "cond|001|0011|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rsc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0111|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "rsc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0111|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "rsc Rd, Rn, #immA" , "a32": "cond|001|0111|0|Rn|Rd|imm:12"},
+ {"inst": "rscS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0111|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rscS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0111|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rscS Rd!=PC, Rn, #immA" , "a32": "cond|001|0111|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rrx Rd, Rn" , "a32": "cond|000|1101|0|0000|Rd|00000|110|Rn" , "io": "C=R"},
+ {"inst": "rrxS Rd, Rn" , "a32": "cond|000|1101|1|0000|Rd|00000|110|Rn" , "io": "N=W Z=W C=X"},
+ {"inst": "sadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0001|Rm" , "io": "GE=W"},
+ {"inst": "sadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|1001|Rm" , "io": "GE=W"},
+ {"inst": "sasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0011|Rm" , "io": "GE=W"},
+ {"inst": "sbc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0110|0|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "C=R"},
+ {"inst": "sbc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0110|0|Rn|Rd|n:5|sop:2|0|Rm" , "io": "C=R"},
+ {"inst": "sbc Rd, Rn, #immA" , "a32": "cond|001|0110|0|Rn|Rd|imm:12" , "io": "C=R"},
+ {"inst": "sbcS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0110|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "sbcS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0110|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "sbcS Rd!=PC, Rn, #immA" , "a32": "cond|001|0110|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "sbfx Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1101|widthM1:5|Rd|lsb:5|101|Rn" , "imm": "SbfxUbfxImm(lsb, width)"},
+ {"inst": "sel Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0100|0|Rn|Rd|1111|1011|Rm" , "io": "GE=R"},
+ {"inst": "setend #immZ" , "a32": "1111|000|1000|0|0001|0000|00|immZ:1|0|0000|0000" , "ext": "ARMv8-"},
+ {"inst": "shadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0001|Rm"},
+ {"inst": "shadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|1001|Rm"},
+ {"inst": "shasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0011|Rm"},
+ {"inst": "shsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0101|Rm"},
+ {"inst": "shsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0111|Rm"},
+ {"inst": "shsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|1111|Rm"},
+ {"inst": "smlabb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1000|Rn" , "io": "Q=X"},
+ {"inst": "smlabt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1100|Rn" , "io": "Q=X"},
+ {"inst": "smlatb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1010|Rn" , "io": "Q=X"},
+ {"inst": "smlatt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1110|Rn" , "io": "Q=X"},
+ {"inst": "smlad Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0001|Rn" , "io": "Q=X"},
+ {"inst": "smladx Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0011|Rn" , "io": "Q=X"},
+ {"inst": "smlal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0111|0|RxHi|RxLo|Rm|1001|Rn"},
+ {"inst": "smlalS RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0111|1|RxHi|RxLo|Rm|1001|Rn" , "io": "N=W Z=W"},
+ {"inst": "smlalbb RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1000|Rn"},
+ {"inst": "smlalbt RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1100|Rn"},
+ {"inst": "smlaltb RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1010|Rn"},
+ {"inst": "smlaltt RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1110|Rn"},
+ {"inst": "smlald RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0001|Rn"},
+ {"inst": "smlaldx RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0011|Rn"},
+ {"inst": "smlawb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1001|0|Rd|Ra|Rm|1000|Rn" , "io": "Q=X"},
+ {"inst": "smlawt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1001|0|Rd|Ra|Rm|1100|Rn" , "io": "Q=X"},
+ {"inst": "smlsd Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0101|Rn" , "io": "Q=X"},
+ {"inst": "smlsdx Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0111|Rn" , "io": "Q=X"},
+ {"inst": "smlsld RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0101|Rn"},
+ {"inst": "smlsldx RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0111|Rn"},
+ {"inst": "smmla Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|0001|Rn"},
+ {"inst": "smmlar Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|0011|Rn"},
+ {"inst": "smmls Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|1101|Rn"},
+ {"inst": "smmlsr Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|1111|Rn"},
+ {"inst": "smmul Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|1|Rd|1111|Rm|0001|Rn"},
+ {"inst": "smmulr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|1|Rd|1111|Rm|0011|Rn"},
+ {"inst": "smuad Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0001|Rn" , "io": "Q=X"},
+ {"inst": "smuadx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0011|Rn" , "io": "Q=X"},
+ {"inst": "smulbb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1000|Rn"},
+ {"inst": "smulbt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1100|Rn"},
+ {"inst": "smultb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1010|Rn"},
+ {"inst": "smultt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1110|Rn"},
+ {"inst": "smull RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0110|0|RdHi|RdLo|Rm|1001|Rn"},
+ {"inst": "smullS RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0110|1|RdHi|RdLo|Rm|1001|Rn" , "io": "N=W Z=W"},
+ {"inst": "smulwb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rd|0000|Rm|1010|Rn"},
+ {"inst": "smulwt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rd|0000|Rm|1110|Rn"},
+ {"inst": "smusd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0101|Rn"},
+ {"inst": "smusdx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0111|Rn"},
+ {"inst": "srsda [Rn==SP]{!}, #mode" , "a32": "1111|100|001|W|0|1101|0000|0101|000|mode:5"},
+ {"inst": "srsdb [Rn==SP]{!}, #mode" , "a32": "1111|100|101|W|0|1101|0000|0101|000|mode:5"},
+ {"inst": "srsia [Rn==SP]{!}, #mode" , "a32": "1111|100|011|W|0|1101|0000|0101|000|mode:5"},
+ {"inst": "srsib [Rn==SP]{!}, #mode" , "a32": "1111|100|111|W|0|1101|0000|0101|000|mode:5"},
+ {"inst": "ssat Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0101|imm:5|Rd|00000|00|1|Rn" , "imm": "SsatImm(sat)", "io": "Q=X"},
+ {"inst": "ssat Rd!=PC, #sat, Rn!=PC, lsl_or_asr #n" , "a32": "cond|011|0101|imm:5|Rd|n:5|sop:2|1|Rn" , "imm": "SsatImm(sat, n)", "io": "Q=X"},
+ {"inst": "ssat16 Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0101|0|imm:4|Rd|1111|0011|Rn" , "imm": "Ssat16Imm(sat)", "io": "Q=X"},
+ {"inst": "ssax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0101|Rm" , "io": "GE=W"},
+ {"inst": "ssub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0111|Rm" , "io": "GE=W"},
+ {"inst": "ssub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|1111|Rm" , "io": "GE=W"},
+ {"inst": "stmda [Rn!=PC]{!}, RsList" , "a32": "cond|100|000W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmdb [Rn!=PC]{!}, RsList" , "a32": "cond|100|100W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmia [Rn!=PC]{!}, RsList" , "a32": "cond|100|010W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmib [Rn!=PC]{!}, RsList" , "a32": "cond|100|110W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmda [Rn!=PC], RsList^" , "a32": "cond|100|0010|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmdb [Rn!=PC], RsList^" , "a32": "cond|100|1010|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmia [Rn!=PC], RsList^" , "a32": "cond|100|0110|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "stmib [Rn!=PC], RsList^" , "a32": "cond|100|1110|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"},
+ {"inst": "str Rs, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU0W|0|Rn|Rs|n:5|sop:2|0|Rm"},
+ {"inst": "str Rs, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU0W|0|Rn|Rs|off:12"},
+ {"inst": "str Rs, [Rn==PC, #+/-off]" , "a32": "cond|010|1U00|0|Rn|Rs|off:12"},
+ {"inst": "strb Rs!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU1W|0|Rn|Rs|n:5|sop:2|0|Rm"},
+ {"inst": "strb Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU1W|0|Rn|Rs|off:12"},
+ {"inst": "strb Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|1U10|0|Rn|Rs|off:12"},
+ {"inst": "strbt Rs!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U11|0|Rn|Rs|n:5|sop:2|0|Rm"},
+ {"inst": "strbt Rs!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U11|0|Rn|Rs|off:12"},
+ {"inst": "strbt Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|0U11|0|Rn|Rs|off:12"},
+ {"inst": "strd Rs<=13, Rs2+, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rs|0000|1111|Rm"},
+ {"inst": "strd Rs<=13, Rs2+, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|0|Rn|Rs|off:4|1111|off:4"},
+ {"inst": "strd Rs<=13, Rs2+, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rs|off:4|1111|off:4"},
+ {"inst": "strex Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|Rd|1111|1001|Rs"},
+ {"inst": "strexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|Rd|1111|1001|Rs"},
+ {"inst": "strexd Rd!=PC, Rs!=PC, Rs2+, [Rn!=PC]" , "a32": "cond|000|1101|0|Rn|Rd|1111|1001|Rs"},
+ {"inst": "strexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|Rd|1111|1001|Rs"},
+ {"inst": "strh Rs!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rs|0000|1011|Rm"},
+ {"inst": "strh Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|0|Rn|Rs|off:4|1011|off:4"},
+ {"inst": "strh Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rs|off:4|1011|off:4"},
+ {"inst": "strht Rs!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|0|Rn|Rs|0000|1011|Rm"},
+ {"inst": "strht Rs!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|0|Rn|Rs|off:4|1011|off:4"},
+ {"inst": "strt Rs, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U01|0|Rn|Rs|n:5|sop:2|0|Rm"},
+ {"inst": "strt Rs, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U01|0|Rn|Rs|off:12"},
+ {"inst": "sub Rd, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0010|0|Rn|Rd|Rs|0|sop:2|1|Rm"},
+ {"inst": "sub Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0010|0|Rn|Rd|n:5|sop:2|0|Rm"},
+ {"inst": "sub Rd, Rn, #immA" , "a32": "cond|001|0010|0|Rn|Rd|imm:12"},
+ {"inst": "subS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0010|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0010|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=PC, Rn, #immA" , "a32": "cond|001|0010|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "svc #immZ" , "a32": "cond|1111|immZ:24"},
+ {"inst": "sxtab Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0101|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
+ {"inst": "sxtab16 Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0100|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
+ {"inst": "sxtah Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0101|1|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
+ {"inst": "sxtb Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0101|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
+ {"inst": "sxtb16 Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0100|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
+ {"inst": "sxth Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0101|1|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
+ {"inst": "teq Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1001|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "teq Rn, Rm, {sop #n}" , "a32": "cond|000|1001|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "teq Rn, #immA" , "a32": "cond|001|1001|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "tst Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1000|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "tst Rn, Rm, {sop #n}" , "a32": "cond|000|1000|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"},
+ {"inst": "tst Rn, #immA" , "a32": "cond|001|1000|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W"},
+ {"inst": "uadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0001|Rm" , "io": "GE=W"},
+ {"inst": "uadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|1001|Rm" , "io": "GE=W"},
+ {"inst": "uasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0011|Rm" , "io": "GE=W"},
+ {"inst": "ubfx Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1111|widthM1:5|Rd|lsb:5|101|Rn" , "imm": "SbfxUbfxImm(lsb, width)"},
+ {"inst": "udf #immZ" , "a32": "1110|011|1111|1|immZ:12|1111|immZ:4"},
+ {"inst": "uhadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|1001|Rm"},
+ {"inst": "uhadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0001|Rm"},
+ {"inst": "uhasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0011|Rm"},
+ {"inst": "uhsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0101|Rm"},
+ {"inst": "uhsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0111|Rm"},
+ {"inst": "uhsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|1111|Rm"},
+ {"inst": "umaal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0010|0|RxHi|RxLo|Rm|1001|Rn"},
+ {"inst": "umlal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0101|0|RxHi|RxLo|Rm|1001|Rn"},
+ {"inst": "umlalS RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0101|1|RxHi|RxLo|Rm|1001|Rn" , "io": "N=W Z=W"},
+ {"inst": "umull RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0100|0|RdHi|RdLo|Rm|1001|Rn"},
+ {"inst": "umullS RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0100|1|RdHi|RdLo|Rm|1001|Rn" , "io": "N=W Z=W"},
+ {"inst": "uqadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0001|Rm"},
+ {"inst": "uqadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|1001|Rm"},
+ {"inst": "uqasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0011|Rm"},
+ {"inst": "uqsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0101|Rm"},
+ {"inst": "uqsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0111|Rm"},
+ {"inst": "uqsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|1111|Rm"},
+ {"inst": "usad8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1100|0|Rd|1111|Rm|0001|Rn"},
+ {"inst": "usada8 Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1100|0|Rd|Ra|Rm|0001|Rn"},
+ {"inst": "usat Rd!=PC, #sat, Rn!=PC, {lsl_or_asr #n}" , "a32": "cond|011|0111|sat:5|Rd|n:5|sop:2|1|Rn"},
+ {"inst": "usat16 Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0111|0|sat:4|Rd|1111|0011|Rn"},
+ {"inst": "usax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0101|Rm" , "io": "GE=W"},
+ {"inst": "usub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0111|Rm" , "io": "GE=W"},
+ {"inst": "usub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|1111|Rm" , "io": "GE=W"},
+ {"inst": "uxtab Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0111|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
+ {"inst": "uxtab16 Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0110|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
+ {"inst": "uxtah Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0111|1|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"},
+ {"inst": "uxtb Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0111|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
+ {"inst": "uxtb16 Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0110|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
+ {"inst": "uxth Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0111|1|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"},
+ {"inst": "wfe" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0010"},
+ {"inst": "wfi" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0011"},
+ {"inst": "yield" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0001"}
+ ]},
+
+ {"category": "GP", "data": [
+ {"inst": "adc Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|101|Rm:3|Rx:3" , "it": "in" , "io": "C=R"},
+ {"inst": "adc Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1010|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "C=R"},
+ {"inst": "adc Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "C=R"},
+ {"inst": "adcS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|101|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"},
+ {"inst": "adcS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1010|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"},
+ {"inst": "adcS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"},
+ {"inst": "add Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|100|Rm:3|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "add Rx!=XX, Rx!=XX, Rm!=XX" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "in"},
+ {"inst": "add Rx, Rx, Rm==SP" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "any"},
+ {"inst": "add Rx==SP, Rx==SP, Rm" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "any"},
+ {"inst": "add Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|0|Rx:3|immZ:8" , "it": "in"},
+ {"inst": "add Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|110|immZ:3|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "add Rx==SP, Rx==SP, #immZ*4" , "t16": "1011|00000|immZ:7" , "it": "any"},
+ {"inst": "add Rd!=SP, Rn==SP, #immZ*4" , "t16": "1010|1|Rd:3|immZ:8" , "it": "any"},
+ {"inst": "add Rd!=XX, Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "add Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "mod": "LSL_3_IF_SP"},
+ {"inst": "add Rd!=XX, Rn!=PC, #immZ" , "t32": "1111|0|immZ:1|1|0000|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"},
+ {"inst": "add Rd!=XX, Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "add Rd!=PC, Rn==SP, #immZ" , "t32": "1111|0|immZ:1|1|0000|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"},
+ {"inst": "add Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1000|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "addS Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|0|Rx:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|110|immZ:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|100|Rm:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=XX, Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W", "mod": "LSL_3_IF_SP"},
+ {"inst": "addS Rd!=XX, Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "addS Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "adr Rd!=HI, #relZ*4" , "t16": "1010|0|Rd:3|relZ:8" , "it": "any"},
+ {"inst": "adr Rd!=XX, #relZ" , "t32": "1111|0|relZ:1|10N0N|0|1111|0|relZ:3|Rd|relZ:8" , "it": "any"},
+ {"inst": "and Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|000|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "and Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "and Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "andS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|000|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "andS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "andS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W", "mod": "APSR_IF_NOT_PC"},
+ {"inst": "asr Rd!=HI, Rn!=HI, #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "asr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "asr Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|10|Rn" , "it": "any"},
+ {"inst": "asr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0010|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "asrS Rd!=HI, Rn!=HI, #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "asrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "asrS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|10|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "asrS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0010|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "b #relS*2" , "t16": "1110|0|relS:11" , "it": "out last"},
+ {"inst": "b #relS*2" , "t32": "1111|0|relS[23]|relS[20:11]|10|ja|1|jb|relS[10:0]" , "it": "out last", "calc": {"ja": "relS[23] ^ relS[22] ^ 1", "jb": "relS[23] ^ relS[21] ^ 1"}},
+ {"inst": "b #relS*2" , "t16": "1101|cond|relS:8" , "it": "out"},
+ {"inst": "b #relS*2" , "t32": "1111|0|relS[19]|cond|relS[16:11]|10|ja|0|jb|relS[10:0]" , "it": "out" , "calc": {"ja": "relS[19] ^ relS[18] ^ 1", "jb": "relS[19] ^ relS[17] ^ 1"}},
+ {"inst": "bfc Rd!=XX, #lsb, #width" , "t32": "1111|001|1011|0|1111|0|lsb:3|Rd|lsb:2|0|msb:5" , "it": "any", "imm": "BfcBfiImm(lsb, width)"},
+ {"inst": "bfi Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1011|0|Rn|0|lsb:3|Rd|lsb:2|0|msb:5" , "it": "any", "imm": "BfcBfiImm(lsb, width)"},
+ {"inst": "bic Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|110|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "bic Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0001|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "bic Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0001|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "bicS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|110|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "bicS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0001|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "bicS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0001|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "bkpt #immZ" , "t16": "1011|111|0|immZ:8" , "it": "uncond"},
+ {"inst": "bl #relS*2" , "t32": "1111|0|relS[23]|relS[20:11]|11|ja|1|jb|relS[10:0]" , "it": "out last", "calc": {"ja": "relS[23] ^ relS[22] ^ 1", "jb": "relS[23] ^ relS[21] ^ 1"}},
+ {"inst": "blx Rm!=PC" , "t16": "0100|011|11|Rm:4|000" , "it": "out last"},
+ {"inst": "blx #relS*4" , "t32": "1111|0|relS[22]|relS[19:10]|11|ja|0|jb|relS[9:0]|0" , "it": "out last", "calc": {"ja": "relS[22] ^ relS[21] ^ 1", "jb": "relS[22] ^ relS[20] ^ 1"}},
+ {"inst": "bx Rm" , "t16": "0100|011|10|Rm:4|000" , "it": "out last"},
+ {"inst": "bxj Rm!=XX" , "t32": "1111|001|1110|0|Rm|1000|1111|00000000" , "it": "out last"},
+ {"inst": "cbz Rn!=HI, #relZ*2" , "t16": "1011|00|relZ:1|1|relZ:5|Rn:3" , "it": "out"},
+ {"inst": "cbnz Rn!=HI, #relZ*2" , "t16": "1011|10|relZ:1|1|relZ:5|Rn:3" , "it": "out"},
+ {"inst": "clz Rd!=XX, Rn!=XX" , "t32": "1111|101|0101|1|Rm|1111|Rd|1000|Rn" , "it": "any"},
+ {"inst": "cmn Rn!=HI, Rm!=HI" , "t16": "0100|001|011|Rm:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|1111|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn!=HI, #immZ" , "t16": "0010|1|Rn:3|immZ:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn!=HI, Rm!=HI" , "t16": "0100|001|010|Rm:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn!=PC, Rm!=PC" , "t16": "0100|010|1|Rn:1|Rm:4|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W", "mod": "UNPRED_IF_ALL_LOW"},
+ {"inst": "cmp Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|1111|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "dbg #immZ" , "t32": "1111|001|1101|0|1111|1000|0000|1111|immZ:4" , "it": "any"},
+ {"inst": "eor Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|001|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "eor Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0100|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "eor Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "eorS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|001|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "eorS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0100|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "eorS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "hlt #immZ" , "t16": "1011|1010|10|immZ:6" , "it": "out", "ext": "ARMv8+"},
+ {"inst": "it #cond!=15" , "t16": "1011|111|1|cond[3:0]|1000" , "it": "out def"},
+ {"inst": "ite #cond!=15" , "t16": "1011|111|1|cond[3:0]|X100" , "it": "out def"},
+ {"inst": "itee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
+ {"inst": "iteee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "iteet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "itet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
+ {"inst": "itete #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "itett #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "itt #cond!=15" , "t16": "1011|111|1|cond[3:0]|X100" , "it": "out def"},
+ {"inst": "itte #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
+ {"inst": "ittee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "ittet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "ittt #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"},
+ {"inst": "ittte #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "itttt #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"},
+ {"inst": "ldmia [Rn!=HI]{!}, RdList" , "t16": "1100|1|Rn:3|imm:8" , "it": "any", "imm": "GpListImm(RdList, 0xFF)"},
+ {"inst": "ldmia [Rn!=PC]{!}, RdList" , "t32": "1110|100|010W|1|Rn|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RdList, 0xDFFF)"},
+ {"inst": "ldmdb [Rn!=PC]{!}, RdList" , "t32": "1110|100|100W|1|Rn|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RdList, 0xDFFF)"},
+ {"inst": "ldr Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|100|Rm:3|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldr Rd, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0010|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "ldr Rd!=HI, [Rn!=HI, #off*4]" , "t16": "0110|1|off:5|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldr Rd!=HI, [Rn==SP, #off*4]" , "t16": "1001|1|Rd:3|off:8" , "it": "any"},
+ {"inst": "ldr Rd!=HI, [Rn==PC, #off*4]" , "t16": "0100|1|Rd:3|off:8" , "it": "any"},
+ {"inst": "ldr Rd, [Rn!=PC, #off]" , "t32": "1111|100|0110|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldr Rd, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0010|1|Rn|Rd|1PUW|off:8" , "it": "any"},
+ {"inst": "ldr Rd, [Rn==PC, #+/-off]" , "t32": "1111|100|0U10|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrb Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|110|Rm:3|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldrb Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "ldrb Rd!=HI, [Rn!=HI, #off*4]" , "t16": "0111|1|off:5|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldrb Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0100|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrb Rd!=XX, [Rn!=PC, #+/-off]{!}" , "t32": "1111|100|0000|1|Rn|Rd|1PUW|off:8" , "it": "any"},
+ {"inst": "ldrb Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|0U00|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrbt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0000|1|Rn|Rd|1110|off:8" , "it": "any"},
+ {"inst": "ldrd Rd!=XX, Rd2!=XX, [Rn==PC, #+/-off*4]" , "t32": "1110|100|1U10|1|Rn|Rd|Rd2|off:8" , "it": "any"},
+ {"inst": "ldrd Rd!=XX, Rd2!=XX, [Rn!=PC, #+/-off*4]{@}{!}" , "t32": "1110|100|PU1W|1|Rn|Rd|Rd2|off:8" , "it": "any"},
+ {"inst": "ldrex Rd!=XX, [Rn!=PC, #off*4]" , "t32": "1110|100|0010|1|Rn|Rd|1111|off:8" , "it": "any"},
+ {"inst": "ldrh Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|101|Rm:3|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldrh Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "ldrh Rd!=HI, [Rn!=HI, #off*4]" , "t16": "1000|1|off:5|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldrh Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0101|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrh Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0001|1|Rn|Rd|1PUW|off:8" , "it": "any"},
+ {"inst": "ldrh Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|0U01|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrht Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0001|1|Rn|Rd|1110|off:8" , "it": "any"},
+ {"inst": "ldrsb Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|011|Rm:3|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldrsb Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1000|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "ldrsb Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1100|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrsb Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|1000|1|Rn|Rd|1PUW|off:8" , "it": "any"},
+ {"inst": "ldrsb Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|1U00|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrsbt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1000|1|Rn|Rd|1110|off:8" , "it": "any"},
+ {"inst": "ldrsh Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|111|Rm:3|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "ldrsh Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1001|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "ldrsh Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1101|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrsh Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|1001|1|Rn|Rd|1PUW|off:8" , "it": "any"},
+ {"inst": "ldrsh Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|1U01|1|Rn|Rd|off:12" , "it": "any"},
+ {"inst": "ldrsht Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1001|1|Rn|Rd|1110|off:8" , "it": "any"},
+ {"inst": "ldrt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0010|1|Rn|Rd|1110|off:8" , "it": "any"},
+ {"inst": "lsl Rd!=HI, Rn!=HI, #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "lsl Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|00|Rn" , "it": "any"},
+ {"inst": "lsl Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "lsl Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0000|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "lslS Rd!=HI, Rn!=HI, #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "lslS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|00|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "lslS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "lslS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1110|101|0000|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "lsr Rd!=HI, Rn!=HI, #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "lsr Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|01|Rn" , "it": "any"},
+ {"inst": "lsr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "lsr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0001|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "lsrS Rd!=HI, Rn!=HI, #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "lsrS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|01|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "lsrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "lsrS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1110|101|0001|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "mcr #CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "t32": "1110|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ext": "ARMv6T2+"},
+ {"inst": "mcr2 #CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "t32": "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ext": "ARMv6T2+"},
+ {"inst": "mcrr #CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "t32": "1110|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ext": "ARMv6T2+"},
+ {"inst": "mcrr2 #CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "t32": "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ext": "ARMv6T2+"},
+ {"inst": "mla Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1000|0|Rn|Ra|Rd|0000|Rm" , "it": "any"},
+ {"inst": "mls Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1000|0|Rn|Ra|Rd|0001|Rm" , "it": "any"},
+ {"inst": "mov Rd, Rn" , "t16": "0100|0110|Rd:1|Rn:4|Rd:3" , "it": "in", "mod": "ARMv6T2_IF_LOW"},
+ {"inst": "mov Rx!=HI, Rx!=HI, lsl Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "mov Rx!=HI, Rx!=HI, lsr Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "mov Rx!=HI, Rx!=HI, asr Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "mov Rx!=HI, Rx!=HI, ror Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "mov Rd!=HI, Rn!=HI, lsl #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "mov Rd!=HI, Rn!=HI, lsr #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "mov Rd!=HI, Rn!=HI, asr #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "mov Rd!=HI, #immZ" , "t16": "0010|0|Rd:3|immZ:8" , "it": "in"},
+ {"inst": "mov Rd!=PC, Rn" , "t32": "1110|101|0010|0|1111|0000|Rd|0000|Rn" , "it": "any", "mod": "UNPRED_COMPLEX"},
+ {"inst": "mov Rd!=XX, Rn!=XX, sop #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any"},
+ {"inst": "mov Rd!=XX, Rn!=XX, sop Rm!=XX" , "t32": "1111|101|00|sop:2|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "mov Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|0|1111|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "movS Rd!=HI, Rn!=HI" , "t16": "0000|0000|00|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rx!=HI, Rx!=HI, lsl Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rx!=HI, Rx!=HI, lsr Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rx!=HI, Rx!=HI, asr Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rx!=HI, Rx!=HI, ror Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=HI, Rn!=HI, lsl #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=HI, Rn!=HI, lsr #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=HI, Rn!=HI, asr #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=HI, #immZ" , "t16": "0010|0|Rd:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=XX, Rn" , "t32": "1110|101|0010|1|1111|0000|Rd|0000|Rn" , "it": "any", "io": "N=W Z=W C=W", "mod": "UNPRED_COMPLEX"},
+ {"inst": "movS Rd!=XX, Rn!=XX, sop Rm!=XX" , "t32": "1110|101|00|sop:2|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=XX, Rn!=XX, sop #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "movS Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|1|1111|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "movt Rx!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0110|0|immZ:4|0|immZ:3|Rx|immZ:8" , "it": "any"},
+ {"inst": "movw Rd!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0010|0|immZ:4|0|immZ:3|Rd|immZ:8" , "it": "any"},
+ {"inst": "mrc #CP, #op1, Rd!=XX, Cn, Cm, {#op2}" , "t32": "1110|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4" , "it": "any"},
+ {"inst": "mrc2 #CP, #op1, Rd!=XX, Cn, Cm, {#op2}" , "t32": "1111|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4" , "it": "any"},
+ {"inst": "mrrc #CP, #op1, Rd!=XX, Rd2!=Rd, Cm" , "t32": "1110|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4" , "it": "any"},
+ {"inst": "mrrc2 #CP, #op1, Rd!=XX, Rd2!=Rd, Cm" , "t32": "1111|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4" , "it": "any"},
+ {"inst": "mrs Rd!=XX, #APSR" , "t32": "11110011111|APSR:1|1111|1000|Rd|0000|0000" , "it": "any"},
+ {"inst": "msr #APSR, Rn!=PC" , "t32": "1111|001|1100|0|Rn|1100|APSR:2|00|0000|0000" , "it": "any"},
+ {"inst": "mul Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|101|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "mulS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|101|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W"},
+ {"inst": "mul Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "mvn Rd!=HI, Rn!=HI" , "t16": "0100|001|111|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "mvn Rd!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0011|0|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any"},
+ {"inst": "mvn Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|0|1111|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "mvnS Rd!=HI, Rn!=HI" , "t16": "0100|001|111|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "mvnS Rd!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0011|1|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "mvnS Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|1|1111|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "nop" , "t16": "1011|111|1000|0|0000" , "it": "any"},
+ {"inst": "nop" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0000" , "it": "any"},
+ {"inst": "orn Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0011|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "orn Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "ornS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0011|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "ornS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "orr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|100|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "orr Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0010|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "orr Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "orrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "orrS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0010|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "orrS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "pkhbt Rd!=XX, Rn!=XX, Rm!=XX, {lsl #n}" , "t32": "1110|101|0110|0|Rn|0|n:3|Rd|n:2|00|Rm" , "it": "any"},
+ {"inst": "pkhtb Rd!=XX, Rn!=XX, Rm!=XX, {asr #n}" , "t32": "1110|101|0110|0|Rn|0|n:3|Rd|n:2|10|Rm" , "it": "any"},
+ {"inst": "pld [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"},
+ {"inst": "pld [Rn!=PC, #off]" , "t32": "1111|100|0100|1|Rn|1111|off:12" , "it": "any"},
+ {"inst": "pld [Rn!=PC, #-off]" , "t32": "1111|100|0000|1|Rn|1111|1100|off:8" , "it": "any"},
+ {"inst": "pld [Rn==PC, #+/-off]" , "t32": "1111|100|0U00|1|Rn|1111|off:12" , "it": "any"},
+ {"inst": "pldw [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"},
+ {"inst": "pldw [Rn!=PC, #off]" , "t32": "1111|100|0101|1|Rn|1111|off:12" , "it": "any"},
+ {"inst": "pldw [Rn!=PC, #-off]" , "t32": "1111|100|0001|1|Rn|1111|1100|off:8" , "it": "any"},
+ {"inst": "pop Rd!=SP" , "t32": "1111|100|0010|1|1101|Rd|1011|00000100" , "it": "any"},
+ {"inst": "pop RdList" , "t16": "1011|110|immMask[15]|immMask[7:0]" , "it": "any", "imm": "GpListImm(RsList, 0x80FF)"},
+ {"inst": "pop RdList" , "t32": "1110|100|0101|1|1101|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0xDFFF)"},
+ {"inst": "push Rs!=XX" , "t32": "1111|100|0010|0|1101|Rs|1101|0000|0100" , "it": "any"},
+ {"inst": "push RsList" , "t16": "1011|010|immMask[14]|immMask[7:0]" , "it": "any", "imm": "GpListImm(RsList, 0x40FF)"},
+ {"inst": "push RsList" , "t32": "1110|100|0101|0|1101|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"},
+ {"inst": "qadd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1000|Rn" , "it": "any", "io": "Q=X"},
+ {"inst": "qadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|0001|Rn" , "it": "any"},
+ {"inst": "qadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
+ {"inst": "qasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
+ {"inst": "qdadd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1001|Rn" , "it": "any", "io": "Q=X"},
+ {"inst": "qdsub Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1011|Rn" , "it": "any", "io": "Q=X"},
+ {"inst": "qsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
+ {"inst": "qsub Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1010|Rn" , "it": "any", "io": "Q=X"},
+ {"inst": "qsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rm|1111|Rd|0001|Rn" , "it": "any"},
+ {"inst": "qsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rm|1111|Rd|0001|Rn" , "it": "any"},
+ {"inst": "rbit Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1010|Rn" , "it": "any"},
+ {"inst": "rev Rd!=HI, Rn!=HI" , "t16": "1011|101|000|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "rev Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1000|Rn" , "it": "any"},
+ {"inst": "rev16 Rd!=HI, Rn!=HI" , "t16": "1011|101|001|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "rev16 Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1001|Rn" , "it": "any"},
+ {"inst": "revsh Rd!=HI, Rn!=HI" , "t16": "1011|101|011|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "revsh Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1011|Rn" , "it": "any"},
+ {"inst": "ror Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|11|Rn" , "it": "any"},
+ {"inst": "ror Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "ror Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0011|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "rorS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|11|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "rorS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"},
+ {"inst": "rorS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0011|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "rsb Rd!=HI, Rn!=HI, #zero" , "t16": "0100|001001|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "rsb Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1110|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "rsb Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1110|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "rsbS Rd!=HI, Rn!=HI, #zero" , "t16": "0100|001001|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "rsbS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1110|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "rsbS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1110|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "rrx Rd!=XX, Rn!=XX" , "t32": "1110|101|0010|0|1111|0000|Rd|0011|Rn" , "it": "any", "io": "C=R"},
+ {"inst": "rrxS Rd!=XX, Rn!=XX" , "t32": "1110|101|0010|1|1111|0000|Rd|0011|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "sadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "sadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "sasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "sbc Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|110|Rm:3|Rx:3" , "it": "in"},
+ {"inst": "sbc Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1011|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "sbc Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1011|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "sbcS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|110|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "sbcS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1011|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "sbcS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1011|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "sbfx Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1010|0|Rn|0|lsb:3|Rd|lsb:2|0|widthM1:5" , "it": "any", "imm": "SbfxUbfxImm(lsb, width)"},
+ {"inst": "sel Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|1000|Rm" , "it": "any"},
+ {"inst": "setend #immZ" , "t16": "1011|0110|010|1|immZ:1|000" , "it": "out"},
+ {"inst": "shadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "shadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "shasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "shsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "shsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "shsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "smlabb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlabt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlatb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0010|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlatt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0011|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlad Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|0|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smladx Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|0|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|0000|Rm" , "it": "any"},
+ {"inst": "smlalbb RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1000|Rm" , "it": "any"},
+ {"inst": "smlalbt RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1001|Rm" , "it": "any"},
+ {"inst": "smlaltb RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1010|Rm" , "it": "any"},
+ {"inst": "smlaltt RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1011|Rm" , "it": "any"},
+ {"inst": "smlald RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1100|Rm" , "it": "any"},
+ {"inst": "smlaldx RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1101|Rm" , "it": "any"},
+ {"inst": "smlawb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlawt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlsd Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlsdx Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlsld RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|1|Rn|RxLo|RxHi|1100|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smlsldx RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|1|Rn|RxLo|RxHi|1101|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smmla Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "it": "any"},
+ {"inst": "smmlar Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "it": "any"},
+ {"inst": "smmls Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|0|Rn|Ra|Rd|0000|Rm" , "it": "any"},
+ {"inst": "smmlsr Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|0|Rn|Ra|Rd|0001|Rm" , "it": "any"},
+ {"inst": "smmul Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "smmulr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|1|Rn|1111|Rd|0001|Rm" , "it": "any"},
+ {"inst": "smuad Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smuadx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|0|Rn|1111|Rd|0001|Rm" , "it": "any", "io": "Q=X"},
+ {"inst": "smulbb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "smulbt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0001|Rm" , "it": "any"},
+ {"inst": "smultb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0010|Rm" , "it": "any"},
+ {"inst": "smultt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0011|Rm" , "it": "any"},
+ {"inst": "smull RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1100|0|Rn|RdLo|RdHi|0000|Rm" , "it": "any"},
+ {"inst": "smulwb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "smulwt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|1|Rn|1111|Rd|0001|Rm" , "it": "any"},
+ {"inst": "smusd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|0|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "smusdx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|0|Rn|1111|Rd|0001|Rm" , "it": "any"},
+ {"inst": "ssat Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|100|00|Rn|0|000|Rd|00|0|imm:5" , "it": "any", "imm": "SsatImm(sat)", "io": "Q=X"},
+ {"inst": "ssat Rd!=XX, #sat, Rn!=XX, lsl_or_asr #n" , "t32": "1111|001|100|sop:2|Rn|0|n:3|Rd|n:2|0|imm:5" , "it": "any", "imm": "SsatImm(sat, n)", "io": "Q=X"},
+ {"inst": "ssat16 Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|1001|0|Rn|0000|Rd|0000|imm:4" , "it": "any", "imm": "Ssat16Imm(sat)", "io": "Q=X"},
+ {"inst": "ssax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "ssub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "ssub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "stmia [Rn!=HI]!, RsList" , "t16": "1100|0|Rn:3|immMask:8" , "it": "any", "imm": "GpListImm(RsList, 0xFF)"},
+ {"inst": "stmia [Rn!=PC]{!}, RsList" , "t32": "1110|100|010W|0|Rn|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"},
+ {"inst": "stmdb [Rn!=PC]{!}, RsList" , "t32": "1110|100|100W|0|Rn|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"},
+ {"inst": "str Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|000|Rm:3|Rn:3|Rs:3" , "it": "any"},
+ {"inst": "str Rs!=PC, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0010|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "str Rs!=HI, [Rn==SP, #off*4]" , "t16": "1001|0|Rs:3|off:8" , "it": "any"},
+ {"inst": "str Rs!=HI, [Rn!=HI, #off*4]" , "t16": "0110|0|off:5|Rn:3|Rs:3" , "it": "any"},
+ {"inst": "str Rs!=PC, [Rn!=PC, #off]" , "t32": "1111|100|0110|0|Rn|Rs|off:12" , "it": "any"},
+ {"inst": "str Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0010|0|Rn|Rs|1PUW|off:8" , "it": "any"},
+ {"inst": "strb Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|010|Rm:3|Rn:3|Rs:3" , "it": "any"},
+ {"inst": "strb Rs!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "strb Rs!=HI, [Rn!=HI, #off*4]" , "t16": "0111|0|off:5|Rn:3|Rs:3" , "it": "any"},
+ {"inst": "strb Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0100|0|Rn|Rs|off:12" , "it": "any"},
+ {"inst": "strb Rs!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0000|0|Rn|Rs|1PUW|off:8" , "it": "any"},
+ {"inst": "strbt Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0000|0|Rn|Rs|1110|off:8" , "it": "any"},
+ {"inst": "strd Rs!=XX, Rs2!=XX, [Rn!=PC, #off]{@}{!}" , "t32": "1110|100|PU1W|0|Rn|Rs|Rs2|off:8" , "it": "any"},
+ {"inst": "strex Rd!=XX, Rs!=XX, [Rn!=PC, #off]" , "t32": "1110|100|0010|0|Rn|Rs|Rd|off:8" , "it": "any", "mod": "UNPRED_COMPLEX"},
+ {"inst": "strexb Rd!=XX, Rs!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|0100|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"},
+ {"inst": "strexd Rd!=XX, Rs!=XX, Rs2!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|Rs2|0111|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"},
+ {"inst": "strexh Rd!=XX, Rs!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|0101|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"},
+ {"inst": "strh Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|001|Rm:3|Rn:3|Rs:3" , "it": "any"},
+ {"inst": "strh Rs!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"},
+ {"inst": "strh Rs!=HI, [Rn!=HI, #off*4]" , "t16": "1000|0|off:5|Rn:3|Rs:3" , "it": "any"},
+ {"inst": "strh Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0101|0|Rn|Rs|off:12" , "it": "any"},
+ {"inst": "strh Rs!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0001|0|Rn|Rs|1PUW|off:8" , "it": "any"},
+ {"inst": "strht Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0001|0|Rn|Rs|1110|off:8" , "it": "any"},
+ {"inst": "strt Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0010|0|Rn|Rs|1110|off:8" , "it": "any"},
+ {"inst": "sub Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|101|Rm:3|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "sub Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|111|immZ:3|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "sub Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|1|Rx:3|immZ:8" , "it": "in"},
+ {"inst": "sub Rx==SP, Rx==SP, #immZ*4" , "t16": "1011|00001|immZ:7" , "it": "any"},
+ {"inst": "sub Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "sub Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"},
+ {"inst": "sub Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1101|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "sub Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1101|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"},
+ {"inst": "sub Rd!=XX, Rn!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0101|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"},
+ {"inst": "sub Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|101|Rm:3|Rn:3|Rd:3" , "it": "in"},
+ {"inst": "subS Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|111|immZ:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rx!=HI, Rx!=HI, #immZ" , "t16": "0001|1|Rx:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "subS Rd!=XX, Rn!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0101|1|Rn|0|immZ:3|Rd|immZ:8" , "it": "any", "io": "N=W Z=W C=W V=W"},
+ {"inst": "svc #immZ" , "t16": "1101|1111|immZ:8" , "it": "any"},
+ {"inst": "sxtab Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0010|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "sxtab16 Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0001|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "sxtah Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0000|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "sxtb Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|001|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "sxtb Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0010|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "sxtb16 Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0001|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "sxth Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|000|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "sxth Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0000|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "tbb Rn!=SP, Rn!=XX" , "t32": "1110|100|0110|1|Rn|1111|0000|0000|Rn" , "it": "out last"},
+ {"inst": "tbh Rn!=SP, Rn!=XX" , "t32": "1110|100|0110|1|Rn|1111|0000|0001|Rn" , "it": "out last"},
+ {"inst": "teq Rn!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0100|1|Rn|0|n:3|1111|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "teq Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "tst Rn!=HI, Rn!=HI" , "t16": "0100|00|1000|Rn:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "tst Rn!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0000|1|Rn|0|n:3|1111|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "tst Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0000|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W"},
+ {"inst": "uadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "uadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "uasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "ubfx Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1110|0|Rn|0|lsb:3|Rd|lsb:2|0|widthM1:5" , "it": "any", "imm": "SbfxUbfxImm(lsb, width)"},
+ {"inst": "uhadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
+ {"inst": "uhadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0110|Rm" , "it": "any"},
+ {"inst": "uhasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
+ {"inst": "uhsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
+ {"inst": "uhsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0110|Rm" , "it": "any"},
+ {"inst": "uhsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0110|Rm" , "it": "any"},
+ {"inst": "umaal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1111|0|Rn|RxLo|RxHi|0110|Rm" , "it": "any"},
+ {"inst": "umlal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1111|0|Rn|RxLo|RxHi|0000|Rm" , "it": "any"},
+ {"inst": "umull RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1101|0|Rn|RdLo|RdHi|0000|Rm" , "it": "any"},
+ {"inst": "uqadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0101|Rm" , "it": "any"},
+ {"inst": "uqadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
+ {"inst": "uqasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
+ {"inst": "uqsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
+ {"inst": "uqsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0101|Rm" , "it": "any"},
+ {"inst": "uqsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0101|Rm" , "it": "any"},
+ {"inst": "usad8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1011|1|Rn|1111|Rd|0000|Rm" , "it": "any"},
+ {"inst": "usada8 Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|1|Rn|Ra|Rd|0000|Rm" , "it": "any"},
+ {"inst": "usat Rd!=XX, #sat, Rn!=XX, {lsl_or_asr #n}" , "t32": "1111|001|110|sop:2|Rn|0|n:3|Rd|n:2|0|sat:5" , "it": "any", "io": "Q=X"},
+ {"inst": "usat16 Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|1101|0|Rn|0000|Rd|0000|sat:4" , "it": "any", "io": "Q=X"},
+ {"inst": "usax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "usub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "usub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"},
+ {"inst": "uxtab Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0010|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "uxtab16 Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0001|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "uxtah Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0000|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "uxtb Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|011|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "uxtb Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0010|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "uxtb16 Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0001|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "uxth Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|010|Rn:3|Rd:3" , "it": "any"},
+ {"inst": "uxth Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0000|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"},
+ {"inst": "wfe" , "t16": "1011|1111|0010|0000" , "it": "any"},
+ {"inst": "wfe" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0010" , "it": "any"},
+ {"inst": "wfi" , "t16": "1011|1111|0011|0000" , "it": "any"},
+ {"inst": "wfi" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0011" , "it": "any"},
+ {"inst": "yield" , "t16": "1011|1111|0001|0000" , "it": "any"},
+ {"inst": "yield" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0001" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT", "level": "ARMv7+", "data": [
+ {"inst": "clrex" , "a32": "1111|010|1011|1|1111|1111|0000|0001|1111"},
+ {"inst": "dbg #immZ" , "a32": "cond|001|1001|0|0000|1111|0000|1111|immZ:4" , "ext": "ARMv8-"},
+ {"inst": "dmb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0101|immZ:4"},
+ {"inst": "dsb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0100|immZ:4"},
+ {"inst": "isb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0110|immZ:4"},
+ {"inst": "pldw [Rn!=PC, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|1U00|1|Rn|1111|n:5|sop:2|0|Rm" , "ext": "MP"},
+ {"inst": "pldw [Rn!=PC, #+/-off]" , "a32": "1111|010|1U00|1|Rn|1111|off:12" , "ext": "MP"},
+ {"inst": "pli [Rn, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|0U10|1|Rn|1111|n:5|sop:2|0|Rm"},
+ {"inst": "pli [Rn, #+/-off]" , "a32": "1111|010|0U10|1|Rn|1111|off:12"},
+ {"inst": "sev" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0100"},
+ {"inst": "sevl" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0101"}
+ ]},
+
+ {"category": "GP GP_EXT", "level": "ARMv7+", "data": [
+ {"inst": "clrex" , "t32": "1111|001|1101|1|1111|1000|1111|0010|1111" , "it": "any"},
+ {"inst": "dmb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0101|immZ:4" , "it": "any"},
+ {"inst": "dsb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0100|immZ:4" , "it": "any"},
+ {"inst": "ldrexb Rd!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|0100|1111" , "it": "any"},
+ {"inst": "ldrexd Rd!=XX, Rd2!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|Rd2 |0111|1111" , "it": "any"},
+ {"inst": "ldrexh Rd!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|0101|1111" , "it": "any"},
+ {"inst": "isb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0110|immZ:4" , "it": "any"},
+ {"inst": "pli [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1000|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"},
+ {"inst": "pli [Rn!=PC, #off]" , "t32": "1111|100|1100|1|Rn|1111|off:12" , "it": "any"},
+ {"inst": "pli [Rn!=PC, #-off]" , "t32": "1111|100|1000|1|Rn|1111|1100|off:8" , "it": "any"},
+ {"inst": "pli [Rn==PC, #+/-off]" , "t32": "1111|100|1U00|1|Rn|1111|off:12" , "it": "any"},
+ {"inst": "sev" , "t16": "1011|1111|0100|0000" , "it": "any"},
+ {"inst": "sev" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0000" , "it": "any"},
+ {"inst": "sevl" , "t16": "1011|1111|0101|0000" , "it": "any"},
+ {"inst": "sevl" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0101" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT", "level": "ARMv8+", "data": [
+ {"inst": "lda Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1100|1001|1111"},
+ {"inst": "ldab Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1100|1001|1111"},
+ {"inst": "ldaex Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1110|1001|1111"},
+ {"inst": "ldaexb Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1110|1001|1111"},
+ {"inst": "ldaexd Rd<=13, Rd2+, [Rn!=PC]" , "a32": "cond|000|1101|1|Rn|Rd|1110|1001|1111"},
+ {"inst": "ldaexh Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1110|1001|1111"},
+ {"inst": "ldah Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1100|1001|1111"},
+ {"inst": "stl Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|1111|1100|1001|Rs"},
+ {"inst": "stlb Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|1111|1100|1001|Rs"},
+ {"inst": "stlex Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|Rd|1110|1001|Rs"},
+ {"inst": "stlexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|Rd|1110|1001|Rs"},
+ {"inst": "stlexd Rd!=PC, Rs!=PC, Rs2+, [Rn!=PC]" , "a32": "cond|000|1101|0|Rn|Rd|1110|1001|Rs"},
+ {"inst": "stlexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|Rd|1110|1001|Rs"},
+ {"inst": "stlh Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|1111|1100|1001|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "level": "ARMv8+", "data": [
+ {"inst": "dcps1" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0001" , "it": "out"},
+ {"inst": "dcps2" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0010" , "it": "out"},
+ {"inst": "dcps3" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0011" , "it": "out"},
+ {"inst": "lda Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1010|1111" , "it": "any"},
+ {"inst": "ldab Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1000|1111" , "it": "any"},
+ {"inst": "ldaex Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1110|1111" , "it": "any"},
+ {"inst": "ldaexb Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1100|1111" , "it": "any"},
+ {"inst": "ldaexd Rd!=PC, Rd2!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|Rd2|1111|1111" , "it": "any"},
+ {"inst": "ldaexh Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1101|1111" , "it": "any"},
+ {"inst": "ldah Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1001|1111" , "it": "any"},
+ {"inst": "stl Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1010|1111" , "it": "any"},
+ {"inst": "stlb Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1000|1111" , "it": "any"},
+ {"inst": "stlex Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1110|Rd" , "it": "any"},
+ {"inst": "stlexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1100|Rd" , "it": "any"},
+ {"inst": "stlexd Rd!=PC, Rs!=PC, Rs2!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|Rs2|1111|Rd" , "it": "any"},
+ {"inst": "stlexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1101|Rd" , "it": "any"},
+ {"inst": "stlh Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1001|1111" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "IDIVA", "data": [
+ {"inst": "sdiv Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|1|Rd|1111|Rm|0001|Rn"},
+ {"inst": "udiv Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1001|1|Rd|1111|Rm|0001|Rn"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "IDIVT", "data": [
+ {"inst": "sdiv Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1100|1|Rn|1111|Rd|1111|Rm" , "it": "any"},
+ {"inst": "udiv Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1101|1|Rn|1111|Rd|1111|Rm" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT", "data": [
+ {"inst": "csdb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0100"},
+ {"inst": "ssbb" , "a32": "1111|010|1011|1|1111|1111|0000|0100|0000"},
+ {"inst": "pssbb" , "a32": "1111|010|1011|1|1111|1111|0000|0100|0100"}
+ ]},
+
+ {"category": "GP GP_EXT", "data": [
+ {"inst": "csdb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0100" , "it": "out"},
+ {"inst": "ssbb" , "t32": "1111|001|1101|1|1111|1000|1111|0100|0000" , "it": "any"},
+ {"inst": "pssbb" , "t32": "1111|001|1101|1|1111|1000|1111|0100|0100" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLRBHB", "data": [
+ {"inst": "clrbhb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0110"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLRBHB", "data": [
+ {"inst": "clrbhb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0110" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [
+ {"inst": "crc32b Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rn|Rd|0000|0100|Rm"},
+ {"inst": "crc32h Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rn|Rd|0000|0100|Rm"},
+ {"inst": "crc32w Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rn|Rd|0000|0100|Rm"},
+ {"inst": "crc32cb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rn|Rd|0010|0100|Rm"},
+ {"inst": "crc32ch Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rn|Rd|0010|0100|Rm"},
+ {"inst": "crc32cw Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rn|Rd|0010|0100|Rm"}
+ ]},
+
+ {"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [
+ {"inst": "crc32b Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|00|Rm" , "it": "out"},
+ {"inst": "crc32h Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|01|Rm" , "it": "out"},
+ {"inst": "crc32w Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|10|Rm" , "it": "out"},
+ {"inst": "crc32cb Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|00|Rm" , "it": "out"},
+ {"inst": "crc32ch Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|01|Rm" , "it": "out"},
+ {"inst": "crc32cw Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|10|Rm" , "it": "out"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PAN", "data": [
+ {"inst": "setpan #immZ" , "a32": "1111|000|1000|1|0000|0000|00|immZ:1|0|0000|0000"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PAN", "data": [
+ {"inst": "setpan #immZ" , "t16": "1011|0110|0001|immZ:1|000" , "it": "out"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RAS", "data": [
+ {"inst": "esb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0000"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RAS", "data": [
+ {"inst": "esb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0000" , "it": "any"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SB", "data": [
+ {"inst": "sb" , "a32": "1111|010|1011|1|1111|1111|0000|0111|0000"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SB", "data": [
+ {"inst": "sb" , "t32": "1111|001|1101|1|1111|1000|1111|0111|0000" , "it": "out"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SECURITY", "data": [
+ {"inst": "smc #immZ" , "a32": "cond|000|1011|0|000000000000|0111|immZ:4"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SECURITY", "data": [
+ {"inst": "smc #immZ" , "t32": "1111|011|1111|1|immZ:4|1000|000000000000" , "it": "any"}
+ ]},
+
+ {"category": "FP", "ext": "FP", "data": [
+ {"inst": "vabs.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|00|Vd|10|10|1|1|'Vn|0|Vn"},
+ {"inst": "vabs.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|00|00|Vd|10|11|1|1|Vn'|0|Vn"},
+ {"inst": "vadd.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|11|Vn|Vd|1010|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vadd.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|11|Vn|Vd|1011|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vcmp.f32 Sn, Sm" , "a32": "cond|11101|'Vn|11|01|00|Vn|10|10|01|'Vm|0|Vm"},
+ {"inst": "vcmp.f32 Sn, #zero" , "a32": "cond|11101|'Vn|11|01|01|Vn|10|10|01|00|0000"},
+ {"inst": "vcmp.f64 Dn, Dm" , "a32": "cond|11101|Vn'|11|01|00|Vn|10|11|01|Vm'|0|Vm"},
+ {"inst": "vcmp.f64 Dn, #zero" , "a32": "cond|11101|Vn'|11|01|01|Vn|10|11|01|00|0000"},
+ {"inst": "vcmpe.f32 Sn, Sm" , "a32": "cond|11101|'Vn|11|01|00|Vn|10|10|11|'Vm|0|Vm"},
+ {"inst": "vcmpe.f32 Sn, #zero" , "a32": "cond|11101|'Vn|11|01|01|Vn|10|10|11|00|0000"},
+ {"inst": "vcmpe.f64 Dn, Dm" , "a32": "cond|11101|Vn'|11|01|00|Vn|10|11|11|Vm'|0|Vm"},
+ {"inst": "vcmpe.f64 Dn, #zero" , "a32": "cond|11101|Vn'|11|01|01|Vn|10|11|11|00|0000"},
+ {"inst": "vcvt.f32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|01|11|Vd|10111|1|Vn'|0|Vn"},
+ {"inst": "vcvt.f64.f32 Dd, Sn" , "a32": "cond|11101|Vd'|11|01|11|Vd|10101|1|'Vn|0|Vn"},
+ {"inst": "vcvt.f32.s32 Sd, Sn" , "a32": "cond|11101|'Vd|11|10|00|Vd|10101|1|'Vn|0|Vn"},
+ {"inst": "vcvt.f32.u32 Sd, Sn" , "a32": "cond|11101|'Vd|11|10|00|Vd|10100|1|'Vn|0|Vn"},
+ {"inst": "vcvt.f64.s32 Dd, Sn" , "a32": "cond|11101|Vd'|11|10|00|Vd|10111|1|'Vn|0|Vn"},
+ {"inst": "vcvt.f64.u32 Dd, Sn" , "a32": "cond|11101|Vd'|11|10|00|Vd|10110|1|'Vn|0|Vn"},
+ {"inst": "vcvt.f32.s16 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.s16.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f32.u16 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.u16.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f32.s32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.s32.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.f32.u32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.u32.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.f64.s16 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.s16.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f64.u16 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.u16.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f64.s32 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.s32.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.f64.u32 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.u32.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvtr.s32.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn"},
+ {"inst": "vcvtr.s32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn"},
+ {"inst": "vcvtr.u32.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn"},
+ {"inst": "vcvtr.u32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn"},
+ {"inst": "vdiv.f32 Sd, Sn, Sm" , "a32": "cond|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vdiv.f64 Dd, Dn, Dm" , "a32": "cond|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vldr.32 Sd, [Rn, #+/-off*4]" , "a32": "cond|1101U|'Vd|01|Rn|Vd|1010|off:8"},
+ {"inst": "vldr.64 Dd, [Rn, #+/-off*4]" , "a32": "cond|1101U|Vd'|01|Rn|Vd|1011|off:8"},
+ {"inst": "vmla.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|00|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vmla.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|00|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vmls.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|00|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vmls.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|00|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vmov.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0000|Vd|1010|0|1|'Vn|0|Vn"},
+ {"inst": "vmov.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0000|Vd|1011|0|1|Vn'|0|Vn"},
+ {"inst": "vmov.f32 Sd, #immVFP" , "a32": "cond|11101|'Vd|11|imm:4|Vd|1010|0000|imm:4" , "imm": "VecVFPImm(immVFP)"},
+ {"inst": "vmov.f64 Dd, #immVFP" , "a32": "cond|11101|Vd'|11|imm:4|Vd|1011|0000|imm:4" , "imm": "VecVFPImm(immVFP)"},
+ {"inst": "vmul.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vmul.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vneg.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0001|Vd|10|10|01|'Vn|0|Vn"},
+ {"inst": "vneg.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0001|Vd|10|11|01|Vn'|0|Vn"},
+ {"inst": "vnmla.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vnmla.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vnmls.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vnmls.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vnmul.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|10|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vnmul.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|10|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vsqrt.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0001|Vd|10|10|11|'Vn|0|Vn"},
+ {"inst": "vsqrt.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0001|Vd|10|11|11|Vn'|0|Vn"},
+ {"inst": "vstr.32 Ss, [Rn, #+/-off*4]" , "a32": "cond|1101U|'Vs|00|Rn|Vs|1010|off:8"},
+ {"inst": "vstr.64 Ds, [Rn, #+/-off*4]" , "a32": "cond|1101U|Vs'|00|Rn|Vs|1011|off:8"},
+ {"inst": "vsub.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|11|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vsub.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm"}
+ ]},
+
+ {"category": "FP", "ext": "FP", "data": [
+ {"inst": "vabs.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|00|Vd|10|10|1|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vabs.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|00|00|Vd|10|11|1|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vadd.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|1010|'Vn|0|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vadd.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|11|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vcmp.f32 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|10|01|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vcmp.f32 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|10|01|00|0000" , "it": "any"},
+ {"inst": "vcmp.f64 Dn, Dm" , "t32": "1110|11101|Vn'|11|01|00|Vn|10|11|01|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vcmp.f64 Dn, #zero" , "t32": "1110|11101|Vn'|11|01|01|Vn|10|11|01|00|0000" , "it": "any"},
+ {"inst": "vcmpe.f32 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|10|11|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vcmpe.f32 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|10|11|00|0000" , "it": "any"},
+ {"inst": "vcmpe.f64 Dn, Dm" , "t32": "1110|11101|Vn'|11|01|00|Vn|10|11|11|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vcmpe.f64 Dn, #zero" , "t32": "1110|11101|Vn'|11|01|01|Vn|10|11|11|00|0000" , "it": "any"},
+ {"inst": "vcvt.f32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10111|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vcvt.f64.f32 Dd, Sn" , "t32": "1110|11101|Vd'|11|01|11|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvt.f32.s32 Sd, Sn" , "t32": "1110|11101|'Vd|11|10|00|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvt.f32.u32 Sd, Sn" , "t32": "1110|11101|'Vd|11|10|00|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvt.f64.s32 Dd, Sn" , "t32": "1110|11101|Vd'|11|10|00|Vd|10111|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvt.f64.u32 Dd, Sn" , "t32": "1110|11101|Vd'|11|10|00|Vd|10110|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvt.f32.s16 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.s16.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f32.u16 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.u16.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f32.s32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.s32.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.f32.u32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.u32.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.f64.s16 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.s16.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f64.u16 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.u16.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"},
+ {"inst": "vcvt.f64.s32 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.s32.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.f64.u32 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvt.u32.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"},
+ {"inst": "vcvtr.s32.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtr.s32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vcvtr.u32.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtr.u32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vdiv.f32 Sd, Sn, Sm" , "t32": "1110|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vdiv.f64 Dd, Dn, Dm" , "t32": "1110|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vldr.32 Sd, [Rn, #+/-off*4]" , "t32": "1110|1101U|'Vd|01|Rn|Vd|1010|off:8" , "it": "any"},
+ {"inst": "vldr.64 Dd, [Rn, #+/-off*4]" , "t32": "1110|1101U|Vd'|01|Rn|Vd|1011|off:8" , "it": "any"},
+ {"inst": "vmla.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|00|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vmls.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|00|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vmov.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0000|Vd|1010|0|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vmov.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0000|Vd|1011|0|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vmov.f32 Sd, #immVFP" , "t32": "1110|11101|'Vd|11|imm:4|Vd|1010|0000|imm:4" , "it": "any", "imm": "VecVFPImm(immVFP)"},
+ {"inst": "vmov.f64 Dd, #immVFP" , "t32": "1110|11101|Vd'|11|imm:4|Vd|1011|0000|imm:4" , "it": "any", "imm": "VecVFPImm(immVFP)"},
+ {"inst": "vmul.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vmul.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vneg.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|10|01|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vneg.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0001|Vd|10|11|01|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vnmla.f32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vnmla.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vnmls.f32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vnmls.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vnmul.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vnmul.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|10|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"},
+ {"inst": "vsqrt.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|10|11|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vsqrt.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0001|Vd|1011|1|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vstr.32 Ss, [Rn, #+/-off*4]" , "t32": "1110|1101U|'Vs|00|Rn|Vs|1010|off:8" , "it": "any"},
+ {"inst": "vstr.64 Ds, [Rn, #+/-off*4]" , "t32": "1110|1101U|Vs'|00|Rn|Vs|1011|off:8" , "it": "any"},
+ {"inst": "vsub.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"},
+ {"inst": "vsub.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"}
+ ]},
+
+ {"category": "FP", "ext": "FP FP16", "data": [
+ {"inst": "vabs.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|00|00|Vd|10|01|1|1|'Vn|0|Vn"},
+ {"inst": "vadd.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|11|Vn|Vd|1001|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vcmp.f16 Sn, Sm" , "a32": "1110|11101|'Vn|11|01|00|Vn|10|01|01|'Vm|0|Vm"},
+ {"inst": "vcmp.f16 Sn, #zero" , "a32": "1110|11101|'Vn|11|01|01|Vn|10|01|01|00|0000"},
+ {"inst": "vcmpe.f16 Sn, Sm" , "a32": "1110|11101|'Vn|11|01|00|Vn|10|01|11|'Vm|0|Vm"},
+ {"inst": "vcmpe.f16 Sn, #zero" , "a32": "1110|11101|'Vn|11|01|01|Vn|10|01|11|00|0000"},
+ {"inst": "vdiv.f16 Sd, Sn, Sm" , "a32": "1110|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vldr.16 Sd, [Rn, #+/-off*2]" , "a32": "1110|1101U|'Vd|01|Rn|Vd|1001|off:8"},
+ {"inst": "vmla.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|00|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vmls.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|00|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vmov.f16 Rd!=PC, Sn" , "a32": "1110|11100|0|01|Vn|Rd|1001|'Vn|00|1|0000"},
+ {"inst": "vmov.f16 Sd, Rn!=PC" , "a32": "1110|11100|0|00|Vd|Rn|1001|'Vd|00|1|0000"},
+ {"inst": "vmov.f16 Sd, #immVFP" , "a32": "1110|11101|'Vd|11|imm:4|Vd|1001|0000|imm:4" , "imm": "VecVFPImm(immVFP)"},
+ {"inst": "vmovx.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|00|00|Vd|1010|01|'Vn|0|Vn"},
+ {"inst": "vmul.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vmul.f16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3"},
+ {"inst": "vmul.f16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3"},
+ {"inst": "vneg.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|0001|Vd|10|01|01|'Vn|0|Vn"},
+ {"inst": "vnmla.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vnmls.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm"},
+ {"inst": "vnmul.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm"},
+ {"inst": "vsqrt.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|0001|Vd|10|01|11|'Vn|0|Vn"},
+ {"inst": "vstr.16 Ss, [Rn, #+/-off*2]" , "a32": "1110|1101U|'Vs|00|Rn|Vs|1001|off:8"},
+ {"inst": "vsub.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|11|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm"}
+ ]},
+
+ {"category": "FP", "ext": "FP FP16", "data": [
+ {"inst": "vabs.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|00|Vd|10|01|1|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vadd.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|1001|'Vn|0|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vcmp.f16 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|01|01|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vcmp.f16 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|01|01|00|0000" , "it": "out"},
+ {"inst": "vcmpe.f16 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|01|11|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vcmpe.f16 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|01|11|00|0000" , "it": "out"},
+ {"inst": "vdiv.f16 Sd, Sn, Sm" , "t32": "1110|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vldr.16 Sd, [Rn, #+/-off*2]" , "t32": "1110|1101U|'Vd|01|Rn|Vd|1001|off:8" , "it": "out"},
+ {"inst": "vmla.f16-32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|00|Vn|Vx|10|sz|'Vn|0|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vmls.f16-32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|00|Vn|Vx|10|sz|'Vn|1|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vmov.f16 Rd!=PC, Sn" , "t32": "1110|11100|0|01|Vn|Rd|1001|'Vn|00|1|0000" , "it": "out"},
+ {"inst": "vmov.f16 Sd, Rn!=PC" , "t32": "1110|11100|0|00|Vd|Rn|1001|'Vd|00|1|0000" , "it": "out"},
+ {"inst": "vmov.f16 Sd, #immVFP" , "t32": "1110|11101|'Vd|11|imm:4|Vd|1001|0000|imm:4" , "it": "out", "imm": "VecVFPImm(immVFP)"},
+ {"inst": "vmovx.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|00|00|Vd|1010|01|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vmul.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vmul.f16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
+ {"inst": "vmul.f16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
+ {"inst": "vneg.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|01|01|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vnmla.f16 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vnmls.f16 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vnmul.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"},
+ {"inst": "vsqrt.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|01|11|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vstr.16 Ss, [Rn, #+/-off*2]" , "t32": "1110|1101U|'Vs|00|Rn|Vs|1001|off:8" , "it": "out"},
+ {"inst": "vsub.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "VFPv4", "data": [
+ {"inst": "vfma.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
+ {"inst": "vfma.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|10|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfma.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|10|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfms.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
+ {"inst": "vfms.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|10|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfms.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|10|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfnma.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
+ {"inst": "vfnma.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfnma.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfnms.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4 FP16"},
+ {"inst": "vfnms.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4"},
+ {"inst": "vfnms.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "ext": "VFPv4"}
+ ]},
+
+ {"category": "ASIMD", "ext": "VFPv4", "data": [
+ {"inst": "vfma.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
+ {"inst": "vfma.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfma.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|10|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfms.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
+ {"inst": "vfms.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|10|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfms.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|10|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfnma.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
+ {"inst": "vfnma.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfnma.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfnms.f16 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out", "ext": "VFPv4 FP16"},
+ {"inst": "vfnms.f32 Sx, Sn, Sm" , "t32": "1110|11101|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any", "ext": "VFPv4"},
+ {"inst": "vfnms.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"}
+ ]},
+
+ {"category": "ASIMD", "ext": "ASIMD", "data": [
+ {"inst": "vaba.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vaba.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vabal.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vabd.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vabd.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabdl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabs.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vabs.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vabs.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vabs.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vabs.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vabs.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vacge.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacge.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacge.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacge.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacgt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacgt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacgt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacgt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacle.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vacle.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vacle.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vacle.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vaclt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vaclt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vaclt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vaclt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vadd.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vadd.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vadd.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vadd.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vadd.x8-64 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vadd.x8-64 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vaddhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00101|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vaddl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vaddw.x8-32 Vd, Vn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vand.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vand.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vand.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
+ {"inst": "vand.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
+ {"inst": "vbic.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbic.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbic.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vbic.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vbif.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbif.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbit.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbit.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbsl.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbsl.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vceq.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00010|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00010|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00001|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00001|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00000|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00000|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00011|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00011|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcls.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcls.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00100|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00100|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclz.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclz.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcnt.x8 Dd, Dn" , "a32": "1111|00111|Vd'|11|00|00|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcnt.x8 Vd, Vn" , "a32": "1111|00111|Vd'|11|00|00|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01110|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01110|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01111|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01111|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.s32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.s32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01101|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01101|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.s32 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f32.s32 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s32.f32 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s32.f32 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f32.u32 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f32.u32 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u32.f32 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u32.f32 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvta.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvta.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvta.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvta.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00110|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00111|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00010|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00010|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00011|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00011|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00100|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00100|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00101|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00101|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vdup.8 Dd, Rn!=PC" , "a32": "cond|11101|1|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.8 Vd, Rn!=PC" , "a32": "cond|11101|1|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Dd, Rn!=PC" , "a32": "cond|11101|0|00|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Vd, Rn!=PC" , "a32": "cond|11101|0|10|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Dd, Rn!=PC" , "a32": "cond|11101|0|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Vd, Rn!=PC" , "a32": "cond|11101|0|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.8 Dd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:3|1|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.8 Vd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:3|1|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Dd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:2|10|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Vd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:2|10|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Dd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:1|100|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Vd, Dn[#i]" , "a32": "1111|00111|Vd'|11|i:1|100|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "veor.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "veor.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vext.8 Dd, Dn, Dm, #immZ<=07" , "a32": "1111|00101|Vd'|11|Vn|Vd|immZ:4|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vext.8 Vd, Vn, Vm, #immZ<=15" , "a32": "1111|00101|Vd'|11|Vn|Vd|immZ:4|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vfma.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfma.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfma.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vfma.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vfms.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfms.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfms.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vfms.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vhadd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vhadd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vhsub.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vhsub.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vins.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|0000|Vd|1010|11|'Vn|0|Vn" , "ext": "FP16"},
+ {"inst": "vld1.8-64 Dd, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 Dd, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 Dd, [Rn!=PC, #off==8]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8 Dd[#i], [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0000|i:3|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8 Dd[#i], [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0000|i:3|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8 Dd[#i], [Rn!=PC, #off==1]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0000|i:3|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.16 Dd[#i], [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.16 Dd[#i], [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0100|i:2|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.16 Dd[#i], [Rn!=PC, #off==2]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.32 Dd[#i], [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.32 Dd[#i], [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1000|i:1|0|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.32 Dd[#i], [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 Dd, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 Dd, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 Dd, [Rn!=PC, #off==1<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==1<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1100|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|1000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|1001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|1001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0011|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0011|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0011|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0001|i:3|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0001|i:3|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, #off==2]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0001|i:3|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==2<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, #off==2<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1101|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0010|i:3|0|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0010|i:3|0|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, #off==3]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0010|i:3|0|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|00|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|00|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, #off==6]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|00|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|10|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|10|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, #off==6]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0110|i:2|10|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|000|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|000|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, #off==12]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|000|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|100|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|100|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, #off==12]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1010|i:1|100|1101" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|0|0|1111" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|0|0|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, #off==3<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|0|0|1101" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|1|0|1111" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|1|0|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, #off==3<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1110|sz|1|0|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vd'|10|Rn|Vd|0001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vd'|10|Rn|Vd|0001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0011|i:3|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0011|i:3|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, #off==4]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0011|i:3|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, #off==8]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|0|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, #off==16]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|1|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, #off==16]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, #off==4<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC]" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, #off==4<<sz]@" , "a32": "1111|01001|Vd'|10|Rn|Vd|1111|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vldmdb.32 [Rn]!, SdList" , "a32": "cond|11010|immVd[0]|11|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vldmdb.64 [Rn]!, DdList" , "a32": "cond|11010|immVd[4]|11|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vldmia.32 [Rn!=PC]{!}, SdList" , "a32": "cond|11001|immVd[0]|W1|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vldmia.64 [Rn!=PC]{!}, DdList" , "a32": "cond|11001|immVd[4]|W1|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vldmia.32 [Rn==PC], SdList" , "a32": "cond|11001|immVd[0]|01|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vldmia.64 [Rn==PC], DdList" , "a32": "cond|11001|immVd[4]|01|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vmax.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmax.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmax.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmax.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmax.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmax.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmaxnm.f16 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
+ {"inst": "vmaxnm.f32 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vmaxnm.f64 Dd, Dn, Dm" , "a32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vmaxnm.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmaxnm.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmaxnm.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmaxnm.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmin.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmin.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmin.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmin.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmin.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmin.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vminnm.f16 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
+ {"inst": "vminnm.f32 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vminnm.f64 Dd, Dn, Dm" , "a32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vminnm.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vminnm.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vminnm.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vminnm.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmla.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmla.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x8-32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x8-32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
+ {"inst": "vmla.f16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
+ {"inst": "vmla.f32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmla.x16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmla.x32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmlal.x8-32 Vx, Dn, Dm" , "a32": "1111|001U1|Vx'|sz|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlal.x16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vx'|01|Vn|Vx|0010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlal.x32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vx'|10|Vn|Vx|0010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmls.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmls.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmls.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x8-32 Dx, Dn, Dm" , "a32": "1111|00110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x8-32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.f16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.f16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.f32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.f32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.x16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.x32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmlsl.x8-32 Vx, Dn, Dm" , "a32": "1111|001U1|Vx'|sz|Vn|Vx|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlsl.x16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vx'|01|Vn|Vx|0110|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlsl.x32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vx'|10|Vn|Vx|0110|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmov Rd!=PC, Sn" , "a32": "cond|11100|0|01|Vn|Rd|1010|'Vn|00|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov Sd, Rn!=PC" , "a32": "cond|11100|0|00|Vd|Rn|1010|'Vd|00|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov Rd!=PC, Rd2!=PC, Ss!=31, Ss2+" , "a32": "cond|11000|1|01|Rd2|Rd|101|000|'Vs|1|Vs" , "ext": "ASIMD"},
+ {"inst": "vmov Sd!=31, Sd2+, Rs!=PC, Rs2!=PC" , "a32": "cond|11000|1|00|Rs2|Rs|101|000|'Vd|1|Vd" , "ext": "ASIMD"},
+ {"inst": "vmov Rd!=PC, Rd2!=PC, Ds" , "a32": "cond|11000|1|01|Rd2|Rd|1011|0|0|Vs'|1|Vs" , "ext": "ASIMD"},
+ {"inst": "vmov Dd, Rs!=PC, Rs2!=PC" , "a32": "cond|11000|1|00|Rs2|Rs|1011|0|0|Vd'|1|Vd" , "ext": "ASIMD"},
+ {"inst": "vmov.x8 Dd[#i], Rn!=PC" , "a32": "cond|11100|1|i:1|0|Vd|Rn|1011|Vd'|i:2|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.x16 Dd[#i], Rn!=PC" , "a32": "cond|11100|0|i:1|0|Vd|Rn|1011|Vd'|i:1|110000" , "ext": "ASIMD"},
+ {"inst": "vmov.x32 Dd[#i], Rn!=PC" , "a32": "cond|11100|0|i:1|0|Vd|Rn|1011|Vd'|001|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.x8 Rd!=PC, Dn[#i]" , "a32": "cond|1110U|1|i:1|1|Vn|Rd|1011|Vn'|i:2|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.x16 Rd!=PC, Dn[#i]" , "a32": "cond|1110U|0|i:1|1|Vn|Rd|1011|Vn'|i:1|110000" , "ext": "ASIMD"},
+ {"inst": "vmov.x32 Rd!=PC, Dn[#i]" , "a32": "cond|11100|0|i:1|1|Vn|Rd|1011|Vn'|001|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.any Dd, Dn" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
+ {"inst": "vmov.any Vd, Vn" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
+ {"inst": "vmov.x8-64 Dd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
+ {"inst": "vmov.x8-64 Vd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
+ {"inst": "vmovl.x8 Vd, Dn" , "a32": "1111|001U1|Vd'|00|1000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmovl.x16 Vd, Dn" , "a32": "1111|001U1|Vd'|01|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmovl.x32 Vd, Dn" , "a32": "1111|001U1|Vd'|10|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmovn.x16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vmul.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmul.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmul.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x8-32|p8 Dd, Dn, Dm" , "a32": "1111|001P0|Vd'|sz|Vn|Vd|1001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x8-32|p8 Vd, Vn, Vm" , "a32": "1111|001P0|Vd'|sz|Vn|Vd|1001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.f32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.f32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmul.x16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmul.x32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmull.x8-32|p8 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmull.p64 Vd, Dn, Dm" , "a32": "1111|00101|Vd'|10|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmull.x16 Vd, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vd'|01|Vn|Vd|1010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmull.x32 Vd, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vd'|10|Vn|Vd|1010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmvn.any Dd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
+ {"inst": "vmvn.any Vd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
+ {"inst": "vmvn.any Dd, Dn" , "a32": "1111|00111|Vd'|11|0000|Vd|0101|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vmvn.any Vd, Vn" , "a32": "1111|00111|Vd'|11|0000|Vd|0101|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vneg.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vneg.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vneg.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vneg.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vneg.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|0011|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vneg.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|0011|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vorn.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
+ {"inst": "vorn.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
+ {"inst": "vorn.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vorn.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vorr.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vorr.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vorr.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vorr.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vpadal.x8-32 Dx, Dn" , "a32": "1111|00111|Vx'|11|sz|00|Vx|0110|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpadal.x8-32 Vx, Vn" , "a32": "1111|00111|Vx'|11|sz|00|Vx|0110|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpadd.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vpadd.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vpaddl.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0010|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpaddl.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0010|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpmax.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vpmax.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vpmax.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vpmin.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vpmin.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vpmin.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vpop.32 SdList" , "a32": "cond|11001|immVd[0]|11|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vpop.64 DdList" , "a32": "cond|11001|immVd[4]|11|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vpush.32 SdList" , "a32": "cond|11010|immVd[0]|10|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vpush.64 DdList" , "a32": "cond|11010|immVd[4]|10|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vqabs.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|0|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqabs.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqadd.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqadd.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmlal.s16-32 Vx, Dn, Dm" , "a32": "1111|00101|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlal.s16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlal.s32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlsl.s16-32 Vx, Dn, Dm" , "a32": "1111|00101|Vx'|sz|Vn|Vx|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlsl.s16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0111|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlsl.s32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0111|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmulh.s16-32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s16-32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmull.s16-32 Vd, Dn, Dm" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmull.s16 Vd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmull.s32 Vd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqmovn.x16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1|U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqmovun.s16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqneg.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|1|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqneg.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|1|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqrshrn.x16-64 Dd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|1001|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqrshrun.s16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqrshrun.s16-64 Dd, Vn, #n" , "a32": "1111|00111|Vd'|imm:6|Vd|1000|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqshl.x8-64 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0111|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshl.x8-64 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0111|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshlu.s8-64 Dd, Dn, #n" , "a32": "1111|00111|Vd'|imm[5:0]|Vd|0110|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshlu.s8-64 Vd, Vn, #n" , "a32": "1111|00111|Vd'|imm[5:0]|Vd|0110|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqshrn.x16-64 Dd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|1001|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqshrun.s16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqshrun.s16-64 Dd, Vn, #n" , "a32": "1111|00111|Vd'|imm:6|Vd|1000|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqsub.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqsub.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vraddhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vrecpe.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vrecpe.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vrecpe.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecpe.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecpe.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecpe.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecps.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vrecps.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vrecps.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vrecps.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vrev16.x8 Dd, Dn" , "a32": "1111|00111|Vd'|11|00|00|Vd|0001|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev16.x8 Vd, Vn" , "a32": "1111|00111|Vd'|11|00|00|Vd|0001|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev32.x8-16 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|1|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev32.x8-16 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|1|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev64.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev64.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrhadd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vrhadd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vrinta.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|00|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrinta.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|00|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrinta.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|00|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrinta.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrinta.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrinta.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrinta.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintm.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintm.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintm.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintm.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintm.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintm.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintm.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintn.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|01|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintn.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|01|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintn.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|01|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintn.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintn.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintn.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintn.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintp.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintp.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintp.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintp.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintp.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintp.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintp.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintr.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintr.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintr.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintx.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintx.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintx.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintx.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintx.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintx.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintx.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintz.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|10|Vd|10|01|11|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintz.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|10|Vd|10|10|11|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintz.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|10|Vd|10|11|11|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintz.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintz.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintz.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintz.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrshr.x8-32 Dd, Dn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vrshr.x8-32 Vd, Vn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vrshr.x8-32 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|0010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrshr.x8-32 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|0010|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow", "pseudoOf": "vmovn"},
+ {"inst": "vrshrn.x16-64 Dd, Vn, #n" , "a32": "1111|00101|Vd'|imm:6|Vd|1000|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vrsqrte.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vrsqrte.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vrsqrte.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrsqrte.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrsqrte.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|00|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrsqrte.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|00|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrsqrts.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vrsqrts.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vrsqrts.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vrsqrts.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vrsra.x8-64 Dx, Dn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0011|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrsra.x8-64 Vx, Vn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0011|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrsubhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vseleq.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
+ {"inst": "vseleq.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vseleq.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vselge.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
+ {"inst": "vselge.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vselge.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vselgt.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|11|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
+ {"inst": "vselgt.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|11|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vselgt.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vselvs.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|01|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"},
+ {"inst": "vselvs.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|01|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vselvs.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|01|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"},
+ {"inst": "vshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vshl.x8-64 Dd, Dn, #n" , "a32": "1111|00101|Vd'|imm[5:0]|Vd|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vshl.x8-64 Vd, Vn, #n" , "a32": "1111|00101|Vd'|imm[5:0]|Vd|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vshll.x8-32 Vd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)", "vecOp": "widen"},
+ {"inst": "vshr.x8-64 Dd, Dn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vshr.x8-64 Vd, Vn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vshr.x8-64 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0000|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vshr.x8-64 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0000|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vshrn.x16-64 Dd, Vn, #n" , "a32": "1111|00101|Vd'|imm:6|Vd|1000|00|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vsli.x8-64 Dx, Dn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vsli.x8-64 Vx, Vn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vsra.x8-64 Dx, Dn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0001|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vsra.x8-64 Vx, Vn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0001|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vsri.x8-64 Dx, Dn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0100|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vsri.x8-64 Vx, Vn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0100|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vst1.8-64 Ds, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 Ds, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 Ds, [Rn!=PC, #off==8]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vstmdb.32 [Rn]!, SdList" , "a32": "cond|11010|immVd[0]|10|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vstmdb.64 [Rn]!, DdList" , "a32": "cond|11010|immVd[4]|10|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vstmia.32 [Rn!=PC]{!}, SdList" , "a32": "cond|11001|immVd[0]|W0|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vstmia.64 [Rn!=PC]{!}, DdList" , "a32": "cond|11001|immVd[4]|W0|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vstmia.32 [Rn==PC], SdList" , "a32": "cond|11001|immVd[0]|00|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"},
+ {"inst": "vstmia.64 [Rn==PC], DdList" , "a32": "cond|11001|immVd[4]|00|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"},
+ {"inst": "vsub.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vsub.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vsub.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsub.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsub.x8-64 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsub.x8-64 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsubhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00101|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vsubl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vsubw.x8-32 Vd, Vn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vswp.any Dx, Dx2!=Dx" , "a32": "1111|00111|Vx'|11|00|10|Vx|0000|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vswp.any Vx, Vx2!=Vx" , "a32": "1111|00111|Vx'|11|00|10|Vx|0000|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|10|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|10|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtrn.x8-32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vtrn.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vtst.x8-32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vtst.x8-32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vuzp.x8-16 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vuzp.x32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
+ {"inst": "vuzp.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vzip.x8-16 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vzip.x32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
+ {"inst": "vzip.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"}
+ ]},
+
+ {"category": "ASIMD", "ext": "ASIMD", "data": [
+ {"inst": "vaba.x8-32 Dd, Dn, Dm" , "t32": "111U|111U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vaba.x8-32 Vd, Vn, Vm" , "t32": "111U|111U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vabal.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vabd.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vabd.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabdl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vabs.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vabs.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vabs.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vabs.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vabs.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vabs.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vacge.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacge.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacge.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacge.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacgt.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacgt.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vacgt.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacgt.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vacle.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vacle.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vacle.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vacle.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vaclt.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vaclt.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vaclt.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vaclt.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vadd.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vadd.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vadd.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vadd.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vadd.x8-64 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vadd.x8-64 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vaddhn.x16-64 Dd, Vn, Vm" , "t32": "1110|11111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vaddl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vaddw.x8-32 Vd, Vn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vand.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vand.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vand.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
+ {"inst": "vand.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"},
+ {"inst": "vbic.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbic.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbic.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vbic.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vbif.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbif.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbit.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbit.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbsl.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vbsl.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.f16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.f16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vceq.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vceq.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00010|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vceq.x8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00010|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcge.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vcge.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00001|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcge.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00001|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcgt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vcgt.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00000|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcgt.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00000|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vcle.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00011|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcle.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00011|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcls.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcls.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vclt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00100|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclt.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00100|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclz.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vclz.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcnt.x8 Dd, Dn" , "t32": "1111|11111|Vd'|11|00|00|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcnt.x8 Vd, Vn" , "t32": "1111|11111|Vd'|11|00|00|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01110|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01110|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01111|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01111|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.s32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.s32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01101|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01101|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vcvt.f32.s32 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f32.s32 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s32.f32 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s32.f32 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f32.u32 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f32.u32 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u32.f32 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u32.f32 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvta.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvta.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvta.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvta.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00110|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00111|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtm.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00010|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00010|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00011|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00011|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtn.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00100|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00100|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00101|0|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00101|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vcvtp.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vdup.8 Dd, Rn!=PC" , "t32": "1110|11101|1|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.8 Vd, Rn!=PC" , "t32": "1110|11101|1|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Dd, Rn!=PC" , "t32": "1110|11101|0|00|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Vd, Rn!=PC" , "t32": "1110|11101|0|10|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Dd, Rn!=PC" , "t32": "1110|11101|0|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Vd, Rn!=PC" , "t32": "1110|11101|0|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"},
+ {"inst": "vdup.8 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:3|1|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.8 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:3|1|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:2|10|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.16 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:2|10|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:1|100|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vdup.32 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:1|100|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "veor.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "veor.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vext.8 Dd, Dn, Dm, #immZ<=07" , "t32": "1110|11111|Vd'|11|Vn|Vd|immZ:4|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vext.8 Vd, Vn, Vm, #immZ<=15" , "t32": "1110|11111|Vd'|11|Vn|Vd|immZ:4|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vfma.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfma.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfma.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vfma.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vfms.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfms.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vfms.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vfms.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vhadd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vhadd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vhsub.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vhsub.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vins.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|0000|Vd|1010|11|'Vn|0|Vn" , "ext": "FP16"},
+ {"inst": "vld1.8-64 Dd, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 Dd, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 Dd, [Rn!=PC, #off==8]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.8 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.8 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.8 Dd[#i], [Rn!=PC, #off==1]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.16 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.16 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.16 Dd[#i], [Rn!=PC, #off==2]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1.32 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld1.32 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1.32 Dd[#i], [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 Dd, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 Dd, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 Dd, [Rn!=PC, #off==1<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==1<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, #off==2]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==2<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, #off==2<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, #off==3]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, #off==6]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, #off==6]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, #off==12]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|1101" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|100|1111" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|100|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3.32 3x{Dd<=27[#i]}++, [Rn!=PC, #off==12]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|100|1101" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|0|0|1111" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|0|0|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=29}+, [Rn!=PC, #off==3<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|0|0|1101" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|1|0|1111" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|1|0|Rm" , "ext": "ASIMD"},
+ {"inst": "vld3r.8-32 3x{Dd<=27}++, [Rn!=PC, #off==3<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1110|sz|1|0|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=29}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.8-32 4x{Dd<=27}++, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0011|i:3|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0011|i:3|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.8 4x{Dd<=29[#i]}+, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0011|i:3|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=29[#i]}+, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.16 4x{Dd<=27[#i]}++, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0111|i:2|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|0|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=29[#i]}+, [Rn!=PC, #off==16]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|0|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|1|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4.32 4x{Dd<=27[#i]}++, [Rn!=PC, #off==16]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1011|i:1|1|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=28}+, [Rn!=PC, #off==4<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vld4r.8-32 4x{Dd<=25}++, [Rn!=PC, #off==4<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1111|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vldmdb.32 [Rn!=PC]!, SdList" , "t32": "1110|11010|immVd[0]|11|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
+ {"inst": "vldmdb.64 [Rn!=PC]!, DdList" , "t32": "1110|11010|immVd[4]|11|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
+ {"inst": "vldmia.32 [Rn!=PC]{!}, SdList" , "t32": "1110|11001|immVd[0]|W1|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
+ {"inst": "vldmia.64 [Rn!=PC]{!}, DdList" , "t32": "1110|11001|immVd[4]|W1|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
+ {"inst": "vmax.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vmax.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vmax.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmax.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmax.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmax.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmaxnm.f16 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vmaxnm.f32 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vmaxnm.f64 Dd, Dn, Dm" , "t32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vmaxnm.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vmaxnm.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vmaxnm.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmaxnm.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmin.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vmin.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vmin.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmin.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmin.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmin.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vminnm.f16 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vminnm.f32 Sd, Sn, Sm" , "t32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vminnm.f64 Dd, Dn, Dm" , "t32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vminnm.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vminnm.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vminnm.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vminnm.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vmla.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmla.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmla.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x8-32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x8-32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
+ {"inst": "vmla.f16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"},
+ {"inst": "vmla.f32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.f32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmla.x16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmla.x32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmla.x32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmlal.x8-32 Vx, Dn, Dm" , "t32": "111U|11111|Vx'|sz|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlal.x16 Vx, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vx'|01|Vn|Vx|0010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlal.x32 Vx, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vx'|10|Vn|Vx|0010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmls.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmls.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmls.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x8-32 Dx, Dn, Dm" , "t32": "1111|11110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x8-32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.f16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.f16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.f32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.f32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.x16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmls.x32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmls.x32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmlsl.x8-32 Vx, Dn, Dm" , "t32": "111U|11111|Vx'|sz|Vn|Vx|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlsl.x16 Vx, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vx'|01|Vn|Vx|0110|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmlsl.x32 Vx, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vx'|10|Vn|Vx|0110|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmov Rd!=PC, Sn" , "t32": "1110|11100|0|01|Vn|Rd|1010|'Vn|00|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov Sd, Rn!=PC" , "t32": "1110|11100|0|00|Vd|Rn|1010|'Vd|00|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov Rd!=PC, Rd2!=PC, Ss!=31, Ss2+" , "t32": "1110|11000|1|01|Rd2|Rd|101|000|'Vs|1|Vs" , "ext": "ASIMD"},
+ {"inst": "vmov Sd!=31, Sd2+, Rs!=PC, Rs2!=PC" , "t32": "1110|11000|1|00|Rs2|Rs|101|000|'Vd|1|Vd" , "ext": "ASIMD"},
+ {"inst": "vmov Rd!=PC, Rd2!=PC, Ds" , "t32": "1110|11000|1|01|Rd2|Rd|1011|0|0|Vs'|1|Vs" , "ext": "ASIMD"},
+ {"inst": "vmov Dd, Rs!=PC, Rs2!=PC" , "t32": "1110|11000|1|00|Rs2|Rs|1011|0|0|Vd'|1|Vd" , "ext": "ASIMD"},
+ {"inst": "vmov.x8 Dd[#i], Rn!=PC" , "t32": "1110|11100|1|i:1|0|Vd|Rn|1011|Vd'|i:2|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.x16 Dd[#i], Rn!=PC" , "t32": "1110|11100|0|i:1|0|Vd|Rn|1011|Vd'|i:1|110000" , "ext": "ASIMD"},
+ {"inst": "vmov.x32 Dd[#i], Rn!=PC" , "t32": "1110|11100|0|i:1|0|Vd|Rn|1011|Vd'|001|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.x8 Rd!=PC, Dn[#i]" , "t32": "1110|1110U|1|i:1|1|Vn|Rd|1011|Vn'|i:2|1|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.x16 Rd!=PC, Dn[#i]" , "t32": "1110|1110U|0|i:1|1|Vn|Rd|1011|Vn'|i:1|110000" , "ext": "ASIMD"},
+ {"inst": "vmov.x32 Rd!=PC, Dn[#i]" , "t32": "1110|11100|0|i:1|1|Vn|Rd|1011|Vn'|001|0000" , "ext": "ASIMD"},
+ {"inst": "vmov.any Dd, Dn" , "t32": "1110|11110|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
+ {"inst": "vmov.any Vd, Vn" , "t32": "1110|11110|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"},
+ {"inst": "vmov.x8-64 Dd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
+ {"inst": "vmov.x8-64 Vd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"},
+ {"inst": "vmovl.x8 Vd, Dn" , "t32": "111U|11111|Vd'|00|1000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmovl.x16 Vd, Dn" , "t32": "111U|11111|Vd'|01|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmovl.x32 Vd, Dn" , "t32": "111U|11111|Vd'|10|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmovn.x16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vmul.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmul.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vmul.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x8-32|p8 Dd, Dn, Dm" , "t32": "111P|11110|Vd'|sz|Vn|Vd|1001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x8-32|p8 Vd, Vn, Vm" , "t32": "111P|11110|Vd'|sz|Vn|Vd|1001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.f32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.f32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmul.x16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"},
+ {"inst": "vmul.x32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmul.x32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vmull.x8-32|p8 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmull.p64 Vd, Dn, Dm" , "t32": "1110|11111|Vd'|10|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmull.x16 Vd, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vd'|01|Vn|Vd|1010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmull.x32 Vd, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vd'|10|Vn|Vd|1010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vmvn.any Dd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
+ {"inst": "vmvn.any Vd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"},
+ {"inst": "vmvn.any Dd, Dn" , "t32": "1111|11111|Vd'|11|0000|Vd|0101|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vmvn.any Vd, Vn" , "t32": "1111|11111|Vd'|11|0000|Vd|0101|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vneg.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vneg.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vneg.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vneg.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vneg.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0011|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vneg.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0011|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vorn.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
+ {"inst": "vorn.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"},
+ {"inst": "vorn.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vorn.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vorr.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vorr.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"},
+ {"inst": "vorr.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vorr.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vpadal.x8-32 Dx, Dn" , "t32": "1111|11111|Vx'|11|sz|00|Vx|0110|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpadal.x8-32 Vx, Vn" , "t32": "1111|11111|Vx'|11|sz|00|Vx|0110|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpadd.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vpadd.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vpaddl.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0010|U|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpaddl.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0010|U|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vpmax.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vpmax.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vpmax.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vpmin.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vpmin.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vpmin.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vpop.32 SdList" , "t32": "1110|11001|immVd[0]|11|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
+ {"inst": "vpop.64 DdList" , "t32": "1110|11001|immVd[4]|11|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
+ {"inst": "vpush.32 SdList" , "t32": "1110|11010|immVd[0]|10|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
+ {"inst": "vpush.64 DdList" , "t32": "1110|11010|immVd[4]|10|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
+ {"inst": "vqabs.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|0|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqabs.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqadd.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqadd.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmlal.s16-32 Vx, Dn, Dm" , "t32": "1110|11111|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlal.s16 Vx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlal.s32 Vx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlsl.s16-32 Vx, Dn, Dm" , "t32": "1110|11111|Vx'|sz|Vn|Vx|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlsl.s16 Vx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0111|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmlsl.s32 Vx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0111|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmulh.s16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmulh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqdmull.s16-32 Vd, Dn, Dm" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmull.s16 Vd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqdmull.s32 Vd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"},
+ {"inst": "vqmovn.x16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1|U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqmovun.s16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqneg.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|1|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqneg.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|1|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrdmulh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqrshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqrshrn.x16-64 Dd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|1001|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqrshrun.s16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqrshrun.s16-64 Dd, Vn, #n" , "t32": "1111|11111|Vd'|imm:6|Vd|1000|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqshl.x8-64 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0111|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshl.x8-64 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0111|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshlu.s8-64 Dd, Dn, #n" , "t32": "1111|11111|Vd'|imm[5:0]|Vd|0110|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshlu.s8-64 Vd, Vn, #n" , "t32": "1111|11111|Vd'|imm[5:0]|Vd|0110|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vqshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqshrn.x16-64 Dd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|1001|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqshrun.s16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"},
+ {"inst": "vqshrun.s16-64 Dd, Vn, #n" , "t32": "1111|11111|Vd'|imm:6|Vd|1000|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vqsub.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vqsub.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"},
+ {"inst": "vraddhn.x16-64 Dd, Vn, Vm" , "t32": "1111|11111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vrecpe.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vrecpe.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"},
+ {"inst": "vrecpe.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecpe.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecpe.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0100|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecpe.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0100|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrecps.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vrecps.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vrecps.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vrecps.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vrev16.x8 Dd, Dn" , "t32": "1111|11111|Vd'|11|00|00|Vd|0001|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev16.x8 Vd, Vn" , "t32": "1111|11111|Vd'|11|00|00|Vd|0001|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev32.x8-16 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|1|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev32.x8-16 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|1|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev64.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|0|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrev64.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|0|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrhadd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vrhadd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vrinta.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|00|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrinta.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|00|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrinta.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|00|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrinta.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrinta.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrinta.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrinta.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintm.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintm.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintm.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintm.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintm.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintm.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintm.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintn.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|01|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintn.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|01|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintn.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|01|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintn.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintn.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintn.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintn.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintp.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintp.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintp.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintp.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintp.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintp.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintp.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintr.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintr.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintr.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintx.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintx.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintx.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintx.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintx.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintx.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintx.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintz.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|01|11|'Vn|0|Vn" , "ext": "ARMv8+ FP16"},
+ {"inst": "vrintz.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|10|11|'Vn|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintz.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|10|Vd|10|11|11|Vn'|0|Vn" , "ext": "ARMv8+"},
+ {"inst": "vrintz.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintz.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vrintz.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrintz.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vrshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrshr.x8-32 Dd, Dn, #zero" , "t32": "1110|11110|Vd'|10|Vd|Vd|0001|Vn'|0|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vrshr.x8-32 Vd, Vn, #zero" , "t32": "1110|11110|Vd'|10|Vd|Vd|0001|Vn'|1|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vrshr.x8-32 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|0010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrshr.x8-32 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|0010|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow", "pseudoOf": "vmovn"},
+ {"inst": "vrshrn.x16-64 Dd, Vn, #n" , "t32": "1110|11111|Vd'|imm:6|Vd|1000|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vrsqrte.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vrsqrte.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vrsqrte.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vrsqrte.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vrsqrte.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|00|10|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrsqrte.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|00|11|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vrsqrts.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vrsqrts.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"},
+ {"inst": "vrsqrts.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vrsqrts.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"},
+ {"inst": "vrsra.x8-64 Dx, Dn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0011|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrsra.x8-64 Vx, Vn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0011|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vrsubhn.x16-64 Dd, Vn, Vm" , "t32": "1111|11111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vseleq.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vseleq.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vseleq.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vselge.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vselge.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vselge.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vselgt.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|11|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vselgt.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|11|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vselgt.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vselvs.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|01|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"},
+ {"inst": "vselvs.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|01|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vselvs.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|01|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"},
+ {"inst": "vshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"},
+ {"inst": "vshl.x8-64 Dd, Dn, #n" , "t32": "1110|11111|Vd'|imm[5:0]|Vd|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vshl.x8-64 Vd, Vn, #n" , "t32": "1110|11111|Vd'|imm[5:0]|Vd|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vshll.x8-32 Vd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)", "vecOp": "widen"},
+ {"inst": "vshr.x8-64 Dd, Dn, #zero" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vshr.x8-64 Vd, Vn, #zero" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"},
+ {"inst": "vshr.x8-64 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0000|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vshr.x8-64 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0000|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vshrn.x16-64 Dd, Vn, #n" , "t32": "1110|11111|Vd'|imm:6|Vd|1000|00|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"},
+ {"inst": "vsli.x8-64 Dx, Dn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vsli.x8-64 Vx, Vn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"},
+ {"inst": "vsra.x8-64 Dx, Dn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0001|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vsra.x8-64 Vx, Vn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0001|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vsri.x8-64 Dx, Dn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0100|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vsri.x8-64 Vx, Vn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0100|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"},
+ {"inst": "vst1.8-64 Ds, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 Ds, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 Ds, [Rn!=PC, #off==8]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|1111" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|Rm" , "ext": "ASIMD"},
+ {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|1101" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|1111" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|Rm" , "ext": "ASIMD"},
+ {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|1101" , "ext": "ASIMD"},
+ {"inst": "vstmdb.32 [Rn!=PC]!, SdList" , "t32": "1110|11010|immVd[0]|10|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
+ {"inst": "vstmdb.64 [Rn!=PC]!, DdList" , "t32": "1110|11010|immVd[4]|10|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
+ {"inst": "vstmia.32 [Rn!=PC]{!}, SdList" , "t32": "1110|11001|immVd[0]|W0|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"},
+ {"inst": "vstmia.64 [Rn!=PC]{!}, DdList" , "t32": "1110|11001|immVd[4]|W0|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"},
+ {"inst": "vsub.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vsub.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"},
+ {"inst": "vsub.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsub.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsub.x8-64 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsub.x8-64 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vsubhn.x16-64 Dd, Vn, Vm" , "t32": "1110|11111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"},
+ {"inst": "vsubl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vsubw.x8-32 Vd, Vn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"},
+ {"inst": "vswp.any Dx, Dx2!=Dx" , "t32": "1111|11111|Vx'|11|00|10|Vx|0000|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vswp.any Vx, Vx2!=Vx" , "t32": "1111|11111|Vx'|11|00|10|Vx|0000|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|10|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|10|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"},
+ {"inst": "vtrn.x8-32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vtrn.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vtst.x8-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vtst.x8-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"},
+ {"inst": "vuzp.x8-16 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vuzp.x32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
+ {"inst": "vuzp.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vzip.x8-16 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"},
+ {"inst": "vzip.x32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"},
+ {"inst": "vzip.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [
+ {"inst": "aesd.x8 Vx, Vm" , "a32": "1111|00111|Vx'|11|00|00|Vx|0|0110|1|Vm'|0|Vm"},
+ {"inst": "aese.x8 Vx, Vm" , "a32": "1111|00111|Vx'|11|00|00|Vx|0|0110|0|Vm'|0|Vm"},
+ {"inst": "aesimc.x8 Vd, Vm" , "a32": "1111|00111|Vd'|11|00|00|Vd|0|0111|1|Vm'|0|Vm"},
+ {"inst": "aesmc.x8 Vd, Vm" , "a32": "1111|00111|Vd'|11|00|00|Vd|0|0111|0|Vm'|0|Vm"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [
+ {"inst": "aesd.x8 Vx, Vm" , "t32": "1111|11111|Vx'|11|00|00|Vx|0|0110|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "aese.x8 Vx, Vm" , "t32": "1111|11111|Vx'|11|00|00|Vx|0|0110|0|Vm'|0|Vm" , "it": "out"},
+ {"inst": "aesimc.x8 Vd, Vm" , "t32": "1111|11111|Vd'|11|00|00|Vd|0|0111|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "aesmc.x8 Vd, Vm" , "t32": "1111|11111|Vd'|11|00|00|Vd|0|0111|0|Vm'|0|Vm" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "BF16", "data": [
+ {"inst": "vmmla.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|00|Vn|Vd|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vcvtb.bf16.f32 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtt.bf16.f32 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10011|1|'Vn|0|Vn"},
+ {"inst": "vdot.bf16 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vdot.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vdot.bf16 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm"},
+ {"inst": "vdot.bf16 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm"},
+ {"inst": "vfmab.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|0|Vm'|1|Vm"},
+ {"inst": "vfmab.bf16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|0|i:1|1|i:1|Vm[2:0]"},
+ {"inst": "vfmat.bf16 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vfmat.bf16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|1|i:1|1|i:1|Vm[2:0]"}
+ ]},
+
+ {"category": "ASIMD", "ext": "BF16", "data": [
+ {"inst": "vmmla.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|00|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vcvtb.bf16.f32 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10010|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtt.bf16.f32 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10011|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vdot.bf16 Dd, Dn, Dm" , "t32": "1110|11000|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vdot.bf16 Vd, Vn, Vm" , "t32": "1110|11000|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vdot.bf16 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11100|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"},
+ {"inst": "vdot.bf16 Vd, Vn, Dm<=15[#i]" , "t32": "1110|11100|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"},
+ {"inst": "vfmab.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vfmab.bf16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|0|i:1|1|i:1|Vm[2:0]" , "it": "out"},
+ {"inst": "vfmat.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vfmat.bf16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|1|i:1|1|i:1|Vm[2:0]" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "DOTPROD", "data": [
+ {"inst": "vsdot.s8 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vsdot.s8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vsdot.s8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|0|Vm"},
+ {"inst": "vsdot.s8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm"},
+ {"inst": "vudot.u8 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|1|Vm"},
+ {"inst": "vudot.u8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vudot.u8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|1|Vm"},
+ {"inst": "vudot.u8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|1|Vm"}
+ ]},
+
+ {"category": "ASIMD", "ext": "DOTPROD", "data": [
+ {"inst": "vsdot.s8 Dd, Dn, Dm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vsdot.s8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vsdot.s8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"},
+ {"inst": "vsdot.s8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"},
+ {"inst": "vudot.u8 Dd, Dn, Dm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vudot.u8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vudot.u8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|1|Vm" , "it": "out"},
+ {"inst": "vudot.u8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|1|Vm" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FCMA", "data": [
+ {"inst": "vcadd.f32 Dd, Dn, Dm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcadd.f32 Vd, Vn, Vm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcmla.f32 Dx, Dn, Dm, #rot2" , "a32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "a32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f32 Dx, Dn, Dm[#i], #rot2" , "a32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f32 Vx, Vn, Dm[#i], #rot2" , "a32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FCMA", "data": [
+ {"inst": "vcadd.f32 Dd, Dn, Dm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcadd.f32 Vd, Vn, Vm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "t32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "t32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f32 Dx, Dn, Dm[#i], #rot2" , "t32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f32 Vx, Vn, Dm[#i], #rot2" , "t32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FCMA FP16", "data": [
+ {"inst": "vcadd.f16 Dd, Dn, Dm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcadd.f16 Vd, Vn, Vm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "a32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f16 Vx, Vn, Vm, #rot2" , "a32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f16 Dx, Dn, Dm<=15[#i], #rot2" , "a32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|0|i:1|0|Vm" , "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f16 Vx, Vn, Dm<=15[#i], #rot2" , "a32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|1|i:1|0|Vm" , "imm": "VecRot2Imm(rot2)"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FCMA FP16", "data": [
+ {"inst": "vcadd.f16 Dd, Dn, Dm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcadd.f16 Vd, Vn, Vm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"},
+ {"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "t32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "t32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f16 Dx, Dn, Dm<=15[#i], #rot2" , "t32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|0|i:1|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"},
+ {"inst": "vcmla.f16 Vx, Vn, Dm<=15[#i], #rot2" , "t32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|1|i:1|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FHM", "data": [
+ {"inst": "vfmal.f16 Dx, Sn, Sm" , "a32": "1111|11000|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm"},
+ {"inst": "vfmal.f16 Vx, Dn, Dm" , "a32": "1111|11000|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vfmal.f16 Dx, Sn, Sm<=15[#i]" , "a32": "1111|11100|Vx'|00|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]"},
+ {"inst": "vfmal.f16 Vx, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vx'|00|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3"},
+ {"inst": "vfmsl.f16 Dx, Sn, Sm" , "a32": "1111|11001|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm"},
+ {"inst": "vfmsl.f16 Vx, Dn, Dm" , "a32": "1111|11001|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vfmsl.f16 Dx, Sn, Sm<=15[#i]" , "a32": "1111|11100|Vx'|01|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]"},
+ {"inst": "vfmsl.f16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|11100|Vx'|01|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FHM", "data": [
+ {"inst": "vfmal.f16 Dx, Sn, Sm" , "t32": "1111|11000|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm" , "it": "out"},
+ {"inst": "vfmal.f16 Vx, Dn, Dm" , "t32": "1111|11000|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vfmal.f16 Dx, Sn, Sm<=15[#i]" , "t32": "1111|11100|Vx'|00|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]" , "it": "out"},
+ {"inst": "vfmal.f16 Vx, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vx'|00|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3" , "it": "out"},
+ {"inst": "vfmsl.f16 Dx, Sn, Sm" , "t32": "1111|11001|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm" , "it": "out"},
+ {"inst": "vfmsl.f16 Vx, Dn, Dm" , "t32": "1111|11001|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vfmsl.f16 Dx, Sn, Sm<=15[#i]" , "t32": "1111|11100|Vx'|01|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]" , "it": "out"},
+ {"inst": "vfmsl.f16 Vx, Dn, Dm<=07[#i]" , "t32": "1111|11100|Vx'|01|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FP16CONV", "data": [
+ {"inst": "vcvt.f16.f32 Dd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01100|0|Vn'|0|Vn"},
+ {"inst": "vcvt.f32.f16 Vd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01110|0|Vn'|0|Vn"},
+ {"inst": "vcvt.f16.s16 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f16.s16 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s16.f16 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s16.f16 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f16.u16 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f16.u16 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u16.f16 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u16.f16 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvta.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10011|1|'Vn|0|Vn"},
+ {"inst": "vcvta.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtb.f32.f16 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|10|Vd|10100|1|'Vn|0|Vn"},
+ {"inst": "vcvtb.f16.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10100|1|'Vn|0|Vn"},
+ {"inst": "vcvtb.f64.f16 Dd, Sn" , "a32": "cond|11101|Vd'|11|00|10|Vd|10110|1|'Vn|0|Vn"},
+ {"inst": "vcvtb.f16.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10110|1|Vn'|0|Vn"},
+ {"inst": "vcvtm.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00110|0|Vn'|0|Vn"},
+ {"inst": "vcvtm.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00110|1|Vn'|0|Vn"},
+ {"inst": "vcvtm.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00111|0|Vn'|0|Vn"},
+ {"inst": "vcvtm.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00111|1|Vn'|0|Vn"},
+ {"inst": "vcvtm.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10011|1|'Vn|0|Vn"},
+ {"inst": "vcvtm.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtn.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00010|0|Vn'|0|Vn"},
+ {"inst": "vcvtn.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00010|1|Vn'|0|Vn"},
+ {"inst": "vcvtn.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00011|0|Vn'|0|Vn"},
+ {"inst": "vcvtn.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00011|1|Vn'|0|Vn"},
+ {"inst": "vcvtn.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10011|1|'Vn|0|Vn"},
+ {"inst": "vcvtn.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtp.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00100|0|Vn'|0|Vn"},
+ {"inst": "vcvtp.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00100|1|Vn'|0|Vn"},
+ {"inst": "vcvtp.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00101|0|Vn'|0|Vn"},
+ {"inst": "vcvtp.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00101|1|Vn'|0|Vn"},
+ {"inst": "vcvtp.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10011|1|'Vn|0|Vn"},
+ {"inst": "vcvtp.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtr.s32.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtr.u32.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn"},
+ {"inst": "vcvtt.f32.f16 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|10|Vd|10101|1|'Vn|0|Vn"},
+ {"inst": "vcvtt.f16.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10101|1|'Vn|0|Vn"},
+ {"inst": "vcvtt.f64.f16 Dd, Sn" , "a32": "cond|11101|Vd'|11|00|10|Vd|10111|1|'Vn|0|Vn"},
+ {"inst": "vcvtt.f16.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10111|1|Vn'|0|Vn"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FP16CONV", "data": [
+ {"inst": "vcvt.f16.f32 Dd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01100|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvt.f32.f16 Vd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01110|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvt.f16.s16 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f16.s16 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s16.f16 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.s16.f16 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f16.u16 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.f16.u16 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u16.f16 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvt.u16.f16 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "it": "out", "imm": "VecFBitsASIMD(fbits)"},
+ {"inst": "vcvta.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvta.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtb.f32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|10|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtb.f16.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10100|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtb.f64.f16 Dd, Sn" , "t32": "1110|11101|Vd'|11|00|10|Vd|10110|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtb.f16.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10110|1|Vn'|0|Vn" , "it": "any"},
+ {"inst": "vcvtm.s16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00110|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtm.s16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00110|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtm.u16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00111|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtm.u16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00111|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtm.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtm.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtn.s16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00010|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtn.s16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00010|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtn.u16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00011|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtn.u16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00011|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtn.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtn.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtp.s16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00100|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtp.s16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00100|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtp.u16.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00101|0|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtp.u16.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|00101|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "vcvtp.s32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10011|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtp.u32.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtr.s32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtr.u32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn" , "it": "out"},
+ {"inst": "vcvtt.f32.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|10|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtt.f16.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10101|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtt.f64.f16 Dd, Sn" , "t32": "1110|11101|Vd'|11|00|10|Vd|10111|1|'Vn|0|Vn" , "it": "any"},
+ {"inst": "vcvtt.f16.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10111|1|Vn'|0|Vn" , "it": "any"}
+ ]},
+
+ {"category": "ASIMD", "ext": "I8MM", "data": [
+ {"inst": "vsmmla.s8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vsudot.u8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|1|Vm"},
+ {"inst": "vsudot.u8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|1|Vm"},
+ {"inst": "vummla.u8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vusdot.s8 Dd, Dn, Dm" , "a32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"},
+ {"inst": "vusdot.s8 Vd, Vn, Vm" , "a32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"},
+ {"inst": "vusdot.s8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm"},
+ {"inst": "vusdot.s8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm"},
+ {"inst": "vusmmla.s8 Vd, Vn, Vm" , "a32": "1111|11001|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm"}
+ ]},
+
+ {"category": "ASIMD", "ext": "I8MM", "data": [
+ {"inst": "vsmmla.s8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vsudot.u8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|1|Vm" , "it": "out"},
+ {"inst": "vsudot.u8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|1|Vm" , "it": "out"},
+ {"inst": "vummla.u8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vusdot.s8 Dd, Dn, Dm" , "t32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vusdot.s8 Vd, Vn, Vm" , "t32": "1111|11001|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "vusdot.s8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"},
+ {"inst": "vusdot.s8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11101|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"},
+ {"inst": "vusmmla.s8 Vd, Vn, Vm" , "t32": "1111|11001|Vd'|10|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "JSCVT", "data": [
+ {"inst": "vjcvt.s32.f64 Sd, Dn" , "a32": "1110|11101|'Vd|11|1001|Vd|1011|11|Vn'|0|Vn"}
+ ]},
+
+ {"category": "ASIMD", "ext": "JSCVT", "data": [
+ {"inst": "vjcvt.s32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|1001|Vd|1011|11|Vn'|0|Vn" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD", "ext": "RDM", "data": [
+ {"inst": "vqrdmlah.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|1|Vm"},
+ {"inst": "vqrdmlah.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vqrdmlah.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3"},
+ {"inst": "vqrdmlah.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3"},
+ {"inst": "vqrdmlah.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm"},
+ {"inst": "vqrdmlah.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm"},
+ {"inst": "vqrdmlsh.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1100|Vn'|0|Vm'|1|Vm"},
+ {"inst": "vqrdmlsh.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1100|Vn'|1|Vm'|1|Vm"},
+ {"inst": "vqrdmlsh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3"},
+ {"inst": "vqrdmlsh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3"},
+ {"inst": "vqrdmlsh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm"},
+ {"inst": "vqrdmlsh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm"}
+ ]},
+
+ {"category": "ASIMD", "ext": "RDM", "data": [
+ {"inst": "vqrdmlah.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vqrdmlah.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vqrdmlah.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
+ {"inst": "vqrdmlah.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
+ {"inst": "vqrdmlah.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm" , "it": "out"},
+ {"inst": "vqrdmlah.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm" , "it": "out"},
+ {"inst": "vqrdmlsh.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1100|Vn'|0|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vqrdmlsh.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1100|Vn'|1|Vm'|1|Vm" , "it": "out"},
+ {"inst": "vqrdmlsh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
+ {"inst": "vqrdmlsh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"},
+ {"inst": "vqrdmlsh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm" , "it": "out"},
+ {"inst": "vqrdmlsh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [
+ {"inst": "sha1c.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "sha1h.32 Vd, Vn" , "a32": "1111|00111|Vd'|11|1001|Vd|0|0101|1|Vn'|0|Vn"},
+ {"inst": "sha1m.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "sha1p.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "sha1su0.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "sha1su1.32 Vx, Vn" , "a32": "1111|00111|Vx'|11|1010|Vx|0|0111|0|Vn'|0|Vn"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [
+ {"inst": "sha1c.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "sha1h.32 Vd, Vn" , "t32": "1111|11111|Vd'|11|1001|Vd|0|0101|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "sha1m.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "sha1p.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "sha1su0.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "sha1su1.32 Vx, Vn" , "t32": "1111|11111|Vx'|11|1010|Vx|0|0111|0|Vn'|0|Vn" , "it": "out"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [
+ {"inst": "sha256h.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "sha256h2.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"},
+ {"inst": "sha256su0.32 Vx, Vn" , "a32": "1111|00111|Vx'|11|1010|Vx|0|0111|1|Vn'|0|Vn"},
+ {"inst": "sha256su1.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [
+ {"inst": "sha256h.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "sha256h2.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"},
+ {"inst": "sha256su0.32 Vx, Vn" , "t32": "1111|11111|Vx'|11|1010|Vx|0|0111|1|Vn'|0|Vn" , "it": "out"},
+ {"inst": "sha256su1.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}
+ ]}
+ ]
+}
diff --git a/3rdparty/asmjit/db/isa_aarch64.json b/3rdparty/asmjit/db/isa_aarch64.json
new file mode 100644
index 00000000000..740085101e4
--- /dev/null
+++ b/3rdparty/asmjit/db/isa_aarch64.json
@@ -0,0 +1,3820 @@
+{
+ "registers": {
+ "r": {"kind": "gp" , "any": "r", "names": ["r0-31"]},
+ "b": {"kind": "vec", "any": "b", "names": ["b0-31"]},
+ "h": {"kind": "vec", "any": "h", "names": ["h0-31"]},
+ "s": {"kind": "vec", "any": "s", "names": ["s0-31"]},
+ "d": {"kind": "vec", "any": "d", "names": ["d0-31"]},
+ "v": {"kind": "vec", "any": "v", "names": ["v0-31"]}
+ },
+
+ "instructions": [
+ {"category": "GP", "data": [
+ {"inst": "adc Wd, Wn, Wm" , "op": "00011010|000|Rm|000000|Rn|Rd" , "io": "C=R"},
+ {"inst": "adc Xd, Xn, Xm" , "op": "10011010|000|Rm|000000|Rn|Rd" , "io": "C=R"},
+ {"inst": "adcs Wd, Wn, Wm" , "op": "00111010|000|Rm|000000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "adcs Xd, Xn, Xm" , "op": "10111010|000|Rm|000000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "add Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "00001011|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "add Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "10001011|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "add Wd|WSP, Wn|WSP, Wm, {extend #n}" , "op": "00001011|001|Rm|option:3|n:3|Rn|Rd"},
+ {"inst": "add Xd|SP, Xn|SP, Rm, {extend #n}" , "op": "10001011|001|Rm|option:3|n:3|Rn|Rd"},
+ {"inst": "add Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "00010001|0|n:1|immZ:12|Rn|Rd"},
+ {"inst": "add Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "10010001|0|n:1|immZ:12|Rn|Rd"},
+ {"inst": "adds Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "00101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adds Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "10101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adds Wd, Wn|WSP, Wm, {extend #n}" , "op": "00101011|001|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adds Xd, Xn|SP, Rm, {extend #n}" , "op": "10101011|001|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adds Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "00110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adds Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "10110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "adr Xd, #relS" , "op": "0|relS[1:0]|10000|relS[20:2]|Rd"},
+ {"inst": "adrp Xd, #relS" , "op": "1|relS[1:0]|10000|relS[20:2]|Rd"},
+ {"inst": "and Wd|WSP, Wn, Wm, {sop #n}" , "op": "00001010|sop|0|Rm|n:6|Rn|Rd" , "imm": "ShiftImm(n, x)"},
+ {"inst": "and Xd|SP, Xn, Xm, {sop #n}" , "op": "10001010|sop|0|Rm|n:6|Rn|Rd" , "imm": "ShiftImm(n, x)"},
+ {"inst": "and Wd|WSP, Wn, #imm" , "op": "00010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 0)"},
+ {"inst": "and Xd|SP, Xn, #imm" , "op": "10010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 1)"},
+ {"inst": "ands Wd|WSP, Wn, Wm, {sop #n}" , "op": "01101010|sop|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "ShiftImm(n, x)"},
+ {"inst": "ands Xd|SP, Xn, Xm, {sop #n}" , "op": "11101010|sop|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "ShiftImm(n, x)"},
+ {"inst": "ands Wd|WSP, Wn, #imm" , "op": "01110010|0|imm:13|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 0)"},
+ {"inst": "ands Xd|SP, Xn, #imm" , "op": "11110010|0|imm:13|Rn|Rd" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 1)"},
+ {"inst": "asr|asrv Wd, Wn, Wm" , "op": "00011010|110|Rm|001010|Rn|Rd"},
+ {"inst": "asr|asrv Xd, Xn, Xm" , "op": "10011010|110|Rm|001010|Rn|Rd"},
+ {"inst": "asr Wd, Wn, #n" , "op": "00010011|00|immr:6|011111|Rn|Rd"},
+ {"inst": "asr Xd, Xn, #n" , "op": "10010011|01|immr:6|111111|Rn|Rd"},
+ {"inst": "at #at_op, Xt" , "op": "11010101|00001|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmAt(at_op)"},
+ {"inst": "b #relS*4" , "op": "000101|relS:26" , "control": "jump"},
+ {"inst": "b.<cond> #relS*4" , "op": "01010100|relS:19|0|cond" , "control": "branch", "io": "N=R Z=R C=R V=R"},
+ {"inst": "bfc Wd, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|11111|Rd"},
+ {"inst": "bfc Xd, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|11111|Rd"},
+ {"inst": "bfi Wd, Wn, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|Rn|Rd"},
+ {"inst": "bfi Xd, Xn, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|Rn|Rd"},
+ {"inst": "bfm Wd, Wn, #immr, #imms" , "op": "00110011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms)"},
+ {"inst": "bfm Xd, Xn, #immr, #imms" , "op": "10110011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms)"},
+ {"inst": "bfxil Wd, Wn, #lsb, #width" , "op": "00110011|00|immr:6|imms:6|Rn|Rd"},
+ {"inst": "bfxil Xd, Xn, #lsb, #width" , "op": "10110011|01|immr:6|imms:6|Rn|Rd"},
+ {"inst": "bic Wd, Wn, Wm, {sop #n}" , "op": "00001010|sop:2|1|Rm|n:6|Rn|Rd"},
+ {"inst": "bic Xd, Xn, Xm, {sop #n}" , "op": "10001010|sop:2|1|Rm|n:6|Rn|Rd"},
+ {"inst": "bics Wd, Wn, Wm, {sop #n}" , "op": "01101010|sop:2|1|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "bics Xd, Xn, Xm, {sop #n}" , "op": "11101010|sop:2|1|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "bl #relS*4" , "op": "100101|relS:26" , "control": "call"},
+ {"inst": "blr Xn" , "op": "11010110|001|11111000000|Rn|00000" , "control": "call"},
+ {"inst": "br Xn" , "op": "11010110|000|11111000000|Rn|00000" , "control": "jump"},
+ {"inst": "brk #imm" , "op": "11010100|001|imm:16|00000"},
+ {"inst": "cbnz Wn, #relS*4" , "op": "00110101|relS:19|Rn" , "control": "branch"},
+ {"inst": "cbnz Xn, #relS*4" , "op": "10110101|relS:19|Rn" , "control": "branch"},
+ {"inst": "cbz Wn, #relS*4" , "op": "00110101|relS:19|Rn" , "control": "branch"},
+ {"inst": "cbz Xn, #relS*4" , "op": "10110101|relS:19|Rn" , "control": "branch"},
+ {"inst": "ccmn Wn, Wm, #nzcv, #cond" , "op": "00111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmn Xn, Xm, #nzcv, #cond" , "op": "10111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmn Wn, #imm, #nzcv, #cond" , "op": "00111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmn Xn, #imm, #nzcv, #cond" , "op": "10111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmp Wn, Wm, #nzcv, #cond" , "op": "01111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmp Xn, Xm, #nzcv, #cond" , "op": "11111010|010|Rm|cond|00|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmp Wn, #imm, #nzcv, #cond" , "op": "01111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ccmp Xn, #imm, #nzcv, #cond" , "op": "11111010|010|imm:5|cond|10|Rn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cinc Wd, Wn, #cond" , "op": "00011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "cinc Xd, Xn, #cond" , "op": "10011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "cinv Wd, Wn, #cond" , "op": "01011010|100|Rn|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "cinv Xd, Xn, #cond" , "op": "11011010|100|Rn|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "clrex {#imm=15}" , "op": "11010101|000|00011|0011|CRm|010|11111" , "CRm": "imm"},
+ {"inst": "cls Wd, Wn" , "op": "01011010|110|00000000101|Rn|Rd"},
+ {"inst": "cls Xd, Xn" , "op": "11011010|110|00000000101|Rn|Rd"},
+ {"inst": "clz Wd, Wn" , "op": "01011010|110|00000000100|Rn|Rd"},
+ {"inst": "clz Xd, Xn" , "op": "11011010|110|00000000100|Rn|Rd"},
+ {"inst": "cmn Wn|WSP, #imm, {lsl #n=0|12}" , "op": "00110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Xn|SP, #imm, {lsl #n=0|12}" , "op": "10110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Wn|WSP, Wm, {extend #n}" , "op": "00101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Xn|SP, Rm, {extend #n}" , "op": "10101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Wn, Wm, {lsl|lsr|asr #n}" , "op": "00101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmn Xn, Xm, {lsl|lsr|asr #n}" , "op": "10101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Wn, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Xn, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Wn|WSP, Wm, {extend #n}" , "op": "01101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Xn|SP, Rm, {extend #n}" , "op": "11101011|001|Rm|option:3|n:3|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Wn|WSP, #imm, {lsl #n=0|12}" , "op": "01110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmp Xn|SP, #imm, {lsl #n=0|12}" , "op": "11110001|0|n:1|imm:12|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cneg Wd, Wn, #cond" , "op": "01011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "cneg Xd, Xn, #cond" , "op": "11011010|100|Rn|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csdb" , "op": "11010101|00|000|011|0010|0010|100|11111"},
+ {"inst": "csel Wd, Wn, Wm, #cond" , "op": "00011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csel Xd, Xn, Xm, #cond" , "op": "10011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "cset Wd, #cond" , "op": "00011010|100|11111|cond|01|11111|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "cset Xd, #cond" , "op": "10011010|100|11111|cond|01|11111|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csetm Wd, #cond" , "op": "01011010|100|11111|cond|00|11111|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csetm Xd, #cond" , "op": "11011010|100|11111|cond|00|11111|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csinc Wd, Wn, Wm, #cond" , "op": "00011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csinc Xd, Xn, Xm, #cond" , "op": "10011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csinv Wd, Wn, Wm, #cond" , "op": "01011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csinv Xd, Xn, Xm, #cond" , "op": "11011010|100|Rm|cond|00|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csneg Wd, Wn, Wm, #cond" , "op": "01011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "csneg Xd, Xn, Xm, #cond" , "op": "11011010|100|Rm|cond|01|Rn|Rd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "dc #dc_op, Xt" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmDC(dc_op)"},
+ {"inst": "dcps1 {#imm}" , "op": "11010100|101|imm:16|00001"},
+ {"inst": "dcps2 {#imm}" , "op": "11010100|101|imm:16|00010"},
+ {"inst": "dcps3 {#imm}" , "op": "11010100|101|imm:16|00011"},
+ {"inst": "dmb #barrier_op" , "op": "11010101|000|00|011|0011|CRm|101|11111" , "imm": "ImmDataBarrier(barrier_op)"},
+ {"inst": "drps" , "op": "11010110|101|11111|00000|01111|1|00000"},
+ {"inst": "dsb #barrier_op" , "op": "11010101|000|00|011|0011|CRm|101|11111" , "imm": "ImmDataBarrier(barrier_op)", "ext": "XS"},
+ {"inst": "eon Wd, Wn, Wm, {sop #n}" , "op": "01001010|sop:2|1|Rm|n:6|Rn|Rd"},
+ {"inst": "eon Xd, Xn, Xm, {sop #n}" , "op": "11001010|sop:2|1|Rm|n:6|Rn|Rd"},
+ {"inst": "eor Wd, Wn, Wm, {sop #n}" , "op": "01001010|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "eor Xd, Xn, Xm, {sop #n}" , "op": "11001010|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "eor Wd|WSP, Wn, #imm" , "op": "01010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 0)"},
+ {"inst": "eor Xd|SP, Xn, #imm" , "op": "11010010|0|imm:13|Rn|Rd" , "imm": "LogicalImm(imm, 1)"},
+ {"inst": "eret" , "op": "11010110|100|11111|0000|00|11111|00000"},
+ {"inst": "extr Wd, Wn, Wm, #imm" , "op": "00010011|100|Rm|0|imm:5|Rn|Rd"},
+ {"inst": "extr Xd, Xn, Xm, #imm" , "op": "10010011|110|Rm|imm:6|Rn|Rd"},
+ {"inst": "hint #imm" , "op": "11010101|000|00|011|0010|imm:7|11111"},
+ {"inst": "hlt #imm" , "op": "11010100|010|imm:16|00000"},
+ {"inst": "hvc #imm" , "op": "11010100|000|imm:16|00010"},
+ {"inst": "ic #ic_op" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|11111" , "imm": "ImmIC(ic_op)"},
+ {"inst": "ic #ic_op, Xt" , "op": "11010101|000|01|op1:3|0111|CRm|op2:3|Rt" , "imm": "ImmIC(ic_op)"},
+ {"inst": "isb {#isb_op=15}" , "op": "11010101|000|00|011|0011|CRm|110|11111" , "imm": "ImmISB(isb_op)"},
+ {"inst": "ldar Wd, [Xn|SP]" , "op": "10001000|110|11111|1|11111|Rn|Rd"},
+ {"inst": "ldar Xd, [Xn|SP]" , "op": "11001000|110|11111|1|11111|Rn|Rd"},
+ {"inst": "ldarb Wd, [Xn|SP]" , "op": "00001000|110|11111|1|11111|Rn|Rd"},
+ {"inst": "ldarh Wd, [Xn|SP]" , "op": "01001000|110|11111|1|11111|Rn|Rd"},
+ {"inst": "ldaxp Wd, Wd2, [Xn|SP]" , "op": "10001000|011|11111|1|Rd2|Rn|Rd"},
+ {"inst": "ldaxp Xd, Xd2, [Xn|SP]" , "op": "11001000|011|11111|1|Rd2|Rn|Rd"},
+ {"inst": "ldaxr Wd, [Xn|SP]" , "op": "10001000|010|11111|1|11111|Rn|Rd"},
+ {"inst": "ldaxr Xd, [Xn|SP]" , "op": "11001000|010|11111|1|11111|Rn|Rd"},
+ {"inst": "ldaxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|1|11111|Rn|Rd"},
+ {"inst": "ldaxrh Xd, [Xn|SP]" , "op": "01001000|010|11111|1|11111|Rn|Rd"},
+ {"inst": "ldnp Wd, Wd2, [Xn|SP, #offS*4]" , "op": "00101000|01|offS:7|Rd2|Rn|Rd"},
+ {"inst": "ldnp Xd, Xd2, [Xn|SP, #offS*8]" , "op": "10101000|01|offS:7|Rd2|Rn|Rd"},
+ {"inst": "ldp Wd, Wd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010100|!post|W|1|offS:7|Rd2|Rn|Rd"},
+ {"inst": "ldp Xd, Xd2, [Xn|SP, #offS*8]{@}{!}" , "op": "1010100|!post|W|1|offS:7|Rd2|Rn|Rd"},
+ {"inst": "ldpsw Xd, Xd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0110100|!post|W|1|offS:7|Rd2|Rn|Rd"},
+ {"inst": "ldr Wd, [Xn|SP, #offZ*4]" , "op": "10111001|01|offZ:12|Rn|Rd"},
+ {"inst": "ldr Xd, [Xn|SP, #offZ*8]" , "op": "11111001|01|offZ:12|Rn|Rd"},
+ {"inst": "ldr Wd, [Xn|SP, #offS*4]@" , "op": "10111000|010|offS:9|01|Rn|Rd"},
+ {"inst": "ldr Xd, [Xn|SP, #offS*8]@" , "op": "11111000|010|offS:9|01|Rn|Rd"},
+ {"inst": "ldr Wd, [Xn|SP, #offS*4]!" , "op": "10111000|010|offS:9|11|Rn|Rd"},
+ {"inst": "ldr Xd, [Xn|SP, #offS*8]!" , "op": "11111000|010|offS:9|11|Rn|Rd"},
+ {"inst": "ldr Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"},
+ {"inst": "ldr Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"},
+ {"inst": "ldr Wd, [PC, #offS*4]" , "op": "00011000|offS:19|Rd"},
+ {"inst": "ldr Xd, [PC, #offS*4]" , "op": "01011000|offS:19|Rd"},
+ {"inst": "ldrb Wd, [Xn|SP, #offZ]" , "op": "00111001|01|offZ:12|Rn|Rd"},
+ {"inst": "ldrb Wd, [Xn|SP, #offS]@" , "op": "00111000|010|offS:9|01|Rn|Rd"},
+ {"inst": "ldrb Wd, [Xn|SP, #offS]!" , "op": "00111000|010|offS:9|11|Rn|Rd"},
+ {"inst": "ldrb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
+ {"inst": "ldrh Wd, [Xn|SP, #offZ*2]" , "op": "01111001|01|offZ:12|Rn|Rd"},
+ {"inst": "ldrh Wd, [Xn|SP, #offS*2]@" , "op": "01111000|010|offS:9|01|Rn|Rd"},
+ {"inst": "ldrh Wd, [Xn|SP, #offS*2]!" , "op": "01111000|010|offS:9|11|Rn|Rd"},
+ {"inst": "ldrh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
+ {"inst": "ldrsb Wd, [Xn|SP, #offZ]" , "op": "00111001|11|offZ:12|Rn|Rd"},
+ {"inst": "ldrsb Xd, [Xn|SP, #offZ]" , "op": "00111001|10|offZ:12|Rn|Rd"},
+ {"inst": "ldrsb Wd, [Xn|SP, #offS]@" , "op": "00111000|110|offS:9|01|Rn|Rd"},
+ {"inst": "ldrsb Xd, [Xn|SP, #offS]@" , "op": "00111000|100|offS:9|01|Rn|Rd"},
+ {"inst": "ldrsb Wd, [Xn|SP, #offS]!" , "op": "00111000|110|offS:9|11|Rn|Rd"},
+ {"inst": "ldrsb Xd, [Xn|SP, #offS]!" , "op": "00111000|100|offS:9|11|Rn|Rd"},
+ {"inst": "ldrsb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
+ {"inst": "ldrsb Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
+ {"inst": "ldrsh Wd, [Xn|SP, #offZ*2]" , "op": "01111001|11|offZ:12|Rn|Rd"},
+ {"inst": "ldrsh Xd, [Xn|SP, #offZ*2]" , "op": "01111001|10|offZ:12|Rn|Rd"},
+ {"inst": "ldrsh Wd, [Xn|SP, #offS*2]@" , "op": "01111000|110|offS:9|01|Rn|Rd"},
+ {"inst": "ldrsh Xd, [Xn|SP, #offS*2]@" , "op": "01111000|100|offS:9|01|Rn|Rd"},
+ {"inst": "ldrsh Wd, [Xn|SP, #offS*2]!" , "op": "01111000|110|offS:9|11|Rn|Rd"},
+ {"inst": "ldrsh Xd, [Xn|SP, #offS*2]!" , "op": "01111000|100|offS:9|11|Rn|Rd"},
+ {"inst": "ldrsh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
+ {"inst": "ldrsh Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
+ {"inst": "ldrsw Xd, [Xn|SP, #offZ*4]" , "op": "10111001|10|offZ:12|Rn|Rd"},
+ {"inst": "ldrsw Xd, [Xn|SP, #offS*4]@" , "op": "10111000|100|offS:9|01|Rn|Rd"},
+ {"inst": "ldrsw Xd, [Xn|SP, #offS*4]!" , "op": "10111000|100|offS:9|11|Rn|Rd"},
+ {"inst": "ldrsw Xd, [PC, #offS*4]" , "op": "10011000|offS:19|Rd"},
+ {"inst": "ldrsw Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRW(iop, n)"},
+ {"inst": "ldtr Wd, [Xn|SP, #offS]" , "op": "10111000|010|offS:9|10|Rn|Rd"},
+ {"inst": "ldtr Xd, [Xn|SP, #offS]" , "op": "11111000|010|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrb Wd, [Xn|SP, #offS]" , "op": "00111000|010|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrh Wd, [Xn|SP, #offS]" , "op": "01111000|010|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrsb Wd, [Xn|SP, #offS]" , "op": "00111000|100|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrsb Xd, [Xn|SP, #offS]" , "op": "00111000|110|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrsh Wd, [Xn|SP, #offS]" , "op": "01111000|100|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrsh Xd, [Xn|SP, #offS]" , "op": "01111000|110|offS:9|10|Rn|Rd"},
+ {"inst": "ldtrsw Xd, [Xn|SP, #offS]" , "op": "10111000|100|offS:9|10|Rn|Rd"},
+ {"inst": "ldur Wd, [Xn|SP, #offS]" , "op": "10111000|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldur Xd, [Xn|SP, #offS]" , "op": "11111000|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldurb Wd, [Xn|SP, #offS]" , "op": "00111000|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldurh Wd, [Xn|SP, #offS]" , "op": "01111000|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldursb Wd, [Xn|SP, #offS]" , "op": "00111000|100|offS:9|00|Rn|Rd"},
+ {"inst": "ldursb Xd, [Xn|SP, #offS]" , "op": "00111000|110|offS:9|00|Rn|Rd"},
+ {"inst": "ldursh Wd, [Xn|SP, #offS]" , "op": "01111000|100|offS:9|00|Rn|Rd"},
+ {"inst": "ldursh Xd, [Xn|SP, #offS]" , "op": "01111000|110|offS:9|00|Rn|Rd"},
+ {"inst": "ldursw Xd, [Xn|SP, #offS]" , "op": "10111000|100|offS:9|00|Rn|Rd"},
+ {"inst": "ldxp Wd, Wd2, [Xn|SP, #offS*4]" , "op": "10001000|011|11111|0|Rd2|Rn|Rd"},
+ {"inst": "ldxp Xd, Xd2, [Xn|SP, #offS*8]" , "op": "11001000|011|11111|0|Rd2|Rn|Rd"},
+ {"inst": "ldxr Wd, [Xn|SP]" , "op": "10001000|010|11111|0|11111|Rn|Rd"},
+ {"inst": "ldxr Xd, [Xn|SP]" , "op": "11001000|010|11111|0|11111|Rn|Rd"},
+ {"inst": "ldxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|0|11111|Rn|Rd"},
+ {"inst": "ldxrh Wd, [Xn|SP]" , "op": "01001000|010|11111|0|11111|Rn|Rd"},
+ {"inst": "lsl|lslv Wd, Wn, Wm" , "op": "00011010|110|Rm|001000|Rn|Rd"},
+ {"inst": "lsl|lslv Xd, Xn, Xm" , "op": "10011010|110|Rm|001000|Rn|Rd"},
+ {"inst": "lsl Wd, Wn, #n" , "op": "01010011|00|immr:6|imms:6|Rn|Rd"},
+ {"inst": "lsl Xd, Xn, #n" , "op": "11010011|01|immr:6|imms:6|Rn|Rd"},
+ {"inst": "lsr|lsrv Wd, Wn, Wm" , "op": "00011010|110|Rm|001001|Rn|Rd"},
+ {"inst": "lsr|lsrv Xd, Xn, Xm" , "op": "10011010|110|Rm|001001|Rn|Rd"},
+ {"inst": "lsr Wd, Wn, #n" , "op": "01010011|00|immr:6|011111|Rn|Rd"},
+ {"inst": "lsr Xd, Xn, #n" , "op": "11010011|01|immr:6|111111|Rn|Rd"},
+ {"inst": "madd Wd, Wn, Wm, Wa" , "op": "00011011|000|Rm|0|Ra|Rn|Rd"},
+ {"inst": "madd Xd, Xn, Xm, Xa" , "op": "10011011|000|Rm|0|Ra|Rn|Rd"},
+ {"inst": "mneg Wd, Wn, Wm" , "op": "00011011|000|Rm|1|11111|Rn|Rd"},
+ {"inst": "mneg Xd, Xn, Xm" , "op": "10011011|000|Rm|1|11111|Rn|Rd"},
+ {"inst": "mov Wd, Wm" , "op": "00101010|000|Rm|0|00000|11111|Rd"},
+ {"inst": "mov Xd, Xm" , "op": "10101010|000|Rm|0|00000|11111|Rd"},
+ {"inst": "mov Wd|WSP, Wn|WSP" , "op": "00010001|000|00000|0|00000|Rn|Rd"},
+ {"inst": "mov Xd|SP, Xn|SP" , "op": "10010001|000|00000|0|00000|Rn|Rd"},
+ {"inst": "mov Wd, #imm" , "op": "01010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, 0, 0)"},
+ {"inst": "mov Xd, #imm" , "op": "11010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, 0, 1)"},
+ {"inst": "mov Wd, #imm" , "op": "00010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, 0, 0)"},
+ {"inst": "mov Xd, #imm" , "op": "10010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, 0, 1)"},
+ {"inst": "mov Wd|WSP, #log_imm" , "op": "00110010|00|immr:6|imms:6|11111|Rd" , "imm": "ImmLogical(log_imm, 0)"},
+ {"inst": "mov Xd|SP, #log_imm" , "op": "10110010|01|immr:6|imms:6|11111|Rd" , "imm": "ImmLogical(log_imm, 1)"},
+ {"inst": "movk Wd, #imm, {lsl #n}" , "op": "01110010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 0)"},
+ {"inst": "movk Xd, #imm, {lsl #n}" , "op": "11110010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 1)"},
+ {"inst": "movn Wd, #imm, {lsl #n}" , "op": "00010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, n, 0)"},
+ {"inst": "movn Xd, #imm, {lsl #n}" , "op": "10010010|1|hw:2|imm:16|Rd" , "imm": "ImmWideInv(imm, n, 1)"},
+ {"inst": "movz Wd, #imm, {lsl #n}" , "op": "01010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 0)"},
+ {"inst": "movz Xd, #imm, {lsl #n}" , "op": "11010010|1|hw:2|imm:16|Rd" , "imm": "ImmWide(imm, n, 1)"},
+ {"inst": "mrs Xd, #sysreg" , "op": "11010101|001|1|sysreg:15|Rd"},
+ {"inst": "msr #sysreg, Xs" , "op": "11010101|000|1|sysreg:15|Rs"},
+ {"inst": "msr #pstatefield, #imm" , "op": "11010101|000|00|op1:3|0100|imm:4|op2:3|11111" , "imm": "ImmMSR(pstatefield)"},
+ {"inst": "msub Wd, Wn, Wm, Wa" , "op": "00011011|000|Rm|1|Ra|Rn|Rd"},
+ {"inst": "msub Xd, Xn, Xm, Xa" , "op": "10011011|000|Rm|1|Ra|Rn|Rd"},
+ {"inst": "mul Wd, Wn, Wm" , "op": "00011011|000|Rm|0|11111|Rn|Rd"},
+ {"inst": "mul Xd, Xn, Xm" , "op": "10011011|000|Rm|0|11111|Rn|Rd"},
+ {"inst": "mvn Wd, Wn, {sop #n}" , "op": "X0101010|sop|1|Rn|n:6|Rn|Rd"},
+ {"inst": "mvn Xd, Xn, {sop #n}" , "op": "X0101010|sop|1|Rn|n:6|Rn|Rd"},
+ {"inst": "neg Wd, Wm, {lsl|lsr|asr #n}" , "op": "01001011|sop:2|0|Rm|n:6|11111|Rd"},
+ {"inst": "neg Xd, Xm, {lsl|lsr|asr #n}" , "op": "11001011|sop:2|0|Rm|n:6|11111|Rd"},
+ {"inst": "negs Wd, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|11111|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "negs Xd, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|11111|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ngc Wd, Wm" , "op": "01011010|000|Rm|0|00000|11111|Rd" , "io": "C=R"},
+ {"inst": "ngc Xd, Xm" , "op": "11011010|000|Rm|0|00000|11111|Rd" , "io": "C=R"},
+ {"inst": "ngcs Wd, Wm" , "op": "01111010|000|Rm|0|00000|11111|Rd" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "ngcs Xd, Xm" , "op": "11111010|000|Rm|0|00000|11111|Rd" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "nop" , "op": "11010101|00|000011|0010|0000|000|11111"},
+ {"inst": "orn Wd, Wn, Wm, {sop #n}" , "op": "00101010|sop:2|1|Rm|n:6|Rn|Rd"},
+ {"inst": "orn Xd, Xn, Xm, {sop #n}" , "op": "10101010|sop:2|1|Rm|n:6|Rn|Rd"},
+ {"inst": "orr Wd, Wn, Wm, {sop #n}" , "op": "00101010|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "orr Xd, Xn, Xm, {sop #n}" , "op": "10101010|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "orr Wd|WSP, Wn, #log_imm" , "op": "00110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 0)"},
+ {"inst": "orr Xd|SP, Xn, #log_imm" , "op": "10110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 1)"},
+ {"inst": "prfm #prf_op, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*8}]" , "op": "11111000|101|Rm|option:3|n:1|10|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
+ {"inst": "prfm #prf_op, [Xn|SP, #offZ]" , "op": "11111001|10|offZ:12|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
+ {"inst": "prfm #prf_op, [PC, #offS*4]" , "op": "11011000|offS:19|prf_op:5" , "imm": "ImmPRF(prf_op)"},
+ {"inst": "prfum #prf_op, [Xn|SP, #offS]" , "op": "11111000|100|offS:9|00|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
+ {"inst": "pssbb" , "op": "11010101|000|00011|0011|0100|100|11111"},
+ {"inst": "rbit Wd, Wn" , "op": "01011010|110|00000|0|00000|Rn|Rd"},
+ {"inst": "rbit Xd, Xn" , "op": "11011010|110|00000|0|00000|Rn|Rd"},
+ {"inst": "ret Xn" , "op": "11010100|010|11111|0|00000|Rn|00000" , "control": "return"},
+ {"inst": "rev Wd, Wn" , "op": "01011010|110|00000|0|00010|Rn|Rd"},
+ {"inst": "rev|rev64 Xd, Xn" , "op": "11011010|110|00000|0|00011|Rn|Rd"},
+ {"inst": "rev16 Wd, Wn" , "op": "01011010|110|00000|0|00001|Rn|Rd"},
+ {"inst": "rev16 Xd, Xn" , "op": "11011010|110|00000|0|00001|Rn|Rd"},
+ {"inst": "rev32 Xd, Xn" , "op": "11011010|110|00000|0|00010|Rn|Rd"},
+ {"inst": "ror|rorv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|01011|Rn|Rd"},
+ {"inst": "ror|rorv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|01011|Rn|Rd"},
+ {"inst": "ror Wd, Wn, #n" , "op": "00010011|100|Rn|n:6|Rn|Rd"},
+ {"inst": "ror Xd, Xn, #n" , "op": "10010011|111|Rn|n:6|Rn|Rd"},
+ {"inst": "sbc Wd, Wn, Wm" , "op": "01011010|000|Rm|0|00000|Rn|Rd" , "io": "C=R"},
+ {"inst": "sbc Xd, Xn, Xm" , "op": "11011010|000|Rm|0|00000|Rn|Rd" , "io": "C=R"},
+ {"inst": "sbcs Wd, Wn, Wm" , "op": "01111010|000|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "sbcs Xd, Xn, Xm" , "op": "11111010|000|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=X V=W"},
+ {"inst": "sbfiz Wd, Wn, #lsb, #width" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 0)"},
+ {"inst": "sbfiz Xd, Xn, #lsb, #width" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 1)"},
+ {"inst": "sbfm Wd, Wn, #immr, #imms" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 0)"},
+ {"inst": "sbfm Xd, Xn, #immr, #imms" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 1)"},
+ {"inst": "sbfx Wd, Wn, #lsb, #width" , "op": "00010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 0)"},
+ {"inst": "sbfx Xd, Xn, #lsb, #width" , "op": "10010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 1)"},
+ {"inst": "sdiv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|00011|Rn|Rd"},
+ {"inst": "sdiv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|00011|Rn|Rd"},
+ {"inst": "sev" , "op": "11010101|000|00011|0010|0000|100|11111"},
+ {"inst": "sevl" , "op": "11010101|000|00011|0010|0000|101|11111"},
+ {"inst": "smaddl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|0|Ra|Rn|Rd"},
+ {"inst": "smc #immZ" , "op": "11010100|000|immZ:16|00011"},
+ {"inst": "smnegl Xd, Wn, Wm" , "op": "10011011|001|Rm|1|11111|Rn|Rd"},
+ {"inst": "smsubl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|1|Ra|Rn|Rd"},
+ {"inst": "smulh Xd, Xn, Xm" , "op": "10011011|010|Rm|0|11111|Rn|Rd"},
+ {"inst": "smull Xd, Wn, Wm" , "op": "10011011|001|Rm|0|11111|Rn|Rd"},
+ {"inst": "ssbb" , "op": "11010101|000|00011|0011|0000|100|11111"},
+ {"inst": "stlr Ws, [Xn|SP]" , "op": "10001000|100|11111|1|11111|Rn|Rs"},
+ {"inst": "stlr Xs, [Xn|SP]" , "op": "11001000|100|11111|1|11111|Rn|Rs"},
+ {"inst": "stlrb Ws, [Xn|SP]" , "op": "00001000|100|11111|1|11111|Rn|Rs"},
+ {"inst": "stlrh Ws, [Xn|SP]" , "op": "01001000|100|11111|1|11111|Rn|Rs"},
+ {"inst": "stlxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|1|Rs2|Rn|Rs"},
+ {"inst": "stlxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|1|Rs2|Rn|Rs"},
+ {"inst": "stlxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|1|11111|Rn|Rs"},
+ {"inst": "stlxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|1|11111|Rn|Rs"},
+ {"inst": "stlxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|1|11111|Rn|Rs"},
+ {"inst": "stlxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|1|11111|Rn|Rs"},
+ {"inst": "stnp Ws, Ws2, [Xn|SP, #offS*4]" , "op": "00101000|00|offS:7|Rs2|Rn|Rs"},
+ {"inst": "stnp Xs, Xs2, [Xn|SP, #offS*8]" , "op": "10101000|00|offS:7|Rs2|Rn|Rs"},
+ {"inst": "stp Ws, Ws2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010100|!post|W|0|offS:7|Rs2|Rn|Rs"},
+ {"inst": "stp Xs, Xs2, [Xn|SP, #offS*8]{@}{!}" , "op": "1010100|!post|W|0|offS:7|Rs2|Rn|Rs"},
+ {"inst": "str Ws, [Xn|SP, #offZ*4]" , "op": "10111001|00|offZ:12|Rn|Rs"},
+ {"inst": "str Xs, [Xn|SP, #offZ*8]" , "op": "11111001|00|offZ:12|Rn|Rs"},
+ {"inst": "str Ws, [Xn|SP, #offS*4]@" , "op": "10111000|000|offS:9|01|Rn|Rs"},
+ {"inst": "str Xs, [Xn|SP, #offS*8]@" , "op": "11111000|000|offS:9|01|Rn|Rs"},
+ {"inst": "str Ws, [Xn|SP, #offS*4]!" , "op": "10111000|000|offS:9|11|Rn|Rs"},
+ {"inst": "str Xs, [Xn|SP, #offS*8]!" , "op": "11111000|000|offS:9|11|Rn|Rs"},
+ {"inst": "str Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"},
+ {"inst": "str Xs, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"},
+ {"inst": "strb Ws, [Xn|SP, #offZ]" , "op": "00111001|00|offZ:12|Rn|Rs"},
+ {"inst": "strb Ws, [Xn|SP, #offS]@" , "op": "00111000|000|offS:9|01|Rn|Rs"},
+ {"inst": "strb Ws, [Xn|SP, #offS]!" , "op": "00111000|000|offS:9|11|Rn|Rs"},
+ {"inst": "strb Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRB_STRB(iop, n)"},
+ {"inst": "strh Ws, [Xn|SP, #offZ*2]" , "op": "01111001|00|offZ:12|Rn|Rs"},
+ {"inst": "strh Ws, [Xn|SP, #offS*2]@" , "op": "01111000|000|offS:9|01|Rn|Rs"},
+ {"inst": "strh Ws, [Xn|SP, #offS*2]!" , "op": "01111000|000|offS:9|11|Rn|Rs"},
+ {"inst": "strh Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRH_STRH(iop, n)"},
+ {"inst": "sttr Ws, [Xn|SP, #offS]" , "op": "10111000|000|offS:9|10|Rn|Rs"},
+ {"inst": "sttr Xs, [Xn|SP, #offS]" , "op": "11111000|000|offS:9|10|Rn|Rs"},
+ {"inst": "sttrb Ws, [Xn|SP, #offS]" , "op": "00111000|000|offS:9|10|Rn|Rs"},
+ {"inst": "sttrh Ws, [Xn|SP, #offS]" , "op": "01111000|000|offS:9|10|Rn|Rs"},
+ {"inst": "stur Ws, [Xn|SP, #offS]" , "op": "10111000|000|offS:9|00|Rn|Rs"},
+ {"inst": "stur Xs, [Xn|SP, #offS]" , "op": "11111000|000|offS:9|00|Rn|Rs"},
+ {"inst": "sturb Ws, [Xn|SP, #offS]" , "op": "00111000|000|offS:9|00|Rn|Rs"},
+ {"inst": "sturh Ws, [Xn|SP, #offS]" , "op": "01111000|000|offS:9|00|Rn|Rs"},
+ {"inst": "stxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|0|Rs2|Rn|Rs"},
+ {"inst": "stxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|0|Rs2|Rn|Rs"},
+ {"inst": "stxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|0|11111|Rn|Rs"},
+ {"inst": "stxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|0|11111|Rn|Rs"},
+ {"inst": "stxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|0|11111|Rn|Rs"},
+ {"inst": "stxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|0|11111|Rn|Rs"},
+ {"inst": "sub Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "01001011|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "sub Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "11001011|sop:2|0|Rm|n:6|Rn|Rd"},
+ {"inst": "sub Wd|WSP, Wn|WSP, Wm, {extend #n}" , "op": "01001011|00|1|Rm|option:3|n:3|Rn|Rd"},
+ {"inst": "sub Xd|SP, Xn|SP, Rm, {extend #n}" , "op": "11001011|00|1|Rm|option:3|n:3|Rn|Rd"},
+ {"inst": "sub Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01010001|0|n:1|immZ:12|Rn|Rd"},
+ {"inst": "sub Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11010001|0|n:1|immZ:12|Rn|Rd"},
+ {"inst": "subs Wd, Wn, Wm, {lsl|lsr|asr #n}" , "op": "01101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subs Xd, Xn, Xm, {lsl|lsr|asr #n}" , "op": "11101011|sop:2|0|Rm|n:6|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subs Wd, Wn|WSP, Wm, {extend #n}" , "op": "01101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subs Xd, Xn|SP, Rm, {extend #n}" , "op": "11101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subs Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "subs Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "svc #immZ" , "op": "11010100|000|immZ:16|00001"},
+ {"inst": "sxtb Wd, Wn" , "op": "00010011|000|00000|0|00111|Rn|Rd"},
+ {"inst": "sxtb Xd, Wn" , "op": "10010011|010|00000|0|00111|Rn|Rd"},
+ {"inst": "sxth Wd, Wn" , "op": "00010011|000|00000|0|01111|Rn|Rd"},
+ {"inst": "sxth Xd, Wn" , "op": "10010011|010|00000|0|01111|Rn|Rd"},
+ {"inst": "sxtw Xd, Wn" , "op": "10010011|010|00000|0|11111|Rn|Rd"},
+ {"inst": "sys #op1, #Cn, #Cm, #op2" , "op": "11010101|000|01|op1:3|CRn|CRm|op2:3|11111"},
+ {"inst": "sys #op1, #Cn, #Cm, #op2, Xt" , "op": "11010101|000|01|op1:3|CRn|CRm|op2:3|Rt"},
+ {"inst": "sysl Xd, #op1, #Cn, #Cm, #op2" , "op": "11010101|001|01|op1:3|CRn|CRm|op2:3|Rd"},
+ {"inst": "tbnz Wt, #imm, #relS*4" , "op": "00110111|imm:5|relS:14|Rt"},
+ {"inst": "tbnz Xt, #imm, #relS*4" , "op": "imm:1|0110111|imm:5|relS:14|Rt"},
+ {"inst": "tbz Wt, #imm, #relS*4" , "op": "00110110|imm:5|relS:14|Rt"},
+ {"inst": "tbz Xt, #imm, #relS*4" , "op": "imm:1|0110110|imm:5|relS:14|Rt"},
+ {"inst": "tlbi #tlbi_op" , "op": "11010101|00|001|op1:3|1000|CRm|op2:3|11111" , "imm": "ImmTLBI(tlbi_op)"},
+ {"inst": "tlbi #tlbi_op, Xt" , "op": "11010101|00|001|op1:3|1000|CRm|op2:3|Rt" , "imm": "ImmTLBI(tlbi_op)"},
+ {"inst": "tst Wn, Wm, {sop #n}" , "op": "01101010|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "tst Xn, Xm, {sop #n}" , "op": "11101010|sop:2|0|Rm|n:6|Rn|11111" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "tst Wn, #imm" , "op": "01110010|0|imm:13|Rn|11111" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 0)"},
+ {"inst": "tst Xn, #imm" , "op": "11110010|0|imm:13|Rn|11111" , "io": "N=W Z=W C=W V=W", "imm": "LogicalImm(imm, 1)"},
+ {"inst": "ubfiz Wd, Wn, #lsb, #width" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 0)"},
+ {"inst": "ubfiz Xd, Xn, #lsb, #width" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFIZ(lsb, width, 1)"},
+ {"inst": "ubfm Wd, Wn, #immr, #imms" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 0)"},
+ {"inst": "ubfm Xd, Xn, #immr, #imms" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFM(immr, imms, 1)"},
+ {"inst": "ubfx Wd, Wn, #lsb, #width" , "op": "01010011|00|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 0)"},
+ {"inst": "ubfx Xd, Xn, #lsb, #width" , "op": "11010011|01|immr:6|imms:6|Rn|Rd" , "imm": "ImmBFX(lsb, width, 1)"},
+ {"inst": "udf #imm" , "op": "00000000|000|00000|imm:16"},
+ {"inst": "udiv Wd, Wn, Wm" , "op": "00011010|110|Rm|0|00010|Rn|Rd"},
+ {"inst": "udiv Xd, Xn, Xm" , "op": "10011010|110|Rm|0|00010|Rn|Rd"},
+ {"inst": "umaddl Xd, Wn, Wm, Xa" , "op": "10011011|101|Rm|0|Ra|Rn|Rd"},
+ {"inst": "umnegl Xd, Wn, Wm" , "op": "10011011|101|Rm|1|11111|Rn|Rd"},
+ {"inst": "umsubl Xd, Wn, Wm, Xa" , "op": "10011011|101|Rm|1|Ra|Rn|Rd"},
+ {"inst": "umulh Xd, Xn, Xm" , "op": "10011011|110|Rm|0|11111|Rn|Rd"},
+ {"inst": "umull Xd, Wn, Wm" , "op": "10011011|101|Rm|0|11111|Rn|Rd"},
+ {"inst": "uxtb Wd, Wn" , "op": "01010011|000|00000|0|00111|Rn|Rd"},
+ {"inst": "uxth Wd, Wn" , "op": "01010011|000|00000|0|01111|Rn|Rd"},
+ {"inst": "wfe" , "op": "11010101|000|00011|0010|0000|010|11111"},
+ {"inst": "wfi" , "op": "11010101|000|00011|0010|0000|011|11111"},
+ {"inst": "yield" , "op": "11010101|000|00011|0010|0000|001|11111"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "BRBE", "data": [
+ {"inst": "brb #brb_op" , "op": "11010101|000|01001|0111|0010|op2:3|11111" , "imm": "ImmBRB(beb_op)"},
+ {"inst": "brb #brb_op, Xt" , "op": "11010101|000|01001|0111|0010|op2:3|Rt" , "imm": "ImmBRB(beb_op)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "BTI", "data": [
+ {"inst": "bti {#targets}" , "op": "11010101|000|00011|0010|0100|op2:3|11111" , "imm": "ImmBTI(targets)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CHK", "data": [
+ {"inst": "chkfeat" , "op": "11010101|000|00011|0010|0101|000|11111"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLRBHB", "data": [
+ {"inst": "clrbhb" , "op": "11010101|000|00011|0010|0010|110|11111"}
+ ]},
+
+ {"category": "GP", "ext": "CPA", "data": [
+ {"inst": "addpt Xd|SP, Xn|SP, Xm, {lsl #n}" , "op": "10011010|000|Rm|001|n:3|Rn|Rd"},
+ {"inst": "maddpt Xd, Xn, Xm, Xa" , "op": "10011011|011|Rm|0|Ra|Rn|Rd"},
+ {"inst": "msubpt Xd, Xn, Xm, Xa" , "op": "10011011|011|Rm|1|Ra|Rn|Rd"},
+ {"inst": "subpt Xd|SP, Xn|SP, Xm, {lsl #n}" , "op": "11011010|000|Rm|001|n:3|Rn|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [
+ {"inst": "crc32b Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10000|Rn|Rd"},
+ {"inst": "crc32h Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10001|Rn|Rd"},
+ {"inst": "crc32w Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10010|Rn|Rd"},
+ {"inst": "crc32x Xd, Xn, Xm" , "op": "10011010|110|Rm|0|10011|Rn|Rd"},
+
+ {"inst": "crc32cb Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10100|Rn|Rd"},
+ {"inst": "crc32ch Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10101|Rn|Rd"},
+ {"inst": "crc32cw Wd, Wn, Wm" , "op": "00011010|110|Rm|0|10110|Rn|Rd"},
+ {"inst": "crc32cx Xd, Xn, Xm" , "op": "10011010|110|Rm|0|10111|Rn|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CSSC", "data": [
+ {"inst": "abs Wd, Wn" , "op": "01011010|110|00000|0|01000|Rn|Rd"},
+ {"inst": "abs Xd, Xn" , "op": "11011010|110|00000|0|01000|Rn|Rd"},
+ {"inst": "cnt Wd, Wn" , "op": "01011010|110|00000|0|00111|Rn|Rd"},
+ {"inst": "cnt Xd, Xn" , "op": "11011010|110|00000|0|00111|Rn|Rd"},
+ {"inst": "ctz Wd, Wn" , "op": "01011010|110|00000|0|00110|Rn|Rd"},
+ {"inst": "ctz Xd, Xn" , "op": "11011010|110|00000|0|00110|Rn|Rd"},
+ {"inst": "smax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11000|Rn|Rd"},
+ {"inst": "smax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11000|Rn|Rd"},
+ {"inst": "smax Wd, Wn, #immS" , "op": "00010001|110|000|immS:8|Rn|Rd"},
+ {"inst": "smax Xd, Xn, #immS" , "op": "10010001|110|000|immS:8|Rn|Rd"},
+ {"inst": "smin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11010|Rn|Rd"},
+ {"inst": "smin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11010|Rn|Rd"},
+ {"inst": "smin Wd, Wn, #immS" , "op": "00010001|110|010|immS:8|Rn|Rd"},
+ {"inst": "smin Xd, Xn, #immS" , "op": "10010001|110|010|immS:8|Rn|Rd"},
+ {"inst": "umax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11001|Rn|Rd"},
+ {"inst": "umax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11001|Rn|Rd"},
+ {"inst": "umax Wd, Wn, #immZ" , "op": "00010001|110|001|immZ:8|Rn|Rd"},
+ {"inst": "umax Xd, Xn, #immZ" , "op": "10010001|110|001|immZ:8|Rn|Rd"},
+ {"inst": "umin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11011|Rn|Rd"},
+ {"inst": "umin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11011|Rn|Rd"},
+ {"inst": "umin Wd, Wn, #immZ" , "op": "00010001|110|011|immZ:8|Rn|Rd"},
+ {"inst": "umin Xd, Xn, #immZ" , "op": "10010001|110|011|immZ:8|Rn|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "D128", "data": [
+ {"inst": "tlbip #tlbip_op, 2x{Xt}+" , "op": "11010101|010|01|op1:3|CRn|CRm|op2:3|Rt" , "imm": "ImmTLBIP(tlbip_op)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "DGH", "data": [
+ {"inst": "dgh" , "op": "11010101|000|00|011|0010|0000|110|11111"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "FLAGM", "data": [
+ {"inst": "cfinv" , "op": "11010101|000|00000|0100|0000|000|11111" , "io": "C=X"},
+ {"inst": "rmif Xn, #shift, #mask" , "op": "10111010|000|shift:6|00001|Rn|0|mask:4" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "setf16 Wn" , "op": "00111010|000|00000|0|10010|Rn|01101" , "io": "N=W Z=W V=W"},
+ {"inst": "setf8 Wn" , "op": "00111010|000|00000|0|00010|Rn|01101" , "io": "N=W Z=W V=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "FLAGM2", "data": [
+ {"inst": "axflag" , "op": "11010101|000|00000|0100|0000|010|11111" , "io": "N=X Z=X C=X V=X"},
+ {"inst": "xaflag" , "op": "11010101|000|00000|0100|0000|001|11111" , "io": "N=X Z=X C=X V=X"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "GCS", "data": [
+ {"inst": "gcsb #dsync" , "op": "11010101|000|00011|0010|0010|011|11111"},
+ {"inst": "gcspopcx" , "op": "11010101|000|01000|0111|0111|101|11111"},
+ {"inst": "gcspopcx Xt" , "op": "11010101|000|01000|0111|0111|101|Rt"},
+ {"inst": "gcspopm Xt" , "op": "11010101|001|01011|0111|0111|001|Rt"},
+ {"inst": "gcspopx" , "op": "11010101|000|01000|0111|0111|110|11111"},
+ {"inst": "gcspopx Xt" , "op": "11010101|000|01000|0111|0111|110|Rt"},
+ {"inst": "gcspushm Xt" , "op": "11010101|000|01011|0111|0111|000|Rt"},
+ {"inst": "gcspushx" , "op": "11010101|000|01000|0111|0111|100|11111"},
+ {"inst": "gcspushx Xt" , "op": "11010101|000|01000|0111|0111|100|Rt"},
+ {"inst": "gcsss1 Xt" , "op": "11010101|000|01011|0111|0111|010|Rt"},
+ {"inst": "gcsss2 Xt" , "op": "11010101|001|01011|0111|0111|011|Rt"},
+ {"inst": "gcsstr Xs, [Xn|SP]" , "op": "11011001|000|11111|0|00011|Rn|Rs"},
+ {"inst": "gcssttr Xs, [Xn|SP]" , "op": "11011001|000|11111|0|00111|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "HBC", "data": [
+ {"inst": "bc.<cond> #relS*4" , "op": "01010100|relS:19|1|cond" , "control": "branch", "io": "N=R Z=R C=R V=R"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "ITE", "data": [
+ {"inst": "trcit Xt" , "op": "11010101|000|01011|0111|0010|111|Rt"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LOR", "data": [
+ {"inst": "ldlar Wd, [Xn|SP]" , "op": "10001000|110|11111|0|11111|Rn|Rd"},
+ {"inst": "ldlar Xd, [Xn|SP]" , "op": "11001000|110|11111|0|11111|Rn|Rd"},
+ {"inst": "ldlarb Wd, [Xn|SP]" , "op": "00001000|110|11111|0|11111|Rn|Rd"},
+ {"inst": "ldlarh Wd, [Xn|SP]" , "op": "01001000|110|11111|0|11111|Rn|Rd"},
+ {"inst": "stllr Ws, [Xn|SP]" , "op": "10001000|100|11111|0|11111|Rn|Rs"},
+ {"inst": "stllr Xs, [Xn|SP]" , "op": "11001000|100|11111|0|11111|Rn|Rs"},
+ {"inst": "stllrb Ws, [Xn|SP]" , "op": "00001000|100|11111|0|11111|Rn|Rs"},
+ {"inst": "stllrh Ws, [Xn|SP]" , "op": "01001000|100|11111|0|11111|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LRCPC", "data": [
+ {"inst": "ldapr Wd, [Xn|SP]" , "op": "10111000|101|11111|1|10000|Rn|Rd"},
+ {"inst": "ldapr Xd, [Xn|SP]" , "op": "11111000|101|11111|1|10000|Rn|Rd"},
+ {"inst": "ldaprb Wd, [Xn|SP]" , "op": "00111000|101|11111|1|10000|Rn|Rd"},
+ {"inst": "ldaprh Wd, [Xn|SP]" , "op": "01111000|101|11111|1|10000|Rn|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LRCPC2", "data": [
+ {"inst": "ldapur Wd, [Xn|SP, #offS]" , "op": "10011001|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldapur Xd, [Xn|SP, #offS]" , "op": "11011001|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldapurb Wd, [Xn|SP, #offS]" , "op": "00011001|010|offS:9|00|Rn|Rd"},
+ {"inst": "ldapurh Wd, [Xn|SP, #offS]" , "op": "01011001|010|offS:9|00|Rn|Rd"},
+
+ {"inst": "ldapursb Wd, [Xn|SP, #offS]" , "op": "00011001|110|offS:9|00|Rn|Rd"},
+ {"inst": "ldapursb Xd, [Xn|SP, #offS]" , "op": "00011001|100|offS:9|00|Rn|Rd"},
+ {"inst": "ldapursh Wd, [Xn|SP, #offS]" , "op": "01011001|110|offS:9|00|Rn|Rd"},
+ {"inst": "ldapursh Xd, [Xn|SP, #offS]" , "op": "01011001|100|offS:9|00|Rn|Rd"},
+ {"inst": "ldapursw Xd, [Xn|SP, #offS]" , "op": "10011001|100|offS:9|00|Rn|Rd"},
+
+ {"inst": "stlur Ws, [Xn|SP, #offS]" , "op": "10011001|000|offS:9|00|Rn|Rs"},
+ {"inst": "stlur Xs, [Xn|SP, #offS]" , "op": "11011001|000|offS:9|00|Rn|Rs"},
+ {"inst": "stlurb Ws, [Xn|SP, #offS]" , "op": "00011001|000|offS:9|00|Rn|Rs"},
+ {"inst": "stlurh Ws, [Xn|SP, #offS]" , "op": "01011001|000|offS:9|00|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LRCPC3", "data": [
+ {"inst": "ldiapp Wd, Wd2, [Xn|SP]" , "op": "10011001|010|Rd2|0|00110|Rn|Rd"},
+ {"inst": "ldiapp Wd, Wd2, [Xn|SP, #8]@" , "op": "10011001|010|Rd2|0|00010|Rn|Rd"},
+ {"inst": "ldiapp Xd, Xd2, [Xn|SP]" , "op": "11011001|010|Rd2|0|00110|Rn|Rd"},
+ {"inst": "ldiapp Xd, Xd2, [Xn|SP, #16]@" , "op": "11011001|010|Rd2|0|00010|Rn|Rd"},
+ {"inst": "stilp Ws, Ws2, [Xn|SP]" , "op": "10011001|000|Rs2|0|00110|Rn|Rs"},
+ {"inst": "stilp Ws, Ws2, [Xn|SP, #8]@" , "op": "10011001|000|Rs2|0|00010|Rn|Rs"},
+ {"inst": "stilp Xs, Xs2, [Xn|SP]" , "op": "11011001|000|Rs2|0|00110|Rn|Rs"},
+ {"inst": "stilp Xs, Xs2, [Xn|SP, #16]@" , "op": "11011001|000|Rs2|0|00010|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LS64", "data": [
+ {"inst": "ld64b 8x{Xd}+, [Xn|SP]" , "op": "11111000|001|11111|1|10100|Rn|Rd"},
+ {"inst": "st64b 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|11111|1|00100|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LS64_ACCDATA", "data": [
+ {"inst": "st64bv0 Rd, 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|Rd|1|01000|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LS64_V", "data": [
+ {"inst": "st64bv Rd, 8x{Xs}+, [Xn|SP]" , "op": "11111000|001|Rd|1|01100|Rn|Rs"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LSE", "data": [
+ {"inst": "cas Ws, Wd, [Xn|SP]" , "op": "10001000|001|Rs|0|11111|Rn|Rd"},
+ {"inst": "casa Ws, Wd, [Xn|SP]" , "op": "10001000|011|Rs|0|11111|Rn|Rd"},
+ {"inst": "casal Ws, Wd, [Xn|SP]" , "op": "10001000|011|Rs|1|11111|Rn|Rd"},
+ {"inst": "casl Ws, Wd, [Xn|SP]" , "op": "10001000|001|Rs|1|11111|Rn|Rd"},
+ {"inst": "cas Xs, Xd, [Xn|SP]" , "op": "11001000|001|Rs|0|11111|Rn|Rd"},
+ {"inst": "casa Xs, Xd, [Xn|SP]" , "op": "11001000|011|Rs|0|11111|Rn|Rd"},
+ {"inst": "casal Xs, Xd, [Xn|SP]" , "op": "11001000|011|Rs|1|11111|Rn|Rd"},
+ {"inst": "casl Xs, Xd, [Xn|SP]" , "op": "11001000|001|Rs|1|11111|Rn|Rd"},
+ {"inst": "casab Ws, Wd, [Xn|SP]" , "op": "00001000|111|Rs|0|11111|Rn|Rd"},
+ {"inst": "casalb Ws, Wd, [Xn|SP]" , "op": "00001000|111|Rs|1|11111|Rn|Rd"},
+ {"inst": "casb Ws, Wd, [Xn|SP]" , "op": "00001000|101|Rs|0|11111|Rn|Rd"},
+ {"inst": "caslb Ws, Wd, [Xn|SP]" , "op": "00001000|101|Rs|1|11111|Rn|Rd"},
+ {"inst": "casah Ws, Wd, [Xn|SP]" , "op": "01001000|111|Rs|0|11111|Rn|Rd"},
+ {"inst": "casalh Ws, Wd, [Xn|SP]" , "op": "01001000|111|Rs|1|11111|Rn|Rd"},
+ {"inst": "cash Ws, Wd, [Xn|SP]" , "op": "01001000|101|Rs|0|11111|Rn|Rd"},
+ {"inst": "caslh Ws, Wd, [Xn|SP]" , "op": "01001000|101|Rs|1|11111|Rn|Rd"},
+ {"inst": "casp 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|001|Rs|0|11111|Rn|Rd"},
+ {"inst": "caspa 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|011|Rs|0|11111|Rn|Rd"},
+ {"inst": "caspal 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|011|Rs|1|11111|Rn|Rd"},
+ {"inst": "caspl 2x{Ws}+, 2x{Wd}+, [Xn|SP]" , "op": "00001000|001|Rs|1|11111|Rn|Rd"},
+ {"inst": "casp 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|001|Rs|0|11111|Rn|Rd"},
+ {"inst": "caspa 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|011|Rs|0|11111|Rn|Rd"},
+ {"inst": "caspal 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|011|Rs|1|11111|Rn|Rd"},
+ {"inst": "caspl 2x{Xs}+, 2x{Xd}+, [Xn|SP]" , "op": "01001000|001|Rs|1|11111|Rn|Rd"},
+ {"inst": "ldadd Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldadda Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldadd Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldadda Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldaddlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|00000|Rn|Rd"},
+ {"inst": "ldclr Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclra Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclral Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclr Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclra Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclral Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclralb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclralh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldclrlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|00100|Rn|Rd"},
+ {"inst": "ldeor Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeora Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeoral Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeor Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeora Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeoral Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeoralb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeoralh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldeorlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|01000|Rn|Rd"},
+ {"inst": "ldset Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldseta Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldset Xs, Wd, [Xn|SP]" , "op": "11111000|001|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldseta Xs, Wd, [Xn|SP]" , "op": "11111000|101|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetal Xs, Wd, [Xn|SP]" , "op": "11111000|111|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetl Xs, Wd, [Xn|SP]" , "op": "11111000|011|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldseth Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsetlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|01100|Rn|Rd"},
+ {"inst": "ldsmax Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmax Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmaxlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|10000|Rn|Rd"},
+ {"inst": "ldsmin Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsmina Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsmin Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsmina Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldsminlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|10100|Rn|Rd"},
+ {"inst": "ldumax Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumax Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumaxlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|11000|Rn|Rd"},
+ {"inst": "ldumin Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|0|11100|Rn|Rd"},
+ {"inst": "ldumina Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|0|11100|Rn|Rd"},
+ {"inst": "ldumin Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|0|11100|Rn|Rd"},
+ {"inst": "ldumina Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminlb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminh Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|0|11100|Rn|Rd"},
+ {"inst": "lduminlh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|0|11100|Rn|Rd"},
+ {"inst": "stadd Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|00000|Rn|11111"},
+ {"inst": "stadda Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|00000|Rn|11111"},
+ {"inst": "staddal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|00000|Rn|11111"},
+ {"inst": "staddl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|00000|Rn|11111"},
+ {"inst": "stadd Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|00000|Rn|11111"},
+ {"inst": "stadda Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|00000|Rn|11111"},
+ {"inst": "staddal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|00000|Rn|11111"},
+ {"inst": "staddl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|00000|Rn|11111"},
+ {"inst": "staddb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|00000|Rn|11111"},
+ {"inst": "staddab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|00000|Rn|11111"},
+ {"inst": "staddalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|00000|Rn|11111"},
+ {"inst": "staddlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|00000|Rn|11111"},
+ {"inst": "staddh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|00000|Rn|11111"},
+ {"inst": "staddah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|00000|Rn|11111"},
+ {"inst": "staddalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|00000|Rn|11111"},
+ {"inst": "staddlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|00000|Rn|11111"},
+ {"inst": "stclr Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|00100|Rn|11111"},
+ {"inst": "stclra Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|00100|Rn|11111"},
+ {"inst": "stclral Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|00100|Rn|11111"},
+ {"inst": "stclr Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|00100|Rn|11111"},
+ {"inst": "stclra Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|00100|Rn|11111"},
+ {"inst": "stclral Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|00100|Rn|11111"},
+ {"inst": "stclralb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|00100|Rn|11111"},
+ {"inst": "stclralh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|00100|Rn|11111"},
+ {"inst": "stclrlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|00100|Rn|11111"},
+ {"inst": "steor Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|01000|Rn|11111"},
+ {"inst": "steora Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|01000|Rn|11111"},
+ {"inst": "steoral Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|01000|Rn|11111"},
+ {"inst": "steorl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|01000|Rn|11111"},
+ {"inst": "steor Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|01000|Rn|11111"},
+ {"inst": "steora Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|01000|Rn|11111"},
+ {"inst": "steoral Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|01000|Rn|11111"},
+ {"inst": "steorl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|01000|Rn|11111"},
+ {"inst": "steorb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|01000|Rn|11111"},
+ {"inst": "steorab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|01000|Rn|11111"},
+ {"inst": "steoralb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|01000|Rn|11111"},
+ {"inst": "steorlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|01000|Rn|11111"},
+ {"inst": "steorh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|01000|Rn|11111"},
+ {"inst": "steorah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|01000|Rn|11111"},
+ {"inst": "steoralh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|01000|Rn|11111"},
+ {"inst": "steorlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|01000|Rn|11111"},
+ {"inst": "stset Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|01100|Rn|11111"},
+ {"inst": "stseta Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|01100|Rn|11111"},
+ {"inst": "stset Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|01100|Rn|11111"},
+ {"inst": "stseta Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|01100|Rn|11111"},
+ {"inst": "stseth Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|01100|Rn|11111"},
+ {"inst": "stsetlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|01100|Rn|11111"},
+ {"inst": "stsmax Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxa Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmax Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxa Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmaxlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|10000|Rn|11111"},
+ {"inst": "stsmin Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|10100|Rn|11111"},
+ {"inst": "stsmina Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|10100|Rn|11111"},
+ {"inst": "stsmin Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|10100|Rn|11111"},
+ {"inst": "stsmina Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|10100|Rn|11111"},
+ {"inst": "stsminlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|10100|Rn|11111"},
+ {"inst": "stumax Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxa Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|11000|Rn|11111"},
+ {"inst": "stumax Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxa Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|11000|Rn|11111"},
+ {"inst": "stumaxlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|11000|Rn|11111"},
+ {"inst": "stumin Ws, [Xn|SP]" , "op": "10111000|001|Rs|0|11100|Rn|11111"},
+ {"inst": "stumina Ws, [Xn|SP]" , "op": "10111000|101|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminal Ws, [Xn|SP]" , "op": "10111000|111|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminl Ws, [Xn|SP]" , "op": "10111000|011|Rs|0|11100|Rn|11111"},
+ {"inst": "stumin Xs, [Xn|SP]" , "op": "11111000|001|Rs|0|11100|Rn|11111"},
+ {"inst": "stumina Xs, [Xn|SP]" , "op": "11111000|101|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminal Xs, [Xn|SP]" , "op": "11111000|111|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminl Xs, [Xn|SP]" , "op": "11111000|011|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminb Ws, [Xn|SP]" , "op": "00111000|001|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminab Ws, [Xn|SP]" , "op": "00111000|101|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminalb Ws, [Xn|SP]" , "op": "00111000|111|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminlb Ws, [Xn|SP]" , "op": "00111000|011|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminh Ws, [Xn|SP]" , "op": "01111000|001|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminah Ws, [Xn|SP]" , "op": "01111000|101|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminalh Ws, [Xn|SP]" , "op": "01111000|111|Rs|0|11100|Rn|11111"},
+ {"inst": "stuminlh Ws, [Xn|SP]" , "op": "01111000|011|Rs|0|11100|Rn|11111"},
+ {"inst": "swp Ws, Wd, [Xn|SP]" , "op": "10111000|001|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpa Ws, Wd, [Xn|SP]" , "op": "10111000|101|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpal Ws, Wd, [Xn|SP]" , "op": "10111000|111|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpl Ws, Wd, [Xn|SP]" , "op": "10111000|011|Rs|1|00000|Rn|Rd"},
+ {"inst": "swp Xs, Xd, [Xn|SP]" , "op": "11111000|001|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpa Xs, Xd, [Xn|SP]" , "op": "11111000|101|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpal Xs, Xd, [Xn|SP]" , "op": "11111000|111|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpl Xs, Xd, [Xn|SP]" , "op": "11111000|011|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpb Ws, Wd, [Xn|SP]" , "op": "00111000|001|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpab Ws, Wd, [Xn|SP]" , "op": "00111000|101|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpalb Ws, Wd, [Xn|SP]" , "op": "00111000|111|Rs|1|00000|Rn|Rd"},
+ {"inst": "swplb Ws, Wd, [Xn|SP]" , "op": "00111000|011|Rs|1|00000|Rn|Rd"},
+ {"inst": "swph Ws, Wd, [Xn|SP]" , "op": "01111000|001|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpah Ws, Wd, [Xn|SP]" , "op": "01111000|101|Rs|1|00000|Rn|Rd"},
+ {"inst": "swpalh Ws, Wd, [Xn|SP]" , "op": "01111000|111|Rs|1|00000|Rn|Rd"},
+ {"inst": "swplh Ws, Wd, [Xn|SP]" , "op": "01111000|011|Rs|1|00000|Rn|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MOPS", "data": [
+ {"inst": "cpyfe [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|00001|Rn|Rd"},
+ {"inst": "cpyfm [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|00001|Rn|Rd"},
+ {"inst": "cpyfp [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|00001|Rn|Rd"},
+ {"inst": "cpyfen [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|10001|Rn|Rd"},
+ {"inst": "cpyfmn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|10001|Rn|Rd"},
+ {"inst": "cpyfpn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|10001|Rn|Rd"},
+ {"inst": "cpyfern [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|00001|Rn|Rd"},
+ {"inst": "cpyfmrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|00001|Rn|Rd"},
+ {"inst": "cpyfprn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|00001|Rn|Rd"},
+ {"inst": "cpyfert [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyfmrt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyfprt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyfert [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyfmrt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyfprt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyfertn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|11001|Rn|Rd"},
+ {"inst": "cpyfmrtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|11001|Rn|Rd"},
+ {"inst": "cpyfprtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|11001|Rn|Rd"},
+ {"inst": "cpyfertrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|01001|Rn|Rd"},
+ {"inst": "cpyfmrtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|01001|Rn|Rd"},
+ {"inst": "cpyfprtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|01001|Rn|Rd"},
+ {"inst": "cpyfertwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|11001|Rn|Rd"},
+ {"inst": "cpyfmrtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|11001|Rn|Rd"},
+ {"inst": "cpyfprtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|11001|Rn|Rd"},
+ {"inst": "cpyfet [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|01101|Rn|Rd"},
+ {"inst": "cpyfmt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|01101|Rn|Rd"},
+ {"inst": "cpyfpt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|01101|Rn|Rd"},
+ {"inst": "cpyfetn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|11101|Rn|Rd"},
+ {"inst": "cpyfmtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|11101|Rn|Rd"},
+ {"inst": "cpyfptn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|11101|Rn|Rd"},
+ {"inst": "cpyfetrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|01101|Rn|Rd"},
+ {"inst": "cpyfmtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|01101|Rn|Rd"},
+ {"inst": "cpyfptrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|01101|Rn|Rd"},
+ {"inst": "cpyfetwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|11101|Rn|Rd"},
+ {"inst": "cpyfmtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|11101|Rn|Rd"},
+ {"inst": "cpyfptwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|11101|Rn|Rd"},
+ {"inst": "cpyfewn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|10001|Rn|Rd"},
+ {"inst": "cpyfmwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|10001|Rn|Rd"},
+ {"inst": "cpyfpwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|10001|Rn|Rd"},
+ {"inst": "cpyfewt [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|00101|Rn|Rd"},
+ {"inst": "cpyfmwt [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|00101|Rn|Rd"},
+ {"inst": "cpyfpwt [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|00101|Rn|Rd"},
+ {"inst": "cpyfewtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|10101|Rn|Rd"},
+ {"inst": "cpyfmwtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|10101|Rn|Rd"},
+ {"inst": "cpyfpwtn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|10101|Rn|Rd"},
+ {"inst": "cpyfewtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|1|00101|Rn|Rd"},
+ {"inst": "cpyfmwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|1|00101|Rn|Rd"},
+ {"inst": "cpyfpwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|1|00101|Rn|Rd"},
+ {"inst": "cpyfewtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|100|Rs|0|10101|Rn|Rd"},
+ {"inst": "cpyfmwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|010|Rs|0|10101|Rn|Rd"},
+ {"inst": "cpyfpwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011001|000|Rs|0|10101|Rn|Rd"},
+ {"inst": "cpye [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|00001|Rn|Rd"},
+ {"inst": "cpym [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|00001|Rn|Rd"},
+ {"inst": "cpyp [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|00001|Rn|Rd"},
+ {"inst": "cpyen [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|10001|Rn|Rd"},
+ {"inst": "cpymn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|10001|Rn|Rd"},
+ {"inst": "cpypn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|10001|Rn|Rd"},
+ {"inst": "cpyern [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|00001|Rn|Rd"},
+ {"inst": "cpymrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|00001|Rn|Rd"},
+ {"inst": "cpyprn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|00001|Rn|Rd"},
+ {"inst": "cpyert [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpymrt [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyprt [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|01001|Rn|Rd"},
+ {"inst": "cpyertn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|11001|Rn|Rd"},
+ {"inst": "cpymrtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|11001|Rn|Rd"},
+ {"inst": "cpyprtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|11001|Rn|Rd"},
+ {"inst": "cpyertrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|01001|Rn|Rd"},
+ {"inst": "cpymrtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|01001|Rn|Rd"},
+ {"inst": "cpyprtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|01001|Rn|Rd"},
+ {"inst": "cpyertwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|11001|Rn|Rd"},
+ {"inst": "cpymrtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|11001|Rn|Rd"},
+ {"inst": "cpyprtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|11001|Rn|Rd"},
+ {"inst": "cpyet [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|01101|Rn|Rd"},
+ {"inst": "cpymt [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|01101|Rn|Rd"},
+ {"inst": "cpypt [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|01101|Rn|Rd"},
+ {"inst": "cpyetn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|11101|Rn|Rd"},
+ {"inst": "cpymtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|11101|Rn|Rd"},
+ {"inst": "cpyptn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|11101|Rn|Rd"},
+ {"inst": "cpyetrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|01101|Rn|Rd"},
+ {"inst": "cpymtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|01101|Rn|Rd"},
+ {"inst": "cpyptrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|01101|Rn|Rd"},
+ {"inst": "cpyetwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|11101|Rn|Rd"},
+ {"inst": "cpymtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|11101|Rn|Rd"},
+ {"inst": "cpyptwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|11101|Rn|Rd"},
+ {"inst": "cpyewn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|10001|Rn|Rd"},
+ {"inst": "cpymwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|10001|Rn|Rd"},
+ {"inst": "cpypwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|10001|Rn|Rd"},
+ {"inst": "cpyewt [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|00101|Rn|Rd"},
+ {"inst": "cpymwt [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|00101|Rn|Rd"},
+ {"inst": "cpypwt [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|00101|Rn|Rd"},
+ {"inst": "cpyewtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|10101|Rn|Rd"},
+ {"inst": "cpymwtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|10101|Rn|Rd"},
+ {"inst": "cpypwtn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|10101|Rn|Rd"},
+ {"inst": "cpyewtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|1|00101|Rn|Rd"},
+ {"inst": "cpymwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|1|00101|Rn|Rd"},
+ {"inst": "cpypwtrn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|1|00101|Rn|Rd"},
+ {"inst": "cpyewtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|100|Rs|0|10101|Rn|Rd"},
+ {"inst": "cpymwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|010|Rs|0|10101|Rn|Rd"},
+ {"inst": "cpypwtwn [Xd]!, [Xs]!, Xn!" , "op": "00011101|000|Rs|0|10101|Rn|Rd"},
+ {"inst": "setge [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|00001|Rn|Rd"},
+ {"inst": "setgm [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|10001|Rn|Rd"},
+ {"inst": "setgp [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|00001|Rn|Rd"},
+ {"inst": "setgen [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|01001|Rn|Rd"},
+ {"inst": "setgmn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|11001|Rn|Rd"},
+ {"inst": "setgpn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|01001|Rn|Rd"},
+ {"inst": "setget [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|00101|Rn|Rd"},
+ {"inst": "setgmt [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|10101|Rn|Rd"},
+ {"inst": "setgpt [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|00101|Rn|Rd"},
+ {"inst": "setgetn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|1|01101|Rn|Rd"},
+ {"inst": "setgmtn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|11101|Rn|Rd"},
+ {"inst": "setgptn [Xd]!, Xn!, Xs" , "op": "00011101|110|Rs|0|01101|Rn|Rd"},
+ {"inst": "sete [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|00001|Rn|Rd"},
+ {"inst": "setm [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|10001|Rn|Rd"},
+ {"inst": "setp [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|00001|Rn|Rd"},
+ {"inst": "seten [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|01001|Rn|Rd"},
+ {"inst": "setmn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|11001|Rn|Rd"},
+ {"inst": "setpn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|01001|Rn|Rd"},
+ {"inst": "setet [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|00101|Rn|Rd"},
+ {"inst": "setmt [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|10101|Rn|Rd"},
+ {"inst": "setpt [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|00101|Rn|Rd"},
+ {"inst": "setetn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|1|01101|Rn|Rd"},
+ {"inst": "setmtn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|11101|Rn|Rd"},
+ {"inst": "setptn [Xd]!, Xn!, Xs" , "op": "00011001|110|Rs|0|01101|Rn|Rd"}
+ ]},
+
+ {"category": "GP MTE", "ext": "MTE", "data": [
+ {"inst": "addg Xd|SP, Xn|SP, #imm1, #imm2" , "op": "10010001|10|imm1:6|00|imm2:4|Rn|Rd"},
+ {"inst": "cmpp Xn|SP, Xm|SP" , "op": "10111010|110|Rm|000000|Rn|11111"},
+ {"inst": "gmi Xd, Xn|SP, Xm" , "op": "10011010|110|Rm|000101|Rn|Rd"},
+ {"inst": "irg Xd, Xn|SP, Xm" , "op": "10011010|110|Rm|000100|Rn|Rd"},
+ {"inst": "ldg Xd, [Xn|SP, #offS*16]" , "op": "11011001|011|offS:9|00|Rn|Rd"},
+ {"inst": "st2g Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|101|offS:9|!post|W|Rn|Rs"},
+ {"inst": "stg Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|001|offS:9|!post|W|Rn|Rs"},
+ {"inst": "stgp Xs, Xs2, [Xn|SP, #offS*16]{@}{!}" , "op": "0110100|!post|W|0|offS:7|Rs2|Rn|Rs"},
+ {"inst": "stz2g Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|111|offS:9|!post|W|Rn|Rs"},
+ {"inst": "stzg Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|011|offS:9|!post|W|Rn|Rs"},
+ {"inst": "subg Xd|SP, Xn|SP, #imm1, #imm2" , "op": "11010001|10|imm1:6|00|imm2:4|Rn|Rd"},
+ {"inst": "subp Xd, Xn|SP, Xm|SP" , "op": "10011010|110|Rm|0|00000|Rn|Rd"},
+ {"inst": "subps Xd, Xn|SP, Xm|SP" , "op": "10011010|110|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=W V=W"}
+ ]},
+
+ {"category": "GP MTE", "ext": "MTE2", "data": [
+ {"inst": "ldgm Xd, [Xn|SP]" , "op": "11011001|111|00000|0|00000|Rn|Rd"},
+ {"inst": "stgm Xs, [Xn|SP]" , "op": "11011001|101|00000|0|00000|Rn|Rs"},
+ {"inst": "stzgm Xs, [Xn|SP]" , "op": "11011001|001|00000|0|00000|Rn|Rs"}
+ ]},
+
+ {"category": "GP PAUTH", "ext": "PAUTH", "data": [
+ {"inst": "autda Xd, Xn|SP" , "op": "11011010|110|00001|000110|Rn|Rd"},
+ {"inst": "autdb Xd, Xn|SP" , "op": "11011010|110|00001|000111|Rn|Rd"},
+ {"inst": "autdza Xd" , "op": "11011010|110|00001|001110|11111|Rd"},
+ {"inst": "autdzb Xd" , "op": "11011010|110|00001|001111|11111|Rd"},
+ {"inst": "autia Xd, Xn|SP" , "op": "11011010|110|00001|000100|Rn|Rd"},
+ {"inst": "autia1716" , "op": "11010101|000|00011|0010|0001|100|11111"},
+ {"inst": "autiasp" , "op": "11010101|000|00011|0010|0011|101|11111"},
+ {"inst": "autiaz" , "op": "11010101|000|00011|0010|0011|100|11111"},
+ {"inst": "autib Xd, Xn|SP" , "op": "11011010|110|00001|000101|Rn|Rd"},
+ {"inst": "autib1716" , "op": "11010101|000|00011|0010|0001|110|11111"},
+ {"inst": "autibsp" , "op": "11010101|000|00011|0010|0011|111|11111"},
+ {"inst": "autibz" , "op": "11010101|000|00011|0010|0011|110|11111"},
+ {"inst": "autiza Xd" , "op": "11011010|110|00001|001100|11111|Rd"},
+ {"inst": "autizb Xd" , "op": "11011010|110|00001|001101|11111|Rd"},
+ {"inst": "blraa Xn, Xm|SP" , "op": "11010111|001|11111|0000|10|Rn|Rm" , "control": "call"},
+ {"inst": "blraaz Xn" , "op": "11010110|001|11111|0000|10|Rn|11111" , "control": "call"},
+ {"inst": "blrab Xn, Xm|SP" , "op": "11010111|001|11111|0000|11|Rn|Rm" , "control": "call"},
+ {"inst": "blrabz Xn" , "op": "11010110|001|11111|0000|11|Rn|11111" , "control": "call"},
+ {"inst": "braa Xn, Xm|SP" , "op": "11010111|000|11111|0000|10|Rn|Rm" , "control": "call"},
+ {"inst": "braaz Xn" , "op": "11010110|000|11111|0000|10|Rn|11111" , "control": "call"},
+ {"inst": "brab Xn, Xm|SP" , "op": "11010111|000|11111|0000|11|Rn|Rm" , "control": "call"},
+ {"inst": "brabz Xn" , "op": "11010110|000|11111|0000|11|Rn|11111" , "control": "call"},
+ {"inst": "eretaa" , "op": "11010110|100|11111|0000|10|11111|11111" , "control": "return"},
+ {"inst": "eretab" , "op": "11010110|100|11111|0000|11|11111|11111" , "control": "return"},
+ {"inst": "ldraa Xd, [Xn|SP, #offS]{!}" , "op": "11111000|0|offS:1|1|offS:9|W1|Rn|Rd"},
+ {"inst": "ldrab Xd, [Xn|SP, #offS]{!}" , "op": "11111000|1|offS:1|1|offS:9|W1|Rn|Rd"},
+ {"inst": "pacda Xd, Xn|SP" , "op": "11011010|110|00001|0|00010|Rn|Rd"},
+ {"inst": "pacdb Xd, Xn|SP" , "op": "11011010|110|00001|0|00011|Rn|Rd"},
+ {"inst": "pacdza Xd" , "op": "11011010|110|00001|0|01010|11111|Rd"},
+ {"inst": "pacdzb Xd" , "op": "11011010|110|00001|0|01011|11111|Rd"},
+ {"inst": "pacga Xd, Xn, Xm|SP" , "op": "10011010|110|Rm|0|01100|Rn|Rd"},
+ {"inst": "pacia Xd, Xn|SP" , "op": "11011010|110|00001|0|00000|Rn|Rd"},
+ {"inst": "pacia1716" , "op": "11010101|000|00011|0010|0001|000|11111"},
+ {"inst": "paciasp" , "op": "11010101|000|00011|0010|0011|001|11111"},
+ {"inst": "paciaz" , "op": "11010101|000|00011|0010|0011|000|11111"},
+ {"inst": "pacib Xd, Xn|SP" , "op": "11011010|110|00001|0|00001|Rn|Rd"},
+ {"inst": "pacib1716" , "op": "11010101|000|00011|0010|0001|010|11111"},
+ {"inst": "pacibsp" , "op": "11010101|000|00011|0010|0011|011|11111"},
+ {"inst": "pacibz" , "op": "11010101|000|00011|0010|0011|010|11111"},
+ {"inst": "paciza Xd" , "op": "11011010|110|00001|0|01000|11111|Rd"},
+ {"inst": "pacizb Xd" , "op": "11011010|110|00001|0|01001|11111|Rd"},
+ {"inst": "retaa" , "op": "11010110|010|11111|0|00010|11111|11111" , "control": "return"},
+ {"inst": "retab" , "op": "11010110|010|11111|0|00011|11111|11111" , "control": "return"},
+ {"inst": "xpacd Xd" , "op": "11011010|110|00001|0|10001|11111|Rd"},
+ {"inst": "xpaci Xd" , "op": "11011010|110|00001|0|10000|11111|Rd"},
+ {"inst": "xpaclri Xd" , "op": "11010101|000|00011|0|01000|00111|11111"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RAS", "data": [
+ {"inst": "esb" , "op": "11010101|000|00011|0010|0010|000|11111"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RPRFM", "data": [
+ {"inst": "rprfm #rprf_op, Xm, [Xn|SP]" , "op": "11111000|101|Rm|imm:1|1|imm:2|10|Rn|11|imm:3" , "imm": "ImmRPRF(rprf_op)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SB", "data": [
+ {"inst": "sb" , "op": "11010101|000|00011|0011|0000|111|11111"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SPE", "data": [
+ {"inst": "psb #psb_tsb_op" , "op": "11010101|000|00011|0010|0010|001|11111" , "imm": "ImmPSB_TSB(psb_tsb_op)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SPECRES", "data": [
+ {"inst": "cfp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|100|Rt" , "imm": "ImmRCTX(rctx)"},
+ {"inst": "cpp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|111|Rt" , "imm": "ImmRCTX(rctx)"},
+ {"inst": "dvp #rctx, Xt" , "op": "11010101|000|01|011|0111|0011|101|Rt" , "imm": "ImmRCTX(rctx)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SPECRES2", "data": [
+ {"inst": "cosp #rctx, Xt" , "op": "11010101|000|01011|0111|0011|110|Rt" , "imm": "ImmRCTX(rctx)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SYSINSTR128", "data": [
+ {"inst": "sysp #op1, #CRn, #CRm, #op2, 2x{Xt}+" , "op": "11010101|010|01|op1:3|CRn|CRm|op2:3|Rt"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SYSREG128", "data": [
+ {"inst": "mrrs 2x{Xd}+, #sysreg" , "op": "11010101|011|1|sysreg:15|Rd"},
+ {"inst": "msrr 2x{Xs}+, #sysreg" , "op": "11010101|010|1|sysreg:15|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "THE", "data": [
+ {"inst": "rcwcas Xs, Xt, [Xn|SP]" , "op": "00011001|001|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwcasa Xs, Xt, [Xn|SP]" , "op": "00011001|101|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwcasal Xs, Xt, [Xn|SP]" , "op": "00011001|111|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwcasl Xs, Xt, [Xn|SP]" , "op": "00011001|011|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwcasp 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|001|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwcaspa 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|101|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwcaspal 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|111|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwcaspl 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "00011001|011|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwclr Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwclra Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwclral Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwclrl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwclrp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwclrpa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwclrpal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwclrpl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwscas Xs, Xt, [Xn|SP]" , "op": "01011001|001|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwscasa Xs, Xt, [Xn|SP]" , "op": "01011001|101|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwscasal Xs, Xt, [Xn|SP]" , "op": "01011001|111|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwscasl Xs, Xt, [Xn|SP]" , "op": "01011001|011|Rs|0|00010|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwscasp 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|001|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwscaspa 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|101|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwscaspal 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|111|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwscaspl 2x{Xs}+, 2x{Xt}+, [Xn|SP]" , "op": "01011001|011|Rs|0|00011|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsclr Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsclra Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsclral Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsclrl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsclrp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsclrpa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsclrpal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsclrpl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|00100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwset Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwseta Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsetal Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsetl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsetp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsetpa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsetpal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsetpl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsset Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsseta Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwssetal Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwssetl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwssetp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwssetpa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwssetpal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwssetpl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|01100|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsswp Xs, Xt, [Xn|SP]" , "op": "01111000|001|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsswpa Xs, Xt, [Xn|SP]" , "op": "01111000|101|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsswpal Xs, Xt, [Xn|SP]" , "op": "01111000|111|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsswpl Xs, Xt, [Xn|SP]" , "op": "01111000|011|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwsswpp Xt, Xt2, [Xn|SP]" , "op": "01011001|001|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsswppa Xt, Xt2, [Xn|SP]" , "op": "01011001|101|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsswppal Xt, Xt2, [Xn|SP]" , "op": "01011001|111|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwsswppl Xt, Xt2, [Xn|SP]" , "op": "01011001|011|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwswp Xs, Xt, [Xn|SP]" , "op": "00111000|001|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwswpa Xs, Xt, [Xn|SP]" , "op": "00111000|101|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwswpal Xs, Xt, [Xn|SP]" , "op": "00111000|111|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwswpl Xs, Xt, [Xn|SP]" , "op": "00111000|011|Rs|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rcwswpp Xt, Xt2, [Xn|SP]" , "op": "00011001|001|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwswppa Xt, Xt2, [Xn|SP]" , "op": "00011001|101|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwswppal Xt, Xt2, [Xn|SP]" , "op": "00011001|111|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"},
+ {"inst": "rcwswppl Xt, Xt2, [Xn|SP]" , "op": "00011001|011|Rt2|1|01000|Rn|Rt" , "io": "N=W Z=W C=W V=W", "ext": "D128"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "TME", "data": [
+ {"inst": "tcancel #imm" , "op": "11010100|011|imm:16|00000"},
+ {"inst": "tcommit" , "op": "11010101|000|00011|0011|0000|011|11111"},
+ {"inst": "tstart Xt" , "op": "11010101|001|00011|0011|0000|011|Rt"},
+ {"inst": "ttest Xd" , "op": "11010101|001|00011|0011|0001|011|Rd"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "TRF", "data": [
+ {"inst": "tsb #psb_tsb_op" , "op": "11010101|000|00011|0010|0010|010|11111" , "imm": "ImmPSB_TSB(psb_tsb_op)"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "WFXT", "data": [
+ {"inst": "wfet Xs" , "op": "11010101|000|00011|0001|0000|000|Rs"},
+ {"inst": "wfit Xs" , "op": "11010101|000|00011|0001|0000|001|Rs"}
+ ]},
+
+ {"category": "ASIMD", "ext": "ASIMD", "data": [
+ {"inst": "abs Dd, Dn" , "op": "01011110|11|10000|01011|10|Vn|Vd"},
+ {"inst": "abs Vd.t, Vn.t" , "op": "00001110|sz|10000|01011|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "abs Vd.t, Vn.t" , "op": "01001110|sz|10000|01011|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "add Dd, Dn, Dm" , "op": "01011110|11|1|Vm|10000|1|Vn|Vd"},
+ {"inst": "add Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10000|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "add Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10000|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "addhn Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01000|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "addhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01000|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "addp Dd, Vn.2D" , "op": "01011110|sz|11000|11011|10|Vn|Vd"},
+ {"inst": "addp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10111|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "addp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10111|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "addv Bd, Vn.8B" , "op": "00001110|00|11000|11011|10|Vn|Vd"},
+ {"inst": "addv Bd, Vn.16B" , "op": "01001110|00|11000|11011|10|Vn|Vd"},
+ {"inst": "addv Hd, Vn.4H" , "op": "00001110|01|11000|11011|10|Vn|Vd"},
+ {"inst": "addv Hd, Vn.8H" , "op": "01001110|01|11000|11011|10|Vn|Vd"},
+ {"inst": "addv Sd, Vn.4S" , "op": "01001110|10|11000|11011|10|Vn|Vd"},
+ {"inst": "and Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|00|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "and Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|00|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "bic Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|01|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "bic Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|01|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "bic Vd.t, #imm, {lsl #n}" , "op": "00101111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "4H 2S", "imm": "ASimdLogicalImm(sz, 1, imm, lsl)"},
+ {"inst": "bic Vd.t, #imm, {lsl #n}" , "op": "01101111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "8H 4S", "imm": "ASimdLogicalImm(sz, 1, imm, lsl)"},
+ {"inst": "bif Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|11|1|Vm|00011|1|Vn|Vx"},
+ {"inst": "bif Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|11|1|Vm|00011|1|Vn|Vx"},
+ {"inst": "bit Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|10|1|Vm|00011|1|Vn|Vx"},
+ {"inst": "bit Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|10|1|Vm|00011|1|Vn|Vx"},
+ {"inst": "bsl Dx.8B, Vn.8B, Vm.8B" , "op": "00101111|01|1|Vm|00011|1|Vn|Vx"},
+ {"inst": "bsl Vx.16B, Vn.16B, Vm.16B" , "op": "01101111|01|1|Vm|00011|1|Vn|Vx"},
+ {"inst": "cls Vd.t, Vn.t" , "op": "00001110|sz|10000|00100|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cls Vd.t, Vn.t" , "op": "01001110|sz|10000|00100|10|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "clz Vd.t, Vn.t" , "op": "00101110|sz|10000|00100|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "clz Vd.t, Vn.t" , "op": "01101110|sz|10000|00100|10|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "cmeq Dd, Dn, Dm" , "op": "01111110|11|1|Vm|10001|1|Vn|Vd"},
+ {"inst": "cmeq Dd, Dn, #0" , "op": "01011110|11|10000|01001|10|Vn|Vd"},
+ {"inst": "cmeq Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10001|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmeq Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01001|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmeq Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10001|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmeq Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01001|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmge Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00111|1|Vn|Vd"},
+ {"inst": "cmge Dd, Dn, #0" , "op": "01111110|11|10000|01000|10|Vn|Vd"},
+ {"inst": "cmge Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00111|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmge Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01000|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmge Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00111|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmge Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01000|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmgt Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00110|1|Vn|Vd"},
+ {"inst": "cmgt Dd, Dn, #0" , "op": "01011110|11|10000|01000|10|Vn|Vd"},
+ {"inst": "cmgt Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00110|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmgt Vd.t, Vn.t, #0" , "op": "00001110|sz|10000|01000|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmgt Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00110|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmgt Vd.t, Vn.t, #0" , "op": "01001110|sz|10000|01000|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmhi Dd, Dn, Dm" , "op": "01111110|11|1|Vm|00110|1|Vn|Vd"},
+ {"inst": "cmhi Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00110|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmhi Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00110|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmhs Dd, Dn, Dm" , "op": "01111110|11|1|Vm|00111|1|Vn|Vd"},
+ {"inst": "cmhs Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00111|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmhs Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00111|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmle Dd, Dn, #0" , "op": "01111110|11|10000|01001|10|Vn|Vd"},
+ {"inst": "cmle Vd.t, Vn.t, #0" , "op": "00101110|sz|10000|01001|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmle Vd.t, Vn.t, #0" , "op": "01101110|sz|10000|01001|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmlt Dd, Dn, #0" , "op": "01011110|11|10000|01010|10|Vn|Vd"},
+ {"inst": "cmlt Vd.t, Vn.t, #0" , "op": "00001110|sz|10000|01010|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmlt Vd.t, Vn.t, #0" , "op": "01001110|sz|10000|01010|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cmtst Dd, Dn, Dm" , "op": "01011110|11|1|Vm|10001|1|Vn|Vd"},
+ {"inst": "cmtst Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10001|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "cmtst Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10001|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "cnt Vd.8B, Vn.8B" , "op": "00001110|sz|10000|00101|10|Vn|Vd"},
+ {"inst": "cnt Vd.16B, Vn.16B" , "op": "01001110|sz|10000|00101|10|Vn|Vd"},
+ {"inst": "dup|mov Bd, Vn.B[#idx]" , "op": "01011110|00|0|idx:4| 1|00000|1|Vn|Vd"},
+ {"inst": "dup|mov Hd, Vn.H[#idx]" , "op": "01011110|00|0|idx:3| 10|00000|1|Vn|Vd"},
+ {"inst": "dup|mov Sd, Vn.S[#idx]" , "op": "01011110|00|0|idx:2| 100|00000|1|Vn|Vd"},
+ {"inst": "dup|mov Dd, Vn.D[#idx]" , "op": "01011110|00|0|idx:1| 1000|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.8B, Wn" , "op": "00001110|00|0|00001|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.4H, Wn" , "op": "00001110|00|0|00010|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.2S, Wn" , "op": "00001110|00|0|11011|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.16B, Wn" , "op": "01001110|00|0|00001|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.8H, Wn" , "op": "01001110|00|0|00010|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.4S, Wn" , "op": "01001110|00|0|11011|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.2D, Xn" , "op": "01001110|00|0|11011|00001|1|Rn|Vd"},
+ {"inst": "dup Vd.8B, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.4H, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.2S, Vn.S[#idx]" , "op": "00001110|00|0|idx:2| 100|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.16B, Vn.B[#idx]" , "op": "01001110|00|0|idx:4| 1|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.8H, Vn.H[#idx]" , "op": "01001110|00|0|idx:3| 10|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.4S, Vn.S[#idx]" , "op": "01001110|00|0|idx:2| 100|00000|1|Vn|Vd"},
+ {"inst": "dup Vd.2D, Vn.D[#idx]" , "op": "01001110|00|0|idx:1| 1000|00000|1|Vn|Vd"},
+ {"inst": "eor Vd.8B, Vn.8B, Vm.8B" , "op": "00101110|00|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "eor Vd.16B, Vn.16B, Vm.16B" , "op": "01101110|00|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "ext Vd.8B, Vn.8B, Vm.8B, #idx" , "op": "00101110|00|0|Vm|00|idx:3|0|Vn|Vd"},
+ {"inst": "ext Vd.16B, Vn.16B, Vm.16B, #idx" , "op": "01101110|00|0|Vm|0|idx:4|0|Vn|Vd"},
+ {"inst": "fabd Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fabd Dd, Dn, Dm" , "op": "01111110|11|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fabd Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|0|Vm|11010|1|Vn|Vd"},
+ {"inst": "fabd Vd.4S, Vn.4S, Vm.4S" , "op": "00101110|10|0|Vm|11010|1|Vn|Vd"},
+ {"inst": "fabd Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|0|Vm|11010|1|Vn|Vd"},
+ {"inst": "fabs Sd, Sn" , "op": "00011110|00|10000|01100|00|Vn|Vd"},
+ {"inst": "fabs Dd, Dn" , "op": "00011110|01|10000|01100|00|Vn|Vd"},
+ {"inst": "fabs Vd.2S, Vn.2S" , "op": "00001110|10|10000|01111|10|Vn|Vd"},
+ {"inst": "fabs Vd.4S, Vn.4S" , "op": "01001110|10|10000|01111|10|Vn|Vd"},
+ {"inst": "fabs Vd.2D, Vn.2D" , "op": "01001110|11|10000|01111|10|Vn|Vd"},
+ {"inst": "facge Sd, Sn, Sm" , "op": "01111110|00|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facge Dd, Dn, Dm" , "op": "01111110|01|0|Vm|11101|1|Vn|Vd"},
+ {"inst": "facge Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facge Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facge Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facgt Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facgt Dd, Dn, Dm" , "op": "01111110|11|0|Vm|11101|1|Vn|Vd"},
+ {"inst": "facgt Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facgt Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "facgt Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11101|1|Vn|Vd"},
+ {"inst": "fadd Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00101|0|Vn|Vd"},
+ {"inst": "fadd Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00101|0|Vn|Vd"},
+ {"inst": "fadd Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fadd Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fadd Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "faddp Sd, Vn.2S" , "op": "01111110|00|11000|01101|10|Vn|Vd"},
+ {"inst": "faddp Dd, Vn.2D" , "op": "01111110|01|11000|01101|10|Vn|Vd"},
+ {"inst": "faddp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "faddp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "faddp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fccmp Sn, Sm, #nzcv, #cond" , "op": "00011110|00|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fccmp Dn, Dm, #nzcv, #cond" , "op": "00011110|01|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fccmpe Sn, Sm, #nzcv, #cond" , "op": "00011110|00|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fccmpe Dn, Dm, #nzcv, #cond" , "op": "00011110|01|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmeq Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmeq Sd, Sn, #0" , "op": "01011110|10|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmeq Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmeq Dd, Dn, #0" , "op": "01011110|11|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmeq Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmeq Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmeq Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmeq Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmeq Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmeq Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmge Sd, Sn, Sm" , "op": "01111110|00|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmge Sd, Sn, #0" , "op": "01111110|10|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmge Dd, Dn, Dm" , "op": "01111110|01|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmge Dd, Dn, #0" , "op": "01111110|11|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmge Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmge Vd.2S, Vn.2S, #0" , "op": "00101110|10|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmge Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmge Vd.4S, Vn.4S, #0" , "op": "01101110|10|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmge Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmge Vd.2D, Vn.2D, #0" , "op": "01101110|11|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Sd, Sn, Sm" , "op": "01111110|10|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmgt Sd, Sn, #0" , "op": "01011110|10|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Dd, Dn, Dm" , "op": "01111110|11|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmgt Dd, Dn, #0" , "op": "01011110|11|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmgt Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmgt Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11100|1|Vn|Vd"},
+ {"inst": "fcmgt Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01100|10|Vn|Vd"},
+ {"inst": "fcmle Sd, Sn, #0" , "op": "01111110|10|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmle Dd, Dn, #0" , "op": "01111110|11|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmle Vd.2S, Vn.2S, #0" , "op": "00101110|10|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmle Vd.4S, Vn.4S, #0" , "op": "01101110|10|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmle Vd.2D, Vn.2D, #0" , "op": "01101110|11|10000|01101|10|Vn|Vd"},
+ {"inst": "fcmlt Sd, Sn, #0" , "op": "01011110|10|10000|01110|10|Vn|Vd"},
+ {"inst": "fcmlt Dd, Dn, #0" , "op": "01011110|11|10000|01110|10|Vn|Vd"},
+ {"inst": "fcmlt Vd.2S, Vn.2S, #0" , "op": "00001110|10|10000|01110|10|Vn|Vd"},
+ {"inst": "fcmlt Vd.4S, Vn.4S, #0" , "op": "01001110|10|10000|01110|10|Vn|Vd"},
+ {"inst": "fcmlt Vd.2D, Vn.2D, #0" , "op": "01001110|11|10000|01110|10|Vn|Vd"},
+ {"inst": "fcmp Sn, Sm" , "op": "00011110|00|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmp Sn, #0" , "op": "00011110|00|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmp Dn, Dm" , "op": "00011110|01|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmp Dn, #0" , "op": "00011110|01|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmpe Sn, Sm" , "op": "00011110|00|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmpe Sn, #0" , "op": "00011110|00|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmpe Dn, Dm" , "op": "00011110|01|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmpe Dn, #0" , "op": "00011110|01|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcsel Sd, Sn, Sm, #cond" , "op": "00011110|00|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "fcsel Dd, Dn, Dm, #cond" , "op": "00011110|01|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "fcvt Sd, Hn" , "op": "00011110|11|10001|00100|00|Vn|Vd"},
+ {"inst": "fcvt Dd, Hn" , "op": "00011110|11|10001|01100|00|Vn|Vd"},
+ {"inst": "fcvt Hd, Sn" , "op": "00011110|00|10001|11100|00|Vn|Vd"},
+ {"inst": "fcvt Dd, Sn" , "op": "00011110|00|10001|01100|00|Vn|Vd"},
+ {"inst": "fcvt Hd, Dn" , "op": "00011110|01|10001|11100|00|Vn|Vd"},
+ {"inst": "fcvt Sd, Dn" , "op": "00011110|01|10001|00100|00|Vn|Vd"},
+ {"inst": "fcvtas Wd, Sn" , "op": "00011110|00|10010|00000|00|Vn|Rd"},
+ {"inst": "fcvtas Xd, Sn" , "op": "10011110|00|10010|00000|00|Vn|Rd"},
+ {"inst": "fcvtas Wd, Dn" , "op": "00011110|01|10010|00000|00|Vn|Rd"},
+ {"inst": "fcvtas Xd, Dn" , "op": "10011110|01|10010|00000|00|Vn|Rd"},
+ {"inst": "fcvtas Sd, Sn" , "op": "01011110|00|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtas Dd, Dn" , "op": "01011110|01|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtas Vd.2S, Vn.2S" , "op": "00001110|00|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtas Vd.4S, Vn.4S" , "op": "01001110|00|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtas Vd.2D, Vn.2D" , "op": "01001110|01|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Wd, Sn" , "op": "00011110|00|10010|10000|00|Vn|Rd"},
+ {"inst": "fcvtau Xd, Sn" , "op": "10011110|00|10010|10000|00|Vn|Rd"},
+ {"inst": "fcvtau Wd, Dn" , "op": "00011110|01|10010|10000|00|Vn|Rd"},
+ {"inst": "fcvtau Xd, Dn" , "op": "10011110|01|10010|10000|00|Vn|Rd"},
+ {"inst": "fcvtau Sd, Sn" , "op": "01111110|00|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Dd, Dn" , "op": "01111110|01|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Vd.2S, Vn.2S" , "op": "00101110|00|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Vd.4S, Vn.4S" , "op": "01101110|00|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Vd.2D, Vn.2D" , "op": "01101110|01|10000|11100|10|Vn|Vd"},
+ {"inst": "fcvtl Vd.4S, Vn.4H" , "op": "00001110|00|10000|10111|10|Vn|Vd"},
+ {"inst": "fcvtl2 Vd.4S, Vn.8H" , "op": "01001110|00|10000|10111|10|Vn|Vd"},
+ {"inst": "fcvtl Vd.2D, Vn.2S" , "op": "00001110|01|10000|10111|10|Vn|Vd"},
+ {"inst": "fcvtl2 Vd.2D, Vn.4S" , "op": "01001110|01|10000|10111|10|Vn|Vd"},
+ {"inst": "fcvtms Wd, Sn" , "op": "00011110|00|11000|00000|00|Vn|Rd"},
+ {"inst": "fcvtms Xd, Sn" , "op": "10011110|00|11000|00000|00|Vn|Rd"},
+ {"inst": "fcvtms Wd, Dn" , "op": "00011110|01|11000|00000|00|Vn|Rd"},
+ {"inst": "fcvtms Xd, Dn" , "op": "10011110|01|11000|00000|00|Vn|Rd"},
+ {"inst": "fcvtms Sd, Sn" , "op": "01011110|00|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtms Dd, Dn" , "op": "01011110|01|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtms Vd.2S, Vn.2S" , "op": "00001110|00|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtms Vd.4S, Vn.4S" , "op": "01001110|00|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtms Vd.2D, Vn.2D" , "op": "01001110|01|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Wd, Sn" , "op": "00011110|00|11000|10000|00|Vn|Rd"},
+ {"inst": "fcvtmu Xd, Sn" , "op": "10011110|00|11000|10000|00|Vn|Rd"},
+ {"inst": "fcvtmu Wd, Dn" , "op": "00011110|01|11000|10000|00|Vn|Rd"},
+ {"inst": "fcvtmu Xd, Dn" , "op": "10011110|01|11000|10000|00|Vn|Rd"},
+ {"inst": "fcvtmu Sd, Sn" , "op": "01111110|00|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Dd, Dn" , "op": "01111110|01|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Vd.2S, Vn.2S" , "op": "00101110|00|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Vd.4S, Vn.4S" , "op": "01101110|00|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Vd.2D, Vn.2D" , "op": "01101110|01|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtn Vd.4S, Vn.4H" , "op": "00001110|00|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtn2 Vd.4S, Vn.8H" , "op": "01001110|00|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtn Vd.2D, Vn.2S" , "op": "00001110|01|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtn2 Vd.2D, Vn.4S" , "op": "01001110|01|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtns Wd, Sn" , "op": "00011110|00|10000|00000|00|Vn|Rd"},
+ {"inst": "fcvtns Xd, Sn" , "op": "10011110|00|10000|00000|00|Vn|Rd"},
+ {"inst": "fcvtns Wd, Dn" , "op": "00011110|01|10000|00000|00|Vn|Rd"},
+ {"inst": "fcvtns Xd, Dn" , "op": "10011110|01|10000|00000|00|Vn|Rd"},
+ {"inst": "fcvtns Sd, Sn" , "op": "01011110|00|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtns Dd, Dn" , "op": "01011110|01|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtns Vd.2S, Vn.2S" , "op": "00001110|00|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtns Vd.4S, Vn.4S" , "op": "01001110|00|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtns Vd.2D, Vn.2D" , "op": "01001110|01|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Wd, Sn" , "op": "00011110|00|10000|10000|00|Vn|Rd"},
+ {"inst": "fcvtnu Xd, Sn" , "op": "10011110|00|10000|10000|00|Vn|Rd"},
+ {"inst": "fcvtnu Wd, Dn" , "op": "00011110|01|10000|10000|00|Vn|Rd"},
+ {"inst": "fcvtnu Xd, Dn" , "op": "10011110|01|10000|10000|00|Vn|Rd"},
+ {"inst": "fcvtnu Sd, Sn" , "op": "01111110|00|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Dd, Dn" , "op": "01111110|01|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Vd.2S, Vn.2S" , "op": "00101110|00|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Vd.4S, Vn.4S" , "op": "01101110|00|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Vd.2D, Vn.2D" , "op": "01101110|01|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Wd, Sn" , "op": "00011110|00|10100|00000|00|Vn|Rd"},
+ {"inst": "fcvtps Xd, Sn" , "op": "10011110|00|10100|00000|00|Vn|Rd"},
+ {"inst": "fcvtps Wd, Dn" , "op": "00011110|01|10100|00000|00|Vn|Rd"},
+ {"inst": "fcvtps Xd, Dn" , "op": "10011110|01|10100|00000|00|Vn|Rd"},
+ {"inst": "fcvtps Sd, Sn" , "op": "01011110|10|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Dd, Dn" , "op": "01011110|11|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Vd.2S, Vn.2S" , "op": "00001110|10|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Vd.4S, Vn.4S" , "op": "01001110|10|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Vd.2D, Vn.2D" , "op": "01001110|11|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Wd, Sn" , "op": "00011110|00|10100|10000|00|Vn|Rd"},
+ {"inst": "fcvtpu Xd, Sn" , "op": "10011110|00|10100|10000|00|Vn|Rd"},
+ {"inst": "fcvtpu Wd, Dn" , "op": "00011110|01|10100|10000|00|Vn|Rd"},
+ {"inst": "fcvtpu Xd, Dn" , "op": "10011110|01|10100|10000|00|Vn|Rd"},
+ {"inst": "fcvtpu Sd, Sn" , "op": "01111110|10|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Dd, Dn" , "op": "01111110|11|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Vd.2S, Vn.2S" , "op": "00101110|10|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Vd.4S, Vn.4S" , "op": "01101110|10|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Vd.2D, Vn.2D" , "op": "01101110|11|10000|11010|10|Vn|Vd"},
+ {"inst": "fcvtx Sd, Dn" , "op": "01111110|01|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtx Vd.4S, Vn.4H" , "op": "00101110|00|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtx2 Vd.4S, Vn.8H" , "op": "01101110|00|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtx Vd.2D, Vn.2S" , "op": "00101110|01|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtx2 Vd.2D, Vn.4S" , "op": "01101110|01|10000|10110|10|Vn|Vd"},
+ {"inst": "fcvtzs Wd, Sn" , "op": "00011110|00|11100|00000|00|Vn|Rd"},
+ {"inst": "fcvtzs Xd, Sn" , "op": "10011110|00|11100|00000|00|Vn|Rd"},
+ {"inst": "fcvtzs Wd, Dn" , "op": "00011110|01|11100|00000|00|Vn|Rd"},
+ {"inst": "fcvtzs Xd, Dn" , "op": "10011110|01|11100|00000|00|Vn|Rd"},
+ {"inst": "fcvtzs Sd, Sn" , "op": "01011110|10|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Dd, Dn" , "op": "01011110|11|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Vd.2S, Vn.2S" , "op": "00001110|10|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Vd.4S, Vn.4S" , "op": "01001110|10|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Vd.2D, Vn.2D" , "op": "01001110|11|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Wd, Sn, #fbits" , "op": "00011110|00|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "fcvtzs Xd, Sn, #fbits" , "op": "10011110|00|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "fcvtzs Wd, Dn, #fbits" , "op": "00011110|01|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "fcvtzs Xd, Dn, #fbits" , "op": "10011110|01|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "fcvtzs Sd, Sn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "fcvtzs Dd, Dn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "fcvtzs Vd.2S, Vn.2S, #fbits" , "op": "00001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "fcvtzs Vd.4S, Vn.4S, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "fcvtzs Vd.2D, Vn.2D, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "fcvtzu Wd, Sn" , "op": "00011110|00|11100|10000|00|Vn|Rd"},
+ {"inst": "fcvtzu Xd, Sn" , "op": "10011110|00|11100|10000|00|Vn|Rd"},
+ {"inst": "fcvtzu Wd, Dn" , "op": "00011110|01|11100|10000|00|Vn|Rd"},
+ {"inst": "fcvtzu Xd, Dn" , "op": "10011110|01|11100|10000|00|Vn|Rd"},
+ {"inst": "fcvtzu Sd, Sn" , "op": "01111110|10|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Dd, Dn" , "op": "01111110|11|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Vd.2S, Vn.2S" , "op": "00101110|10|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Vd.4S, Vn.4S" , "op": "01101110|10|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Vd.2D, Vn.2D" , "op": "01101110|11|10000|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Wd, Sn, #fbits" , "op": "00011110|00|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "fcvtzu Xd, Sn, #fbits" , "op": "10011110|00|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "fcvtzu Wd, Dn, #fbits" , "op": "00011110|01|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "fcvtzu Xd, Dn, #fbits" , "op": "10011110|01|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "fcvtzu Sd, Sn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "fcvtzu Dd, Dn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "fcvtzu Vd.2S, Vn.2S, #fbits" , "op": "00101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "fcvtzu Vd.4S, Vn.4S, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "fcvtzu Vd.2D, Vn.2D, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "fdiv Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00011|0|Vn|Vd"},
+ {"inst": "fdiv Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00011|0|Vn|Vd"},
+ {"inst": "fdiv Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "fdiv Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "fdiv Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "fmadd Sd, Sn, Sm, Sa" , "op": "00011111|00|0|Vm|0|Va|Vn|Vd"},
+ {"inst": "fmadd Dd, Dn, Dm, Da" , "op": "00011111|01|0|Vm|0|Va|Vn|Vd"},
+ {"inst": "fmax Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01001|0|Vn|Vd"},
+ {"inst": "fmax Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01001|0|Vn|Vd"},
+ {"inst": "fmax Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmax Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmax Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmaxnm Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01101|0|Vn|Vd"},
+ {"inst": "fmaxnm Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01101|0|Vn|Vd"},
+ {"inst": "fmaxnm Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fmaxnm Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fmaxnm Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fmaxnmp Sd, Vn.2S" , "op": "01111110|00|11000|01100|10|Vn|Vd"},
+ {"inst": "fmaxnmp Dd, Vn.2D" , "op": "01111110|01|11000|01100|10|Vn|Vd"},
+ {"inst": "fmaxnmp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fmaxnmp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fmaxnmp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fmaxnmv Sd, Vn.4S" , "op": "01101110|00|11000|01100|10|Vn|Vd"},
+ {"inst": "fmaxp Sd, Vn.2S" , "op": "01111110|00|11000|01111|10|Vn|Vd"},
+ {"inst": "fmaxp Dd, Vn.2D" , "op": "01111110|01|11000|01111|10|Vn|Vd"},
+ {"inst": "fmaxp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmaxp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmaxp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmaxv Sd, Vn.4S" , "op": "01101110|00|11000|01111|10|Vn|Vd"},
+ {"inst": "fmin Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01011|0|Vn|Vd"},
+ {"inst": "fmin Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01011|0|Vn|Vd"},
+ {"inst": "fmin Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmin Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fmin Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fminnm Sd, Sn, Sm" , "op": "00011110|00|1|Vm|01111|0|Vn|Vd"},
+ {"inst": "fminnm Dd, Dn, Dm" , "op": "00011110|01|1|Vm|01111|0|Vn|Vd"},
+ {"inst": "fminnm Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fminnm Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fminnm Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fminnmp Sd, Vn.2S" , "op": "01111110|10|11000|01100|10|Vn|Vd"},
+ {"inst": "fminnmp Dd, Vn.2D" , "op": "01111110|11|11000|01100|10|Vn|Vd"},
+ {"inst": "fminnmp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fminnmp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fminnmp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11000|1|Vn|Vd"},
+ {"inst": "fminnmv Sd, Vn.4S" , "op": "01101110|10|11000|01100|10|Vn|Vd"},
+ {"inst": "fminp Sd, Vn.2S" , "op": "01111110|10|11000|01111|10|Vn|Vd"},
+ {"inst": "fminp Dd, Vn.2D" , "op": "01111110|11|11000|01111|10|Vn|Vd"},
+ {"inst": "fminp Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fminp Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fminp Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11110|1|Vn|Vd"},
+ {"inst": "fminv Sd, Vn.4S" , "op": "01101110|10|11000|01111|10|Vn|Vd"},
+ {"inst": "fmla Sx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"},
+ {"inst": "fmla Dx, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|0001|idx[0]|0|Vn|Vx"},
+ {"inst": "fmla Vx.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmla Vx.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmla Vx.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmla Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"},
+ {"inst": "fmla Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|0001|idx[1]|0|Vn|Vx"},
+ {"inst": "fmla Vx.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|0001|idx[0]|0|Vn|Vx"},
+ {"inst": "fmls Sx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"},
+ {"inst": "fmls Dx, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|0101|idx[0]|0|Vn|Vx"},
+ {"inst": "fmls Vx.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmls Vx.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmls Vx.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmls Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"},
+ {"inst": "fmls Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|0101|idx[1]|0|Vn|Vx"},
+ {"inst": "fmls Vx.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|0101|idx[0]|0|Vn|Vx"},
+ {"inst": "fmov Wd, Sn" , "op": "00011110|00|10011|00000|00|Vn|Rd"},
+ {"inst": "fmov Xd, Dn" , "op": "10011110|01|10011|00000|00|Vn|Rd"},
+ {"inst": "fmov Xd, Vn.D[#1]" , "op": "10011110|10|10111|00000|00|Vn|Rd"},
+ {"inst": "fmov Sd, Wn" , "op": "00011110|00|10011|10000|00|Rn|Vd"},
+ {"inst": "fmov Sd, Sn" , "op": "00011110|00|10000|00100|00|Vn|Vd"},
+ {"inst": "fmov Sd, #fimm" , "op": "00011110|00|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmov Dd, Xn" , "op": "10011110|01|10011|10000|00|Rn|Vd"},
+ {"inst": "fmov Dd, Dn" , "op": "00011110|01|10000|00100|00|Vn|Vd"},
+ {"inst": "fmov Dd, #fimm" , "op": "00011110|01|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmov Vd.D[#1], Xn" , "op": "10011110|10|10111|10000|00|Rn|Vd"},
+ {"inst": "fmov Vd.2S, #fimm" , "op": "00001111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmov Vd.4S, #fimm" , "op": "01001111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmov Vd.2D, #fimm" , "op": "01101111|00|000|abc:3|111101|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmsub Sd, Sn, Sm, Sa" , "op": "00011111|00|0|Vm|1|Va|Vn|Vd"},
+ {"inst": "fmsub Dd, Dn, Dm, Da" , "op": "00011111|01|0|Vm|1|Va|Vn|Vd"},
+ {"inst": "fmul Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00001|0|Vn|Vd"},
+ {"inst": "fmul Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00001|0|Vn|Vd"},
+ {"inst": "fmul Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
+ {"inst": "fmul Dd, Dn, Vm.D[#idx]" , "op": "01011111|11|0|Vm|1001|idx[0]|0|Vn|Vd"},
+ {"inst": "fmul Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|00|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmul Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|00|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmul Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|01|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmul Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
+ {"inst": "fmul Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|11|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
+ {"inst": "fmul Vd.2D, Vn.2D, Vm.D[#idx]" , "op": "01001111|11|0|Vm|1001|idx[0]|0|Vn|Vd"},
+ {"inst": "fmulx Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmulx Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmulx Sd, Sn, Vm.S[#idx]" , "op": "01111111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
+ {"inst": "fmulx Dd, Dn, Vm.D[#idx]" , "op": "01111111|11|0|Vm|1001|idx:1|0|Vn|Vd"},
+ {"inst": "fmulx Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmulx Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmulx Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "fmulx Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
+ {"inst": "fmulx Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|1001|idx[1]|0|Vn|Vd"},
+ {"inst": "fmulx Vd.2D, Vn.2D, Vm.D[#idx]" , "op": "01101111|11|0|Vm|1001|idx:1|0|Vn|Vd"},
+ {"inst": "fneg Sd, Sn" , "op": "00011110|00|10000|10100|00|Vn|Vd"},
+ {"inst": "fneg Dd, Dn" , "op": "00011110|01|10000|10100|00|Vn|Vd"},
+ {"inst": "fneg Vd.2S, Vn.2S" , "op": "00101110|10|10000|01111|10|Vn|Vd"},
+ {"inst": "fneg Vd.4S, Vn.4S" , "op": "01101110|10|10000|01111|10|Vn|Vd"},
+ {"inst": "fneg Vd.2D, Vn.2D" , "op": "01101110|11|10000|01111|10|Vn|Vd"},
+ {"inst": "fnmadd Sd, Sn, Sm, Sa" , "op": "00011111|00|1|Vm|0|Va|Vn|Vd"},
+ {"inst": "fnmadd Dd, Dn, Dm, Da" , "op": "00011111|01|1|Vm|0|Va|Vn|Vd"},
+ {"inst": "fnmsub Sd, Sn, Sm, Sa" , "op": "00011111|00|1|Vm|1|Va|Vn|Vd"},
+ {"inst": "fnmsub Dd, Dn, Dm, Da" , "op": "00011111|01|1|Vm|1|Va|Vn|Vd"},
+ {"inst": "fnmul Sd, Sn, Sm" , "op": "00011110|00|1|Vm|10001|0|Vn|Vd"},
+ {"inst": "fnmul Dd, Dn, Dm" , "op": "00011110|01|1|Vm|10001|0|Vn|Vd"},
+ {"inst": "frecpe Sd, Sn" , "op": "01011110|10|10000|11101|10|Vn|Vd"},
+ {"inst": "frecpe Dd, Dn" , "op": "01011110|11|10000|11101|10|Vn|Vd"},
+ {"inst": "frecpe Vd.2S, Vn.2S" , "op": "00001110|10|10000|11101|10|Vn|Vd"},
+ {"inst": "frecpe Vd.4S, Vn.4S" , "op": "01001110|10|10000|11101|10|Vn|Vd"},
+ {"inst": "frecpe Vd.2D, Vn.2D" , "op": "01001110|11|10000|11101|10|Vn|Vd"},
+ {"inst": "frecps Sd, Sn, Sm" , "op": "01011110|00|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frecps Dd, Dn, Dm" , "op": "01011110|01|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frecps Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|00|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frecps Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|00|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frecps Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|01|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frecpx Sd, Sn, Sm" , "op": "01011110|10|10000|11111|10|Vn|Vd"},
+ {"inst": "frecpx Dd, Dn, Dm" , "op": "01011110|11|10000|11111|10|Vn|Vd"},
+ {"inst": "frinta Sd, Sn" , "op": "00011110|00|10011|00100|00|Vn|Vd"},
+ {"inst": "frinta Dd, Dn" , "op": "00011110|01|10011|00100|00|Vn|Vd"},
+ {"inst": "frinta Vd.2S, Vn.2S" , "op": "00101110|00|10000|11000|10|Vn|Vd"},
+ {"inst": "frinta Vd.4S, Vn.4S" , "op": "01101110|00|10000|11000|10|Vn|Vd"},
+ {"inst": "frinta Vd.2D, Vn.2D" , "op": "01101110|01|10000|11000|10|Vn|Vd"},
+ {"inst": "frinti Sd, Sn" , "op": "00011110|00|10011|11100|00|Vn|Vd"},
+ {"inst": "frinti Dd, Dn" , "op": "00011110|01|10011|11100|00|Vn|Vd"},
+ {"inst": "frinti Vd.2S, Vn.2S" , "op": "00101110|10|10000|11001|10|Vn|Vd"},
+ {"inst": "frinti Vd.4S, Vn.4S" , "op": "01101110|10|10000|11001|10|Vn|Vd"},
+ {"inst": "frinti Vd.2D, Vn.2D" , "op": "01101110|11|10000|11001|10|Vn|Vd"},
+ {"inst": "frintm Sd, Sn" , "op": "00011110|00|10010|10100|00|Vn|Vd"},
+ {"inst": "frintm Dd, Dn" , "op": "00011110|01|10010|10100|00|Vn|Vd"},
+ {"inst": "frintm Vd.2S, Vn.2S" , "op": "00001110|00|10000|11001|10|Vn|Vd"},
+ {"inst": "frintm Vd.4S, Vn.4S" , "op": "01001110|00|10000|11001|10|Vn|Vd"},
+ {"inst": "frintm Vd.2D, Vn.2D" , "op": "01001110|01|10000|11001|10|Vn|Vd"},
+ {"inst": "frintn Sd, Sn" , "op": "00011110|00|10010|00100|00|Vn|Vd"},
+ {"inst": "frintn Dd, Dn" , "op": "00011110|01|10010|00100|00|Vn|Vd"},
+ {"inst": "frintn Vd.2S, Vn.2S" , "op": "00001110|00|10000|11000|10|Vn|Vd"},
+ {"inst": "frintn Vd.4S, Vn.4S" , "op": "01001110|00|10000|11000|10|Vn|Vd"},
+ {"inst": "frintn Vd.2D, Vn.2D" , "op": "01001110|01|10000|11000|10|Vn|Vd"},
+ {"inst": "frintp Sd, Sn" , "op": "00011110|00|10010|01100|00|Vn|Vd"},
+ {"inst": "frintp Dd, Dn" , "op": "00011110|01|10010|01100|00|Vn|Vd"},
+ {"inst": "frintp Vd.2S, Vn.2S" , "op": "00001110|10|10000|11000|10|Vn|Vd"},
+ {"inst": "frintp Vd.4S, Vn.4S" , "op": "01001110|10|10000|11000|10|Vn|Vd"},
+ {"inst": "frintp Vd.2D, Vn.2D" , "op": "01001110|11|10000|11000|10|Vn|Vd"},
+ {"inst": "frintx Sd, Sn" , "op": "00011110|00|10011|10100|00|Vn|Vd"},
+ {"inst": "frintx Dd, Dn" , "op": "00011110|01|10011|10100|00|Vn|Vd"},
+ {"inst": "frintx Vd.2S, Vn.2S" , "op": "00101110|00|10000|11001|10|Vn|Vd"},
+ {"inst": "frintx Vd.4S, Vn.4S" , "op": "01101110|00|10000|11001|10|Vn|Vd"},
+ {"inst": "frintx Vd.2D, Vn.2D" , "op": "01101110|01|10000|11001|10|Vn|Vd"},
+ {"inst": "frintz Sd, Sn" , "op": "00011110|00|10010|11100|00|Vn|Vd"},
+ {"inst": "frintz Dd, Dn" , "op": "00011110|01|10010|11100|00|Vn|Vd"},
+ {"inst": "frintz Vd.2S, Vn.2S" , "op": "00001110|10|10000|11001|10|Vn|Vd"},
+ {"inst": "frintz Vd.4S, Vn.4S" , "op": "01001110|10|10000|11001|10|Vn|Vd"},
+ {"inst": "frintz Vd.2D, Vn.2D" , "op": "01001110|11|10000|11001|10|Vn|Vd"},
+ {"inst": "frsqrte Sd, Sn" , "op": "01111110|10|10000|11101|10|Vn|Vd"},
+ {"inst": "frsqrte Dd, Dn" , "op": "01111110|11|10000|11101|10|Vn|Vd"},
+ {"inst": "frsqrte Vd.2S, Vn.2S" , "op": "00101110|10|10000|11101|10|Vn|Vd"},
+ {"inst": "frsqrte Vd.4S, Vn.4S" , "op": "01101110|10|10000|11101|10|Vn|Vd"},
+ {"inst": "frsqrte Vd.2D, Vn.2D" , "op": "01101110|11|10000|11101|10|Vn|Vd"},
+ {"inst": "frsqrts Sd, Sn, Sm" , "op": "01011110|10|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frsqrts Dd, Dn, Dm" , "op": "01011110|11|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frsqrts Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frsqrts Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "frsqrts Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "fsqrt Sd, Sn" , "op": "00011110|10|10000|11100|00|Vn|Vd"},
+ {"inst": "fsqrt Dd, Dn" , "op": "00011110|11|10000|11100|00|Vn|Vd"},
+ {"inst": "fsqrt Vd.2S, Vn.2S" , "op": "00101110|10|10000|11111|10|Vn|Vd"},
+ {"inst": "fsqrt Vd.4S, Vn.4S" , "op": "01101110|10|10000|11111|10|Vn|Vd"},
+ {"inst": "fsqrt Vd.2D, Vn.2D" , "op": "01101110|11|10000|11111|10|Vn|Vd"},
+ {"inst": "fsub Sd, Sn, Sm" , "op": "00011110|00|1|Vm|00111|0|Vn|Vd"},
+ {"inst": "fsub Dd, Dn, Dm" , "op": "00011110|01|1|Vm|00111|0|Vn|Vd"},
+ {"inst": "fsub Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fsub Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "fsub Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11010|1|Vn|Vd"},
+ {"inst": "ins|mov Vd.B[#idx], Wn" , "op": "01001110|00|0|idx:4|1 |00011|1|Rn|Vd"},
+ {"inst": "ins|mov Vd.H[#idx], Wn" , "op": "01001110|00|0|idx:3|10 |00011|1|Rn|Vd"},
+ {"inst": "ins|mov Vd.S[#idx], Wn" , "op": "01001110|00|0|idx:2|100 |00011|1|Rn|Vd"},
+ {"inst": "ins|mov Vd.D[#idx], Xn" , "op": "01001110|00|0|idx:1|1000|00011|1|Rn|Vd"},
+ {"inst": "ins|mov Vd.B[#idx1], Vn.B[#idx2]" , "op": "01101110|00|0|idx1:4|1 |0|idx2:4|1 |Rn|Vd"},
+ {"inst": "ins|mov Vd.H[#idx1], Vn.H[#idx2]" , "op": "01101110|00|0|idx1:3|10 |0|idx2:3|01 |Rn|Vd"},
+ {"inst": "ins|mov Vd.S[#idx1], Vn.S[#idx2]" , "op": "01101110|00|0|idx1:2|100 |0|idx2:2|001 |Rn|Vd"},
+ {"inst": "ins|mov Vd.D[#idx1], Vn.D[#idx2]" , "op": "01101110|00|0|idx1:1|1000|0|idx2:1|0001|Rn|Vd"},
+ {"inst": "ld1 Vx.B[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|000|idx:3 |Rn|Vx"},
+ {"inst": "ld1 Vx.H[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|010|idx:2| 0|Rn|Vx"},
+ {"inst": "ld1 Vx.S[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|100|idx:1|00|Rn|Vx"},
+ {"inst": "ld1 Vx.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|100| 001|Rn|Vx"},
+ {"inst": "ld1 Vx.B[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |000|idx:3 |Rn|Vx"},
+ {"inst": "ld1 Vx.H[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |010|idx:2| 0|Rn|Vx"},
+ {"inst": "ld1 Vx.S[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |100|idx:1|00|Rn|Vx"},
+ {"inst": "ld1 Vx.D[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |100| 001|Rn|Vx"},
+ {"inst": "ld1 Vx.B[#idx], [Xn|SP, #off=1]@" , "op": "0|idx:1|001101|110|11111|000|idx:3 |Rn|Vx"},
+ {"inst": "ld1 Vx.H[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|110|11111|010|idx:2| 0|Rn|Vx"},
+ {"inst": "ld1 Vx.S[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|110|11111|100|idx:1|00|Rn|Vx"},
+ {"inst": "ld1 Vx.D[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|110|11111|100| 001|Rn|Vx"},
+ {"inst": "ld1 1x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 1x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 2x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 2x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 3x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 3x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 4x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 4x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 1x{Vd.t}, [Xn|SP, #off==8]@" , "op": "00001100|110|11111|0111|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 1x{Vd.t}, [Xn|SP, #off==16]@" , "op": "01001100|110|11111|0111|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 2x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|1010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 2x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|1010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 3x{Vd.t}, [Xn|SP, #off==24]@" , "op": "00001100|110|11111|0110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 3x{Vd.t}, [Xn|SP, #off==48]@" , "op": "01001100|110|11111|0110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1 4x{Vd.t}, [Xn|SP, #off==32]@" , "op": "00001100|110|11111|0010|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1 4x{Vd.t}, [Xn|SP, #off==64]@" , "op": "01001100|110|11111|0010|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1r 1x{Vd.t}, [Xn|SP]" , "op": "00001101|010|00000|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1r 1x{Vd.t}, [Xn|SP]" , "op": "01001101|010|00000|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1r 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|110|Rm |1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1r 1x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|110|Rm |1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld1r 1x{Vd.t}, [Xn|SP, #off==1<<sz]@" , "op": "00001101|110|11111|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld1r 1x{Vd.t}, [Xn|SP, #off==1<<sz]@" , "op": "01001101|110|11111|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld2 2x{Vx.B}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|000|idx:3 |Rn|Vx"},
+ {"inst": "ld2 2x{Vx.H}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|010|idx:2| 0|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.S}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|100|idx:1|00|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.D}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|100| 001|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.B}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |000|idx:3 |Rn|Vx"},
+ {"inst": "ld2 2x{Vx.H}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |010|idx:2| 0|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.S}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |100|idx:1|00|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.D}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|111|Rm |100| 001|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.B}[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|111|11111|000|idx:3 |Rn|Vx"},
+ {"inst": "ld2 2x{Vx.H}[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|111|11111|010|idx:2| 0|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.S}[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|111|11111|100|idx:1|00|Rn|Vx"},
+ {"inst": "ld2 2x{Vx.D}[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|111|11111|100| 001|Rn|Vx"},
+ {"inst": "ld2 2x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|1000|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld2 2x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|1000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld2 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |1000|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld2 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |1000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld2 2x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|1000|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld2 2x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|1000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld2r 2x{Vd.t}, [Xn|SP]" , "op": "00001101|011|00000|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld2r 2x{Vd.t}, [Xn|SP]" , "op": "01001101|011|00000|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld2r 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|111|Rm |1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld2r 2x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|111|Rm |1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld2r 2x{Vd.t}, [Xn|SP, #off==2<<sz]@" , "op": "00001101|111|11111|1100|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld2r 2x{Vd.t}, [Xn|SP, #off==2<<sz]@" , "op": "01001101|111|11111|1100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld3 3x{Vx.B}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|001|idx:3 |Rn|Vx"},
+ {"inst": "ld3 3x{Vx.H}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|011|idx:2| 0|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.S}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|101|idx:1|00|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.D}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00000|101| 001|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.B}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |001|idx:3 |Rn|Vx"},
+ {"inst": "ld3 3x{Vx.H}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |011|idx:2| 0|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.S}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101|idx:1|00|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.D}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101| 001|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.B}[#idx], [Xn|SP, #off=3]@" , "op": "0|idx:1|001101|110|11111|001|idx:3 |Rn|Vx"},
+ {"inst": "ld3 3x{Vx.H}[#idx], [Xn|SP, #off=6]@" , "op": "0|idx:1|001101|110|11111|011|idx:2| 0|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.S}[#idx], [Xn|SP, #off=12]@" , "op": "0|idx:1|001101|110|11111|101|idx:1|00|Rn|Vx"},
+ {"inst": "ld3 3x{Vx.D}[#idx], [Xn|SP, #off=24]@" , "op": "0|idx:1|001101|110|11111|101| 001|Rn|Vx"},
+ {"inst": "ld3 3x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0100|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld3 3x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld3 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0100|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld3 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld3 3x{Vd.t}, [Xn|SP, #off==16]@" , "op": "00001100|110|11111|0100|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld3 3x{Vd.t}, [Xn|SP, #off==32]@" , "op": "01001100|110|11111|0100|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld3r 3x{Vd.t}, [Xn|SP]" , "op": "00001101|010|00000|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld3r 3x{Vd.t}, [Xn|SP]" , "op": "01001101|010|00000|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld3r 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|110|Rm |1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld3r 3x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|110|Rm |1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld3r 3x{Vd.t}, [Xn|SP, #off==3<<sz]@" , "op": "00001101|110|11111|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld3r 3x{Vd.t}, [Xn|SP, #off==3<<sz]@" , "op": "01001101|110|11111|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld4 4x{Vx.B}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|001|idx:3 |Rn|Vx"},
+ {"inst": "ld4 4x{Vx.H}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|011|idx:2| 0|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.S}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|101|idx:1|00|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.D}[#idx], [Xn|SP]" , "op": "0|idx:1|001101|011|00000|101| 001|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.B}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |001|idx:3 |Rn|Vx"},
+ {"inst": "ld4 4x{Vx.H}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |011|idx:2| 0|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.S}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101|idx:1|00|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.D}[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|110|Rm |101| 001|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.B}[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|110|11111|001|idx:3 |Rn|Vx"},
+ {"inst": "ld4 4x{Vx.H}[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|110|11111|011|idx:2| 0|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.S}[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|110|11111|101|idx:1|00|Rn|Vx"},
+ {"inst": "ld4 4x{Vx.D}[#idx], [Xn|SP, #off=32]@" , "op": "0|idx:1|001101|110|11111|101| 001|Rn|Vx"},
+ {"inst": "ld4 4x{Vd.t}, [Xn|SP]" , "op": "00001100|010|00000|0000|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld4 4x{Vd.t}, [Xn|SP]" , "op": "01001100|010|00000|0000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld4 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001100|110|Rm |0000|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld4 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001100|110|Rm |0000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld4 4x{Vd.t}, [Xn|SP, #off==32]@" , "op": "00001100|110|11111|0000|sz|Rn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "ld4 4x{Vd.t}, [Xn|SP, #off==64]@" , "op": "01001100|110|11111|0000|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld4r 4x{Vd.t}, [Xn|SP]" , "op": "00001101|011|00000|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld4r 4x{Vd.t}, [Xn|SP]" , "op": "01001101|011|00000|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld4r 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "00001101|111|Rm |1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld4r 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|111|Rm |1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@" , "op": "00001101|111|11111|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
+ {"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@" , "op": "01001101|111|11111|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "ldnp Sd, Sd2, [Xn|SP, #offS*4]" , "op": "00101100|01|offS:7|Vd2|Vn|Vd"},
+ {"inst": "ldnp Dd, Dd2, [Xn|SP, #offS*8]" , "op": "01101100|01|offS:7|Vd2|Vn|Vd"},
+ {"inst": "ldnp Qd, Qd2, [Xn|SP, #offS*16]" , "op": "10101100|01|offS:7|Vd2|Vn|Vd"},
+ {"inst": "ldp Sd, Sd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010110|!post|W|1|offS:7|Vd2|Vn|Vd"},
+ {"inst": "ldp Dd, Dd2, [Xn|SP, #offS*8]{@}{!}" , "op": "0110110|!post|W|1|offS:7|Vd2|Vn|Vd"},
+ {"inst": "ldp Qd, Qd2, [Xn|SP, #offS*16]{@}{!}" , "op": "1010110|!post|W|1|offS:7|Vd2|Vn|Vd"},
+ {"inst": "ldr Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111100|011|Rm|option:3|n:1|10|Rn|Vd"},
+ {"inst": "ldr Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111100|011|Rm|option:3|n:1|10|Rn|Vd"},
+ {"inst": "ldr Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]" , "op": "10111100|011|Rm|option:3|n:1|10|Rn|Vd"},
+ {"inst": "ldr Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]" , "op": "11111100|011|Rm|option:3|n:1|10|Rn|Vd"},
+ {"inst": "ldr Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]" , "op": "00111100|111|Rm|option:3|n:1|10|Rn|Vd"},
+ {"inst": "ldr Sd, [PC, #offS*4]" , "op": "00011100|offS:19|Vd"},
+ {"inst": "ldr Dd, [PC, #offS*4]" , "op": "01011100|offS:19|Vd"},
+ {"inst": "ldr Qd, [PC, #offS*4]" , "op": "10011100|offS:19|Vd"},
+ {"inst": "ldr Bd, [Xn|SP, #offZ]" , "op": "00111101|01|offZ:12|Rn|Vd"},
+ {"inst": "ldr Hd, [Xn|SP, #offZ*2]" , "op": "01111101|01|offZ:12|Rn|Vd"},
+ {"inst": "ldr Sd, [Xn|SP, #offZ*4]" , "op": "10111101|01|offZ:12|Rn|Vd"},
+ {"inst": "ldr Dd, [Xn|SP, #offZ*8]" , "op": "11111101|01|offZ:12|Rn|Vd"},
+ {"inst": "ldr Qd, [Xn|SP, #offZ*16]" , "op": "00111101|11|offZ:12|Rn|Vd"},
+ {"inst": "ldr Bd, [Xn|SP, #offS]!" , "op": "00111100|010|offS:9|11|Rn|Vd"},
+ {"inst": "ldr Hd, [Xn|SP, #offS*2]!" , "op": "01111100|010|offS:9|11|Rn|Vd"},
+ {"inst": "ldr Sd, [Xn|SP, #offS*4]!" , "op": "10111100|010|offS:9|11|Rn|Vd"},
+ {"inst": "ldr Dd, [Xn|SP, #offS*8]!" , "op": "11111100|010|offS:9|11|Rn|Vd"},
+ {"inst": "ldr Qd, [Xn|SP, #offS*16]!" , "op": "00111100|110|offS:9|11|Rn|Vd"},
+ {"inst": "ldr Bd, [Xn|SP, #offS]@" , "op": "00111100|010|offS:9|01|Rn|Vd"},
+ {"inst": "ldr Hd, [Xn|SP, #offS*2]@" , "op": "01111100|010|offS:9|01|Rn|Vd"},
+ {"inst": "ldr Sd, [Xn|SP, #offS*4]@" , "op": "10111100|010|offS:9|01|Rn|Vd"},
+ {"inst": "ldr Dd, [Xn|SP, #offS*8]@" , "op": "11111100|010|offS:9|01|Rn|Vd"},
+ {"inst": "ldr Qd, [Xn|SP, #offS*16]@" , "op": "00111100|110|offS:9|01|Rn|Vd"},
+ {"inst": "ldur Bd, [Xn|SP, #offS]" , "op": "00111100|010|offS:9|00|Rn|Vd"},
+ {"inst": "ldur Hd, [Xn|SP, #offS]" , "op": "01111100|010|offS:9|00|Rn|Vd"},
+ {"inst": "ldur Sd, [Xn|SP, #offS]" , "op": "10111100|010|offS:9|00|Rn|Vd"},
+ {"inst": "ldur Dd, [Xn|SP, #offS]" , "op": "11111100|010|offS:9|00|Rn|Vd"},
+ {"inst": "ldur Qd, [Xn|SP, #offS]" , "op": "00111100|110|offS:9|00|Rn|Vd"},
+ {"inst": "mla Vx.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10010|1|Vn|Vx" , "t": "8B 4H 2S"},
+ {"inst": "mla Vx.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10010|1|Vn|Vx" , "t": "16B 8H 4S"},
+ {"inst": "mla Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
+ {"inst": "mla Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
+ {"inst": "mla Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|0000|idx[1]|0|Vn|Vx"},
+ {"inst": "mla Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|0000|idx[1]|0|Vn|Vx"},
+ {"inst": "mls Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10010|1|Vn|Vx" , "t": "8B 4H 2S"},
+ {"inst": "mls Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10010|1|Vn|Vx" , "t": "16B 8H 4S"},
+ {"inst": "mls Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0100|idx[2]|0|Vn|Vx"},
+ {"inst": "mls Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|0100|idx[2]|0|Vn|Vx"},
+ {"inst": "mls Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0]|Vm|0100|idx[1]|0|Vn|Vx"},
+ {"inst": "mls Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0]|Vm|0100|idx[1]|0|Vn|Vx"},
+ {"inst": "mov Vd.8B, Vn.8B" , "op": "00001110|10|1|Vn|00011|1|Vn|Vd"},
+ {"inst": "mov Vd.16B, Vn.16B" , "op": "01001110|10|1|Vn|00011|1|Vn|Vd"},
+ {"inst": "movi Dd, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovPImm(0, imm, n)"},
+ {"inst": "movi Vd.t, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovPImm(sz, imm, n)", "t": "8B 4H 2S"},
+ {"inst": "movi Vd.t, #imm, {lsl #n}" , "op": "01|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovPImm(sz, imm, n)", "t": "16B 8H 4S 2D"},
+ {"inst": "mul Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10011|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "mul Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10011|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "mul Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1000|idx[2]|0|Vn|Vd"},
+ {"inst": "mul Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1000|idx[2]|0|Vn|Vd"},
+ {"inst": "mul Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0]|Vm|1000|idx[1]|0|Vn|Vd"},
+ {"inst": "mul Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0]|Vm|1000|idx[1]|0|Vn|Vd"},
+ {"inst": "mvni Dd, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovNImm(0, imm, n)"},
+ {"inst": "mvni Vd.t, #imm, {lsl #n}" , "op": "00|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovNImm(sz, imm, n)", "t": "8B 4H 2S"},
+ {"inst": "mvni Vd.t, #imm, {lsl #n}" , "op": "01|op:1|01111|00|0|00|abc:3|cmode:4|01|defgh:5|Vd" , "imm": "ASimdMovNImm(sz, imm, n)", "t": "16B 8H 4S 2D"},
+ {"inst": "neg Dd, Dn" , "op": "01111110|11|10000|01011|10|Vn|Vd"},
+ {"inst": "neg Vd.t, Vn.t" , "op": "00101110|sz|10000|01011|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "neg Vd.t, Vn.t" , "op": "01101110|sz|10000|01011|10|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "not|mvn Vd.8B, Vn.8B" , "op": "00101110|00|10000|00101|10|Vn|Vd"},
+ {"inst": "not|mvn Vd.16B, Vn.16B" , "op": "01101110|00|10000|00101|10|Vn|Vd"},
+ {"inst": "orn Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|11|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "orn Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|11|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "orr Vd.8B, Vn.8B, Vm.8B" , "op": "00001110|10|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "orr Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|10|1|Vm|00011|1|Vn|Vd"},
+ {"inst": "orr Vd.t, #imm, {lsl #n}" , "op": "00001111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "4H 2S", "imm": "ASimdLogicalImm(sz, 0, imm, n)"},
+ {"inst": "orr Vd.t, #imm, {lsl #n}" , "op": "01001111|00000|abc:3|cmode:4|01|defgh:5|Vd" , "t": "8H 4S", "imm": "ASimdLogicalImm(sz, 0, imm, n)"},
+ {"inst": "pmul Vd.8B, Vn.8B, Vm.8B" , "op": "00101110|00|1|Vm|10011|1|Vn|Vd"},
+ {"inst": "pmul Vd.16B, Vn.16B, Vm.16B" , "op": "01101110|00|1|Vm|10011|1|Vn|Vd"},
+ {"inst": "pmull Vd.8H, Vn.8B, Vm.8B" , "op": "00001110|00|1|Vm|11100|0|Vn|Vd"},
+ {"inst": "pmull Vd.1Q, Vn.1D, Vm.1D" , "op": "00001110|11|1|Vm|11100|0|Vn|Vd"},
+ {"inst": "pmull2 Vd.8H, Vn.16B, Vm.16B" , "op": "01001110|00|1|Vm|11100|0|Vn|Vd"},
+ {"inst": "pmull2 Vd.1Q, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11100|0|Vn|Vd"},
+ {"inst": "raddhn Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01000|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "raddhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01000|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "rbit Vd.8B, Vn.8B" , "op": "00101110|01|10000|00101|10|Vn|Vd"},
+ {"inst": "rbit Vd.16B, Vn.16B" , "op": "01101110|01|10000|00101|10|Vn|Vd"},
+ {"inst": "rev16 Vd.8B, Vn.8B" , "op": "00001110|sz|10000|00001|10|Vn|Vd"},
+ {"inst": "rev16 Vd.16B, Vn.16B" , "op": "01001110|sz|10000|00001|10|Vn|Vd"},
+ {"inst": "rev32 Vd.t, Vn.t" , "op": "00101110|sz|10000|00000|10|Vn|Vd" , "t": "8B 4H"},
+ {"inst": "rev32 Vd.t, Vn.t" , "op": "01101110|sz|10000|00000|10|Vn|Vd" , "t": "16B 8H"},
+ {"inst": "rev64 Vd.t, Vn.t" , "op": "00001110|sz|10000|00000|10|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "rev64 Vd.t, Vn.t" , "op": "01001110|sz|10000|00000|10|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "rshrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10001|1|Vn|Vd" , "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "rshrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10001|1|Vn|Vx" , "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "rsubhn Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01100|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "rsubhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01100|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "saba Vx.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01111|1|Vn|Vx" , "t": "8B 4H 2S"},
+ {"inst": "saba Vx.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01111|1|Vn|Vx" , "t": "16B 8H 4S"},
+ {"inst": "sabal Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "sabal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "sabd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01110|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "sabd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01110|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "sabdl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "sabdl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "sadalp Vx.ta, Vn.tb" , "op": "00001110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
+ {"inst": "sadalp Vx.ta, Vn.tb" , "op": "01001110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "saddl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "saddl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "saddlp Vd.ta, Vn.tb" , "op": "00001110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
+ {"inst": "saddlp Vd.ta, Vn.tb" , "op": "01001110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "saddlv Hd, Vn.8B" , "op": "00001110|00|11000|00011|10|Vn|Vd"},
+ {"inst": "saddlv Hd, Vn.16B" , "op": "01001110|00|11000|00011|10|Vn|Vd"},
+ {"inst": "saddlv Sd, Vn.4H" , "op": "00001110|01|11000|00011|10|Vn|Vd"},
+ {"inst": "saddlv Sd, Vn.8H" , "op": "01001110|01|11000|00011|10|Vn|Vd"},
+ {"inst": "saddlv Dd, Vn.4S" , "op": "01001110|10|11000|00011|10|Vn|Vd"},
+ {"inst": "saddw Vd.ta, Vn.ta, Vm.tb" , "op": "00001110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "saddw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01001110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "scvtf Sd, Wn" , "op": "00011110|00|1|00010|00000|0|Rn|Vd"},
+ {"inst": "scvtf Sd, Wn, #fbits" , "op": "00011110|00|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "scvtf Sd, Xn" , "op": "10011110|00|1|00010|00000|0|Rn|Vd"},
+ {"inst": "scvtf Sd, Xn, #fbits" , "op": "10011110|00|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "scvtf Sd, Sn" , "op": "01011110|00|10000|11101|10|Vn|Vd"},
+ {"inst": "scvtf Sd, Sn, #bits" , "op": "01011111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "scvtf Dd, Wn" , "op": "00011110|01|1|00010|00000|0|Rn|Vd"},
+ {"inst": "scvtf Dd, Wn, #fbits" , "op": "00011110|01|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "scvtf Dd, Xn" , "op": "10011110|01|1|00010|00000|0|Rn|Vd"},
+ {"inst": "scvtf Dd, Xn, #fbits" , "op": "10011110|01|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "scvtf Dd, Dn" , "op": "01011110|01|10000|11101|10|Vn|Vd"},
+ {"inst": "scvtf Dd, Dn, #bits" , "op": "01011111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "scvtf Vd.2S, Vn.2S" , "op": "00001110|00|10000|11101|10|Vn|Vd"},
+ {"inst": "scvtf Vd.4S, Vn.4S" , "op": "01001110|00|10000|11101|10|Vn|Vd"},
+ {"inst": "scvtf Vd.2D, Vn.2D" , "op": "01001110|01|10000|11101|10|Vn|Vd"},
+ {"inst": "scvtf Vd.2S, Vn.2S, #fbits" , "op": "00001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "scvtf Vd.4S, Vn.4S, #fbits" , "op": "01001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "scvtf Vd.2D, Vn.2D, #fbits" , "op": "01001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "shadd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00000|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "shadd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00000|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "shl Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|01010|1|Vn|Vd" , "imm": "ASimdSHL(n, 3)"},
+ {"inst": "shl Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|01010|1|Vn|Vd" , "imm": "ASimdSHL(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "shl Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|01010|1|Vn|Vd" , "imm": "ASimdSHL(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "shll Vd.8H, Vn.8B, #8" , "op": "00101110|00|10000|10011|10|Vn|Vd"},
+ {"inst": "shll2 Vd.8H, Vn.16B, #8" , "op": "01101110|00|10000|10011|10|Vn|Vd"},
+ {"inst": "shll Vd.4S, Vn.4H, #16" , "op": "00101110|01|10000|10011|10|Vn|Vd"},
+ {"inst": "shll2 Vd.4S, Vn.8H, #16" , "op": "01101110|01|10000|10011|10|Vn|Vd"},
+ {"inst": "shll Vd.2D, Vn.2S, #32" , "op": "00101110|10|10000|10011|10|Vn|Vd"},
+ {"inst": "shll2 Vd.2D, Vn.4S, #32" , "op": "01101110|10|10000|10011|10|Vn|Vd"},
+ {"inst": "shrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|100001|Vn|Vd" , "imm": "ASimdSHRN(n, sz)", "t": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "shrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|100001|Vn|Vx" , "imm": "ASimdSHRN(n, sz)", "t": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "shsub Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00100|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "shsub Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00100|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "sli Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
+ {"inst": "sli Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "sli Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "smax Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01100|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "smax Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01100|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "smaxp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10100|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "smaxp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10100|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "smaxv Bd, Vn.8B" , "op": "00001110|00|11000|01010|10|Vn|Vd"},
+ {"inst": "smaxv Bd, Vn.16B" , "op": "01001110|00|11000|01010|10|Vn|Vd"},
+ {"inst": "smaxv Hd, Vn.4H" , "op": "00001110|01|11000|01010|10|Vn|Vd"},
+ {"inst": "smaxv Hd, Vn.8H" , "op": "01001110|01|11000|01010|10|Vn|Vd"},
+ {"inst": "smaxv Sd, Vn.4S" , "op": "01001110|10|11000|01010|10|Vn|Vd"},
+ {"inst": "smin Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01101|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "smin Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01101|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "sminp Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10101|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "sminp Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10101|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "sminv Bd, Vn.8B" , "op": "00001110|00|11000|11010|10|Vn|Vd"},
+ {"inst": "sminv Bd, Vn.16B" , "op": "01001110|00|11000|11010|10|Vn|Vd"},
+ {"inst": "sminv Hd, Vn.4H" , "op": "00001110|01|11000|11010|10|Vn|Vd"},
+ {"inst": "sminv Hd, Vn.8H" , "op": "01001110|01|11000|11010|10|Vn|Vd"},
+ {"inst": "sminv Sd, Vn.4S" , "op": "01001110|10|11000|11010|10|Vn|Vd"},
+ {"inst": "smlal Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10000|0|Vn|Vx" , "t": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "smlal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10000|0|Vn|Vx" , "t": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "smlal Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vx"},
+ {"inst": "smlal2 Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vx"},
+ {"inst": "smlal Vx.2D, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vx"},
+ {"inst": "smlal2 Vx.2D, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vx"},
+ {"inst": "smlsl Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10100|0|Vn|Vx" , "t": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "smlsl2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10100|0|Vn|Vx" , "t": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "smlsl Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vx"},
+ {"inst": "smlsl2 Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vx"},
+ {"inst": "smlsl Vx.2D, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vx"},
+ {"inst": "smlsl2 Vx.2D, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vx"},
+ {"inst": "smov Wd, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00101|1|Vn|Rd"},
+ {"inst": "smov Wd, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00101|1|Vn|Rd"},
+ {"inst": "smov Xd, Vn.B[#idx]" , "op": "01001110|00|0|idx:4| 1|00101|1|Vn|Rd"},
+ {"inst": "smov Xd, Vn.H[#idx]" , "op": "01001110|00|0|idx:3| 10|00101|1|Vn|Rd"},
+ {"inst": "smov Xd, Vn.S[#idx]" , "op": "01001110|00|0|idx:2|100|00101|1|Vn|Rd"},
+ {"inst": "smull Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "smull2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "smull Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
+ {"inst": "smull2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
+ {"inst": "smull Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
+ {"inst": "smull2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
+ {"inst": "sqabs Bd, Bn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqabs Hd, Hn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqabs Sd, Sn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqabs Dd, Dn" , "op": "01011110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqabs Vd.t, Vn.t" , "op": "00001110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "sqabs Vd.t, Vn.t" , "op": "01001110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sqadd Bd, Bn, Bm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqadd Hd, Hn, Hm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqadd Sd, Sn, Sm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqadd Dd, Dn, Dm" , "op": "01011110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqadd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "sqadd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sqdmlal Sx, Hn, Hm" , "op": "01011110|01|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal Dx, Sn, Sm" , "op": "01011110|10|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal Sx, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0011|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal Dx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0011|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.4H 2D.2S"},
+ {"inst": "sqdmlal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10010|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.8H 2D.4S"},
+ {"inst": "sqdmlal Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "00011111|01|idx[1:0]|Vm:4|0011|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal2 Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0011|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal Vx.2D, Vn.2S, Vm.S[#idx]" , "op": "00011111|10|idx[0] |Vm |0011|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlal2 Vx.2D, Vn.4S, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0011|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl Sx, Hn, Hm" , "op": "01011110|01|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl Dx, Sn, Sm" , "op": "01011110|10|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl Sx, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl Dx, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.4H 2D.2S"},
+ {"inst": "sqdmlsl2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10110|0|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "4S.8H 2D.4S"},
+ {"inst": "sqdmlsl Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "00011111|01|idx[1:0]|Vm:4|0111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl2 Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|0111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl Vx.2D, Vn.2S, Vm.S[#idx]" , "op": "00011111|10|idx[0] |Vm |0111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmlsl2 Vx.2D, Vn.4S, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |0111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Hd, Hn, Hm" , "op": "01011110|01|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Sd, Sn, Sm" , "op": "01011110|10|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Hd, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|1100|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |1100|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 4H 2S"},
+ {"inst": "sqdmulh Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 8H 4S"},
+ {"inst": "sqdmulh Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1100|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1100|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1100|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmulh Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1100|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull Sd, Hn, Hm" , "op": "01011110|01|1|Vm|11010|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull Dd, Sn, Sm" , "op": "01011110|10|1|Vm|11010|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull Sd, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|1011|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull Dd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |1011|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "~ 4S.4H 2D.2S"},
+ {"inst": "sqdmull2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "~ 4S.8H 2D.4S"},
+ {"inst": "sqdmull Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1011|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1011|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1011|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqdmull2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1011|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqneg Bd, Bn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqneg Hd, Hn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqneg Sd, Sn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqneg Dd, Dn" , "op": "01111110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqneg Vd.t, Vn.t" , "op": "00101110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "sqneg Vd.t, Vn.t" , "op": "01101110|sz|10000|00111|10|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sqrdmulh Hd, Hn, Hm" , "op": "01111110|01|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Sd, Sn, Sm" , "op": "01111110|10|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Hd, Hn, Vm.H[#idx]" , "op": "01011111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Sd, Sn, Vm.S[#idx]" , "op": "01011111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 4H 2S"},
+ {"inst": "sqrdmulh Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10110|1|Vn|Vd" , "io": "QC|=SAT", "t": "~ 8H 4S"},
+ {"inst": "sqrdmulh Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Vd.2S, Vn.2S, Vm.S[#idx]" , "op": "00001111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrdmulh Vd.4S, Vn.4S, Vm.S[#idx]" , "op": "01001111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrshl Bd, Bn, Bm" , "op": "01011110|00|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrshl Hd, Hn, Hm" , "op": "01011110|01|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrshl Sd, Sn, Sm" , "op": "01011110|10|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqrshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "sqrshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sqrshrn Bd, Hn, #n" , "op": "01011111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqrshrn Hd, Sn, #n" , "op": "01011111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqrshrn Sd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqrshrn Vd.8B, Vn.8H, #n" , "op": "00001111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqrshrn2 Vx.16B, Vn.8H, #n" , "op": "01001111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqrshrn Vd.4H, Vn.4S, #n" , "op": "00001111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqrshrn2 Vx.8H, Vn.4S, #n" , "op": "01001111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqrshrn Vd.2S, Vn.2D, #n" , "op": "00001111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqrshrn2 Vx.4S, Vn.2D, #n" , "op": "01001111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqrshrun Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqrshrun Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqrshrun Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqrshrun Vd.8B, Vn.8H, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqrshrun2 Vx.16B, Vn.8H, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqrshrun Vd.4H, Vn.4S, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqrshrun2 Vx.8H, Vn.4S, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqrshrun Vd.2S, Vn.2D, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqrshrun2 Vx.4S, Vn.2D, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqshl Bd, Bn, Bm" , "op": "01011110|00|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqshl Hd, Hn, Hm" , "op": "01011110|01|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqshl Sd, Sn, Sm" , "op": "01011110|10|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqshl Bd, Bn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 0)"},
+ {"inst": "sqshl Hd, Hn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 1)"},
+ {"inst": "sqshl Sd, Sn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 2)"},
+ {"inst": "sqshl Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
+ {"inst": "sqshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "sqshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sqshl Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "sqshl Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "sqshlu Bd, Bn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 0)"},
+ {"inst": "sqshlu Hd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 1)"},
+ {"inst": "sqshlu Sd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 2)"},
+ {"inst": "sqshlu Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
+ {"inst": "sqshlu Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "sqshlu Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "sqshrn Bd, Hn, #n" , "op": "01011111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqshrn Hd, Sn, #n" , "op": "01011111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqshrn Sd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqshrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)", "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "sqshrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)", "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "sqshrun Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqshrun Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqshrun Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqshrun Vd.8B, Vn.8H, #n" , "op": "00101111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqshrun2 Vx.16B, Vn.8H, #n" , "op": "01101111|0|immh:4|immb:3|10000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "sqshrun Vd.4H, Vn.4S, #n" , "op": "00101111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqshrun2 Vx.8H, Vn.4S, #n" , "op": "01101111|0|immh:4|immb:3|10000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "sqshrun Vd.2S, Vn.2D, #n" , "op": "00101111|0|immh:4|immb:3|10000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqshrun2 Vx.4S, Vn.2D, #n" , "op": "01101111|0|immh:4|immb:3|10000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "sqsub Bd, Bn, Bm" , "op": "01011110|00|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqsub Hd, Hn, Hm" , "op": "01011110|01|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqsub Sd, Sn, Sm" , "op": "01011110|10|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqsub Dd, Dn, Dm" , "op": "01011110|11|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqsub Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "sqsub Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sqxtn Bd, Hn" , "op": "01011110|00|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqxtn Hd, Sn" , "op": "01011110|01|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqxtn Sd, Dn" , "op": "01011110|10|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqxtn Vd.ta, Vn.tb" , "op": "00001110|sz|10000|10100|10|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "sqxtn2 Vx.ta, Vn.tb" , "op": "01001110|sz|10000|10100|10|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "sqxtun Bd, Hn" , "op": "01011110|00|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqxtun Hd, Sn" , "op": "01011110|01|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqxtun Sd, Dn" , "op": "01011110|10|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sqxtun Vd.ta, Vn.tb" , "op": "00001110|sz|10000|10100|10|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "sqxtun2 Vx.ta, Vn.tb" , "op": "01001110|sz|10000|10100|10|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "srhadd Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|00010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "srhadd Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|00010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "sri Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "sri Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "sri Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01000|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "srshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "srshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "srshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "srshr Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "srshr Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "srshr Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "srsra Dx, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "srsra Vx.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "srsra Vx.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "sshl Dd, Dn, Dm" , "op": "01011110|11|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "sshl Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "sshl Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sshll Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "sshll2 Vd.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "sshr Dd, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "sshr Vd.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "sshr Vd.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "ssra Dx, Dn, #n" , "op": "01011111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "ssra Vx.t, Vn.t, #n" , "op": "00001111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "ssra Vx.t, Vn.t, #n" , "op": "01001111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "ssubl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "ssubl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "ssubw Vd.ta, Vn.ta, Vm.tb" , "op": "00001110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "ssubw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01001110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "st1 Vs.B[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|000|idx:3 |Rn|Vs"},
+ {"inst": "st1 Vs.H[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|010|idx:2| 0|Rn|Vs"},
+ {"inst": "st1 Vs.S[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|100|idx:1|00|Rn|Vs"},
+ {"inst": "st1 Vs.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|100| 001|Rn|Vs"},
+ {"inst": "st1 Vs.B[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |000|idx:3 |Rn|Vs"},
+ {"inst": "st1 Vs.H[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |010|idx:2| 0|Rn|Vs"},
+ {"inst": "st1 Vs.S[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |100|idx:1|00|Rn|Vs"},
+ {"inst": "st1 Vs.D[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |100| 001|Rn|Vs"},
+ {"inst": "st1 Vs.B[#idx], [Xn|SP, #off=1]@" , "op": "0|idx:1|001101|100|11111|000|idx:3 |Rn|Vs"},
+ {"inst": "st1 Vs.H[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|100|11111|010|idx:2| 0|Rn|Vs"},
+ {"inst": "st1 Vs.S[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|100|11111|100|idx:1|00|Rn|Vs"},
+ {"inst": "st1 Vs.D[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|100|11111|100| 001|Rn|Vs"},
+ {"inst": "st1 1x{Vs.t}, [Xn|SP]" , "op": "00001100|000|00000|0111|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 1x{Vs.t}, [Xn|SP]" , "op": "01001100|000|00000|0111|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 2x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|1010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 2x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|1010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 3x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0110|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 3x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0110|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 4x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 4x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 1x{Vs.t}, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0111|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 1x{Vs.t}, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0111|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |1010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |1010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0110|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0110|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 1x{Vs.t}, [Xn|SP, #off==8]@" , "op": "00001100|100|11111|0111|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 1x{Vs.t}, [Xn|SP, #off==16]@" , "op": "01001100|100|11111|0111|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 2x{Vs.t}+, [Xn|SP, #off==16]@" , "op": "00001100|100|11111|1010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 2x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "01001100|100|11111|1010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 3x{Vs.t}+, [Xn|SP, #off==24]@" , "op": "00001100|100|11111|0110|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 3x{Vs.t}+, [Xn|SP, #off==48]@" , "op": "01001100|100|11111|0110|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st1 4x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "00001100|100|11111|0010|sz|Rn|Vs" , "t": "8B 4H 2S 1D"},
+ {"inst": "st1 4x{Vs.t}+, [Xn|SP, #off==64]@" , "op": "01001100|100|11111|0010|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st2 2x{Vs.B}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|000|idx:3 |Rn|Vs"},
+ {"inst": "st2 2x{Vs.H}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|010|idx:2| 0|Rn|Vs"},
+ {"inst": "st2 2x{Vs.S}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|100|idx:1|00|Rn|Vs"},
+ {"inst": "st2 2x{Vs.D}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|100| 001|Rn|Vs"},
+ {"inst": "st2 2x{Vs.B}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |000|idx:3 |Rn|Vs"},
+ {"inst": "st2 2x{Vs.H}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |010|idx:2| 0|Rn|Vs"},
+ {"inst": "st2 2x{Vs.S}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |100|idx:1|00|Rn|Vs"},
+ {"inst": "st2 2x{Vs.D}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|101|Rm |100| 001|Rn|Vs"},
+ {"inst": "st2 2x{Vs.B}+[#idx], [Xn|SP, #off=2]@" , "op": "0|idx:1|001101|101|11111|000|idx:3 |Rn|Vs"},
+ {"inst": "st2 2x{Vs.H}+[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|101|11111|010|idx:2| 0|Rn|Vs"},
+ {"inst": "st2 2x{Vs.S}+[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|101|11111|100|idx:1|00|Rn|Vs"},
+ {"inst": "st2 2x{Vs.D}+[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|101|11111|100| 001|Rn|Vs"},
+ {"inst": "st2 2x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|1000|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st2 2x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|1000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st2 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |1000|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st2 2x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |1000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st2 2x{Vs.t}+, [Xn|SP, #off==16]@" , "op": "00001100|100|11111|1000|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st2 2x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "01001100|100|11111|1000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st3 3x{Vs.B}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|001|idx:3 |Rn|Vs"},
+ {"inst": "st3 3x{Vs.H}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|011|idx:2| 0|Rn|Vs"},
+ {"inst": "st3 3x{Vs.S}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|101|idx:1|00|Rn|Vs"},
+ {"inst": "st3 3x{Vs.D}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00000|101| 001|Rn|Vs"},
+ {"inst": "st3 3x{Vs.B}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |001|idx:3 |Rn|Vs"},
+ {"inst": "st3 3x{Vs.H}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |011|idx:2| 0|Rn|Vs"},
+ {"inst": "st3 3x{Vs.S}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101|idx:1|00|Rn|Vs"},
+ {"inst": "st3 3x{Vs.D}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101| 001|Rn|Vs"},
+ {"inst": "st3 3x{Vs.B}+[#idx], [Xn|SP, #off=3]@" , "op": "0|idx:1|001101|100|11111|001|idx:3 |Rn|Vs"},
+ {"inst": "st3 3x{Vs.H}+[#idx], [Xn|SP, #off=6]@" , "op": "0|idx:1|001101|100|11111|011|idx:2| 0|Rn|Vs"},
+ {"inst": "st3 3x{Vs.S}+[#idx], [Xn|SP, #off=12]@" , "op": "0|idx:1|001101|100|11111|101|idx:1|00|Rn|Vs"},
+ {"inst": "st3 3x{Vs.D}+[#idx], [Xn|SP, #off=24]@" , "op": "0|idx:1|001101|100|11111|101| 001|Rn|Vs"},
+ {"inst": "st3 3x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0100|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st3 3x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0100|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st3 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0100|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st3 3x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0100|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st3 3x{Vs.t}+, [Xn|SP, #off==16]@" , "op": "00001100|100|11111|0100|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st3 3x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "01001100|100|11111|0100|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st4 4x{Vs.B}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|001|idx:3 |Rn|Vs"},
+ {"inst": "st4 4x{Vs.H}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|011|idx:2| 0|Rn|Vs"},
+ {"inst": "st4 4x{Vs.S}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|101|idx:1|00|Rn|Vs"},
+ {"inst": "st4 4x{Vs.D}+[#idx], [Xn|SP]" , "op": "0|idx:1|001101|001|00000|101| 001|Rn|Vs"},
+ {"inst": "st4 4x{Vs.B}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |001|idx:3 |Rn|Vs"},
+ {"inst": "st4 4x{Vs.H}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |011|idx:2| 0|Rn|Vs"},
+ {"inst": "st4 4x{Vs.S}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101|idx:1|00|Rn|Vs"},
+ {"inst": "st4 4x{Vs.D}+[#idx], [Xn|SP, Xm]@" , "op": "0|idx:1|001101|100|Rm |101| 001|Rn|Vs"},
+ {"inst": "st4 4x{Vs.B}+[#idx], [Xn|SP, #off=4]@" , "op": "0|idx:1|001101|100|11111|001|idx:3 |Rn|Vs"},
+ {"inst": "st4 4x{Vs.H}+[#idx], [Xn|SP, #off=8]@" , "op": "0|idx:1|001101|100|11111|011|idx:2| 0|Rn|Vs"},
+ {"inst": "st4 4x{Vs.S}+[#idx], [Xn|SP, #off=16]@" , "op": "0|idx:1|001101|100|11111|101|idx:1|00|Rn|Vs"},
+ {"inst": "st4 4x{Vs.D}+[#idx], [Xn|SP, #off=32]@" , "op": "0|idx:1|001101|100|11111|101| 001|Rn|Vs"},
+ {"inst": "st4 4x{Vs.t}+, [Xn|SP]" , "op": "00001100|000|00000|0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st4 4x{Vs.t}+, [Xn|SP]" , "op": "01001100|000|00000|0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st4 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "00001100|100|Rm |0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st4 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "00001100|100|11111|0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
+ {"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==64]@" , "op": "01001100|100|11111|0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
+ {"inst": "stnp Sd, Sd2, [Xn|SP, #offS*4]" , "op": "00101100|00|offS:7|Vs2|Vn|Vs"},
+ {"inst": "stnp Dd, Dd2, [Xn|SP, #offS*8]" , "op": "01101100|00|offS:7|Vs2|Vn|Vs"},
+ {"inst": "stnp Qd, Qd2, [Xn|SP, #offS*16]" , "op": "10101100|00|offS:7|Vs2|Vn|Vs"},
+ {"inst": "stp Sd, Sd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010110|!post|W|0|offS:7|Vs2|Vn|Vs"},
+ {"inst": "stp Dd, Dd2, [Xn|SP, #offS*8]{@}{!}" , "op": "0110110|!post|W|0|offS:7|Vs2|Vn|Vs"},
+ {"inst": "stp Qd, Qd2, [Xn|SP, #offS*16]{@}{!}" , "op": "1010110|!post|W|0|offS:7|Vs2|Vn|Vs"},
+ {"inst": "str Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111100|001|Rm|option:3|n:1|10|Rn|Vs"},
+ {"inst": "str Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111100|001|Rm|option:3|n:1|10|Rn|Vs"},
+ {"inst": "str Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]" , "op": "10111100|001|Rm|option:3|n:1|10|Rn|Vs"},
+ {"inst": "str Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]" , "op": "11111100|001|Rm|option:3|n:1|10|Rn|Vs"},
+ {"inst": "str Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]" , "op": "00111100|101|Rm|option:3|n:1|10|Rn|Vs"},
+ {"inst": "str Bd, [Xn|SP, #offZ]" , "op": "00111101|00|offZ:12|Rn|Vs"},
+ {"inst": "str Hd, [Xn|SP, #offZ*2]" , "op": "01111101|00|offZ:12|Rn|Vs"},
+ {"inst": "str Sd, [Xn|SP, #offZ*4]" , "op": "10111101|00|offZ:12|Rn|Vs"},
+ {"inst": "str Dd, [Xn|SP, #offZ*8]" , "op": "11111101|00|offZ:12|Rn|Vs"},
+ {"inst": "str Qd, [Xn|SP, #offZ*16]" , "op": "00111101|10|offZ:12|Rn|Vs"},
+ {"inst": "str Bd, [Xn|SP, #offS]!" , "op": "00111100|000|offS:9|11|Rn|Vs"},
+ {"inst": "str Hd, [Xn|SP, #offS*2]!" , "op": "01111100|000|offS:9|11|Rn|Vs"},
+ {"inst": "str Sd, [Xn|SP, #offS*4]!" , "op": "10111100|000|offS:9|11|Rn|Vs"},
+ {"inst": "str Dd, [Xn|SP, #offS*8]!" , "op": "11111100|000|offS:9|11|Rn|Vs"},
+ {"inst": "str Qd, [Xn|SP, #offS*16]!" , "op": "00111100|100|offS:9|11|Rn|Vs"},
+ {"inst": "str Bd, [Xn|SP, #offS]@" , "op": "00111100|000|offS:9|01|Rn|Vs"},
+ {"inst": "str Hd, [Xn|SP, #offS*2]@" , "op": "01111100|000|offS:9|01|Rn|Vs"},
+ {"inst": "str Sd, [Xn|SP, #offS*4]@" , "op": "10111100|000|offS:9|01|Rn|Vs"},
+ {"inst": "str Dd, [Xn|SP, #offS*8]@" , "op": "11111100|000|offS:9|01|Rn|Vs"},
+ {"inst": "str Qd, [Xn|SP, #offS*16]@" , "op": "00111100|100|offS:9|01|Rn|Vs"},
+ {"inst": "stur Bd, [Xn|SP, #offS]" , "op": "00111100|000|offS:9|00|Rn|Vs"},
+ {"inst": "stur Hd, [Xn|SP, #offS]" , "op": "01111100|000|offS:9|00|Rn|Vs"},
+ {"inst": "stur Sd, [Xn|SP, #offS]" , "op": "10111100|000|offS:9|00|Rn|Vs"},
+ {"inst": "stur Dd, [Xn|SP, #offS]" , "op": "11111100|000|offS:9|00|Rn|Vs"},
+ {"inst": "stur Qd, [Xn|SP, #offS]" , "op": "00111100|100|offS:9|00|Rn|Vs"},
+ {"inst": "sub Dd, Dn, Dm" , "op": "01111110|11|1|Vm|10000|1|Vn|Vd"},
+ {"inst": "sub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10000|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "sub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10000|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "subhn Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|01100|0|Vn|Vd" , "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "subhn2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|01100|0|Vn|Vx" , "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "suqadd Bx, Bn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "suqadd Hx, Hn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "suqadd Sx, Sn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "suqadd Dx, Dn" , "op": "01011110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "suqadd Vx.t, Vn.t" , "op": "00001110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "suqadd Vx.t, Vn.t" , "op": "01001110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "sxtl Vd.ta, Vn.tb" , "op": "00001111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.8B 4S.4H 2D.2S" },
+ {"inst": "sxtl2 Vd.ta, Vn.tb" , "op": "01001111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "tbl Vd.8B, Vn.16B, Vm.8B" , "op": "00001110|00|0|Vm|0|00|000|Vn|Vd"},
+ {"inst": "tbl Vd.16B, Vn.16B, Vm.16B" , "op": "01001110|00|0|Vm|0|00|000|Vn|Vd"},
+ {"inst": "tbl Vd.8B, 2x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|01|000|Vn|Vd"},
+ {"inst": "tbl Vd.16B, 2x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|01|000|Vn|Vd"},
+ {"inst": "tbl Vd.8B, 3x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|10|000|Vn|Vd"},
+ {"inst": "tbl Vd.16B, 3x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|10|000|Vn|Vd"},
+ {"inst": "tbl Vd.8B, 4x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|11|000|Vn|Vd"},
+ {"inst": "tbl Vd.16B, 4x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|11|000|Vn|Vd"},
+ {"inst": "tbx Vx.8B, Vn.16B, Vm.8B" , "op": "00001110|00|0|Vm|0|00|100|Vn|Vx"},
+ {"inst": "tbx Vx.16B, Vn.16B, Vm.16B" , "op": "01001110|00|0|Vm|0|00|100|Vn|Vx"},
+ {"inst": "tbx Vx.8B, 2x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|01|100|Vn|Vx"},
+ {"inst": "tbx Vx.16B, 2x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|01|100|Vn|Vx"},
+ {"inst": "tbx Vx.8B, 3x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|10|100|Vn|Vx"},
+ {"inst": "tbx Vx.16B, 3x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|10|100|Vn|Vx"},
+ {"inst": "tbx Vx.8B, 4x{Vn.16B}+, Vm.8B" , "op": "00001110|00|0|Vm|0|11|100|Vn|Vx"},
+ {"inst": "tbx Vx.16B, 4x{Vn.16B}+, Vm.16B" , "op": "01001110|00|0|Vm|0|11|100|Vn|Vx"},
+ {"inst": "trn1 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|00101|0|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "trn1 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|00101|0|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "trn2 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|01101|0|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "trn2 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|01101|0|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "uaba Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01111|1|Vn|Vx" , "t": "8B 4H 2S"},
+ {"inst": "uaba Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01111|1|Vn|Vx" , "t": "16B 8H 4S"},
+ {"inst": "uabal Vx.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "uabal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01010|0|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uabd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01110|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "uabd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01110|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "uabdl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "uabdl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|01110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uadalp Vx.ta, Vn.tb" , "op": "00101110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
+ {"inst": "uadalp Vx.ta, Vn.tb" , "op": "01101110|sz|10000|00110|10|Vn|Vx" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uaddl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "uaddl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|00000|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uaddlp Vd.ta, Vn.tb" , "op": "00101110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "4H.8B 2S.4H 1D.2S"},
+ {"inst": "uaddlp Vd.ta, Vn.tb" , "op": "01101110|sz|10000|00010|10|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uaddlv Hd, Vn.8B" , "op": "00101110|00|11000|00011|10|Vn|Vd"},
+ {"inst": "uaddlv Hd, Vn.16B" , "op": "01101110|00|11000|00011|10|Vn|Vd"},
+ {"inst": "uaddlv Sd, Vn.4H" , "op": "00101110|01|11000|00011|10|Vn|Vd"},
+ {"inst": "uaddlv Sd, Vn.8H" , "op": "01101110|01|11000|00011|10|Vn|Vd"},
+ {"inst": "uaddlv Dd, Vn.4S" , "op": "01101110|10|11000|00011|10|Vn|Vd"},
+ {"inst": "uaddw Vd.ta, Vn.ta, Vm.tb" , "op": "00101110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "uaddw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01101110|sz|1|Vm|00010|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "ucvtf Sd, Wn" , "op": "00011110|00|1|00011|00000|0|Rn|Vd"},
+ {"inst": "ucvtf Sd, Wn, #fbits" , "op": "00011110|00|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "ucvtf Sd, Xn" , "op": "10011110|00|1|00011|00000|0|Rn|Vd"},
+ {"inst": "ucvtf Sd, Xn, #fbits" , "op": "10011110|00|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "ucvtf Sd, Sn" , "op": "01111110|00|10000|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Sd, Sn, #bits" , "op": "01111111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "ucvtf Dd, Wn" , "op": "00011110|01|1|00011|00000|0|Rn|Vd"},
+ {"inst": "ucvtf Dd, Wn, #fbits" , "op": "00011110|01|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "ucvtf Dd, Xn" , "op": "10011110|01|1|00011|00000|0|Rn|Vd"},
+ {"inst": "ucvtf Dd, Xn, #fbits" , "op": "10011110|01|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "ucvtf Dd, Dn" , "op": "01111110|01|10000|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Dd, Dn, #bits" , "op": "01111111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "ucvtf Vd.2S, Vn.2S" , "op": "00101110|00|10000|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Vd.4S, Vn.4S" , "op": "01101110|00|10000|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Vd.2D, Vn.2D" , "op": "01101110|01|10000|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Vd.2S, Vn.2S, #fbits" , "op": "00101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "ucvtf Vd.4S, Vn.4S, #fbits" , "op": "01101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 32)"},
+ {"inst": "ucvtf Vd.2D, Vn.2D, #fbits" , "op": "01101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 64)"},
+ {"inst": "uhadd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00000|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "uhadd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00000|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "uhsub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00100|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "uhsub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00100|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "umax Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01100|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "umax Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01100|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "umaxp Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10100|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "umaxp Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10100|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "umaxv Bd, Vn.8B" , "op": "00101110|00|11000|01010|10|Vn|Vd"},
+ {"inst": "umaxv Bd, Vn.16B" , "op": "01101110|00|11000|01010|10|Vn|Vd"},
+ {"inst": "umaxv Hd, Vn.4H" , "op": "00101110|01|11000|01010|10|Vn|Vd"},
+ {"inst": "umaxv Hd, Vn.8H" , "op": "01101110|01|11000|01010|10|Vn|Vd"},
+ {"inst": "umaxv Sd, Vn.4S" , "op": "01101110|10|11000|01010|10|Vn|Vd"},
+ {"inst": "umin Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01101|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "umin Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01101|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "uminp Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10101|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "uminp Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10101|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "uminv Bd, Vn.8B" , "op": "00101110|00|11000|11010|10|Vn|Vd"},
+ {"inst": "uminv Bd, Vn.16B" , "op": "01101110|00|11000|11010|10|Vn|Vd"},
+ {"inst": "uminv Hd, Vn.4H" , "op": "00101110|01|11000|11010|10|Vn|Vd"},
+ {"inst": "uminv Hd, Vn.8H" , "op": "01101110|01|11000|11010|10|Vn|Vd"},
+ {"inst": "uminv Sd, Vn.4S" , "op": "01101110|10|11000|11010|10|Vn|Vd"},
+ {"inst": "umlal Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "umlal2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "umlal Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
+ {"inst": "umlal2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
+ {"inst": "umlal Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
+ {"inst": "umlal2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
+ {"inst": "umlsl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "umlsl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "umlsl Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
+ {"inst": "umlsl2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
+ {"inst": "umlsl Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
+ {"inst": "umlsl2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
+ {"inst": "umov Wd, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00111|1|Vn|Rd"},
+ {"inst": "umov Wd, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00111|1|Vn|Rd"},
+ {"inst": "umov|mov Wd, Vn.S[#idx]" , "op": "00001110|00|0|idx:2| 100|00111|1|Vn|Rd"},
+ {"inst": "umov|mov Xd, Vn.D[#idx]" , "op": "01001110|00|0|idx:1|1000|00111|1|Vn|Rd"},
+ {"inst": "umull Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "umull2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|11000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "umull Vd.4S, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
+ {"inst": "umull2 Vd.4S, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|1010|idx[2]|0|Vn|Vd"},
+ {"inst": "umull Vd.2D, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
+ {"inst": "umull2 Vd.2D, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0] |Vm |1010|idx[1]|0|Vn|Vd"},
+ {"inst": "uqadd Bd, Bn, Bm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqadd Hd, Hn, Hm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqadd Sd, Sn, Sm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqadd Dd, Dn, Dm" , "op": "01111110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqadd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "uqadd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "uqrshl Bd, Bn, Bm" , "op": "01111110|00|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqrshl Hd, Hn, Hm" , "op": "01111110|01|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqrshl Sd, Sn, Sm" , "op": "01111110|10|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqrshl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqrshl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "uqrshl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01011|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "uqrshrn Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "uqrshrn Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "uqrshrn Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "uqrshrn Vd.8B, Vn.8H, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "uqrshrn2 Vx.16B, Vn.8H, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "uqrshrn Vd.4H, Vn.4S, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "uqrshrn2 Vx.8H, Vn.4S, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "uqrshrn Vd.2S, Vn.2D, #n" , "op": "00101111|0|immh:4|immb:3|10011|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "uqrshrn2 Vx.4S, Vn.2D, #n" , "op": "01101111|0|immh:4|immb:3|10011|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "uqshl Bd, Bn, Bm" , "op": "01111110|00|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqshl Hd, Hn, Hm" , "op": "01111110|01|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqshl Sd, Sn, Sm" , "op": "01111110|10|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqshl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqshl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "uqshl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01001|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "uqshl Bd, Bn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 0)"},
+ {"inst": "uqshl Hd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 1)"},
+ {"inst": "uqshl Sd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 2)"},
+ {"inst": "uqshl Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, 3)"},
+ {"inst": "uqshl Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "uqshl Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|01110|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "uqshrn Bd, Hn, #n" , "op": "01111111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 0)"},
+ {"inst": "uqshrn Hd, Sn, #n" , "op": "01111111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 1)"},
+ {"inst": "uqshrn Sd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 2)"},
+ {"inst": "uqshrn Vd.ta, Vn.tb, #n" , "op": "00001111|0|immh:4|immb:3|10010|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "uqshrn2 Vx.ta, Vn.tb, #n" , "op": "01001111|0|immh:4|immb:3|10010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "uqsub Bd, Bn, Bm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqsub Hd, Hn, Hm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqsub Sd, Sn, Sm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqsub Dd, Dn, Dm" , "op": "01111110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqsub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "uqsub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00101|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "uqxtn Bd, Hn" , "op": "01111110|00|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqxtn Hd, Sn" , "op": "01111110|01|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqxtn Sd, Dn" , "op": "01111110|10|10000|10100|10|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "uqxtn Vd.ta, Vn.tb" , "op": "00101110|sz|10000|10100|10|Vn|Vd" , "io": "QC|=SAT", "ta.tb": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "uqxtn2 Vx.ta, Vn.tb" , "op": "01101110|sz|10000|10100|10|Vn|Vx" , "io": "QC|=SAT", "ta.tb": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "urecpe Vd.2S, Vn.2S" , "op": "00001110|10|10000|11100|10|Vn|Vd"},
+ {"inst": "urecpe Vd.4S, Vn.4S" , "op": "01001110|10|10000|11100|10|Vn|Vd"},
+ {"inst": "urhadd Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|00010|1|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "urhadd Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|00010|1|Vn|Vd" , "t": "16B 8H 4S"},
+ {"inst": "urshl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "urshl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "urshl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01010|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "urshr Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "urshr Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "urshr Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00100|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "ursqrte Vd.2S, Vn.2S" , "op": "00101110|10|10000|11100|10|Vn|Vd"},
+ {"inst": "ursqrte Vd.4S, Vn.4S" , "op": "01101110|10|10000|11100|10|Vn|Vd"},
+ {"inst": "ursra Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "ursra Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "ursra Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00110|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "ushl Dd, Dn, Dm" , "op": "01111110|11|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT"},
+ {"inst": "ushl Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "8B 4H 2S"},
+ {"inst": "ushl Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|01000|1|Vn|Vd" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "ushll Vd.ta, Vn.tb, #n" , "op": "00101111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "ushll2 Vd.ta, Vn.tb, #n" , "op": "01101111|0|immh:4|immb:3|10100|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftPImm(n, sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "ushr Dd, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "ushr Vd.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "ushr Vd.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00000|1|Vn|Vd" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "usqadd Bx, Bn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "usqadd Hx, Hn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "usqadd Sx, Sn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "usqadd Dx, Dn" , "op": "01111110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "usqadd Vx.t, Vn.t" , "op": "00101110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S"},
+ {"inst": "usqadd Vx.t, Vn.t" , "op": "01101110|sz|10000|00011|10|Vn|Vx" , "io": "QC|=SAT", "t": "16B 8H 4S 2D"},
+ {"inst": "usra Dx, Dn, #n" , "op": "01111111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, 3)"},
+ {"inst": "usra Vx.t, Vn.t, #n" , "op": "00101111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "8B 4H 2S"},
+ {"inst": "usra Vx.t, Vn.t, #n" , "op": "01101111|0|immh:4|immb:3|00010|1|Vn|Vx" , "io": "QC|=SAT", "imm": "ASimdShiftNImm(n, sz)", "t": "16B 8H 4S 2D"},
+ {"inst": "usubl Vd.ta, Vn.tb, Vm.tb" , "op": "00101110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "usubl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01101110|sz|1|Vm|00100|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "usubw Vd.ta, Vn.ta, Vm.tb" , "op": "00101110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "usubw2 Vd.ta, Vn.ta, Vm.tb" , "op": "01101110|sz|1|Vm|00110|0|Vn|Vd" , "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uxtl Vd.ta, Vn.tb" , "op": "00101111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.8B 4S.4H 2D.2S"},
+ {"inst": "uxtl2 Vd.ta, Vn.tb" , "op": "01101111|0|immh:4|000|10100|1|Vn|Vd" , "imm": "ASimdXtlImm(sz)", "ta.tb": "8H.16B 4S.8H 2D.4S"},
+ {"inst": "uzp1 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|00011|0|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "uzp1 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|00011|0|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "uzp2 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|01011|0|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "uzp2 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|01011|0|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "xtn Vd.ta, Vn.tb" , "op": "00001110|sz|10000|10010|10|Vn|Vd" , "t": "8B.8H 4H.4S 2S.2D"},
+ {"inst": "xtn2 Vx.ta, Vn.tb" , "op": "01001110|sz|10000|10010|10|Vn|Vx" , "t": "16B.8H 8H.4S 4S.2D"},
+ {"inst": "zip1 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|00111|0|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "zip1 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|00111|0|Vn|Vd" , "t": "16B 8H 4S 2D"},
+ {"inst": "zip2 Vd.t, Vn.t, Vm.t" , "op": "00001110|sz|0|Vm|01111|0|Vn|Vd" , "t": "8B 4H 2S"},
+ {"inst": "zip2 Vd.t, Vn.t, Vm.t" , "op": "01001110|sz|0|Vm|01111|0|Vn|Vd" , "t": "16B 8H 4S 2D"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [
+ {"inst": "aesd Vd.16B, Vn.16B" , "op": "01001110|00|10100|00101|10|Vn|Vd"},
+ {"inst": "aese Vd.16B, Vn.16B" , "op": "01001110|00|10100|00100|10|Vn|Vd"},
+ {"inst": "aesimc Vd.16B, Vn.16B" , "op": "01001110|00|10100|00111|10|Vn|Vd"},
+ {"inst": "aesmc Vd.16B, Vn.16B" , "op": "01001110|00|10100|00110|10|Vn|Vd"}
+ ]},
+
+ {"category": "ASIMD", "ext": "BF16", "data": [
+ {"inst": "bfcvt Hd, Sn" , "op": "00011110|01|10001|10100|00|Vn|Vd"},
+ {"inst": "bfcvtn Vd.4H, Vn.4S" , "op": "00001110|10|10000|10110|10|Vn|Vd"},
+ {"inst": "bfcvtn2 Vd.8H, Vn.4S" , "op": "01001110|10|10000|10110|10|Vn|Vd"},
+ {"inst": "bfdot Vx.2S, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "bfdot Vx.4S, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "bfdot Vx.2S, Vn.4H, Vm.2H[#idx]" , "op": "00001111|01|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
+ {"inst": "bfdot Vx.4S, Vn.8H, Vm.2H[#idx]" , "op": "01001111|01|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
+ {"inst": "bfmlalb Vx.4S, Vn.8H, Vm.8H" , "op": "00101110|11|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "bfmlalb Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "00001111|11|idx[1:0]|Vm:4|1111|idx[2]|1|Vn|Vx"},
+ {"inst": "bfmlalt Vx.4S, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "bfmlalt Vx.4S, Vn.8H, Vm.H[#idx]" , "op": "01001111|11|idx[1:0]|Vm:4|1111|idx[2]|1|Vn|Vx"},
+ {"inst": "bfmmla Vx.4S, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|11101|1|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "DOTPROD", "data": [
+ {"inst": "sdot Vx.2S, Vn.8B, Vm.8B" , "op": "00001110|10|0|Vm|10010|1|Vn|Vx"},
+ {"inst": "sdot Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|10|0|Vm|10010|1|Vn|Vx"},
+ {"inst": "sdot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"},
+ {"inst": "sdot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"},
+ {"inst": "udot Vx.2S, Vn.8B, Vm.8B" , "op": "00101110|10|0|Vm|10010|1|Vn|Vx"},
+ {"inst": "udot Vx.4S, Vn.16B, Vm.16B" , "op": "01101110|10|0|Vm|10010|1|Vn|Vx"},
+ {"inst": "udot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00101111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"},
+ {"inst": "udot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01101111|10|idx[0]|Vm|1110|idx[1]|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FAMINMAX", "data": [
+ {"inst": "famax Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "famax Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "famax Vd.2S, Vn.2S, Vm.2S" , "op": "00001110|10|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "famax Vd.4S, Vn.4S, Vm.4S" , "op": "01001110|10|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "famax Vd.2D, Vn.2D, Vm.2D" , "op": "01001110|11|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "famin Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "famin Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "famin Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "famin Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11011|1|Vn|Vd"},
+ {"inst": "famin Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11011|1|Vn|Vd"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FCMA", "data": [
+ {"inst": "fcadd Vd.t, Vn.t, Vm.t, #rotate" , "op": "00101110|sz|0|Vm|111|imm:1|01|Vn|Vd" , "imm": "ASimdRotateImm_90_270(rotate)", "t": "4H 2S"},
+ {"inst": "fcadd Vd.t, Vn.t, Vm.t, #rotate" , "op": "01101110|sz|0|Vm|111|imm:1|01|Vn|Vd" , "imm": "ASimdRotateImm_90_270(rotate)", "t": "8H 4S 2D"},
+ {"inst": "fcmla Vd.t, Vn.t, Vm.t, #rotate" , "op": "00101110|sz|0|Vm|110|imm:2|1|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)", "t": "4H 2S"},
+ {"inst": "fcmla Vd.t, Vn.t, Vm.t, #rotate" , "op": "01101110|sz|0|Vm|110|imm:2|1|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)", "t": "8H 4S 2D"},
+ {"inst": "fcmla Vd.4H, Vn.4H, Vm.H[#idx], #rotate" , "op": "00101111|01|idx[0]|Vm|1|imm:2|1|idx[1]|0|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)"},
+ {"inst": "fcmla Vd.8H, Vn.8H, Vm.H[#idx], #rotate" , "op": "01101111|01|idx[0]|Vm|1|imm:2|1|idx[1]|0|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)"},
+ {"inst": "fcmla Vd.4S, Vn.4S, Vm.S[#idx], #rotate" , "op": "01101111|10|0|Vm|1|imm:2|1|idx:1|0|Vn|Vd" , "imm": "ASimdRotateImm_0_90_180_270(rotate)"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FHM", "data": [
+ {"inst": "fmlal Vx.2S, Vn.2H, Vm.2H" , "op": "00001110|00|1|Vm|11101|1|Vn|Vx"},
+ {"inst": "fmlal Vx.4S, Vn.4H, Vm.4H" , "op": "01001110|00|1|Vm|11101|1|Vn|Vx"},
+ {"inst": "fmlal Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00001111|10|imm[1:0]|Vm:4|0000|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlal Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01001111|10|imm[1:0]|Vm:4|0000|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlal2 Vx.2S, Vn.2H, Vm.2H" , "op": "00101110|00|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmlal2 Vx.4S, Vn.4H, Vm.4H" , "op": "01101110|00|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmlal2 Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00101111|10|imm[1:0]|Vm:4|1000|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlal2 Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01101111|10|imm[1:0]|Vm:4|1000|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlsl Vx.2S, Vn.2H, Vm.2H" , "op": "00001110|10|1|Vm|11101|1|Vn|Vx"},
+ {"inst": "fmlsl Vx.4S, Vn.4H, Vm.4H" , "op": "01001110|10|1|Vm|11101|1|Vn|Vx"},
+ {"inst": "fmlsl Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00001111|10|imm[1:0]|Vm:4|0100|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlsl Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01001111|10|imm[1:0]|Vm:4|0100|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlsl2 Vx.2S, Vn.2H, Vm.2H" , "op": "00101110|10|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmlsl2 Vx.4S, Vn.4H, Vm.4H" , "op": "01101110|10|1|Vm|11001|1|Vn|Vx"},
+ {"inst": "fmlsl2 Vx.2S, Vn.2H, Vm.H[#idx]" , "op": "00101111|10|imm[1:0]|Vm:4|1100|imm[2]|0|Vn|Vx"},
+ {"inst": "fmlsl2 Vx.4S, Vn.4H, Vm.H[#idx]" , "op": "01101111|10|imm[1:0]|Vm:4|1100|imm[2]|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FP16", "data": [
+ {"inst": "fabd Hd, Hn, Hm" , "op": "01111110|11|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "fabd Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "fabd Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "fabs Hd, Hn" , "op": "00011110|11|10000|01100|00|Vn|Vd"},
+ {"inst": "fabs Vd.4H, Vn.4H" , "op": "00001110|11|11100|01111|10|Vn|Vd"},
+ {"inst": "fabs Vd.8H, Vn.8H" , "op": "01001110|11|11100|01111|10|Vn|Vd"},
+ {"inst": "facge Hd, Hn, Hm" , "op": "01111110|01|0|Vm|00101|1|Vn|Vd"},
+ {"inst": "facge Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00101|1|Vn|Vd"},
+ {"inst": "facge Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00101|1|Vn|Vd"},
+ {"inst": "facgt Hd, Hn, Hm" , "op": "01111110|11|0|Vm|00101|1|Vn|Vd"},
+ {"inst": "facgt Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00101|1|Vn|Vd"},
+ {"inst": "facgt Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00101|1|Vn|Vd"},
+ {"inst": "fadd Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00101|0|Vn|Vd"},
+ {"inst": "fadd Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "fadd Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "faddp Hd, Vn.2H" , "op": "01011110|00|11000|01101|10|Vn|Vd"},
+ {"inst": "faddp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "faddp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "fccmp Hn, Hm, #nzcv, #cond" , "op": "00011110|11|1|Vm|cond|01|Vn|0|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fccmpe Hn, Hm, #nzcv, #cond" , "op": "00011110|11|1|Vm|cond|01|Vn|1|nzcv" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmeq Hd, Hn, Hm" , "op": "01011110|01|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmeq Hd, Hn, #0" , "op": "01011110|11|11100|01101|10|Vn|Vd"},
+ {"inst": "fcmeq Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmeq Vd.4H, Vn.4H, #0" , "op": "00001110|11|11100|01101|10|Vn|Vd"},
+ {"inst": "fcmeq Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmeq Vd.8H, Vn.8H, #0" , "op": "01001110|11|11100|01101|10|Vn|Vd"},
+ {"inst": "fcmge Hd, Hn, Hm" , "op": "01111110|01|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmge Hd, Hn, #0" , "op": "01111110|11|11100|01100|10|Vn|Vd"},
+ {"inst": "fcmge Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmge Vd.4H, Vn.4H, #0" , "op": "00101110|11|11100|01100|10|Vn|Vd"},
+ {"inst": "fcmge Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmge Vd.8H, Vn.8H, #0" , "op": "01101110|11|11100|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Hd, Hn, Hm" , "op": "01111110|11|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmgt Hd, Hn, #0" , "op": "01011110|11|11100|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmgt Vd.4H, Vn.4H, #0" , "op": "00001110|11|11100|01100|10|Vn|Vd"},
+ {"inst": "fcmgt Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00100|1|Vn|Vd"},
+ {"inst": "fcmgt Vd.8H, Vn.8H, #0" , "op": "01001110|11|11100|01100|10|Vn|Vd"},
+ {"inst": "fcmle Hd, Hn, #0" , "op": "01111110|11|11100|01101|10|Vn|Vd"},
+ {"inst": "fcmle Vd.4H, Vn.4H, #0" , "op": "00101110|11|11100|01101|10|Vn|Vd"},
+ {"inst": "fcmle Vd.8H, Vn.8H, #0" , "op": "01101110|11|11100|01101|10|Vn|Vd"},
+ {"inst": "fcmlt Hd, Hn, #0" , "op": "01011110|11|11100|01110|10|Vn|Vd"},
+ {"inst": "fcmlt Vd.4H, Vn.4H, #0" , "op": "00001110|11|11100|01110|10|Vn|Vd"},
+ {"inst": "fcmlt Vd.8H, Vn.8H, #0" , "op": "01001110|11|11100|01110|10|Vn|Vd"},
+ {"inst": "fcmp Hn, Hm" , "op": "00011110|11|1|Vm|00100|0|Vn|00000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmp Hn, #0" , "op": "00011110|11|1|00000|00100|0|Vn|01000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmpe Hn, Hm" , "op": "00011110|11|1|Vm|00100|0|Vn|10000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcmpe Hn, #0" , "op": "00011110|11|1|00000|00100|0|Vn|11000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "fcsel Hd, Hn, Hm, #cond" , "op": "00011110|11|1|Vm|cond|11|Vn|Vd" , "io": "N=R Z=R C=R V=R"},
+ {"inst": "fcvtas Wd, Hn" , "op": "00011110|11|10010|00000|00|Vn|Rd"},
+ {"inst": "fcvtas Xd, Hn" , "op": "10011110|11|10010|00000|00|Vn|Rd"},
+ {"inst": "fcvtas Hd, Hn" , "op": "01011110|01|11100|11100|10|Vn|Vd"},
+ {"inst": "fcvtas Vd.4H, Vn.4H" , "op": "00001110|01|11100|11100|10|Vn|Vd"},
+ {"inst": "fcvtas Vd.8H, Vn.8H" , "op": "01001110|01|11100|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Wd, Hn" , "op": "00011110|11|10010|10000|00|Vn|Rd"},
+ {"inst": "fcvtau Xd, Hn" , "op": "10011110|11|10010|10000|00|Vn|Rd"},
+ {"inst": "fcvtau Hd, Hn" , "op": "01111110|01|11100|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Vd.4H, Vn.4H" , "op": "00101110|01|11100|11100|10|Vn|Vd"},
+ {"inst": "fcvtau Vd.8H, Vn.8H" , "op": "01101110|01|11100|11100|10|Vn|Vd"},
+ {"inst": "fcvtms Wd, Hn" , "op": "00011110|11|11000|00000|00|Vn|Rd"},
+ {"inst": "fcvtms Xd, Hn" , "op": "10011110|11|11000|00000|00|Vn|Rd"},
+ {"inst": "fcvtms Hd, Hn" , "op": "01011110|01|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtms Vd.4H, Vn.4H" , "op": "00001110|01|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtms Vd.8H, Vn.8H" , "op": "01001110|01|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Wd, Hn" , "op": "00011110|11|11000|10000|00|Vn|Rd"},
+ {"inst": "fcvtmu Xd, Hn" , "op": "10011110|11|11000|10000|00|Vn|Rd"},
+ {"inst": "fcvtmu Hd, Hn" , "op": "01111110|01|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Vd.4H, Vn.4H" , "op": "00101110|01|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtmu Vd.8H, Vn.8H" , "op": "01101110|01|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtns Wd, Hn" , "op": "00011110|11|10000|00000|00|Vn|Rd"},
+ {"inst": "fcvtns Xd, Hn" , "op": "10011110|11|10000|00000|00|Vn|Rd"},
+ {"inst": "fcvtns Hd, Hn" , "op": "01011110|01|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtns Vd.4H, Vn.4H" , "op": "00001110|01|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtns Vd.8H, Vn.8H" , "op": "01001110|01|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Wd, Hn" , "op": "00011110|11|10000|10000|00|Vn|Rd"},
+ {"inst": "fcvtnu Xd, Hn" , "op": "10011110|11|10000|10000|00|Vn|Rd"},
+ {"inst": "fcvtnu Hd, Hn" , "op": "01111110|01|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Vd.4H, Vn.4H" , "op": "00101110|01|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtnu Vd.8H, Vn.8H" , "op": "01101110|01|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Wd, Hn" , "op": "00011110|11|10100|00000|00|Vn|Rd"},
+ {"inst": "fcvtps Xd, Hn" , "op": "10011110|11|10100|00000|00|Vn|Rd"},
+ {"inst": "fcvtps Hd, Hn" , "op": "01011110|11|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Vd.4H, Vn.4H" , "op": "00001110|11|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtps Vd.8H, Vn.8H" , "op": "01001110|11|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Wd, Hn" , "op": "00011110|11|10100|10000|00|Vn|Rd"},
+ {"inst": "fcvtpu Xd, Hn" , "op": "10011110|11|10100|10000|00|Vn|Rd"},
+ {"inst": "fcvtpu Hd, Hn" , "op": "01111110|11|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Vd.4H, Vn.4H" , "op": "00101110|11|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtpu Vd.8H, Vn.8H" , "op": "01101110|11|11100|11010|10|Vn|Vd"},
+ {"inst": "fcvtzs Wd, Hn" , "op": "00011110|11|11100|00000|00|Vn|Rd"},
+ {"inst": "fcvtzs Xd, Hn" , "op": "10011110|11|11100|00000|00|Vn|Rd"},
+ {"inst": "fcvtzs Hd, Hn" , "op": "01011110|11|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Vd.4H, Vn.4H" , "op": "00001110|11|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Vd.8H, Vn.8H" , "op": "01001110|11|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtzs Wd, Hn, #fbits" , "op": "00011110|11|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "fcvtzs Xd, Hn, #fbits" , "op": "10011110|11|011000|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "fcvtzs Hd, Hn, #fbits" , "op": "01011111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "fcvtzs Vd.4H, Vn.4H, #fbits" , "op": "00001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "fcvtzs Vd.8H, Vn.8H, #fbits" , "op": "01001111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "fcvtzu Wd, Hn" , "op": "00011110|11|11100|10000|00|Vn|Rd"},
+ {"inst": "fcvtzu Xd, Hn" , "op": "10011110|11|11100|10000|00|Vn|Rd"},
+ {"inst": "fcvtzu Hd, Hn" , "op": "01111110|11|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Vd.4H, Vn.4H" , "op": "00101110|11|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Vd.8H, Vn.8H" , "op": "01101110|11|11100|11011|10|Vn|Vd"},
+ {"inst": "fcvtzu Wd, Hn, #fbits" , "op": "00011110|11|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "fcvtzu Xd, Hn, #fbits" , "op": "10011110|11|011001|scale:6|Vn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "fcvtzu Hd, Hn, #fbits" , "op": "01111111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "fcvtzu Vd.4H, Vn.4H, #fbits" , "op": "00101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "fcvtzu Vd.8H, Vn.8H, #fbits" , "op": "01101111|0|immh:4|immb:3|11111|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "fdiv Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00011|0|Vn|Vd"},
+ {"inst": "fdiv Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "fdiv Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "fmadd Hd, Hn, Hm, Ha" , "op": "00011111|11|0|Vm|0|Va|Vn|Vd"},
+ {"inst": "fmax Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01001|0|Vn|Vd"},
+ {"inst": "fmax Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fmax Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fmaxnm Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01101|0|Vn|Vd"},
+ {"inst": "fmaxnm Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fmaxnm Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fmaxnmp Hd, Vn.2H" , "op": "01011110|00|11000|01100|10|Vn|Vd"},
+ {"inst": "fmaxnmp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fmaxnmp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fmaxnmv Hd, Vn.4H" , "op": "00001110|00|11000|01100|10|Vn|Vd"},
+ {"inst": "fmaxnmv Hd, Vn.8H" , "op": "01001110|00|11000|01100|10|Vn|Vd"},
+ {"inst": "fmaxp Hd, Vn.2H" , "op": "01011110|00|11000|01111|10|Vn|Vd"},
+ {"inst": "fmaxp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fmaxp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fmaxv Hd, Vn.4H" , "op": "00001110|00|11000|01111|10|Vn|Vd"},
+ {"inst": "fmaxv Hd, Vn.8H" , "op": "01001110|00|11000|01111|10|Vn|Vd"},
+ {"inst": "fmin Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01011|0|Vn|Vd"},
+ {"inst": "fmin Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fmin Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fminnm Hd, Hn, Hm" , "op": "00011110|11|1|Vm|01111|0|Vn|Vd"},
+ {"inst": "fminnm Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fminnm Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fminnmp Hd, Vn.2H" , "op": "01011110|10|11000|01100|10|Vn|Vd"},
+ {"inst": "fminnmp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fminnmp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00000|1|Vn|Vd"},
+ {"inst": "fminnmv Hd, Vn.4H" , "op": "00001110|10|11000|01100|10|Vn|Vd"},
+ {"inst": "fminnmv Hd, Vn.8H" , "op": "01001110|10|11000|01100|10|Vn|Vd"},
+ {"inst": "fminp Hd, Vn.2H" , "op": "01011110|10|11000|01111|10|Vn|Vd"},
+ {"inst": "fminp Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fminp Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00110|1|Vn|Vd"},
+ {"inst": "fminv Hd, Vn.4H" , "op": "00001110|10|11000|01111|10|Vn|Vd"},
+ {"inst": "fminv Hd, Vn.8H" , "op": "01001110|10|11000|01111|10|Vn|Vd"},
+ {"inst": "fmla Hx, Hn, Vm.H[#idx]" , "op": "01011111|00|idx[1:0]|Vm:4|0001|idx[2]|0|Vn|Vx"},
+ {"inst": "fmla Vx.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00001|1|Vn|Vx"},
+ {"inst": "fmla Vx.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00001|1|Vn|Vx"},
+ {"inst": "fmla Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|00|idx[1:0]|Vm:4|0001|idx[2]|0|Vn|Vx"},
+ {"inst": "fmla Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|00|idx[1:0]|Vm:4|0001|idx[2]|0|Vn|Vx"},
+ {"inst": "fmls Hx, Hn, Vm.H[#idx]" , "op": "01011111|00|idx[1:0]|Vm:4|0101|idx[2]|0|Vn|Vx"},
+ {"inst": "fmls Vx.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00001|1|Vn|Vx"},
+ {"inst": "fmls Vx.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00001|1|Vn|Vx"},
+ {"inst": "fmls Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|00|idx[1:0]|Vm:4|0101|idx[2]|0|Vn|Vx"},
+ {"inst": "fmls Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|00|idx[1:0]|Vm:4|0101|idx[2]|0|Vn|Vx"},
+ {"inst": "fmov Wd, Hn" , "op": "00011110|11|10011|00000|00|Vn|Rd"},
+ {"inst": "fmov Xd, Hn" , "op": "10011110|11|10011|00000|00|Vn|Rd"},
+ {"inst": "fmov Hd, Wn" , "op": "00011110|11|10011|10000|00|Rn|Vd"},
+ {"inst": "fmov Hd, Xn" , "op": "10011110|11|10011|10000|00|Rn|Vd"},
+ {"inst": "fmov Hd, Hn" , "op": "00011110|11|10000|00100|00|Vn|Vd"},
+ {"inst": "fmov Hd, #fimm" , "op": "00011110|11|1|imm:8|100|00000|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmov Vd.4H, #fimm" , "op": "00001111|00|000|abc:3|111111|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmov Vd.8H, #fimm" , "op": "01001111|00|000|abc:3|111111|defgh:5|Vd" , "imm": "ASimdFMovImm(fimm)"},
+ {"inst": "fmsub Hd, Hn, Hm, Ha" , "op": "00011111|11|0|Vm|1|Va|Vn|Vd"},
+ {"inst": "fmul Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00001|0|Vn|Vd"},
+ {"inst": "fmul Hd, Hn, Vm.H[#idx]" , "op": "01011111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
+ {"inst": "fmul Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|01|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "fmul Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|01|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "fmul Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00001111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
+ {"inst": "fmul Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01001111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
+ {"inst": "fmulx Hd, Hn, Hm" , "op": "01011110|01|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "fmulx Hd, Hn, Vm.H[#idx]" , "op": "01111111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
+ {"inst": "fmulx Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "fmulx Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00011|1|Vn|Vd"},
+ {"inst": "fmulx Vd.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
+ {"inst": "fmulx Vd.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|00|idx[1:0]|Vm:4|1001|idx[2]|0|Vn|Vd"},
+ {"inst": "fneg Hd, Hn" , "op": "00011110|11|10000|10100|00|Vn|Vd"},
+ {"inst": "fneg Vd.4H, Vn.4H" , "op": "00101110|11|11100|01111|10|Vn|Vd"},
+ {"inst": "fneg Vd.8H, Vn.8H" , "op": "01101110|11|11100|01111|10|Vn|Vd"},
+ {"inst": "fnmadd Hd, Hn, Hm, Ha" , "op": "00011111|11|1|Vm|0|Va|Vn|Vd"},
+ {"inst": "fnmsub Hd, Hn, Hm, Ha" , "op": "00011111|11|1|Vm|1|Va|Vn|Vd"},
+ {"inst": "fnmul Hd, Hn, Hm" , "op": "00011110|11|1|Vm|10001|0|Vn|Vd"},
+ {"inst": "frecpe Hd, Hn" , "op": "01011110|11|11100|11101|10|Vn|Vd"},
+ {"inst": "frecpe Vd.4H, Vn.4H" , "op": "00001110|11|11100|11101|10|Vn|Vd"},
+ {"inst": "frecpe Vd.8H, Vn.8H" , "op": "01001110|11|11100|11101|10|Vn|Vd"},
+ {"inst": "frecps Hd, Hn, Hm" , "op": "01011110|01|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "frecps Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "frecps Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "frecpx Hd, Hn, Hm" , "op": "01011110|11|11100|11111|10|Vn|Vd"},
+ {"inst": "frinta Hd, Hn" , "op": "00011110|11|10011|00100|00|Vn|Vd"},
+ {"inst": "frinta Vd.4H, Vn.4H" , "op": "00101110|01|11100|11000|10|Vn|Vd"},
+ {"inst": "frinta Vd.8H, Vn.8H" , "op": "01101110|01|11100|11000|10|Vn|Vd"},
+ {"inst": "frinti Hd, Hn" , "op": "00011110|11|10011|11100|00|Vn|Vd"},
+ {"inst": "frinti Vd.4H, Vn.4H" , "op": "00101110|11|11100|11001|10|Vn|Vd"},
+ {"inst": "frinti Vd.8H, Vn.8H" , "op": "01101110|11|11100|11001|10|Vn|Vd"},
+ {"inst": "frintm Hd, Hn" , "op": "00011110|11|10010|10100|00|Vn|Vd"},
+ {"inst": "frintm Vd.4H, Vn.4H" , "op": "00001110|01|11100|11001|10|Vn|Vd"},
+ {"inst": "frintm Vd.8H, Vn.8H" , "op": "01001110|01|11100|11001|10|Vn|Vd"},
+ {"inst": "frintn Hd, Hn" , "op": "00011110|11|10010|00100|00|Vn|Vd"},
+ {"inst": "frintn Vd.4H, Vn.4H" , "op": "00001110|01|11100|11000|10|Vn|Vd"},
+ {"inst": "frintn Vd.8H, Vn.8H" , "op": "01001110|01|11100|11000|10|Vn|Vd"},
+ {"inst": "frintp Hd, Hn" , "op": "00011110|11|10010|01100|00|Vn|Vd"},
+ {"inst": "frintp Vd.4H, Vn.4H" , "op": "00001110|11|11100|11000|10|Vn|Vd"},
+ {"inst": "frintp Vd.8H, Vn.8H" , "op": "01001110|11|11100|11000|10|Vn|Vd"},
+ {"inst": "frintx Hd, Hn" , "op": "00011110|11|10011|10100|00|Vn|Vd"},
+ {"inst": "frintx Vd.4H, Vn.4H" , "op": "00101110|01|11100|11001|10|Vn|Vd"},
+ {"inst": "frintx Vd.8H, Vn.8H" , "op": "01101110|01|11100|11001|10|Vn|Vd"},
+ {"inst": "frintz Hd, Hn" , "op": "00011110|11|10010|11100|00|Vn|Vd"},
+ {"inst": "frintz Vd.4H, Vn.4H" , "op": "00001110|11|11100|11001|10|Vn|Vd"},
+ {"inst": "frintz Vd.8H, Vn.8H" , "op": "01001110|11|11100|11001|10|Vn|Vd"},
+ {"inst": "frsqrte Hd, Hn" , "op": "01111110|11|11100|11101|10|Vn|Vd"},
+ {"inst": "frsqrte Vd.4H, Vn.4H" , "op": "00101110|11|11100|11101|10|Vn|Vd"},
+ {"inst": "frsqrte Vd.8H, Vn.8H" , "op": "01101110|11|11100|11101|10|Vn|Vd"},
+ {"inst": "frsqrts Hd, Hn, Hm" , "op": "01011110|11|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "frsqrts Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "frsqrts Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "fsqrt Hd, Hn" , "op": "00011110|11|10000|11100|00|Vn|Vd"},
+ {"inst": "fsqrt Vd.4H, Vn.4H" , "op": "00101110|11|11100|11111|10|Vn|Vd"},
+ {"inst": "fsqrt Vd.8H, Vn.8H" , "op": "01101110|11|11100|11111|10|Vn|Vd"},
+ {"inst": "fsub Hd, Hn, Hm" , "op": "00011110|11|1|Vm|00111|0|Vn|Vd"},
+ {"inst": "fsub Vd.4H, Vn.4H, Vm.4H" , "op": "00001110|11|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "fsub Vd.8H, Vn.8H, Vm.8H" , "op": "01001110|11|0|Vm|00010|1|Vn|Vd"},
+ {"inst": "scvtf Hd, Wn" , "op": "00011110|11|1|00010|00000|0|Rn|Vd"},
+ {"inst": "scvtf Hd, Wn, #fbits" , "op": "00011110|11|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "scvtf Hd, Xn" , "op": "10011110|11|1|00010|00000|0|Rn|Vd"},
+ {"inst": "scvtf Hd, Xn, #fbits" , "op": "10011110|11|0|00010|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "scvtf Hd, Hn" , "op": "01011110|01|11100|11101|10|Vn|Vd"},
+ {"inst": "scvtf Hd, Hn, #bits" , "op": "01011111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "scvtf Vd.4H, Vn.4H" , "op": "00001110|01|11100|11101|10|Vn|Vd"},
+ {"inst": "scvtf Vd.8H, Vn.8H" , "op": "01001110|01|11100|11101|10|Vn|Vd"},
+ {"inst": "scvtf Vd.4H, Vn.4H, #fbits" , "op": "00001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "scvtf Vd.8H, Vn.8H, #fbits" , "op": "01001111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "ucvtf Hd, Wn" , "op": "00011110|11|1|00011|00000|0|Rn|Vd"},
+ {"inst": "ucvtf Hd, Wn, #fbits" , "op": "00011110|11|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 32)"},
+ {"inst": "ucvtf Hd, Xn" , "op": "10011110|11|1|00011|00000|0|Rn|Vd"},
+ {"inst": "ucvtf Hd, Xn, #fbits" , "op": "10011110|11|0|00011|scale:6|Rn|Vd" , "imm": "ASimdFBitsScaleImm(fbits, 64)"},
+ {"inst": "ucvtf Hd, Hn" , "op": "01111110|01|11100|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Hd, Hn, #bits" , "op": "01111111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "ucvtf Vd.4H, Vn.4H" , "op": "00101110|01|11100|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Vd.8H, Vn.8H" , "op": "01101110|01|11100|11101|10|Vn|Vd"},
+ {"inst": "ucvtf Vd.4H, Vn.4H, #fbits" , "op": "00101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"},
+ {"inst": "ucvtf Vd.8H, Vn.8H, #fbits" , "op": "01101111|0|immh:4|immb:3|11100|1|Vn|Vd" , "imm": "ASimdFBitsHBImm(fbits, 16)"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FP8", "data": [
+ {"inst": "bf1cvtl Vd.8H, Vn.8B" , "op": "00101110|10|10000|10111|10|Vn|Vd"},
+ {"inst": "bf1cvtl2 Vd.8H, Vn.16B" , "op": "01101110|10|10000|10111|10|Vn|Vd"},
+ {"inst": "bf2cvtl Vd.8H, Vn.8B" , "op": "00101110|11|10000|10111|10|Vn|Vd"},
+ {"inst": "bf2cvtl2 Vd.8H, Vn.16B" , "op": "01101110|11|10000|10111|10|Vn|Vd"},
+ {"inst": "f1cvtl Vd.8H, Vn.8B" , "op": "00101110|00|10000|10111|10|Vn|Vd"},
+ {"inst": "f1cvtl2 Vd.8H, Vn.16B" , "op": "01101110|00|10000|10111|10|Vn|Vd"},
+ {"inst": "f2cvtl Vd.8H, Vn.8B" , "op": "00101110|01|10000|10111|10|Vn|Vd"},
+ {"inst": "f2cvtl2 Vd.8H, Vn.16B" , "op": "01101110|01|10000|10111|10|Vn|Vd"},
+ {"inst": "fcvtn Vd.8B, Vn.4H, Vm.4H" , "op": "00001110|01|0|Vm|11110|1|Vn|Vd"},
+ {"inst": "fcvtn Vd.16B, Vn.8H, Vm.8H" , "op": "01001110|01|0|Vm|11110|1|Vn|Vd"},
+ {"inst": "fcvtn Vd.8B, Vn.4S, Vm.4S" , "op": "00001110|00|0|Vm|11110|1|Vn|Vd"},
+ {"inst": "fcvtn2 Vx.16B, Vn.4S, Vm.4S" , "op": "01001110|00|0|Vm|11110|1|Vn|Vx"},
+ {"inst": "fscale Vd.4H, Vn.4H, Vm.4H" , "op": "00101110|11|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "fscale Vd.8H, Vn.8H, Vm.8H" , "op": "01101110|11|0|Vm|00111|1|Vn|Vd"},
+ {"inst": "fscale Vd.2S, Vn.2S, Vm.2S" , "op": "00101110|10|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "fscale Vd.4S, Vn.4S, Vm.4S" , "op": "01101110|10|1|Vm|11111|1|Vn|Vd"},
+ {"inst": "fscale Vd.2D, Vn.2D, Vm.2D" , "op": "01101110|11|1|Vm|11111|1|Vn|Vd"}
+
+ ]},
+
+ {"category": "ASIMD", "ext": "FP8DOT2", "data": [
+ {"inst": "fdot Vx.4H, Vn.8B, Vm.8B" , "op": "00001110|01|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "fdot Vx.8H, Vn.16B, Vm.16B" , "op": "01001110|01|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "fdot Vx.4H, Vn.8B, Vm.2B[#idx]" , "op": "00001111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
+ {"inst": "fdot Vx.8H, Vn.16B, Vm.2B[#idx]" , "op": "01001111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FP8DOT4", "data": [
+ {"inst": "fdot Vx.2S, Vn.8B, Vm.8B" , "op": "00001110|00|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "fdot Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|00|0|Vm|11111|1|Vn|Vx"},
+ {"inst": "fdot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|00|idx[0]|Vm|0000|idx[1]|0|Vn|Vx"},
+ {"inst": "fdot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|00|idx[0]|Vm|0000|idx[1]|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FP8FMA", "data": [
+ {"inst": "fmlalb Vx.8H, Vn.16B, Vm.16B" , "op": "00001110|110|Vm|11111|1|Vn|Vx"},
+ {"inst": "fmlalt Vx.8H, Vn.16B, Vm.16B" , "op": "01001110|110|Vm|11111|1|Vn|Vx"},
+ {"inst": "fmlalb Vx.8H, Vn.16B, Vm.B[#idx]" , "op": "00001111|11|idx[2:0]|Vm:3|0000|idx[3]|0|Vn|Vx"},
+ {"inst": "fmlalt Vx.8H, Vn.16B, Vm.B[#idx]" , "op": "01001111|11|idx[2:0]|Vm:3|0000|idx[3]|0|Vn|Vx"},
+ {"inst": "fmlallbb Vx.4S, Vn.16B, Vm.16B" , "op": "00001110|000|Vm|11000|1|Vn|Vx"},
+ {"inst": "fmlallbt Vx.4S, Vn.16B, Vm.16B" , "op": "00001110|010|Vm|11000|1|Vn|Vx"},
+ {"inst": "fmlalltb Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|000|Vm|11000|1|Vn|Vx"},
+ {"inst": "fmlalltt Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|010|Vm|11000|1|Vn|Vx"},
+ {"inst": "fmlallbb Vx.4S, Vn.16B, Vm.B[#idx]" , "op": "00101111|00|idx[2:0]|Vm:3|1000|idx[3]|0|Vn|Vx"},
+ {"inst": "fmlallbt Vx.4S, Vn.16B, Vm.B[#idx]" , "op": "00101111|01|idx[2:0]|Vm:3|1000|idx[3]|0|Vn|Vx"},
+ {"inst": "fmlalltb Vx.4S, Vn.16B, Vm.B[#idx]" , "op": "01101111|00|idx[2:0]|Vm:3|1000|idx[3]|0|Vn|Vx"},
+ {"inst": "fmlalltt Vx.4S, Vn.16B, Vm.B[#idx]" , "op": "01101111|01|idx[2:0]|Vm:3|1000|idx[3]|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "FRINTTS", "data": [
+ {"inst": "frint32x Sd, Sn" , "op": "00011110|00|10100|01100|00|Vn|Vd"},
+ {"inst": "frint32x Dd, Dn" , "op": "00011110|01|10100|01100|00|Vn|Vd"},
+ {"inst": "frint32x Vd.2S, Vn.2S" , "op": "00101110|00|10000|11110|10|Vn|Vd"},
+ {"inst": "frint32x Vd.4S, Vn.4S" , "op": "01101110|00|10000|11110|10|Vn|Vd"},
+ {"inst": "frint32x Vd.2D, Vn.2D" , "op": "01101110|01|10000|11110|10|Vn|Vd"},
+ {"inst": "frint32z Sd, Sn" , "op": "00011110|00|10100|00100|00|Vn|Vd"},
+ {"inst": "frint32z Dd, Dn" , "op": "00011110|01|10100|00100|00|Vn|Vd"},
+ {"inst": "frint32z Vd.2S, Vn.2S" , "op": "00001110|00|10000|11110|10|Vn|Vd"},
+ {"inst": "frint32z Vd.4S, Vn.4S" , "op": "01001110|00|10000|11110|10|Vn|Vd"},
+ {"inst": "frint32z Vd.2D, Vn.2D" , "op": "01001110|01|10000|11110|10|Vn|Vd"},
+ {"inst": "frint64x Sd, Sn" , "op": "00011110|00|10100|11100|00|Vn|Vd"},
+ {"inst": "frint64x Dd, Dn" , "op": "00011110|01|10100|11100|00|Vn|Vd"},
+ {"inst": "frint64x Vd.2S, Vn.2S" , "op": "00101110|00|10000|11111|10|Vn|Vd"},
+ {"inst": "frint64x Vd.4S, Vn.4S" , "op": "01101110|00|10000|11111|10|Vn|Vd"},
+ {"inst": "frint64x Vd.2D, Vn.2D" , "op": "01101110|01|10000|11111|10|Vn|Vd"},
+ {"inst": "frint64z Sd, Sn" , "op": "00011110|00|10100|10100|00|Vn|Vd"},
+ {"inst": "frint64z Dd, Dn" , "op": "00011110|01|10100|10100|00|Vn|Vd"},
+ {"inst": "frint64z Vd.2S, Vn.2S" , "op": "00001110|00|10000|11111|10|Vn|Vd"},
+ {"inst": "frint64z Vd.4S, Vn.4S" , "op": "01001110|00|10000|11111|10|Vn|Vd"},
+ {"inst": "frint64z Vd.2D, Vn.2D" , "op": "01001110|01|10000|11111|10|Vn|Vd"}
+ ]},
+
+ {"category": "ASIMD", "ext": "I8MM", "data": [
+ {"inst": "smmla Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|10|0|Vm|10100|1|Vn|Vx"},
+ {"inst": "sudot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|00|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
+ {"inst": "sudot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|00|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
+ {"inst": "ummla Vx.4S, Vn.16B, Vm.16B" , "op": "01101110|10|0|Vm|10100|1|Vn|Vx"},
+ {"inst": "usdot Vx.2S, Vn.8B, Vm.tb" , "op": "00001110|10|0|Vm|10011|1|Vn|Vx"},
+ {"inst": "usdot Vx.4S, Vn.16B, Vm.tb" , "op": "01001110|10|0|Vm|10011|1|Vn|Vx"},
+ {"inst": "usdot Vx.2S, Vn.8B, Vm.4B[#idx]" , "op": "00001111|10|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
+ {"inst": "usdot Vx.4S, Vn.16B, Vm.4B[#idx]" , "op": "01001111|10|idx[0]|Vm|1111|idx[1]|0|Vn|Vx"},
+ {"inst": "usmmla Vx.4S, Vn.16B, Vm.16B" , "op": "01001110|10|0|Vm|10101|1|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD", "ext": "JSCVT", "data": [
+ {"inst": "fjcvtzs Wd, Dn" , "op": "00011110|011|11110|00000|0|Vn|Vd"}
+ ]},
+
+ {"category": "ASIMD", "ext": "LUT", "data": [
+ {"inst": "luti2 Vd.16B, Vn.16B, Vm[#idx]" , "op": "01001110|100|Vm|0|idx:2|100|Vn|Vd"},
+ {"inst": "luti2 Vd.8H, Vn.8H, Vm[#idx]" , "op": "01001110|110|Vm|0|idx:3|00|Vn|Vd"},
+ {"inst": "luti4 Vd.16B, Vn.16B, Vm[#idx]" , "op": "01001110|010|Vm|0|idx:1|1000|Vn|Vd"},
+ {"inst": "luti4 Vd.8H, 2x{Vn.8H}, Vm[#idx]" , "op": "01001110|010|Vm|0|idx:2|100|Vn|Vd"}
+ ]},
+
+ {"category": "ASIMD", "ext": "LRCPC3", "data": [
+ {"inst": "ldap1 Vd.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00001|10000|1|Rn|Vd"},
+ {"inst": "ldapur Bd, [Xn|SP, #offS]" , "op": "00011101|010|offS:9|10|Rn|Vd"},
+ {"inst": "ldapur Hd, [Xn|SP, #offS]" , "op": "01011101|010|offS:9|10|Rn|Vd"},
+ {"inst": "ldapur Sd, [Xn|SP, #offS]" , "op": "10011101|010|offS:9|10|Rn|Vd"},
+ {"inst": "ldapur Dd, [Xn|SP, #offS]" , "op": "11011101|010|offS:9|10|Rn|Vd"},
+ {"inst": "ldapur Qd, [Xn|SP, #offS]" , "op": "00011101|110|offS:9|10|Rn|Vd"},
+ {"inst": "stl1 Vs.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00001|10000|1|Rn|Vs"},
+ {"inst": "stlur Bs, [Xn|SP, #offS]" , "op": "00011101|000|offS:9|10|Rn|Vs"},
+ {"inst": "stlur Hs, [Xn|SP, #offS]" , "op": "01011101|000|offS:9|10|Rn|Vs"},
+ {"inst": "stlur Ss, [Xn|SP, #offS]" , "op": "10011101|000|offS:9|10|Rn|Vs"},
+ {"inst": "stlur Ds, [Xn|SP, #offS]" , "op": "11011101|000|offS:9|10|Rn|Vs"},
+ {"inst": "stlur Qs, [Xn|SP, #offS]" , "op": "00011101|100|offS:9|10|Rn|Vs"}
+ ]},
+
+ {"category": "ASIMD", "ext": "RDM", "data": [
+ {"inst": "sqrdmlah Hx, Hn, Hm" , "op": "01111110|01|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Sx, Sn, Sm" , "op": "01111110|10|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Hx, Hn, Vn.H[#idx]" , "op": "01111111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Sx, Sn, Vn.S[#idx]" , "op": "01111111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 4H 2S"},
+ {"inst": "sqrdmlah Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|0|Vm|10000|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 8H 4S"},
+ {"inst": "sqrdmlah Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|1101|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlah Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0] |Vm |1101|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Hx, Hn, Hm" , "op": "01111110|01|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Sx, Sn, Sm" , "op": "01111110|10|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Hx, Hn, Vn.H[#idx]" , "op": "01111111|01|idx[1:0]|Vm:4|1111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Sx, Sn, Vn.S[#idx]" , "op": "01111111|10|idx[0] |Vm |1111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Vx.t, Vn.t, Vm.t" , "op": "00101110|sz|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 4H 2S"},
+ {"inst": "sqrdmlsh Vx.t, Vn.t, Vm.t" , "op": "01101110|sz|0|Vm|10001|1|Vn|Vx" , "io": "QC|=SAT", "t": "~ 8H 4S"},
+ {"inst": "sqrdmlsh Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|1111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Vx.2S, Vn.2S, Vm.S[#idx]" , "op": "00101111|10|idx[0] |Vm |1111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Vx.8H, Vn.8H, Vm.H[#idx]" , "op": "01101111|01|idx[1:0]|Vm:4|1111|idx[2]|0|Vn|Vx" , "io": "QC|=SAT"},
+ {"inst": "sqrdmlsh Vx.4S, Vn.4S, Vm.S[#idx]" , "op": "01101111|10|idx[0] |Vm |1111|idx[1]|0|Vn|Vx" , "io": "QC|=SAT"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [
+ {"inst": "sha1c Qx, Sn, Vm.4S" , "op": "01011110|00|0|Vm|00000|0|Vn|Vx"},
+ {"inst": "sha1h Sd, Sn" , "op": "01011110|00|10100|00000|10|Vn|Vd"},
+ {"inst": "sha1m Qx, Sn, Vm.4S" , "op": "01011110|00|0|Vm|00100|0|Vn|Vx"},
+ {"inst": "sha1p Qx, Sn, Vm.4S" , "op": "01011110|00|0|Vm|00010|0|Vn|Vx"},
+ {"inst": "sha1su0 Vx.4S, Vn.4S, Vm.4S" , "op": "01011110|00|0|Vm|00110|0|Vn|Vx"},
+ {"inst": "sha1su1 Vx.4S, Vn.4S" , "op": "01011110|00|1|01000|00011|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [
+ {"inst": "sha256h Qx, Qn, Vm.4S" , "op": "01011110|00|0|Vm|01000|0|Vn|Vx"},
+ {"inst": "sha256h2 Qx, Qn, Vm.4S" , "op": "01011110|00|0|Vm|01010|0|Vn|Vx"},
+ {"inst": "sha256su0 Vx.4S, Vn.4S" , "op": "01011110|00|10100|00010|10|Vn|Vx"},
+ {"inst": "sha256su1 Vx.4S, Vn.4S, Vm.4S" , "op": "01011110|00|0|Vm|01100|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA3", "data": [
+ {"inst": "bcax Vd.16B, Vn.16B, Vm.16B, Va.16B" , "op": "11001110|00|1|Vm|0|Va|Vn|Vd"},
+ {"inst": "eor3 Vd.16B, Vn.16B, Vm.16B, Va.16B" , "op": "11001110|00|0|Vm|0|Va|Vn|Vd"},
+ {"inst": "rax1 Vd.2D, Vn.2D, Vm.2D" , "op": "11001110|01|1|Vm|10001|1|Vn|Vd"},
+ {"inst": "xar Vd.2D, Vn.2D, Vm.2D, #imm" , "op": "11001110|10|0|Vm|imm:6|Vn|Vd"}
+
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SHA512", "data": [
+ {"inst": "sha512h Qx, Qn, Vm.2D" , "op": "11001110|01|1|Vm|10000|0|Vn|Vx"},
+ {"inst": "sha512h2 Qx, Qn, Vm.2D" , "op": "11001110|01|1|Vm|10000|1|Vn|Vx"},
+ {"inst": "sha512su0 Vx.2D, Vn.2D" , "op": "11001110|11|00000|01000|00|Vn|Vx"},
+ {"inst": "sha512su1 Vx.2D, Vn.2D, Vm.2D" , "op": "11001110|01|1|Vm|10001|0|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SM3", "data": [
+ {"inst": "sm3partw1 Vx.4S, Vn.4S, Vm.4S" , "op": "11001110|01|1|Vm|11000|0|Vn|Vx"},
+ {"inst": "sm3partw2 Vx.4S, Vn.4S, Vm.4S" , "op": "11001110|01|1|Vm|11000|1|Vn|Vx"},
+ {"inst": "sm3ss1 Vd.4S, Vn.4S, Vm.4S, Va.4S" , "op": "11001110|01|0|Vm|0|Va|Vn|Vd"},
+ {"inst": "sm3tt1a Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|00|Vn|Vx"},
+ {"inst": "sm3tt1b Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|01|Vn|Vx"},
+ {"inst": "sm3tt2a Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|10|Vn|Vx"},
+ {"inst": "sm3tt2b Vx.4S, Vn.4S, Vm.4[#idx]" , "op": "11001110|01|0|Vm|10|idx:2|11|Vn|Vx"}
+ ]},
+
+ {"category": "ASIMD CRYPTO_HASH", "ext": "SM4", "data": [
+ {"inst": "sm4e Vx.4S, Vn.4S" , "op": "11001110|11|0|00000|10000|1|Vn|Vx"},
+ {"inst": "sm4ekey Vd.4S, Vn.4S, Vm.4S" , "op": "11001110|01|1|Vm|11001|0|Vn|Vd"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE", "data": [
+ {"inst": "abs Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|0|10110101|Pg:3|Zn|Zd"},
+ {"inst": "add Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000000|Zn|Zd"},
+ {"inst": "add Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10000011|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+ {"inst": "add Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|000000000|Pg:3|Zm|Zdn"},
+ {"inst": "addp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010001101|Pg:3|Zm|Zdn"},
+ {"inst": "addpl Xd|SP, Xn|SP, #immS" , "op": "00000100|01|1|Rn|01010|immS:6|Rd"},
+ {"inst": "addvl Xd|SP, Xn|SP, #immS" , "op": "00000100|00|1|Rn|01010|immS:6|Rd"},
+ {"inst": "adr Zd.t, [Zn.t, Zm.t, {lsl #n}]" , "op": "00000100|sz|1|Zm|1010|msz|Zn|Zd" , "t": "~~SD"},
+ {"inst": "adr Zd.D, [Zn.D, Zm.D, {sxtw #n}]" , "op": "00000100|00|1|Zm|1010|msz|Zn|Zd"},
+ {"inst": "adr Zd.D, [Zn.D, Zm.D, {uxtw #n}]" , "op": "00000100|01|1|Zm|1010|msz|Zn|Zd"},
+ {"inst": "and Zd.D, Zn.D, Zm.D" , "op": "00000100|00|1|Zm|001100|Zn|Zd"},
+ {"inst": "and Zdn.t, Zdn.t, #imm" , "op": "00000101|10|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 0, t)"},
+ {"inst": "and Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|0|Pn|0|Pd"},
+ {"inst": "and Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011010000|Pg:3|Zm|Zdn"},
+ {"inst": "ands Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|01|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "andv Vd, Pg, Zn.t" , "op": "00000100|sz|011010001|Pg:3|Zn|Vd"},
+ {"inst": "asr Zd.t, Zn.t, Zm.D" , "op": "00000100|sz|1|Zm|100000|Zn|Zd" , "t": "BHS~"},
+ {"inst": "asr Zd.t, Zn.t, #imm" , "op": "00000100|imm:2|1|imm:5|100100|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "asr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010000100|Pg:3|Zm|Zdn"},
+ {"inst": "asr Zdn.t, Pg/M, Zdn.t, Zm.D" , "op": "00000100|sz|011000100|Pg:3|Zm|Zdn" , "t": "BHS~"},
+ {"inst": "asr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000000100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "asrd Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000100100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "asrr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010100100|Pg:3|Zm|Zdn"},
+ {"inst": "bic Zd.D, Zn.D, Zm.D" , "op": "00000100|11|1|Zm|001100|Zn|Zd"},
+ {"inst": "bic Zdn.t, Zdn.t, #imm" , "op": "00000101|10|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 1, t)"},
+ {"inst": "bic Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011010000|Pg:3|Zm|Zdn"},
+ {"inst": "bic Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|0|Pn|1|Pd"},
+ {"inst": "bics Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|10|Pm|01|Pg|0|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "brka Pd.B, Pg/MZ, Pn.B" , "op": "00100101|00|01000001|Pg|0|Pn|M|Pd"},
+ {"inst": "brkas Pd.B, Pg/M, Pn.B" , "op": "00100101|01|01000001|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "brkb Pd.B, Pg/MZ, Pn.B" , "op": "00100101|10|01000001|Pg|0|Pn|M|Pd"},
+ {"inst": "brkbs Pd.B, Pg/M, Pn.B" , "op": "00100101|11|01000001|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "brkn Pdm.B, Pg/Z, Pn.B, Pdm.B" , "op": "00100101|00|01100001|Pg|0|Pn|0|Pdm"},
+ {"inst": "brkns Pdm.B, Pg/Z, Pn.B, Pdm.B" , "op": "00100101|01|01100001|Pg|0|Pn|0|Pdm" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "brkpa Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|11|Pg|0|Pn|0|Pd"},
+ {"inst": "brkpas Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|11|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "brkpb Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|11|Pg|0|Pn|1|Pd"},
+ {"inst": "brkpbs Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|11|Pg|0|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "clasta Wdn, Pg, Wdn, Zm.t" , "op": "00000101|sz|110000101|Pg:3|Zm|Rdn" , "t": "BHS~"},
+ {"inst": "clasta Xdn, Pg, Xdn, Zm.D" , "op": "00000101|11|110000101|Pg:3|Zm|Rdn"},
+ {"inst": "clasta Bdn, Pg, Bdn, Zm.t" , "op": "00000101|00|101010100|Pg:3|Zm|Vdn"},
+ {"inst": "clasta Hdn, Pg, Hdn, Zm.t" , "op": "00000101|01|101010100|Pg:3|Zm|Vdn"},
+ {"inst": "clasta Sdn, Pg, Sdn, Zm.t" , "op": "00000101|10|101010100|Pg:3|Zm|Vdn"},
+ {"inst": "clasta Ddn, Pg, Ddn, Zm.t" , "op": "00000101|11|101010100|Pg:3|Zm|Vdn"},
+ {"inst": "clasta Zdn.t, Pg, Zdn.t, Zm.t" , "op": "00000101|sz|101000100|Pg:3|Zm|Zdn"},
+ {"inst": "clastb Wdn, Pg, Wdn, Zm.t" , "op": "00000101|sz|110001101|Pg:3|Zm|Rdn" , "t": "BHS~"},
+ {"inst": "clastb Xdn, Pg, Xdn, Zm.D" , "op": "00000101|11|110001101|Pg:3|Zm|Rdn"},
+ {"inst": "clastb Bdn, Pg, Bdn, Zm.t" , "op": "00000101|00|101011100|Pg:3|Zm|Vdn"},
+ {"inst": "clastb Hdn, Pg, Hdn, Zm.t" , "op": "00000101|01|101011100|Pg:3|Zm|Vdn"},
+ {"inst": "clastb Sdn, Pg, Sdn, Zm.t" , "op": "00000101|10|101011100|Pg:3|Zm|Vdn"},
+ {"inst": "clastb Ddn, Pg, Ddn, Zm.t" , "op": "00000101|11|101011100|Pg:3|Zm|Vdn"},
+ {"inst": "clastb Zdn.t, Pg, Zdn.t, Zm.t" , "op": "00000101|sz|101001100|Pg:3|Zm|Zdn"},
+ {"inst": "cls Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011000101|Pg:3|Zn|Zd"},
+ {"inst": "clz Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011001101|Pg:3|Zn|Zd"},
+ {"inst": "cmpeq Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|101|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpeq Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|001|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmpeq Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|100|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpgt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|100|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpgt Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|010|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmpgt Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|000|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpge Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|100|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpge Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|010|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmpge Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|000|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmphi Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|000|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmphi Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|110|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmphi Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|0|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmphs Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|000|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmphs Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|110|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmphs Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|0|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmple Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|100|Pg:3|Zm|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmple Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|011|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmple Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|001|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmplo Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|000|Pg:3|Zm|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmplo Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|111|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmplo Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|1|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpls Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|000|Pg:3|Zm|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpls Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|111|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmpls Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100100|sz|1|immS:7|1|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmplt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zn|100|Pg:3|Zm|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmplt Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|011|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmplt Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|001|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpne Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "00100100|sz|0|Zm|101|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cmpne Pd.t, Pg/Z, Zn.t, Zm.D" , "op": "00100100|sz|0|Zm|001|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BHS~"},
+ {"inst": "cmpne Pd.t, Pg/Z, Zn.t, #immS" , "op": "00100101|sz|0|immS:5|100|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "cnot Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011011101|Pg:3|Zn|Zd"},
+ {"inst": "cnt Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011010101|Pg:3|Zn|Zd"},
+ {"inst": "cntb Xd, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "cntd Xd, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "cnth Xd, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "cntp Xd, Pg, Pn.t" , "op": "00100101|sz|10000010|Pg|0|Pn|Rd"},
+ {"inst": "cntw Xd, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111000|pattern:5|Rd" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "compact Zd.t, Pg, Zn.t" , "op": "00000101|sz|10000010|Pg|0|Pn|Rd" , "t": "~~SD"},
+ {"inst": "cpy Zd.t, Pg/M, Wn|SP" , "op": "00000101|sz|101000101|Pg:3|Rn|Zd" , "t": "BHS~"},
+ {"inst": "cpy Zd.D, Pg/M, Xn|SP" , "op": "00000101|11|101000101|Pg:3|Rn|Zd"},
+ {"inst": "cpy Zd.B, Pg/M, Bn" , "op": "00000101|00|100000100|Pg:3|Rn|Zd"},
+ {"inst": "cpy Zd.H, Pg/M, Hn" , "op": "00000101|01|100000100|Pg:3|Rn|Zd"},
+ {"inst": "cpy Zd.S, Pg/M, Sn" , "op": "00000101|10|100000100|Pg:3|Rn|Zd"},
+ {"inst": "cpy Zd.D, Pg/M, Dn" , "op": "00000101|11|100000100|Pg:3|Rn|Zd"},
+ {"inst": "cpy Zd.t, Pg/MZ, #imm, {lsl #n}" , "op": "00000101|sz|01|Pg|0|M|n:1|imm:8|Zd"},
+ {"inst": "ctermeq Rn, Rm" , "op": "00100101|1X|1|Rm|001000|Rn|00000"},
+ {"inst": "ctermne Rn, Rm" , "op": "00100101|1X|1|Rm|001000|Rn|10000"},
+ {"inst": "decb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "decd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "decd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|110001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "dech Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "dech Zdn.H, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|110001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "decp Xdn, Pm.t" , "op": "00100101|sz|1011011000100|Pm|Rdn"},
+ {"inst": "decp Zdn.t, Pm.t" , "op": "00100101|sz|1011011000000|Pm|Zdn" , "t": "~HSD"},
+ {"inst": "decw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "decw Zdn.S, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|110001|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "dup Zd.t, Wn|SP" , "op": "00000101|sz|100000001110|Rn|Zd" , "T": "BHS~"},
+ {"inst": "dup Zd.t, Xn|SP" , "op": "00000101|11|100000001110|Rn|Zd"},
+ {"inst": "dup Zd.t, Zn.t[#idx]" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "imm": "SveDupImm(sz, idx)"},
+ {"inst": "dup Zd.t, #imm, {lsl #n}" , "op": "00100101|sz|11100011|n:1|imm:8|Zd"},
+ {"inst": "dupm Zd.t, #imm" , "op": "00000101|11|0000|imm:13|Zd" , "imm": "SveDupmImm(sz, imm)"},
+ {"inst": "eon Zdn.t, Zdn.t, #imm" , "op": "00000101|01|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 1, t)"},
+ {"inst": "eor Zd.D, Zn.D, Zm.D" , "op": "00000100|10|1|Zm|001100|Zn|Zd"},
+ {"inst": "eor Zdn.t, Zdn.t, #imm" , "op": "00000101|01|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 0, t)"},
+ {"inst": "eor Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011001000|Pg:3|Zm|Zdn"},
+ {"inst": "eor Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|1|Pn|0|Pd"},
+ {"inst": "eors Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|01|00|Pm|01|Pg|1|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "eorv Bd, Pg, Zn.t" , "op": "00000100|00|011001001|Pg:3|Zn|Vd"},
+ {"inst": "eorv Hd, Pg, Zn.t" , "op": "00000100|01|011001001|Pg:3|Zn|Vd"},
+ {"inst": "eorv Sd, Pg, Zn.t" , "op": "00000100|10|011001001|Pg:3|Zn|Vd"},
+ {"inst": "eorv Dd, Pg, Zn.t" , "op": "00000100|11|011001001|Pg:3|Zn|Vd"},
+ {"inst": "ext Zdn.B, Zdn.B, Zm.B, #imm" , "op": "00000101|00|1|imm:5|000|imm:3|Zm|Zdn"},
+ {"inst": "fabd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001000100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fabs Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011100101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "facge Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|110|Pg:3|Zn|1|Pd" , "t": "~HSD"},
+ {"inst": "facgt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|111|Pg:3|Zn|1|Pd" , "t": "~HSD"},
+ {"inst": "facle Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|110|Pg:3|Zm|1|Pd" , "t": "~HSD"},
+ {"inst": "faclt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|111|Pg:3|Zm|1|Pd" , "t": "~HSD"},
+ {"inst": "fadd Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000000|Zn|Zd" , "t": "~HSD"},
+ {"inst": "fadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000000100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fadd Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011000100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrOneImm(immF)"},
+ {"inst": "fadda Hdn, Pg, Hdn, Zm.H" , "op": "01100101|01|011000001|Pg:3|Zm|Vdn"},
+ {"inst": "fadda Sdn, Pg, Sdn, Zm.S" , "op": "01100101|10|011000001|Pg:3|Zm|Vdn"},
+ {"inst": "fadda Ddn, Pg, Ddn, Zm.D" , "op": "01100101|11|011000001|Pg:3|Zm|Vdn"},
+ {"inst": "faddv Hd, Pg, Zn.H" , "op": "01100101|01|000000001|Pg:3|Zn|Vd"},
+ {"inst": "faddv Sd, Pg, Zn.S" , "op": "01100101|10|000000001|Pg:3|Zn|Vd"},
+ {"inst": "faddv Dd, Pg, Zn.D" , "op": "01100101|11|000000001|Pg:3|Zn|Vd"},
+ {"inst": "fcadd Zdn.t, Pg/M, Zdn.t, Zm.t, #rot2" , "op": "01100100|sz|00000|imm:1|100|Pg:3|Zm|Zdn" , "t": "~HSD", "imm": "Rot1Imm(rot1)"},
+ {"inst": "fcmeq Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|011|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmeq Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|0|10010001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmge Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|010|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmge Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|0|10000001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmgt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|010|Pg:3|Zn|1|Pd" , "t": "~HSD"},
+ {"inst": "fcmgt Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|0|10000001|Pg:3|Zn|1|Pd" , "t": "~HSD"},
+ {"inst": "fcmle Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|010|Pg:3|Zm|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmle Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|010001001|Pg:3|Zn|1|Pd" , "t": "~HSD"},
+ {"inst": "fcmlt Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zn|010|Pg:3|Zm|1|Pd" , "t": "~HSD"},
+ {"inst": "fcmlt Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|010001001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmne Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|011|Pg:3|Zn|1|Pd" , "t": "~HSD"},
+ {"inst": "fcmne Pd.t, Pg/Z, Zn.t, #zero" , "op": "01100101|sz|010011001|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcmuo Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|110|Pg:3|Zn|0|Pd" , "t": "~HSD"},
+ {"inst": "fcpy Zd.t, Pg/M, #immVFP" , "op": "00000101|sz|01|Pg|110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)"},
+ {"inst": "fcvt Zd.S, Pg/M, Zn.H" , "op": "01100101|10|001001101|Pg:3|Zn|Zd"},
+ {"inst": "fcvt Zd.D, Pg/M, Zn.H" , "op": "01100101|11|001001101|Pg:3|Zn|Zd"},
+ {"inst": "fcvt Zd.H, Pg/M, Zn.S" , "op": "01100101|10|001000101|Pg:3|Zn|Zd"},
+ {"inst": "fcvt Zd.D, Pg/M, Zn.S" , "op": "01100101|11|001011101|Pg:3|Zn|Zd"},
+ {"inst": "fcvt Zd.H, Pg/M, Zn.D" , "op": "01100101|11|001000101|Pg:3|Zn|Zd"},
+ {"inst": "fcvt Zd.S, Pg/M, Zn.D" , "op": "01100101|11|001010101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.H, Pg/M, Zn.H" , "op": "01100101|01|011010101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.S, Pg/M, Zn.H" , "op": "01100101|01|011100101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.D, Pg/M, Zn.H" , "op": "01100101|01|011110101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.S, Pg/M, Zn.S" , "op": "01100101|10|011100101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.D, Pg/M, Zn.S" , "op": "01100101|11|011100101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.S, Pg/M, Zn.D" , "op": "01100101|11|011000101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzs Zd.D, Pg/M, Zn.D" , "op": "01100101|11|011110101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.H, Pg/M, Zn.H" , "op": "01100101|01|011011101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.S, Pg/M, Zn.H" , "op": "01100101|01|011101101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.D, Pg/M, Zn.H" , "op": "01100101|01|011111101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.S, Pg/M, Zn.S" , "op": "01100101|10|011101101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.D, Pg/M, Zn.S" , "op": "01100101|11|011101101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.S, Pg/M, Zn.D" , "op": "01100101|11|011001101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtzu Zd.D, Pg/M, Zn.D" , "op": "01100101|11|011111101|Pg:3|Zn|Zd"},
+ {"inst": "fdiv Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001101100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fdivr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001100100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fdup Zd.t, #immVFP" , "op": "00100101|sz|111001110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)"},
+ {"inst": "fexpa Zd.t, Zn.t" , "op": "00000100|sz|100000101110|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmad Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmax Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000110100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmax Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011110100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
+ {"inst": "fmaxnm Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000100100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmaxnm Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011100100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
+ {"inst": "fmaxnmv Hd, Pg, Zn.H" , "op": "01100101|01|000100001|Pg:3|Zm|Zd"},
+ {"inst": "fmaxnmv Sd, Pg, Zn.S" , "op": "01100101|10|000100001|Pg:3|Zm|Zd"},
+ {"inst": "fmaxnmv Dd, Pg, Zn.D" , "op": "01100101|11|000100001|Pg:3|Zm|Zd"},
+ {"inst": "fmaxv Hd, Pg, Zn.H" , "op": "01100101|01|000110001|Pg:3|Zm|Zd"},
+ {"inst": "fmaxv Sd, Pg, Zn.S" , "op": "01100101|10|000110001|Pg:3|Zm|Zd"},
+ {"inst": "fmaxv Dd, Pg, Zn.D" , "op": "01100101|11|000110001|Pg:3|Zm|Zd"},
+ {"inst": "fmin Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000111100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmin Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011111100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
+ {"inst": "fminnm Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000101100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fminnm Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011101100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpZeroOrOneImm(immF)"},
+ {"inst": "fminnmv Hd, Pg, Zn.H" , "op": "01100101|01|000101001|Pg:3|Zm|Zd"},
+ {"inst": "fminnmv Sd, Pg, Zn.S" , "op": "01100101|10|000101001|Pg:3|Zm|Zd"},
+ {"inst": "fminnmv Dd, Pg, Zn.D" , "op": "01100101|11|000101001|Pg:3|Zm|Zd"},
+ {"inst": "fminv Hd, Pg, Zn.H" , "op": "01100101|01|000111001|Pg:3|Zm|Zd"},
+ {"inst": "fminv Sd, Pg, Zn.S" , "op": "01100101|10|000111001|Pg:3|Zm|Zd"},
+ {"inst": "fminv Dd, Pg, Zn.D" , "op": "01100101|11|000111001|Pg:3|Zm|Zd"},
+ {"inst": "fmla Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|000|Pg:3|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmla Zda.H, Zn.H, Zm.H[#idx]" , "op": "01100100|0|idx:1|1|idx:2|Zm:3|000000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmla Zda.S, Zn.S, Zm.S[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|000000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmla Zda.D, Zn.D, Zm.D[#idx]" , "op": "01100100|11|1|idx:1|Zm:4|000000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmls Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|001|Pg:3|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmls Zda.H, Zn.H, Zm.H[#idx]" , "op": "01100100|0|idx:1|1|idx:2|Zm:3|000001|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmls Zda.S, Zn.S, Zm.S[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|000001|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmls Zda.D, Zn.D, Zm.D[#idx]" , "op": "01100100|11|1|idx:1|Zm:4|000001|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmov Zd.t, #zero" , "op": "00100101|sz|111000110|00000000|Zd" , "t": "~HSD", "aliasOf": "dup"},
+ {"inst": "fmov Zd.t, #immVFP" , "op": "00100101|sz|111001110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)", "aliasOf": "fdup"},
+ {"inst": "fmov Zd.t, Pg/M, #zero" , "op": "00000101|sz|01|Pg|010|00000000|Zd" , "t": "~HSD", "aliasOf": "cpy"},
+ {"inst": "fmov Zd.t, Pg/M, #immVFP" , "op": "00000101|sz|01|Pg|110|imm:8|Zd" , "t": "~HSD", "imm": "VecVFPImm(immVFP)", "aliasOf": "fcpy"},
+ {"inst": "fmsb Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|101|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmul Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000010|Zn|Zd" , "t": "~HSD"},
+ {"inst": "fmul Zd.H, Zn.H, Zm.H[#idx]" , "op": "01100100|0|idx:1|1|idx:2|Zm:3|001000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmul Zd.S, Zn.S, Zm.S[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|001000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmul Zd.D, Zn.D, Zm.D[#idx]" , "op": "01100100|11|1|idx:1|Zm:4|001000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmul Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000010100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmul Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011010100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrTwoImm(immF)"},
+ {"inst": "fmulx Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001010100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fneg Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011101101|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fnmad Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|110|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fnmla Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|010|Pg:3|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fnmls Zda.t, Pg/M, Zn.t, Zm.t" , "op": "01100101|sz|1|Zm|011|Pg:3|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fnmsb Zdn.t, Pg/M, Zm.t, Za.t" , "op": "01100101|sz|1|Za|111|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "frecpe Zd.t, Zn.t" , "op": "01100101|sz|001110001100|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frecps Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000110|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frecpx Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|001100101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frinta Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000100101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frinti Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000111101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frintm Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000010101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frintn Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000000101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frintp Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000001101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frintx Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000110101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frintz Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|000011101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frsqrte Zd.t, Zn.t" , "op": "01100101|sz|001111001100|Zn|Zd" , "t": "~HSD"},
+ {"inst": "frsqrts Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000111|Zn|Zd" , "t": "~HSD"},
+ {"inst": "fscale Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|001001100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fsqrt Zd.t, Pg/M, Zn.t" , "op": "01100101|sz|001101101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "fsub Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000001|Zn|Zd" , "t": "~HSD"},
+ {"inst": "fsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000001100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fsub Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011001100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrOneImm(immF)"},
+ {"inst": "fsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100101|sz|000011100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fsubr Zdn.t, Pg/M, Zdn.t, #immF" , "op": "01100101|sz|011011100|Pg:3|0000|imm:1|Zdn" , "t": "~HSD", "imm": "FpHalfOrOneImm(immF)"},
+ {"inst": "ftmad Zdn.t, Zdn.t, Zm.t, #imm" , "op": "01100101|sz|010|imm:3|100000|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "ftsmul Zd.t, Zn.t, Zm.t" , "op": "01100101|sz|0|Zm|000011|Zn|Zd" , "t": "~HSD"},
+ {"inst": "ftssel Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|101100|Zn|Zd" , "t": "~HSD"},
+ {"inst": "incb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "incd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "incd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "inch Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "inch Zdn.H, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "incp Xdn, Pm.t" , "op": "00100101|sz|1011001000100|Pm|Rdn"},
+ {"inst": "incp Zdn.t, Pm.t" , "op": "00100101|sz|1011001000000|Pm|Zdn" , "t": "~HSD"},
+ {"inst": "incw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111000|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "incw Zdn.S, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "index Zd.t, Wn, Wm" , "op": "00000100|sz|1|Rm|010011|Rn|Zd" , "t": "BHS~"},
+ {"inst": "index Zd.D, Xn, Xm" , "op": "00000100|11|1|Rm|010011|Rn|Zd"},
+ {"inst": "index Zd.t, Wn, #immS" , "op": "00000100|sz|1|immS:5|010001|Rn|Zd" , "t": "BHS~"},
+ {"inst": "index Zd.D, Xn, #immS" , "op": "00000100|11|1|immS:5|010001|Rn|Zd"},
+ {"inst": "index Zd.t, #immS, Wm" , "op": "00000100|sz|1|Rm|010010|immS:5|Zd" , "t": "BHS~"},
+ {"inst": "index Zd.D, #immS, Xm" , "op": "00000100|11|1|Rm|010010|immS:5|Zd"},
+ {"inst": "index Zd.t, #immSa, #immSb" , "op": "00000100|sz|1|immSb:5|010000|immSa:5|Zd"},
+ {"inst": "insr Zdn.t, Wm" , "op": "00000101|sz|100100001110|Rm|Zdn" , "t": "BHS~"},
+ {"inst": "insr Zdn.D, Xm" , "op": "00000101|11|100100001110|Rm|Zdn"},
+ {"inst": "insr Zdn.B, Bm" , "op": "00000101|00|110100001110|Vm|Zdn"},
+ {"inst": "insr Zdn.H, Hm" , "op": "00000101|01|110100001110|Vm|Zdn"},
+ {"inst": "insr Zdn.S, Sm" , "op": "00000101|10|110100001110|Vm|Zdn"},
+ {"inst": "insr Zdn.D, Dm" , "op": "00000101|11|110100001110|Vm|Zdn"},
+ {"inst": "lasta Wd, Pg, Zn.t" , "op": "00000101|sz|100000101|Pg:3|Zn|Rd" , "t": "BHS~"},
+ {"inst": "lasta Xd, Pg, Zn.D" , "op": "00000101|11|100000101|Pg:3|Zn|Rd"},
+ {"inst": "lasta Bd, Pg, Zn.B" , "op": "00000101|00|100010100|Pg:3|Zn|Rd"},
+ {"inst": "lasta Hd, Pg, Zn.H" , "op": "00000101|01|100010100|Pg:3|Zn|Rd"},
+ {"inst": "lasta Sd, Pg, Zn.S" , "op": "00000101|10|100010100|Pg:3|Zn|Rd"},
+ {"inst": "lasta Dd, Pg, Zn.D" , "op": "00000101|11|100010100|Pg:3|Zn|Rd"},
+ {"inst": "lastb Wd, Pg, Zn.t" , "op": "00000101|sz|100001101|Pg:3|Zn|Rd" , "t": "BHS~"},
+ {"inst": "lastb Xd, Pg, Zn.D" , "op": "00000101|11|100001101|Pg:3|Zn|Rd"},
+ {"inst": "lastb Bd, Pg, Zn.B" , "op": "00000101|00|100011100|Pg:3|Zn|Rd"},
+ {"inst": "lastb Hd, Pg, Zn.H" , "op": "00000101|01|100011100|Pg:3|Zn|Rd"},
+ {"inst": "lastb Sd, Pg, Zn.S" , "op": "00000101|10|100011100|Pg:3|Zn|Rd"},
+ {"inst": "lastb Dd, Pg, Zn.D" , "op": "00000101|11|100011100|Pg:3|Zn|Rd"},
+
+ {"inst": "lsl Zd.t, Zn.t, Zm.D" , "op": "00000100|sz|1|Zm|100011|Zn|Zd" , "t": "BHS~"},
+ {"inst": "lsl Zd.t, Zn.t, #imm" , "op": "00000100|imm:2|1|imm:5|100111|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "lsl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010011100|Pg:3|Zm|Zdn"},
+ {"inst": "lsl Zdn.t, Pg/M, Zdn.t, Zm.D" , "op": "00000100|sz|011011100|Pg:3|Zm|Zdn" , "t": "BHS~"},
+ {"inst": "lsl Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000011100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "lslr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010111100|Pg:3|Zm|Zdn"},
+ {"inst": "lsr Zd.t, Zn.t, Zm.D" , "op": "00000100|sz|1|Zm|100001|Zn|Zd" , "t": "BHS~"},
+ {"inst": "lsr Zd.t, Zn.t, #imm" , "op": "00000100|imm:2|1|imm:5|100101|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "lsr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010001100|Pg:3|Zm|Zdn"},
+ {"inst": "lsr Zdn.t, Pg/M, Zdn.t, Zm.D" , "op": "00000100|sz|011001100|Pg:3|Zm|Zdn" , "t": "BHS~"},
+ {"inst": "lsr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000001100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "lsrr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010101100|Pg:3|Zm|Zdn"},
+ {"inst": "mad Zdn.t, Pg/M, Zm.t, Za.t" , "op": "00000100|sz|0|Zm|110|Pg:3|Za|Zdn"},
+ {"inst": "mla Zda.t, Pg/M, Zn.t, Zm.t" , "op": "00000100|sz|0|Zm|010|Pg:3|Za|Zdn"},
+ {"inst": "mls Zda.t, Pg/M, Zn.t, Zm.t" , "op": "00000100|sz|0|Zm|011|Pg:3|Za|Zdn"},
+ {"inst": "mov Pd.B, Pn.B" , "op": "001001011000|Pn|01|Pn|0|Pn|0|Pd" , "aliasOf": "orr"},
+ {"inst": "mov Zd.t, Wn|SP" , "op": "00000101|sz|100000001110|Rn|Zd" , "aliasOf": "dup", "T": "BHS~"},
+ {"inst": "mov Zd.t, Xn|SP" , "op": "00000101|11|100000001110|Rn|Zd" , "aliasOf": "dup"},
+ {"inst": "mov Zd.B, Bn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(0, 0)"},
+ {"inst": "mov Zd.H, Hn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(1, 0)"},
+ {"inst": "mov Zd.S, Sn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(2, 0)"},
+ {"inst": "mov Zd.D, Dn" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(3, 0)"},
+ {"inst": "mov Zd.D, Zn.D" , "op": "00000100|01|1|Zn|001100|Zn|Zd" , "aliasOf": "orr"},
+ {"inst": "mov Zd.t, Zn.t[#idx]" , "op": "00000101|imm:2|1|imm:5|001000|Zn|Zd" , "aliasOf": "dup", "imm": "SveDupImm(sz, idx)"},
+ {"inst": "mov Zd.t, #imm" , "op": "00000101|11|0000|imm:13|Zd" , "aliasOf": "dupm", "imm": "SveDupmImm(sz, imm)"},
+ {"inst": "mov Zd.t, #imm, {lsl #n}" , "op": "00100101|sz|11100011|n:1|imm:8|Zd" , "aliasOf": "dup"},
+ {"inst": "mov Pd.B, Pg/M, Pn.B" , "op": "00100101|00|00|Pd|01|Pg|1|Pn|1|Pd" , "aliasOf": "sel"},
+ {"inst": "mov Pd.B, Pg/Z, Pn.B" , "op": "00100101|00|00|Pn|01|Pg|0|Pn|0|Pd" , "aliasOf": "and"},
+ {"inst": "mov Zd.t, Pg/M, Wn|SP" , "op": "00000101|sz|101000101|Pg:3|Rn|Zd" , "aliasOf": "cpy", "t": "BHS~"},
+ {"inst": "mov Zd.D, Pg/M, Xn|SP" , "op": "00000101|11|101000101|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
+ {"inst": "mov Zd.B, Pg/M, Bn" , "op": "00000101|00|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
+ {"inst": "mov Zd.H, Pg/M, Hn" , "op": "00000101|01|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
+ {"inst": "mov Zd.S, Pg/M, Sn" , "op": "00000101|10|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
+ {"inst": "mov Zd.D, Pg/M, Dn" , "op": "00000101|11|100000100|Pg:3|Rn|Zd" , "aliasOf": "cpy"},
+ {"inst": "mov Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|1|Zd|11|Pg|Zn|Zd" , "aliasOf": "sel"},
+ {"inst": "mov Zd.t, Pg/MZ, #imm, {lsl #n}" , "op": "00000101|sz|01|Pg|0M|n:1|imm:8|Zd" , "aliasOf": "cpy"},
+ {"inst": "movprfx Zd, Zn" , "op": "00000100|00|100000101111|Zn|Zd"},
+ {"inst": "movprfx Zd.t, Pg/MZ, Zn.t" , "op": "00000100|sz|01000M001|Pg:3|Zn|Zd"},
+ {"inst": "movs Pd.B, Pn.B" , "op": "00100101|11|00|Pn|01|Pn|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W", "aliasOf": "orrs"},
+ {"inst": "movs Pd.B, Pg/Z, Pn.B" , "op": "00100101|01|00|Pn|01|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W", "aliasOf": "ands"},
+ {"inst": "msb Zdn.t, Pg/M, Zm.t, Za.t" , "op": "00000100|sz|0|Zm|111|Pg:3|Za|Zdn"},
+ {"inst": "mul Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|110000110|immS:8|Zdn"},
+ {"inst": "mul Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010000000|Pg:3|Zm|Zdn"},
+ {"inst": "nand Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|10|00|Pm|01|Pg|1|Pn|1|Pd"},
+ {"inst": "nands Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|1|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "neg Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010111101|Pg:3|Zm|Zdn"},
+ {"inst": "nor Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|10|00|Pm|01|Pg|1|Pn|0|Pd"},
+ {"inst": "nors Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|1|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "not Pd.B, Pg/Z, Pn.B" , "op": "00100101|00|00|Pg|01|Pg|1|Pn|0|Pd"},
+ {"inst": "not Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|011110101|Pg:3|Zn|Zd"},
+ {"inst": "nots Pd.B, Pg/Z, Pn.B" , "op": "00100101|01|00|Pg|01|Pg|1|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "orn Zdn.t, Zdn.t, #imm" , "op": "00000101|00|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 1, t)"},
+ {"inst": "orn Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|10|00|Pm|01|Pg|0|Pn|1|Pd"},
+ {"inst": "orns Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|0|Pn|1|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "orr Zd.D, Zn.D, Zm.D" , "op": "00000100|01|1|Zm|001100|Zn|Zd"},
+ {"inst": "orr Zdn.t, Zdn.t, #imm" , "op": "00000101|00|0000|imm:13|Zdn" , "imm": "SveLogicalImm(imm, 0, t)"},
+ {"inst": "orr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|011000000|Pg:3|Zm|Zdn"},
+ {"inst": "orr Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100100|10|00|Pm|01|Pg|0|Pn|0|Pd"},
+ {"inst": "orrs Pd.B, Pg/Z, Pn.B, Pm.B" , "op": "00100101|11|00|Pm|01|Pg|0|Pn|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "orv Bd, Pg, Zn.B" , "op": "00000100|00|011000001|Pg:3|Zn|Vd"},
+ {"inst": "orv Hd, Pg, Zn.H" , "op": "00000100|01|011000001|Pg:3|Zn|Vd"},
+ {"inst": "orv Sd, Pg, Zn.S" , "op": "00000100|10|011000001|Pg:3|Zn|Vd"},
+ {"inst": "orv Dd, Pg, Zn.D" , "op": "00000100|11|011000001|Pg:3|Zn|Vd"},
+ {"inst": "pfalse Pd.B" , "op": "00100101|00|011000111001|000000|Pd"},
+ {"inst": "pfirst Pdn.B, Pg, Pdn.B" , "op": "00100101|01|0110001100000|Pg|0|Pdn"},
+ {"inst": "pnext Pdn.t, Pg, Pdn.t" , "op": "00100101|sz|0110011100010|Pg|0|Pdn"},
+
+ {"inst": "ptest Pg, Pn.B" , "op": "00100101|01|01000011|Pg|0|Pn|00000" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "ptrue Pd.t, {#pattern}" , "op": "00100101|sz|011000111000|pattern:5|0|Pd"},
+ {"inst": "ptrues Pd.t, {#pattern}" , "op": "00100101|sz|011001111000|pattern:5|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "punpkhi Pd.H, Pn.B" , "op": "00000101|00|1100010100000|Pn|0|Pd"},
+ {"inst": "punpklo Pd.H, Pn.B" , "op": "00000101|00|1100000100000|Pn|0|Pd"},
+ {"inst": "rbit Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|100111100|Pg:3|Zn|Zd"},
+ {"inst": "rdffr Pd.B" , "op": "00100101|00|011001111100000000|Pd"},
+ {"inst": "rdffr Pd.B, Pg/Z" , "op": "00100101|00|0110001111000|Pg|0|Pd"},
+ {"inst": "rdffrs Pd.B, Pg/Z" , "op": "00100101|01|0110001111000|Pg|0|Pd" , "io": "N=W Z=W C=W V=W"},
+ {"inst": "rdvl Xd, #immS" , "op": "00000100|10|11111101010|immS:6|Rd"},
+ {"inst": "rev Pd.t, Pn.t" , "op": "00000101|sz|1101000100000|Pn|0|Pd"},
+ {"inst": "rev Zd.t, Zn.t" , "op": "00000101|sz|111000001110|Zn|Zd"},
+ {"inst": "revb Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|100100100|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "revh Zd.t, Pg/M, Zn.t" , "op": "00000101|sz|100101100|Pg:3|Zn|Zd" , "t": "~~SD"},
+ {"inst": "revw Zd.D, Pg/M, Zn.D" , "op": "00000101|11|100110100|Pg:3|Zn|Zd"},
+ {"inst": "rshrnb Zd.ta, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000110|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "rshrnt Zd.ta, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000111|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sabd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|01100000|Pg:3|Zm|Zdn"},
+ {"inst": "saddv Dd, Pg, Zn.t" , "op": "00000100|sz|0|00000001|Pg:3|Zn|Vd" , "t": "BHS~"},
+ {"inst": "scvtf Zd.H, Pg/M, Zn.H" , "op": "01100101|01|0|10010101|Pg:3|Zn|Zd"},
+ {"inst": "scvtf Zd.H, Pg/M, Zn.S" , "op": "01100101|01|0|10100101|Pg:3|Zn|Zd"},
+ {"inst": "scvtf Zd.S, Pg/M, Zn.S" , "op": "01100101|10|0|10100101|Pg:3|Zn|Zd"},
+ {"inst": "scvtf Zd.D, Pg/M, Zn.S" , "op": "01100101|11|0|10000101|Pg:3|Zn|Zd"},
+ {"inst": "scvtf Zd.H, Pg/M, Zn.D" , "op": "01100101|01|0|10110101|Pg:3|Zn|Zd"},
+ {"inst": "scvtf Zd.S, Pg/M, Zn.D" , "op": "01100101|11|0|10100101|Pg:3|Zn|Zd"},
+ {"inst": "scvtf Zd.D, Pg/M, Zn.D" , "op": "01100101|11|0|10110101|Pg:3|Zn|Zd"},
+ {"inst": "sdiv Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|10100000|Pg:3|Zm|Zdn" , "t": "~~SD"},
+ {"inst": "sdivr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|10110000|Pg:3|Zm|Zdn" , "t": "~~SD"},
+ {"inst": "sdot Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000000|Zn|Zda" , "ta": "~~SD", "tb": "~~BH"},
+ {"inst": "sdot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000000|Zn|Zda"},
+ {"inst": "sdot Zda.D, Zn.H, Zm.H[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000000|Zn|Zda"},
+ {"inst": "sel Pd.B, Pg, Pn.B, Pm.B" , "op": "00100101|00|00|Pm|01|Pg|1|Pn|1|Pd"},
+ {"inst": "sel Zd.t, Pg, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|11|Pg|Zn|Zd"},
+ {"inst": "setffr" , "op": "00100101|00|10|1100100100|0000000000"},
+ {"inst": "shrnb Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|1|imm:5|0001|00|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "t": "~BHS"},
+ {"inst": "shrnt Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|1|imm:5|0001|01|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "t": "~BHS"},
+ {"inst": "smax Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|1|01000110|immS:8|Zdn"},
+ {"inst": "smax Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|01000000|Pg:3|Zm|Zdn"},
+ {"inst": "smaxv Bd, Pg, Zn.B" , "op": "00000100|00|0|01000001|Pg:3|Zn|Vd"},
+ {"inst": "smaxv Hd, Pg, Zn.H" , "op": "00000100|01|0|01000001|Pg:3|Zn|Vd"},
+ {"inst": "smaxv Sd, Pg, Zn.S" , "op": "00000100|10|0|01000001|Pg:3|Zn|Vd"},
+ {"inst": "smaxv Dd, Pg, Zn.D" , "op": "00000100|11|0|01000001|Pg:3|Zn|Vd"},
+ {"inst": "smin Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|1|01010110|immS:8|Zdn"},
+ {"inst": "smin Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|01010000|Pg:3|Zm|Zdn"},
+ {"inst": "sminv Bd, Pg, Zn.B" , "op": "00000100|00|0|01010001|Pg:3|Zn|Vd"},
+ {"inst": "sminv Hd, Pg, Zn.H" , "op": "00000100|01|0|01010001|Pg:3|Zn|Vd"},
+ {"inst": "sminv Sd, Pg, Zn.S" , "op": "00000100|10|0|01010001|Pg:3|Zn|Vd"},
+ {"inst": "sminv Dd, Pg, Zn.D" , "op": "00000100|11|0|01010001|Pg:3|Zn|Vd"},
+ {"inst": "smulh Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|0|10010000|Pg:3|Zm|Zdn"},
+ {"inst": "splice Zdn.t, Pg, Zdn.t, Zm.t" , "op": "00000101|sz|1|01100100|Pg:3|Zn|Zdn"},
+ {"inst": "sqadd Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000100|Zn|Zd"},
+ {"inst": "sqadd Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|1|0010011|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+ {"inst": "sqdecb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110010|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdech Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdech Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdech Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110010|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecp Xdn, Pm.t, Wdn" , "op": "00100101|sz|1|010101000100|Pm|Rdn"},
+ {"inst": "sqdecp Xdn, Pm.t" , "op": "00100101|sz|1|010101000110|Pm|Rdn"},
+ {"inst": "sqdecp Zdn.t, Pm.t" , "op": "00100101|sz|1|010101000000|Pm|Zdn" , "t": "~HSD"},
+ {"inst": "sqdecw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111110|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqdecw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110010|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqinch Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqinch Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqinch Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincp Xdn, Pm.t, Wdn" , "op": "00100101|sz|1010001000100|Pm|Rdn"},
+ {"inst": "sqincp Xdn, Pm.t" , "op": "00100101|sz|1010001000110|Pm|Rdn"},
+ {"inst": "sqincp Zdn.t, Pm.t" , "op": "00100101|sz|1010001000000|Pm|Zdn" , "t": "~HSD"},
+ {"inst": "sqincw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111100|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "sqincw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110000|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+
+ {"inst": "sqsub Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000110|Zn|Zd"},
+ {"inst": "sqsub Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10011011|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+
+ {"inst": "sub Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000001|Zn|Zd"},
+ {"inst": "sub Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10000111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+ {"inst": "sub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|000001000|Pg:3|Zm|Zdn"},
+ {"inst": "subr Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10001111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+ {"inst": "subr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|000011000|Pg:3|Zm|Zdn"},
+ {"inst": "sunpkhi Zd.t, Zn.tb" , "op": "00000101|sz|110001001110|Zn|Zd"},
+ {"inst": "sunpklo Zd.t, Zn.tb" , "op": "00000101|sz|110000001110|Zn|Zd"},
+ {"inst": "sxtb Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010000101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "sxth Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010010101|Pg:3|Zn|Zd" , "t": "~~SD"},
+ {"inst": "sxtw Zd.D, Pg/M, Zn.D" , "op": "00000100|11|010100101|Pg:3|Zn|Zd"},
+ {"inst": "tbl Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|001100|Zn|Zd"},
+ {"inst": "trn1 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011100|Zn|Zd"},
+ {"inst": "trn1 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0101000|Pn|0|Pd"},
+ {"inst": "trn2 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011101|Zn|Zd"},
+ {"inst": "trn2 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0101010|Pn|0|Pd"},
+ {"inst": "uabd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|001101000|Pg:3|Zm|Zdn"},
+ {"inst": "uaddv Dd, Pg, Zn.t" , "op": "00000100|sz|000001001|Pg:3|Zn|Vd" , "t": "BHS~"},
+ {"inst": "ucvtf Zd.H, Pg/M, Zn.H" , "op": "01100101|01|010011101|Pg:3|Zn|Zd"},
+ {"inst": "ucvtf Zd.H, Pg/M, Zn.S" , "op": "01100101|01|010101101|Pg:3|Zn|Zd"},
+ {"inst": "ucvtf Zd.S, Pg/M, Zn.S" , "op": "01100101|10|010101101|Pg:3|Zn|Zd"},
+ {"inst": "ucvtf Zd.D, Pg/M, Zn.S" , "op": "01100101|11|010001101|Pg:3|Zn|Zd"},
+ {"inst": "ucvtf Zd.H, Pg/M, Zn.D" , "op": "01100101|01|010111101|Pg:3|Zn|Zd"},
+ {"inst": "ucvtf Zd.S, Pg/M, Zn.D" , "op": "01100101|11|010101101|Pg:3|Zn|Zd"},
+ {"inst": "ucvtf Zd.D, Pg/M, Zn.D" , "op": "01100101|11|010111101|Pg:3|Zn|Zd"},
+ {"inst": "udiv Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010101000|Pg:3|Zm|Zdn" , "t": "~~SD"},
+ {"inst": "udivr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010111000|Pg:3|Zm|Zdn" , "t": "~~SD"},
+ {"inst": "udot Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000001|Zn|Zda" , "ta": "~~SD", "tb": "~~BH"},
+ {"inst": "udot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000001|Zn|Zda"},
+ {"inst": "udot Zda.D, Zn.H, Zm.H[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000001|Zn|Zda"},
+ {"inst": "umax Zdn.t, Zdn.t, #immZ" , "op": "00100101|sz|101001110|immZ:8|Zdn"},
+ {"inst": "umax Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|001001000|Pg:3|Zm|Zdn"},
+ {"inst": "umaxv Bd, Pg, Zn.B" , "op": "00000100|00|001001001|Pg:3|Zn|Vd"},
+ {"inst": "umaxv Hd, Pg, Zn.H" , "op": "00000100|01|001001001|Pg:3|Zn|Vd"},
+ {"inst": "umaxv Sd, Pg, Zn.S" , "op": "00000100|10|001001001|Pg:3|Zn|Vd"},
+ {"inst": "umaxv Dd, Pg, Zn.D" , "op": "00000100|11|001001001|Pg:3|Zn|Vd"},
+ {"inst": "umin Zdn.t, Zdn.t, #immS" , "op": "00100101|sz|101011110|immS:8|Zdn"},
+ {"inst": "umin Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|001011000|Pg:3|Zm|Zdn"},
+ {"inst": "uminv Bd, Pg, Zn.B" , "op": "00000100|00|001011001|Pg:3|Zn|Vd"},
+ {"inst": "uminv Hd, Pg, Zn.H" , "op": "00000100|01|001011001|Pg:3|Zn|Vd"},
+ {"inst": "uminv Sd, Pg, Zn.S" , "op": "00000100|10|001011001|Pg:3|Zn|Vd"},
+ {"inst": "uminv Dd, Pg, Zn.D" , "op": "00000100|11|001011001|Pg:3|Zn|Vd"},
+ {"inst": "umulh Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "00000100|sz|010011000|Pg:3|Zm|Zdn"},
+ {"inst": "uqadd Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000101|Zn|Zd"},
+ {"inst": "uqadd Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10010111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+ {"inst": "uqdecb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110011|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdech Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdech Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdech Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110011|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecp Xdn, Pm.t" , "op": "00100101|sz|1010111000100|Pm|Rdn"},
+ {"inst": "uqdecp Xdn, Pm.t" , "op": "00100101|sz|1010111000110|Pm|Rdn"},
+ {"inst": "uqdecp Zdn.t, Pm.t" , "op": "00100101|sz|1010111000000|Pm|Zdn" , "t": "~HSD"},
+ {"inst": "uqdecw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111111|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqdecw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110011|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincb Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|00|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincb Xdn, {#pattern}, {mul #imm}" , "op": "00000100|00|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincd Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincd Xdn, {#pattern}, {mul #imm}" , "op": "00000100|11|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincd Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|11|10|imm:4|110001|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqinch Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|01|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqinch Xdn, {#pattern}, {mul #imm}" , "op": "00000100|01|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqinch Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|01|01|imm:4|110001|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincp Xdn, Pm.t" , "op": "00100101|sz|1010011000100|Pm|Rdn"},
+ {"inst": "uqincp Xdn, Pm.t" , "op": "00100101|sz|1010011000110|Pm|Rdn"},
+ {"inst": "uqincp Zdn.t, Pm.t" , "op": "00100101|sz|1010011000000|Pm|Zdn" , "t": "~HSD"},
+ {"inst": "uqincw Xdn, Wdn, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincw Xdn, {#pattern}, {mul #imm}" , "op": "00000100|10|11|imm:4|111101|pattern:5|Rdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqincw Zdn.D, {#pattern}, {mul #imm}" , "op": "00000100|10|10|imm:4|110001|pattern:5|Zdn" , "imm": "SvePatternImm(pattern, imm)"},
+ {"inst": "uqsub Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|000111|Zn|Zd"},
+ {"inst": "uqsub Zdn.t, Zdn.t, #imm, {lsl #n}" , "op": "00100101|sz|10011111|n:1|imm:8|Zdn" , "imm": "Sve8BitImm(imm)"},
+ {"inst": "uunpkhi Zd.t, Zn.tb" , "op": "00000101|sz|110011001110|Zn|Zd"},
+ {"inst": "uunpklo Zd.t, Zn.tb" , "op": "00000101|sz|110010001110|Zn|Zd"},
+ {"inst": "uxtb Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010001101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "uxth Zd.t, Pg/M, Zn.t" , "op": "00000100|sz|010011101|Pg:3|Zn|Zd" , "t": "~~SD"},
+ {"inst": "uxtw Zd.D, Pg/M, Zn.D" , "op": "00000100|11|010101101|Pg:3|Zn|Zd"},
+ {"inst": "uzp1 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100100|Pn|0|Pd"},
+ {"inst": "uzp1 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011010|Zn|Zd"},
+ {"inst": "uzp2 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100110|Pn|0|Pd"},
+ {"inst": "uzp2 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011011|Zn|Zd"},
+ {"inst": "whilege Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X00|Rn|0|Pd"},
+ {"inst": "whilegt Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X00|Rn|1|Pd"},
+ {"inst": "whilehi Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X10|Rn|1|Pd"},
+ {"inst": "whilehs Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X10|Rn|0|Pd"},
+ {"inst": "whilele Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X01|Rn|1|Pd"},
+ {"inst": "whilelo Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X11|Rn|0|Pd"},
+ {"inst": "whilels Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X11|Rn|1|Pd"},
+ {"inst": "whilelt Pd.t, Rn, Rm" , "op": "00100101|sz|1|Rm|000X01|Rn|0|Pd"},
+ {"inst": "wrffr Pn.B" , "op": "00100101|00|1010001001000|Pn|00000"},
+ {"inst": "zip1 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100000|Pn|0|Pd"},
+ {"inst": "zip1 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011000|Zn|Zd"},
+ {"inst": "zip2 Pd.t, Pn.t, Pm.t" , "op": "00000101|sz|10|Pm|0100010|Pn|0|Pd"},
+ {"inst": "zip2 Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|011001|Zn|Zd"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE_BF16", "data": [
+ {"inst": "bfcvt Zd.H, Pg/M, Zn.S" , "op": "01100101|10|001010101|Pg:3|Zn|Zd"},
+ {"inst": "bfcvtnt Zd.H, Pg/M, Zn.S" , "op": "01100100|10|001010101|Pg:3|Zn|Zd"},
+ {"inst": "bfdot Zda.S, Zn.H, Zm.H" , "op": "01100100|01|1|Zm|100000|Zn|Zda"},
+ {"inst": "bfdot Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|01|1|idx:2|Zm:3|010000|Zn|Zda"},
+ {"inst": "bfmlalb Zda.S, Zn.H, Zm.H" , "op": "01100100|11|1|Zm|100000|Zn|Zda"},
+ {"inst": "bfmlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|11|1|idx:2|Zm:3|0100|idx:1|0|Zn|Zda"},
+ {"inst": "bfmlalt Zda.S, Zn.H, Zm.H" , "op": "01100100|11|1|Zm|100001|Zn|Zda"},
+ {"inst": "bfmlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|11|1|idx:2|Zm:3|0100|idx:1|1|Zn|Zda"},
+ {"inst": "bfmmla Zda.S, Zn.H, Zm.H" , "op": "01100100|01|1|Zm|111001|Zn|Zda"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE_F32MM", "data": [
+ {"inst": "fmmla Zda.S, Zn.S, Zm.S" , "op": "01100100|10|1|Zm|111001|Zn|Zda", "t": "~~SD"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE_F64MM", "data": [
+ {"inst": "fmmla Zda.D, Zn.D, Zm.D" , "op": "01100100|11|1|Zm|111001|Zn|Zda", "t": "~~SD"},
+ {"inst": "trn1 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000110|Zn|Zd"},
+ {"inst": "trn2 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000111|Zn|Zd"},
+ {"inst": "uzp1 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000010|Zn|Zd"},
+ {"inst": "uzp2 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000011|Zn|Zd"},
+ {"inst": "zip1 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000000|Zn|Zd"},
+ {"inst": "zip2 Zd.Q, Zn.Q, Zm.Q" , "op": "00000101|10|1|Zm|000001|Zn|Zd"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE_I8MM", "data": [
+ {"inst": "smmla Zda.S, Zn.B, Zm.B" , "op": "01000101|00|0|Zm|100110|Zn|Zda"},
+ {"inst": "sudot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000111|Zn|Zda"},
+ {"inst": "ummla Zda.S, Zn.B, Zm.B" , "op": "01000101|11|0|Zm|100110|Zn|Zda"},
+ {"inst": "usdot Zda.S, Zn.B, Zm.B" , "op": "01000100|10|0|Zm|011110|Zn|Zda"},
+ {"inst": "usdot Zda.S, Zn.B, Zm.B[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000110|Zn|Zda"},
+ {"inst": "usmmla Zda.S, Zn.B, Zm.B" , "op": "01000101|10|0|Zm|100110|Zn|Zda"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE2", "data": [
+ {"inst": "adclb Zda.t, Pg/M, Zn.t" , "op": "01000101|0|sz[0]|0|Zm|110100|Zn|Zda" , "t": "~~SD"},
+ {"inst": "adclt Zda.t, Pg/M, Zn.t" , "op": "01000101|0|sz[0]|0|Zm|110101|Zn|Zda" , "t": "~~SD"},
+ {"inst": "addhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011000|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "addhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011001|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "bcax Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|01|1|Zm|001110|Zk|Zdn"},
+ {"inst": "bsl Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|00|1|Zm|001111|Zk|Zdn"},
+ {"inst": "bsl1n Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|01|1|Zm|001111|Zk|Zdn"},
+ {"inst": "bsl2n Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|10|1|Zm|001111|Zk|Zdn"},
+ {"inst": "cadd Zdn.t, Zdn.t, Zm.t, #rot1" , "op": "01000101|sz|0|00000110|11|imm:1|Zm|Zdn" , "imm": "Rot1Imm(rot1)"},
+ {"inst": "cdot Zda.ta, Zn.tb, Zm.tb, #rot2" , "op": "01000100|sz|0|Zm|0001|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)", "ta": "~~SD", "tb": "~~BH"},
+ {"inst": "cdot Zda.S, Zn.B, Zm.B[#idx], #rot2" , "op": "01000100|10|1|idx:2|Zm:3|0100|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "cdot Zda.D, Zn.H, Zm.H[#idx], #rot2" , "op": "01000100|11|1|idx:1|Zm:4|0100|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "cmla Zda.t, Zn.t, Zm.t, #rot2" , "op": "01000100|sz|0|Zm|0010|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "cmla Zda.H, Zn.H, Zm.H[#idx], #rot2" , "op": "01000100|10|1|idx:2|Zm:3|0110|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "cmla Zda.S, Zn.S, Zm.S[#idx], #rot2" , "op": "01000100|11|1|idx:1|Zm:4|0110|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "eor3 Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|00|1|Zm|001110|Zk|Zdn"},
+ {"inst": "ext Zd.B, 2x{Zn.B}+, #imm" , "op": "00000101|01|1|imm:5|000|imm:3|Zn|Zd"},
+ {"inst": "faddp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010000100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fcmla Zda.t, Pg/M, Zn.t, Zm.t, #rot2" , "op": "01100100|sz|0|Zm|0|imm:2|Pg:3|Zn|Zda" , "t": "~HSD", "imm": "Rot2Imm(rot2)"},
+ {"inst": "fcmla Zda.H, Zn.H, Zm.H[#idx], #rot2" , "op": "01100100|10|1|idx:2|Zm:3|0001|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "fcmla Zda.S, Zn.S, Zm.S[#idx], #rot2" , "op": "01100100|11|1|idx:1|Zm:4|0001|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "fcvtlt Zd.S, Pg/M, Zn.H" , "op": "01100100|10|001001101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtlt Zd.D, Pg/M, Zn.S" , "op": "01100100|11|001011101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtnt Zd.H, Pg/M, Zn.S" , "op": "01100100|10|001000101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtnt Zd.S, Pg/M, Zn.D" , "op": "01100100|11|001010101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtx Zd.S, Pg/M, Zn.D" , "op": "01100101|00|001010101|Pg:3|Zn|Zd"},
+ {"inst": "fcvtxnt Zd.S, Pg/M, Zn.D" , "op": "01100100|00|001010101|Pg:3|Zn|Zd"},
+ {"inst": "flogb Zd.t, Pg/M, Zn.t" , "op": "01100101|00|011|sz|0101|Pg:3|Zn|Zd" , "t": "~HSD"},
+ {"inst": "fmaxnmp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010100100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmaxp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010110100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fminnmp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010101100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fminp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01100100|sz|010111100|Pg:3|Zm|Zdn" , "t": "~HSD"},
+ {"inst": "fmlalb Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|100000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0100|idx:1|0|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlalt Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|100001|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0100|idx:1|1|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlslb Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|101000|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0110|idx:1|0|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlslt Zda.S, Zn.H, Zm.H" , "op": "01100100|10|1|Zm|101001|Zn|Zda" , "t": "~HSD"},
+ {"inst": "fmlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01100100|10|1|idx:2|Zm:3|0110|idx:1|1|Zn|Zda" , "t": "~HSD"},
+ {"inst": "histcnt Zd.t, Pg/Z, Zn.t, Zm.t" , "op": "01000101|sz|1|Zm|110|Pg:3|Zn|Zd" , "t": "~~SD"},
+ {"inst": "histseg Zd.B, Zn.B, Zm.B" , "op": "01000101|00|1|Zm|101000|Zn|Zd"},
+ {"inst": "match Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01000101|sz|1|Zm|100|Pg:3|Zn|0|Pd" , "io": "N=W Z=W C=W V=W", "t": "BH~~"},
+ {"inst": "mla Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000010|Zn|Zda"},
+ {"inst": "mla Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000010|Zn|Zda"},
+ {"inst": "mla Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000010|Zn|Zda"},
+ {"inst": "mls Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000011|Zn|Zda"},
+ {"inst": "mls Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000011|Zn|Zda"},
+ {"inst": "mls Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000011|Zn|Zda"},
+ {"inst": "mul Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011000|Zn|Zd"},
+ {"inst": "mul Zd.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|111110|Zn|Zd"},
+ {"inst": "mul Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|111110|Zn|Zd"},
+ {"inst": "mul Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|111110|Zn|Zd"},
+ {"inst": "nbsl Zdn.D, Zdn.D, Zm.D, Zk.D" , "op": "00000100|11|1|Zm|001111|Zk|Zdn"},
+ {"inst": "nmatch Pd.t, Pg/Z, Zn.t, Zm.t" , "op": "01000101|sz|1|Zm|100|Pg:3|Zn|1|Pd" , "io": "N=W Z=W C=W V=W", "t": "BH~~"},
+ {"inst": "pmul Zd.B, Zn.B, Zm.B" , "op": "00000100|00|1|Zm|011001|Zn|Zd"},
+ {"inst": "pmullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011010|Zn|Zd" , "ta": "QH~D", "tb": "DB~S"},
+ {"inst": "pmullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011011|Zn|Zd" , "ta": "QH~D", "tb": "DB~S"},
+ {"inst": "raddhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011010|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "raddhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011011|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "rsubhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011110|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "rsubhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011111|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "saba Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|111110|Zn|Zd"},
+ {"inst": "sabalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sabalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sabdlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sabdlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sadalp Zda.ta, Pg/M, Zn.tb" , "op": "01000100|sz|0|00100101|Pg:3|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "saddlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "saddlbt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|100000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "saddlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "saddwb Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "saddwt Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sbclb Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|110100|Zn|Zda" , "t": "~~SD"},
+ {"inst": "sbclt Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|110101|Zn|Zda" , "t": "~~SD"},
+ {"inst": "shadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10000100|Pg:3|Zm|Zdn"},
+ {"inst": "shsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10010100|Pg:3|Zm|Zdn"},
+ {"inst": "shsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10110100|Pg:3|Zm|Zdn"},
+ {"inst": "sli Zd.t, Zn.t, #idxmm" , "op": "01000101|imm:2|0|imm:5|111101|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "smaxp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10100101|Pg:3|Zm|Zdn"},
+ {"inst": "sminp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|10110101|Pg:3|Zm|Zdn"},
+ {"inst": "smlalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "smlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1000|idx:1|0|Zn|Zda"},
+ {"inst": "smlalb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1000|idx:1|0|Zn|Zda"},
+ {"inst": "smlalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010001|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "smlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1000|idx:1|1|Zn|Zda"},
+ {"inst": "smlalt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1000|idx:1|1|Zn|Zda"},
+ {"inst": "smlslb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010100|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "smlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1010|idx:1|0|Zn|Zda"},
+ {"inst": "smlslb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1010|idx:1|0|Zn|Zda"},
+ {"inst": "smlslt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010101|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "smlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1010|idx:1|1|Zn|Zda"},
+ {"inst": "smlslt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1010|idx:1|1|Zn|Zda"},
+ {"inst": "smulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011010|Zn|Zd"},
+ {"inst": "smullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "smullb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1100|idx:1|0|Zn|Zda"},
+ {"inst": "smullb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1100|idx:1|0|Zn|Zda"},
+ {"inst": "smullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "smullt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1100|idx:1|1|Zn|Zda"},
+ {"inst": "smullt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1100|idx:1|1|Zn|Zda"},
+ {"inst": "splice Zd.t, Pg, 2x{Zn.t}+" , "op": "00000101|sz|1|01101100|Pg:3|Zn|Zd"},
+ {"inst": "sqabs Zd.t, Pg/M, Zn.t" , "op": "01000100|sz|0|01000101|Pg:3|Zn|Zd"},
+ {"inst": "sqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|0|11000100|Pg:3|Zm|Zdn"},
+ {"inst": "sqcadd Zdn.t, Zdn.t, Zm.t, #rot1" , "op": "01000101|sz|0|0000111011|imm:1|Zm|Zdn" , "imm": "Rot1Imm(rot1)"},
+ {"inst": "sqdmlalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011000|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0010|idx:1|0|Zn|Zda"},
+ {"inst": "sqdmlalb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0010|idx:1|0|Zn|Zda"},
+ {"inst": "sqdmlalbt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000010|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmlalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011001|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0010|idx:1|1|Zn|Zda"},
+ {"inst": "sqdmlalt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0010|idx:1|1|Zn|Zda"},
+ {"inst": "sqdmlslb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011010|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0011|idx:1|0|Zn|Zda"},
+ {"inst": "sqdmlslb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0011|idx:1|0|Zn|Zda"},
+ {"inst": "sqdmlslbt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|000011|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmlslt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|011011|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|0011|idx:1|1|Zn|Zda"},
+ {"inst": "sqdmlslt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|0011|idx:1|1|Zn|Zda"},
+ {"inst": "sqdmulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011100|Zn|Zd" , "t": "~HSD"},
+ {"inst": "sqdmulh Zd.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|111100|Zn|Zd"},
+ {"inst": "sqdmulh Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|111100|Zn|Zd"},
+ {"inst": "sqdmulh Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|111100|Zn|Zd"},
+ {"inst": "sqdmullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011000|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmullb Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1110|idx:1|0|Zn|Zd"},
+ {"inst": "sqdmullb Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|1110|idx:1|0|Zn|Zd"},
+ {"inst": "sqdmullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011001|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "sqdmullt Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1110|idx:1|1|Zn|Zd"},
+ {"inst": "sqdmullt Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|1110|idx:1|1|Zn|Zd"},
+ {"inst": "sqneg Zd.t, Pg/M, Zn.t" , "op": "01000100|sz|001001101|Pg:3|Zm|Zdn"},
+ {"inst": "sqrdcmlah Zda.t, Zn.t, Zm.t, #rot2" , "op": "01000100|sz|0|Zm|0011|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "sqrdcmlah Zda.H, Zn.H, Zm.H[#idx], #rot2" , "op": "01000100|10|1|idx:2|Zm:3|0111|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "sqrdcmlah Zda.S, Zn.S, Zm.S[#idx], #rot2" , "op": "01000100|11|1|idx:1|Zm:4|0111|imm:2|Zn|Zda" , "imm": "Rot2Imm(rot2)"},
+ {"inst": "sqrdmlah Zda.t, Zn.t, Zm.t" , "op": "01000100|sz|0|Zm|011100|Zn|Zda"},
+ {"inst": "sqrdmlah Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000100|Zn|Zda"},
+ {"inst": "sqrdmlah Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000100|Zn|Zda"},
+ {"inst": "sqrdmlah Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000100|Zn|Zda"},
+ {"inst": "sqrdmlsh Zda.t, Zn.t, Zm.t" , "op": "01000100|sz|0|Zm|011101|Zn|Zda"},
+ {"inst": "sqrdmlsh Zda.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|000101|Zn|Zda"},
+ {"inst": "sqrdmlsh Zda.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|000101|Zn|Zda"},
+ {"inst": "sqrdmlsh Zda.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|000101|Zn|Zda"},
+ {"inst": "sqrdmulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011101|Zn|Zd"},
+ {"inst": "sqrdmulh Zd.H, Zn.H, Zm.H[#idx]" , "op": "01000100|0|idx:1|1|idx:2|Zm:3|111101|Zn|Zd"},
+ {"inst": "sqrdmulh Zd.S, Zn.S, Zm.S[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|111101|Zn|Zd"},
+ {"inst": "sqrdmulh Zd.D, Zn.D, Zm.D[#idx]" , "op": "01000100|11|1|idx:1|Zm:4|111101|Zn|Zd"},
+ {"inst": "sqrshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001010100|Pg:3|Zm|Zdn"},
+ {"inst": "sqrshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001110100|Pg:3|Zm|Zdn"},
+ {"inst": "sqrshrnb Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001010|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqrshrnt Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001011|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqrshrunb Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000010|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqrshrunt Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000011|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001000100|Pg:3|Zm|Zdn"},
+ {"inst": "sqshl Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000110100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "sqshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001100100|Pg:3|Zm|Zdn"},
+ {"inst": "sqshlu Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|001111100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "sqshrnb Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "sqshrnt Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001001|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "sqshrunb Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "sqshrunt Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|000000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "sqsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011010100|Pg:3|Zm|Zdn"},
+ {"inst": "sqsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011110100|Pg:3|Zm|Zdn"},
+ {"inst": "sqxtnb Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010000|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqxtnt Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010001|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqxtunb Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010100|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "sqxtunt Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010101|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "srhadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010100100|Pg:3|Zm|Zdn"},
+ {"inst": "sri Zd.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111100|Zn|Zd" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "srshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000010100|Pg:3|Zm|Zdn"},
+ {"inst": "srshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000110100|Pg:3|Zm|Zdn"},
+ {"inst": "srshr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|001100100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "srsra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111010|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "sshllb Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101000|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "sshllt Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101001|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "ssra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111000|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "ssublb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "ssublbt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|100010|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "ssublt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "ssubltb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|100011|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "ssubwb Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010100|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "ssubwt Zd.ta, Zn.t, Zm.tb" , "op": "01000101|sz|0|Zm|010101|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "subhnb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011100|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "subhnt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|1|Zm|011101|Zn|Zd" , "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "suqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011100100|Pg:3|Zm|Zdn"},
+ {"inst": "tbl Zd.t, 2x{Zn.t}+, Zm.t" , "op": "00000101|sz|1|Zm|001010|Zn|Zd"},
+ {"inst": "tbx Zd.t, Zn.t, Zm.t" , "op": "00000101|sz|1|Zm|001011|Zn|Zd"},
+ {"inst": "uaba Zda.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|111111|Zn|Zd"},
+ {"inst": "uabalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110010|Zn|Zd" , "TODO": "ta.tb?"},
+ {"inst": "uabalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|110011|Zn|Zd" , "TODO": "ta.tb?"},
+ {"inst": "uabdlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uabdlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|001111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uadalp Zda.ta, Pg/M, Zn.tb" , "op": "01000100|sz|000101101|Pg:3|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uaddlb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000010|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uaddlt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000011|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uaddwb Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010010|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uaddwt Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010011|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "uhadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010001100|Pg:3|Zm|Zdn"},
+ {"inst": "uhsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010011100|Pg:3|Zm|Zdn"},
+ {"inst": "uhsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010111100|Pg:3|Zm|Zdn"},
+ {"inst": "umaxp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010101101|Pg:3|Zm|Zdn"},
+ {"inst": "uminp Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010111101|Pg:3|Zm|Zdn"},
+ {"inst": "umlalb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010010|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "umlalb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1001|idx:1|0|Zn|Zda"},
+ {"inst": "umlalb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1001|idx:1|0|Zn|Zda"},
+ {"inst": "umlalt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010011|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "umlalt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1001|idx:1|1|Zn|Zda"},
+ {"inst": "umlalt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1001|idx:1|1|Zn|Zda"},
+ {"inst": "umlslb Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010110|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "umlslb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1011|idx:1|0|Zn|Zda"},
+ {"inst": "umlslb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1011|idx:1|0|Zn|Zda"},
+ {"inst": "umlslt Zda.ta, Zn.tb, Zm.tb" , "op": "01000100|sz|0|Zm|010111|Zn|Zda" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "umlslt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1011|idx:1|1|Zn|Zda"},
+ {"inst": "umlslt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1011|idx:1|1|Zn|Zda"},
+ {"inst": "umulh Zd.t, Zn.t, Zm.t" , "op": "00000100|sz|1|Zm|011011|Zn|Zd"},
+ {"inst": "umullb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "umullb Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1101|idx:1|0|Zn|Zda"},
+ {"inst": "umullb Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1101|idx:1|0|Zn|Zda"},
+ {"inst": "umullt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|011111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "umullt Zda.S, Zn.H, Zm.H[#idx]" , "op": "01000100|10|1|idx:2|Zm:3|1101|idx:1|1|Zn|Zda"},
+ {"inst": "umullt Zda.D, Zn.S, Zm.S[#idx]" , "op": "01000100|11|1|idx:2|Zm:3|1101|idx:1|1|Zn|Zda"},
+ {"inst": "uqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011001100|Pg:3|Zm|Zdn"},
+ {"inst": "uqrshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001011100|Pg:3|Zm|Zdn"},
+ {"inst": "uqrshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001111100|Pg:3|Zm|Zdn"},
+ {"inst": "uqrshrnb Zd.ta, Zd.tb, #idxmm" , "op": "01000101|0|imm:1|1|imm:5|001110|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "uqrshrnt Zd.ta, Zd.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001111|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "uqshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001001100|Pg:3|Zm|Zdn"},
+ {"inst": "uqshl Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|000111100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "uqshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|001101100|Pg:3|Zm|Zdn"},
+ {"inst": "uqshrnb Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001100|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "uqshrnt Zd.t, Zn.tb, #imm" , "op": "01000101|0|imm:1|1|imm:5|001101|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "uqsub Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011011100|Pg:3|Zm|Zdn"},
+ {"inst": "uqsubr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011111100|Pg:3|Zm|Zdn"},
+ {"inst": "uqxtnb Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010010|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "uqxtnt Zd.ta, Zn.tb" , "op": "01000101|0|imm:1|1|imm:2|000010011|Zn|Zd" , "imm": "SveXtImm(sz)", "ta": "~BHS", "tb": "~HSD"},
+ {"inst": "urecpe Zd.S, Pg/M, Zn.S" , "op": "01000100|10|000000101|Pg:3|Zn|Zd"},
+ {"inst": "urhadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|010101100|Pg:3|Zm|Zdn"},
+ {"inst": "urshl Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000011100|Pg:3|Zm|Zdn"},
+ {"inst": "urshlr Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|000111100|Pg:3|Zm|Zdn"},
+ {"inst": "urshr Zdn.t, Pg/M, Zdn.t, #imm" , "op": "00000100|imm:2|001101100|Pg:3|imm:5|Zdn" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "ursqrte Zd.S, Pg/M, Zn.S" , "op": "01000100|10|000001101|Pg:3|Zn|Zd"},
+ {"inst": "ursra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111011|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "ushllb Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101010|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "ushllt Zd.t, Zn.t, #imm" , "op": "01000101|0|imm:1|0|imm:5|101011|Zn|Zd" , "imm": "SveShiftImm6(sz, imm)"},
+ {"inst": "usqadd Zdn.t, Pg/M, Zdn.t, Zm.t" , "op": "01000100|sz|011101100|Pg:3|Zm|Zdn"},
+ {"inst": "usra Zda.t, Zn.t, #imm" , "op": "01000101|imm:2|0|imm:5|111001|Zn|Zda" , "imm": "SveShiftImm7(sz, imm)"},
+ {"inst": "usublb Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "usublt Zd.ta, Zn.tb, Zm.tb" , "op": "01000101|sz|0|Zm|000111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "usubwb Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010110|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "usubwt Zd.ta, Zn.ta, Zm.tb" , "op": "01000101|sz|0|Zm|010111|Zn|Zd" , "ta": "~HSD", "tb": "~BHS"},
+ {"inst": "whilerw Pd.t, Xn, Xm" , "op": "00100101|sz|1|Rm|001100|Rn|1|Pd"},
+ {"inst": "whilewr Pd.t, Xn, Xm" , "op": "00100101|sz|1|Rm|001100|Rn|0|Pd"},
+ {"inst": "xar Zdn.t, Zdn.t, Zm.t, #imm" , "op": "00000100|imm:2|1|imm:5|001101|Zm|Zdn" , "imm": "SveShiftImm7(sz, imm)"}
+ ]},
+
+ {"category": "SVE CRYPTO_HASH", "ext": "SVE2_AES", "data": [
+ {"inst": "aesd Zdn.B, Zdn.B, Zm.B" , "op": "01000101|00|100010111|001|Zm|Zdn"},
+ {"inst": "aese Zdn.B, Zdn.B, Zm.B" , "op": "01000101|00|100010111|000|Zm|Zdn"},
+ {"inst": "aesimc Zdn.B, Zdn.B" , "op": "01000101|00|100000111|001|00000|Zdn"},
+ {"inst": "aesmc Zdn.B, Zdn.B" , "op": "01000101|00|100000111|000|00000|Zdn"}
+ ]},
+
+ {"category": "SVE", "ext": "SVE2_BITPERM", "data": [
+ {"inst": "bdep Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|101101|Zn|Zd"},
+ {"inst": "bext Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|101100|Zn|Zd"},
+ {"inst": "bgrp Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|101110|Zn|Zd"}
+ ]},
+
+ {"category": "SVE CRYPTO_HASH", "ext": "SVE2_SHA3", "data": [
+ {"inst": "rax1 Zd.D, Zn.D, Zm.D" , "op": "01000101|00|1|Zm|111101|Zn|Zd"}
+ ]},
+
+ {"category": "SVE CRYPTO_HASH", "ext": "SVE2_SM4", "data": [
+ {"inst": "sm4e Zdn.S, Zdn.S, Zm.S" , "op": "01000101|00|1|00011111000|Zm|Zdn"},
+ {"inst": "sm4ekey Zd.S, Zn.S, Zm.S" , "op": "01000101|00|1|Zm|111100|Zn|Zd"}
+ ]},
+
+ {"category": "SME", "ext": "SME", "data": [
+ {"inst": "smstart {#sme_mode=1}" , "op": "11010101|00|000011|0100|0|op:2|1|011|11111" , "imm": "ImmSMEMode(sme_mode)"},
+ {"inst": "smstop {#sme_mode=1}" , "op": "11010101|00|000011|0100|0|op:2|0|011|11111" , "imm": "ImmSMEMode(sme_mode)"}
+ ]}
+ ]
+}
diff --git a/3rdparty/asmjit/db/isa_aarch64_sme.json b/3rdparty/asmjit/db/isa_aarch64_sme.json
new file mode 100644
index 00000000000..31d45696e16
--- /dev/null
+++ b/3rdparty/asmjit/db/isa_aarch64_sme.json
@@ -0,0 +1,15 @@
+{
+ "instructions": [
+ {"category": "SME", "ext": "SME", "data": [
+ {"inst": "smstart {#sme_mode=1}" , "op": "11010101|00|000011|0100|0|op:2|1|011|11111" , "imm": "ImmSMEMode(sme_mode)"},
+ {"inst": "smstop {#sme_mode=1}" , "op": "11010101|00|000011|0100|0|op:2|0|011|11111" , "imm": "ImmSMEMode(sme_mode)"},
+
+ {"inst": "eorbt Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|100100|Zn|Zda"},
+ {"inst": "eortb Zd.t, Zn.t, Zm.t" , "op": "01000101|sz|0|Zm|100101|Zn|Zda"},
+ {"inst": "TODO_psel Pd, Pn, Pm.t[Wv, #imm]" , "op": "00100101|sz|0110011100010|Pg|0|Pdn"},
+ {"inst": "revd Zd.Q, Pg/M, Zn.Q" , "op": "00000101|00|101110100|Pg:3|Zn|Zd"},
+ {"inst": "sclamp Zd.t, Zn.t, Zm.t" , "op": "01000100|sz|0|Zm|110000|Zn|Zda"},
+ {"inst": "uclamp Zd.t, Zn.t, Zm.t" , "op": "01000100|sz|0|Zm|110001|Zn|Zda"}
+ ]}
+ ]
+}
diff --git a/3rdparty/asmjit/db/isa_x86.json b/3rdparty/asmjit/db/isa_x86.json
new file mode 100644
index 00000000000..d6be812a05e
--- /dev/null
+++ b/3rdparty/asmjit/db/isa_x86.json
@@ -0,0 +1,4244 @@
+{
+ "instructions": [
+ {"category": "GP", "instructions": [
+ {"any": "adc x:al, imm8" , "alt": true, "op": "[OP] 14 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "adc x:axv, immv" , "alt": true, "op": "[OP] 15 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] adc x:~r8/m8, ~r8" , "op": "[MR] 10 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] adc x:~rv/mv, ~rv" , "op": "[MR] 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] adc x:r8/m8, imm8" , "op": "[M ] 80 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] adc x:rv/mv, imms8" , "op": "[M ] 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] adc x:rv/mv, immv" , "op": "[M ] 81 /2 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "adc x:~r8, ~r8/m8" , "op": "[RM] 12 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "adc x:~rv, ~rv/mv" , "op": "[RM] 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "add x:al, imm8" , "alt": true, "op": "[OP] 04 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "add x:axv, immv" , "alt": true, "op": "[OP] 05 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] add x:~r8/m8, ~r8" , "op": "[MR] 00 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] add x:~rv/mv, ~rv" , "op": "[MR] 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] add x:r8/m8, imm8" , "op": "[M ] 80 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] add x:rv/mv, imms8" , "op": "[M ] 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] add x:rv/mv, immv" , "op": "[M ] 81 /0 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "add x:~r8, ~r8/m8" , "op": "[RM] 02 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "add x:~rv, ~rv/mv" , "op": "[RM] 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "and x:al, imm8" , "alt": true, "op": "[OP] 24 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "and x:ax, imm16" , "alt": true, "op": "[OP] 66 25 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "and X:eax, imm32" , "alt": true, "op": "[OP] 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "and X:rax, immu32" , "alt": true, "op": "[OP] 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "and X:rax, imms32" , "alt": true, "op": "[OP] REX.W 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and x:r8/m8, imm8" , "op": "[M ] 80 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and x:r16/m16, imm16" , "op": "[M ] 66 81 /4 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and X:r32/m32, imm32" , "op": "[M ] 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and X:r64, immu32" , "op": "[M ] 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and X:r64/m64, imms32" , "op": "[M ] REX.W 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and x:rv/mv, imms8" , "op": "[M ] 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and x:~r8/m8, ~r8" , "op": "[MR] 20 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] and x:~rv/mv, ~rv" , "op": "[MR] 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "and x:~r8, ~r8/m8" , "op": "[RM] 22 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "and x:~rv, ~rv/mv" , "op": "[RM] 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "bsf w:rv, rv/mv" , "op": "[RM] 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"},
+ {"any": "bsr w:rv, rv/mv" , "op": "[RM] 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"},
+ {"any": "bswap X:rv" , "op": "[OP] 0F C8+r"},
+ {"any": "bt R:rv/mv, rv" , "op": "[MR] 0F A3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "bt R:rv/mv, imm8" , "op": "[M ] 0F BA /4 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] btc x:rv/mv, rv" , "op": "[MR] 0F BB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] btc x:rv/mv, imm8" , "op": "[M ] 0F BA /7 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] btr x:rv/mv, rv" , "op": "[MR] 0F B3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] btr x:rv/mv, imm8" , "op": "[M ] 0F BA /6 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] bts x:rv/mv, rv" , "op": "[MR] 0F AB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] bts x:rv/mv, imm8" , "op": "[M ] 0F BA /5 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"},
+ {"x86": "[bnd|repIgnore] call rel16" , "op": "[OP] 66 E8 cw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "[bnd|repIgnore] call rel32" , "op": "[OP] E8 cd" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"x86": "[bnd|repIgnore] call R:r16/m16" , "op": "[OP] 66 FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"x86": "[bnd|repIgnore] call R:r32/m32" , "op": "[OP] FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"x64": "[bnd|repIgnore] call R:r64/m64" , "op": "[OP] FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "cbw x:<ax>" , "op": "[OP] 66 98"},
+ {"any": "cdq W:<edx>, <eax>" , "op": "[OP] 99"},
+ {"any": "cdqe X:<rax>" , "op": "[OP] REX.W 98"},
+ {"any": "clc" , "op": "[OP] F8" , "io": "CF=0"},
+ {"any": "cld" , "op": "[OP] FC" , "io": "DF=0"},
+ {"any": "cmc" , "op": "[OP] F5" , "io": "CF=X"},
+ {"any": "cmp R:r8/m8, r8" , "op": "[MR] 38 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:rv/mv, rv" , "op": "[MR] 39 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:r8, r8/m8" , "op": "[RM] 3A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:rv, rv/mv" , "op": "[RM] 3B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:al, imm8" , "alt": true, "op": "[OP] 3C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:axv, immv" , "alt": true, "op": "[OP] 3D iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:r8/m8, imm8" , "op": "[M ] 80 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:rv/mv, imms8" , "op": "[M ] 83 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmp R:rv/mv, immv" , "op": "[M ] 81 /7 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[rep|repne] cmps R:m8(ds:zsi), R:m8(es:zdi)" , "op": "[OP] A6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "[rep|repne] cmps R:m16(ds:zsi), R:m16(es:zdi)" , "op": "[OP] 66 A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "[rep|repne] cmps R:m32(ds:zsi), R:m32(es:zdi)" , "op": "[OP] A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "[rep|repne] cmps R:m64(ds:zsi), R:m64(es:zdi)" , "op": "[OP] REX.W A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "cwde X:<eax>" , "op": "[OP] 98"},
+ {"any": "cqo W:<rdx>, <rax>" , "op": "[OP] REX.W 99"},
+ {"any": "cwd w:<dx>, <ax>" , "op": "[OP] 66 99"},
+ {"x86": "dec x:r16" , "op": "[OP] 66 48+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"x86": "dec X:r32" , "op": "[OP] 48+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "[lock|xacqrel] dec x:r8/m8" , "op": "[OP] FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "[lock|xacqrel] dec x:rv/mv" , "op": "[OP] FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "div x:<ax>, R:r8/m8" , "op": "[M ] F6 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "div x:<dxv>, x:<axv>, rv/mv" , "op": "[M ] F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "enter imm16, imm8" , "op": "[OP] C8 iw ib" , "volatile": true},
+ {"any": "idiv x:<ax>, R:r8/m8" , "op": "[M ] F6 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "idiv x:<dxv>, x:<axv>, rv/mv" , "op": "[M ] F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "imul x:<ax>, R:r8/m8" , "op": "[M ] F6 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"any": "imul w:<dxv>, x:<axv>, rv/mv" , "op": "[M ] F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"any": "imul x:~rv, ~rv/mv" , "op": "[RM] 0F AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"any": "imul w:rv, R:rv/mv, imms8" , "op": "[RM] 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"any": "imul w:rv, R:rv/mv, immv" , "op": "[RM] 69 /r iv" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"x86": "inc x:r16" , "op": "[OP] 66 40+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"x86": "inc X:r32" , "op": "[OP] 40+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "[lock] inc x:r8/m8" , "op": "[M ] FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "[lock] inc x:rv/mv" , "op": "[M ] FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "iret" , "op": "[OP] 66 CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "iretd" , "op": "[OP] CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "iretq" , "op": "[OP] REX.W CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "[bnd] jb rel8" , "op": "[OP] 72 cb" , "io": "CF=R"},
+ {"x86": "[bnd] jb rel16" , "op": "[OP] 66 0F 82 cw" , "io": "CF=R"},
+ {"any": "[bnd] jb rel32" , "op": "[OP] 0F 82 cd" , "io": "CF=R"},
+ {"any": "[bnd] jbe rel8" , "op": "[OP] 76 cb" , "io": "CF=R ZF=R"},
+ {"x86": "[bnd] jbe rel16" , "op": "[OP] 66 0F 86 cw" , "io": "CF=R ZF=R"},
+ {"any": "[bnd] jbe rel32" , "op": "[OP] 0F 86 cd" , "io": "CF=R ZF=R"},
+ {"any": "[bnd] jl rel8" , "op": "[OP] 7C cb" , "io": "SF=R OF=R"},
+ {"x86": "[bnd] jl rel16" , "op": "[OP] 66 0F 8C cw" , "io": "SF=R OF=R"},
+ {"any": "[bnd] jl rel32" , "op": "[OP] 0F 8C cd" , "io": "SF=R OF=R"},
+ {"any": "[bnd] jle rel8" , "op": "[OP] 7E cb" , "io": "ZF=R SF=R OF=R"},
+ {"x86": "[bnd] jle rel16" , "op": "[OP] 66 0F 8E cw" , "io": "ZF=R SF=R OF=R"},
+ {"any": "[bnd] jle rel32" , "op": "[OP] 0F 8E cd" , "io": "ZF=R SF=R OF=R"},
+ {"any": "[bnd] jnb rel8" , "op": "[OP] 73 cb" , "io": "CF=R"},
+ {"x86": "[bnd] jnb rel16" , "op": "[OP] 66 0F 83 cw" , "io": "CF=R"},
+ {"any": "[bnd] jnb rel32" , "op": "[OP] 0F 83 cd" , "io": "CF=R"},
+ {"any": "[bnd] jnbe rel8" , "op": "[OP] 77 cb" , "io": "CF=R ZF=R"},
+ {"x86": "[bnd] jnbe rel16" , "op": "[OP] 66 0F 87 cw" , "io": "CF=R ZF=R"},
+ {"any": "[bnd] jnbe rel32" , "op": "[OP] 0F 87 cd" , "io": "CF=R ZF=R"},
+ {"any": "[bnd] jnl rel8" , "op": "[OP] 7D cb" , "io": "SF=R OF=R"},
+ {"x86": "[bnd] jnl rel16" , "op": "[OP] 66 0F 8D cw" , "io": "SF=R OF=R"},
+ {"any": "[bnd] jnl rel32" , "op": "[OP] 0F 8D cd" , "io": "SF=R OF=R"},
+ {"any": "[bnd] jnle rel8" , "op": "[OP] 7F cb" , "io": "ZF=R SF=R OF=R"},
+ {"x86": "[bnd] jnle rel16" , "op": "[OP] 66 0F 8F cw" , "io": "ZF=R SF=R OF=R"},
+ {"any": "[bnd] jnle rel32" , "op": "[OP] 0F 8F cd" , "io": "ZF=R SF=R OF=R"},
+ {"any": "[bnd] jno rel8" , "op": "[OP] 71 cb" , "io": "OF=R"},
+ {"x86": "[bnd] jno rel16" , "op": "[OP] 66 0F 81 cw" , "io": "OF=R"},
+ {"any": "[bnd] jno rel32" , "op": "[OP] 0F 81 cd" , "io": "OF=R"},
+ {"any": "[bnd] jnp rel8" , "op": "[OP] 7B cb" , "io": "PF=R"},
+ {"x86": "[bnd] jnp rel16" , "op": "[OP] 66 0F 8B cw" , "io": "PF=R"},
+ {"any": "[bnd] jnp rel32" , "op": "[OP] 0F 8B cd" , "io": "PF=R"},
+ {"any": "[bnd] jns rel8" , "op": "[OP] 79 cb" , "io": "SF=R"},
+ {"x86": "[bnd] jns rel16" , "op": "[OP] 66 0F 89 cw" , "io": "SF=R"},
+ {"any": "[bnd] jns rel32" , "op": "[OP] 0F 89 cd" , "io": "SF=R"},
+ {"any": "[bnd] jnz rel8" , "op": "[OP] 75 cb" , "io": "ZF=R"},
+ {"x86": "[bnd] jnz rel16" , "op": "[OP] 66 0F 85 cw" , "io": "ZF=R"},
+ {"any": "[bnd] jnz rel32" , "op": "[OP] 0F 85 cd" , "io": "ZF=R"},
+ {"any": "[bnd] jo rel8" , "op": "[OP] 70 cb" , "io": "OF=R"},
+ {"x86": "[bnd] jo rel16" , "op": "[OP] 66 0F 80 cw" , "io": "OF=R"},
+ {"any": "[bnd] jo rel32" , "op": "[OP] 0F 80 cd" , "io": "OF=R"},
+ {"any": "[bnd] jp rel8" , "op": "[OP] 7A cb" , "io": "PF=R"},
+ {"x86": "[bnd] jp rel16" , "op": "[OP] 66 0F 8A cw" , "io": "PF=R"},
+ {"any": "[bnd] jp rel32" , "op": "[OP] 0F 8A cd" , "io": "PF=R"},
+ {"any": "[bnd] js rel8" , "op": "[OP] 78 cb" , "io": "SF=R"},
+ {"x86": "[bnd] js rel16" , "op": "[OP] 66 0F 88 cw" , "io": "SF=R"},
+ {"any": "[bnd] js rel32" , "op": "[OP] 0F 88 cd" , "io": "SF=R"},
+ {"any": "[bnd] jz rel8" , "op": "[OP] 74 cb" , "io": "ZF=R"},
+ {"x86": "[bnd] jz rel16" , "op": "[OP] 66 0F 84 cw" , "io": "ZF=R"},
+ {"any": "[bnd] jz rel32" , "op": "[OP] 0F 84 cd" , "io": "ZF=R"},
+ {"x86": "[bnd] jecxz R:<cx>, rel8" , "op": "[OP] 67 E3 cb"},
+ {"x86": "[bnd] jecxz R:<ecx>, rel8" , "op": "[OP] E3 cb"},
+ {"x64": "[bnd] jecxz R:<ecx>, rel8" , "op": "[OP] 67 E3 cb"},
+ {"x64": "[bnd] jecxz R:<rcx>, rel8" , "op": "[OP] E3 cb"},
+ {"any": "[bnd] jmp rel8" , "op": "[OP] EB cb"},
+ {"x86": "[bnd] jmp rel16" , "op": "[OP] 66 E9 cw"},
+ {"any": "[bnd] jmp rel32" , "op": "[OP] E9 cd"},
+ {"x86": "[bnd] jmp R:r32/m32" , "op": "[M ] FF /4"},
+ {"x64": "[bnd] jmp R:r64/m64" , "op": "[M ] FF /4"},
+ {"x86": "lcall imm16, imm16" , "op": "[OP] 66 9A iw iw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"x86": "lcall imm16, imm32" , "op": "[OP] 9A id iw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "lcall R:m16_16" , "op": "[M ] 66 FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "lcall R:m16_32" , "op": "[M ] FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"x64": "lcall R:m16_64" , "op": "[M ] REX.W FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "lea w:r16, mem" , "op": "[RM] 67 8D /r"},
+ {"any": "lea W:r32, mem" , "op": "[RM] 8D /r"},
+ {"any": "lea W:r64, mem" , "op": "[RM] REX.W 8D /r"},
+ {"any": "leave" , "op": "[OP]C9" , "volatile": true},
+ {"x86": "ljmp imm16, imm16" , "op": "[OP] 66 EA iw iw"},
+ {"x86": "ljmp imm16, imm32" , "op": "[OP] EA id iw"},
+ {"any": "ljmp R:m16_16" , "op": "[M ] 66 FF /5"},
+ {"any": "ljmp R:m16_32" , "op": "[M ] FF /5"},
+ {"any": "ljmp R:m16_64" , "op": "[M ] REX.W FF /5"},
+ {"any": "[rep] lods w:al, R:m8(ds:zsi)" , "op": "[OP] AC" , "io": "DF=R"},
+ {"any": "[rep] lods w:ax, R:m16(ds:zsi)" , "op": "[OP] 66 AD" , "io": "DF=R"},
+ {"any": "[rep] lods W:eax, R:m32(ds:zsi)" , "op": "[OP] AD" , "io": "DF=R"},
+ {"any": "[rep] lods W:rax, R:m64(ds:zsi)" , "op": "[OP] REX.W AD" , "io": "DF=R"},
+ {"x86": "loop x:<cx>, rel8" , "op": "[OP] 67 E2 cb"},
+ {"x86": "loop X:<ecx>, rel8" , "op": "[OP] E2 cb"},
+ {"x64": "loop X:<ecx>, rel8" , "op": "[OP] 67 E2 cb"},
+ {"x64": "loop X:<rcx>, rel8" , "op": "[OP] E2 cb"},
+ {"x86": "loope x:<cx>, rel8" , "op": "[OP] 67 E1 cb" , "io": "ZF=R"},
+ {"x86": "loope X:<ecx>, rel8" , "op": "[OP] E1 cb" , "io": "ZF=R"},
+ {"x64": "loope X:<ecx>, rel8" , "op": "[OP] 67 E1 cb" , "io": "ZF=R"},
+ {"x64": "loope X:<rcx>, rel8" , "op": "[OP] E1 cb" , "io": "ZF=R"},
+ {"x86": "loopne x:<cx>, rel8" , "op": "[OP] 67 E0 cb" , "io": "ZF=R"},
+ {"x86": "loopne X:<ecx>, rel8" , "op": "[OP] E0 cb" , "io": "ZF=R"},
+ {"x64": "loopne X:<ecx>, rel8" , "op": "[OP] 67 E0 cb" , "io": "ZF=R"},
+ {"x64": "loopne X:<rcx>, rel8" , "op": "[OP] E0 cb" , "io": "ZF=R"},
+ {"any": "[xrelease] mov w:r8/m8, r8" , "op": "[MR] 88 /r"},
+ {"any": "[xrelease] mov w:rv/mv, rv" , "op": "[MR] 89 /r"},
+ {"any": "[xrelease] mov w:r8/m8, imm8" , "op": "[M ] C6 /0 ib"},
+ {"any": "[xrelease] mov w:rv/mv, immv" , "op": "[M ] C7 /0 iv"},
+ {"any": "mov w:r8, r8/m8" , "op": "[RM] 8A /r"},
+ {"any": "mov w:rv, rv/mv" , "op": "[RM] 8B /r"},
+ {"any": "mov w:r8, imm8" , "op": "[OP] B0+r ib"},
+ {"any": "mov w:r16, imm16" , "op": "[OP] 66 B8+r iw"},
+ {"any": "mov W:r32, imm32" , "op": "[OP] B8+r id"},
+ {"any": "mov W:r64, imm64" , "op": "[OP] REX.W B8+r iq"},
+ {"any": "mov w:r16/m16, sreg" , "op": "[MR] 66 8C /r"},
+ {"any": "mov W:r32/m16, sreg" , "op": "[MR] 8C /r"},
+ {"any": "mov W:r64/m16, sreg" , "op": "[MR] REX.W 8C /r"},
+ {"any": "mov W:sreg, r16/m16" , "op": "[RM] 66 8E /r"},
+ {"any": "mov W:sreg, r32/m16" , "op": "[RM] 8E /r"},
+ {"any": "mov W:sreg, r64/m16" , "op": "[RM] REX.W 8E /r"},
+ {"any": "mov w:al, moff8" , "op": "[OP] A0 moff"},
+ {"any": "mov w:ax, moff16" , "op": "[OP] 66 A1 moff"},
+ {"any": "mov W:eax, moff32" , "op": "[OP] A1 moff"},
+ {"any": "mov W:rax, moff64" , "op": "[OP] REX.W A1 moff"},
+ {"any": "mov W:moff8, al" , "op": "[OP] A2 moff"},
+ {"any": "mov W:moff16, ax" , "op": "[OP] 66 A3 moff"},
+ {"any": "mov W:moff32, eax" , "op": "[OP] A3 moff"},
+ {"any": "mov W:moff64, rax" , "op": "[OP] REX.W A3 moff"},
+ {"x86": "mov W:r32, creg" , "op": "[MR] 0F 20 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x64": "mov W:r64, creg" , "op": "[MR] 0F 20 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x86": "mov W:creg, r32" , "op": "[RM] 0F 22 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x64": "mov W:creg, r64" , "op": "[RM] 0F 22 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x86": "mov W:r32, dreg" , "op": "[MR] 0F 21 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x64": "mov W:r64, dreg" , "op": "[MR] 0F 21 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x86": "mov W:dreg, r32" , "op": "[RM] 0F 23 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"x64": "mov W:dreg, r64" , "op": "[RM] 0F 23 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"},
+ {"any": "movabs W:r64, imm64" , "op": "[OP] REX.W B8+r iq"},
+ {"any": "movabs w:al, moff8" , "op": "[OP] A0 moff"},
+ {"any": "movabs w:ax, moff16" , "op": "[OP] 66 A1 moff"},
+ {"any": "movabs W:eax, moff32" , "op": "[OP] A1 moff"},
+ {"any": "movabs W:rax, moff64" , "op": "[OP] REX.W A1 moff"},
+ {"any": "movabs W:moff8, al" , "op": "[OP] A2 moff"},
+ {"any": "movabs W:moff16, ax" , "op": "[OP] 66 A3 moff"},
+ {"any": "movabs W:moff32, eax" , "op": "[OP] A3 moff"},
+ {"any": "movabs W:moff64, rax" , "op": "[OP] REX.W A3 moff"},
+ {"any": "[rep] movs W:m8(es:zdi), R:m8(ds:zsi)" , "op": "[OP] A4" , "io": "DF=R"},
+ {"any": "[rep] movs W:m16(es:zdi), R:m16(ds:zsi)" , "op": "[OP] 66 A5" , "io": "DF=R"},
+ {"any": "[rep] movs W:m32(es:zdi), R:m32(ds:zsi)" , "op": "[OP] A5" , "io": "DF=R"},
+ {"any": "[rep] movs W:m64(es:zdi), R:m64(ds:zsi)" , "op": "[OP] REX.W A5" , "io": "DF=R"},
+ {"any": "movsx w:rv, r8/m8" , "op": "[RM] 0F BE /r"},
+ {"any": "movsx W:ry, r16/m16" , "op": "[RM] 0F BF /r"},
+ {"x64": "movsxd W:r16, r16/m16" , "op": "[RM] 66 63 /r"},
+ {"x64": "movsxd W:r32, r32/m32" , "op": "[RM] 63 /r"},
+ {"x64": "movsxd W:r64, r32/m32" , "op": "[RM] REX.W 63 /r"},
+ {"any": "movzx w:rv, r8/m8" , "op": "[RM] 0F B6 /r"},
+ {"any": "movzx W:r32, r16/m16" , "op": "[RM] 0F B7 /r"},
+ {"any": "movzx W:r64, r16/m16" , "op": "[RM] REX.W 0F B7 /r"},
+ {"any": "mul x:<ax>, r8/m8" , "op": "[M ] F6 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"},
+ {"any": "mul w:<dxv>, x:<axv>, rv/mv" , "op": "[M ] F7 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"},
+ {"any": "[lock|xacqrel] neg x:r8/m8" , "op": "[M ] F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] neg x:rv/mv" , "op": "[M ] F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "nop" , "op": "[OP] 90"},
+ {"any": "nop R:rv/mv" , "op": "[M ] 0F 1F /0"},
+ {"any": "nop R:rv/mv, rv" , "op": "[MR] 0F 1F /r"},
+ {"any": "[lock|xacqrel] not x:r8/m8" , "op": "[M ] F6 /2"},
+ {"any": "[lock|xacqrel] not x:rv/mv" , "op": "[M ] F7 /2"},
+ {"any": "or x:al, imm8" , "alt": true, "op": "[OP] 0C ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "or x:axv, immv" , "alt": true, "op": "[OP] 0D iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] or x:~r8/m8, ~r8" , "op": "[MR] 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] or x:~rv/mv, ~rv" , "op": "[MR] 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] or x:r8/m8, imm8" , "op": "[M ] 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] or x:rv/mv, immv" , "op": "[M ] 81 /1 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] or x:rv/mv, imms8" , "op": "[M ] 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "or x:~r8, ~r8/m8" , "op": "[RM] 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "or x:~rv, ~rv/mv" , "op": "[RM] 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "pop w:r16/m16" , "op": "[M ] 66 8F /0"},
+ {"x86": "pop W:r32/m32" , "op": "[M ] 8F /0"},
+ {"x64": "pop W:r64/m64" , "op": "[M ] 8F /0"},
+ {"any": "pop w:r16" , "op": "[OP] 66 58+r"},
+ {"x86": "pop W:r32" , "op": "[OP] 58+r"},
+ {"x64": "pop W:r64" , "op": "[OP] 58+r"},
+ {"x86": "pop W:ds" , "op": "[OP] 1F"},
+ {"x86": "pop W:es" , "op": "[OP] 07"},
+ {"x86": "pop W:ss" , "op": "[OP] 17"},
+ {"any": "pop W:fs" , "op": "[OP] 0F A1"},
+ {"any": "pop W:gs" , "op": "[OP] 0F A9"},
+ {"any": "popf" , "op": "[OP] 66 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"},
+ {"x86": "popfd" , "op": "[OP] 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"},
+ {"x64": "popfq" , "op": "[OP] 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"},
+ {"any": "push R:r16/m16" , "op": "[M ] 66 FF /6"},
+ {"x86": "push R:r32/m32" , "op": "[M ] FF /6"},
+ {"x64": "push R:r64/m64" , "op": "[M ] FF /6"},
+ {"any": "push R:r16" , "op": "[OP] 66 50+r"},
+ {"x86": "push R:r32" , "op": "[OP] 50+r"},
+ {"x64": "push R:r64" , "op": "[OP] 50+r"},
+ {"x86": "push R:cs" , "op": "[OP] 0E"},
+ {"x86": "push R:ss" , "op": "[OP] 16"},
+ {"x86": "push R:ds" , "op": "[OP] 1E"},
+ {"x86": "push R:es" , "op": "[OP] 06"},
+ {"any": "push R:fs" , "op": "[OP] 0F A0"},
+ {"any": "push R:gs" , "op": "[OP] 0F A8"},
+ {"any": "push imm8" , "op": "[OP] 6A ib"},
+ {"any": "push imm16" , "op": "[OP] 66 68 iw"},
+ {"x86": "push imm32" , "op": "[OP] 68 id"},
+ {"x64": "push imms32" , "op": "[OP] 68 id"},
+ {"any": "pushf" , "op": "[OP] 66 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"},
+ {"x86": "pushfd" , "op": "[OP] 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"},
+ {"x64": "pushfq" , "op": "[OP] 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"},
+ {"any": "pushw imm16" , "op": "[OP] 66 68 iw"},
+ {"any": "rcl x:r8/m8, cl" , "op": "[M ] D2 /2" , "io": "CF=X OF=X"},
+ {"any": "rcl x:rv/mv, cl" , "op": "[M ] D3 /2" , "io": "CF=X OF=X"},
+ {"any": "rcl x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /2" , "io": "CF=X OF=X"},
+ {"any": "rcl x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /2" , "io": "CF=X OF=X"},
+ {"any": "rcl x:r8/m8, imm8" , "op": "[M ] C0 /2 ib" , "io": "CF=X OF=X"},
+ {"any": "rcl x:rv/mv, imm8" , "op": "[M ] C1 /2 ib" , "io": "CF=X OF=X"},
+ {"any": "rcr x:r8/m8, cl" , "op": "[M ] D2 /3" , "io": "CF=X OF=X"},
+ {"any": "rcr x:rv/mv, cl" , "op": "[M ] D3 /3" , "io": "CF=X OF=X"},
+ {"any": "rcr x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /3" , "io": "CF=X OF=X"},
+ {"any": "rcr x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /3" , "io": "CF=X OF=X"},
+ {"any": "rcr x:r8/m8, imm8" , "op": "[M ] C0 /3 ib" , "io": "CF=X OF=X"},
+ {"any": "rcr x:rv/mv, imm8" , "op": "[M ] C1 /3 ib" , "io": "CF=X OF=X"},
+ {"any": "[bnd|repIgnore] ret" , "op": "[OP] C3"},
+ {"any": "[bnd|repIgnore] ret immu16" , "op": "[OP] C2 iw"},
+ {"any": "retf" , "op": "[OP] CB"},
+ {"any": "retf immu16" , "op": "[OP] CA iw"},
+ {"any": "rol x:r8/m8, cl" , "op": "[M ] D2 /0" , "io": "CF=W OF=W"},
+ {"any": "rol x:rv/mv, cl" , "op": "[M ] D3 /0" , "io": "CF=W OF=W"},
+ {"any": "rol x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /0" , "io": "CF=W OF=W"},
+ {"any": "rol x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /0" , "io": "CF=W OF=W"},
+ {"any": "rol x:r8/m8, imm8" , "op": "[M ] C0 /0 ib" , "io": "CF=W OF=W"},
+ {"any": "rol x:rv/mv, imm8" , "op": "[M ] C1 /0 ib" , "io": "CF=W OF=W"},
+ {"any": "ror x:r8/m8, cl" , "op": "[M ] D2 /1" , "io": "CF=W OF=W"},
+ {"any": "ror x:rv/mv, cl" , "op": "[M ] D3 /1" , "io": "CF=W OF=W"},
+ {"any": "ror x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /1" , "io": "CF=W OF=W"},
+ {"any": "ror x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /1" , "io": "CF=W OF=W"},
+ {"any": "ror x:r8/m8, imm8" , "op": "[M ] C0 /1 ib" , "io": "CF=W OF=W"},
+ {"any": "ror x:rv/mv, imm8" , "op": "[M ] C1 /1 ib" , "io": "CF=W OF=W"},
+ {"any": "sar x:r8/m8, cl" , "op": "[M ] D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sar x:rv/mv, cl" , "op": "[M ] D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sar x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sar x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sar x:r8/m8, imm8" , "op": "[M ] C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sar x:rv/mv, imm8" , "op": "[M ] C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sbb x:al, imm8" , "alt": true, "op": "[OP] 1C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "sbb x:axv, immv" , "alt": true, "op": "[OP] 1D iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] sbb x:r8/m8, r8" , "op": "[MR] 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] sbb x:rv/mv, rv" , "op": "[MR] 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] sbb x:r8/m8, imm8" , "op": "[M ] 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] sbb x:rv/mv, imms8" , "op": "[M ] 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[lock|xacqrel] sbb x:rv/mv, immv" , "op": "[M ] 81 /3 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "sbb x:r8, r8/m8" , "op": "[RM] 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "sbb x:rv, rv/mv" , "op": "[RM] 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"any": "[rep|repne] scas R:al, R:m8(es:zdi)" , "op": "[OP] AE" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "[rep|repne] scas R:ax, R:m16(es:zdi)" , "op": "[OP] 66 AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "[rep|repne] scas R:eax, R:m32(es:zdi)" , "op": "[OP] AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "[rep|repne] scas R:rax, R:m64(es:zdi)" , "op": "[OP] REX.W AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"},
+ {"any": "setb w:r8/m8" , "op": "[M ] 0F 92 /r" , "io": "CF=R"},
+ {"any": "setbe w:r8/m8" , "op": "[M ] 0F 96 /r" , "io": "CF=R ZF=R"},
+ {"any": "setl w:r8/m8" , "op": "[M ] 0F 9C /r" , "io": "SF=R OF=R"},
+ {"any": "setle w:r8/m8" , "op": "[M ] 0F 9E /r" , "io": "ZF=R SF=R OF=R"},
+ {"any": "setnb w:r8/m8" , "op": "[M ] 0F 93 /r" , "io": "CF=R"},
+ {"any": "setnbe w:r8/m8" , "op": "[M ] 0F 97 /r" , "io": "CF=R ZF=R"},
+ {"any": "setnl w:r8/m8" , "op": "[M ] 0F 9D /r" , "io": "SF=R OF=R"},
+ {"any": "setnle w:r8/m8" , "op": "[M ] 0F 9F /r" , "io": "ZF=R SF=R OF=R"},
+ {"any": "setno w:r8/m8" , "op": "[M ] 0F 91 /r" , "io": "OF=R"},
+ {"any": "setnp w:r8/m8" , "op": "[M ] 0F 9B /r" , "io": "PF=R"},
+ {"any": "setns w:r8/m8" , "op": "[M ] 0F 99 /r" , "io": "SF=R"},
+ {"any": "setnz w:r8/m8" , "op": "[M ] 0F 95 /r" , "io": "ZF=R"},
+ {"any": "seto w:r8/m8" , "op": "[M ] 0F 90 /r" , "io": "OF=R"},
+ {"any": "setp w:r8/m8" , "op": "[M ] 0F 9A /r" , "io": "PF=R"},
+ {"any": "sets w:r8/m8" , "op": "[M ] 0F 98 /r" , "io": "SF=R"},
+ {"any": "setz w:r8/m8" , "op": "[M ] 0F 94 /r" , "io": "ZF=R"},
+ {"any": "shl x:r8/m8, cl" , "op": "[M ] D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shl x:rv/mv, cl" , "op": "[M ] D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shl x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shl x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shl x:r8/m8, imm8" , "op": "[M ] C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shl x:rv/mv, imm8" , "op": "[M ] C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shld x:rv/mv, rv, cl" , "op": "[MR] 0F A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"any": "shld x:rv/mv, rv, imm8" , "op": "[MR] 0F A4 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"any": "shr x:r8/m8, cl" , "op": "[M ] D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shr x:rv/mv, cl" , "op": "[M ] D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shr x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shr x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shr x:r8/m8, imm8" , "op": "[M ] C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shr x:rv/mv, imm8" , "op": "[M ] C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "shrd x:rv/mv, rv, cl" , "op": "[MR] 0F AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"any": "shrd x:rv/mv, rv, imm8" , "op": "[MR] 66 0F AC /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"any": "stc" , "op": "[OP] F9" , "io": "CF=1"},
+ {"any": "std" , "op": "[OP] FD" , "io": "DF=1"},
+ {"any": "[rep] stos W:m8(es:zdi), R:al" , "op": "[OP] AA" , "io": "DF=R"},
+ {"any": "[rep] stos W:m16(es:zdi), R:ax" , "op": "[OP] 66 AB" , "io": "DF=R"},
+ {"any": "[rep] stos W:m32(es:zdi), R:eax" , "op": "[OP] AB" , "io": "DF=R"},
+ {"any": "[rep] stos W:m64(es:zdi), R:rax" , "op": "[OP] REX.W AB" , "io": "DF=R"},
+ {"any": "sub x:al, imm8" , "alt": true, "op": "[OP] 2C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sub x:axv, immv" , "alt": true, "op": "[OP] 2D iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] sub x:r8/m8, r8" , "op": "[MR] 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] sub x:rv/mv, rv" , "op": "[MR] 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] sub x:r8/m8, imm8" , "op": "[M ] 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] sub x:rv/mv, imms8" , "op": "[M ] 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] sub x:rv/mv, immv" , "op": "[M ] 81 /5 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sub x:r8, r8/m8" , "op": "[RM] 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "sub x:rv, rv/mv" , "op": "[RM] 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "test R:~r8/m8, ~r8" , "op": "[MR] 84 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "test R:~rv/mv, ~rv" , "op": "[MR] 85 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "test R:al, imm8" , "alt": true, "op": "[OP] A8 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "test R:axv, immv" , "alt": true, "op": "[OP] A9 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "test R:r8/m8, imm8" , "op": "[M ] F6 /0 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "test R:rv/mv, immv" , "op": "[M ] F7 /0 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "ud0 r32, r32/m32" , "op": "[RM] 0F FF /r"},
+ {"any": "ud1 r32, r32/m32" , "op": "[RM] 0F B9 /r"},
+ {"any": "ud2" , "op": "[OP] 0F 0B"},
+ {"any": "xchg x:~ax, x:~r16" , "alt": true, "op": "[OP] 66 90+r"},
+ {"any": "xchg X:~eax, X:~r32" , "alt": true, "op": "[OP] 90+r"},
+ {"any": "xchg X:~rax, X:~r64" , "alt": true, "op": "[OP] REX.W 90+r"},
+ {"any": "xchg x:~r16, x:~ax" , "alt": true, "op": "[OP] 66 90+r"},
+ {"any": "xchg X:~r32, X:~eax" , "alt": true, "op": "[OP] 90+r"},
+ {"any": "xchg X:~r64, X:~rax" , "alt": true, "op": "[OP] REX.W 90+r"},
+ {"any": "[ilock|xacquire] xchg x:~r8/m8, x:~r8" , "op": "[MR] 86 /r"},
+ {"any": "[ilock|xacquire] xchg x:~rv/mv, x:~rv" , "op": "[MR] 87 /r"},
+ {"any": "[ilock|xacquire] xchg x:~r8, x:~r8/m8" , "op": "[RM] 86 /r"},
+ {"any": "[ilock|xacquire] xchg x:~rv, x:~rv/mv" , "op": "[RM] 87 /r"},
+ {"any": "xor x:al, imm8" , "alt": true, "op": "[OP] 34 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "xor x:axv, immv" , "alt": true, "op": "[OP] 35 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] xor x:~r8/m8, ~r8" , "op": "[MR] 30 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] xor x:~rv/mv, ~rv" , "op": "[MR] 31 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] xor x:r8/m8, imm8" , "op": "[M ] 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] xor x:rv/mv, imms8" , "op": "[M ] 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "[lock|xacqrel] xor x:rv/mv, immv" , "op": "[M ] 81 /6 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "xor x:~r8, ~r8/m8" , "op": "[RM] 32 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"any": "xor x:~rv, ~rv/mv" , "op": "[RM] 33 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}
+ ]},
+
+ {"category": "GP GP_IN_OUT", "volatile": true, "instructions": [
+ {"any": "in w:al, imm8" , "op": "E4 ib"},
+ {"any": "in w:ax, imm8" , "op": "66 E5 ib"},
+ {"any": "in W:eax, imm8" , "op": "E5 ib"},
+ {"any": "in w:al, dx" , "op": "EC"},
+ {"any": "in w:ax, dx" , "op": "66 ED"},
+ {"any": "in W:eax, dx" , "op": "ED"},
+ {"any": "[rep] ins W:m8(es:zdi), dx" , "op": "6C"},
+ {"any": "[rep] ins W:m16(es:zdi), dx" , "op": "66 6D"},
+ {"any": "[rep] ins W:m32(es:zdi), dx" , "op": "6D"},
+ {"any": "out imm8, al" , "op": "E6 ib"},
+ {"any": "out imm8, ax" , "op": "66 E7 ib"},
+ {"any": "out imm8, eax" , "op": "E7 ib"},
+ {"any": "out R:dx, R:al" , "op": "EE"},
+ {"any": "out R:dx, R:ax" , "op": "66 EF"},
+ {"any": "out R:dx, R:eax" , "op": "EF"},
+ {"any": "[rep] outs R:dx, R:m8(ds:zsi)" , "op": "6E"},
+ {"any": "[rep] outs R:dx, R:m16(ds:zsi)" , "op": "66 6F"},
+ {"any": "[rep] outs R:dx, R:m32(ds:zsi)" , "op": "6F"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "I486", "instructions": [
+ {"any": "[lock|xacqrel] cmpxchg x:r8/m8, r8, <al>" , "op": "[MR] 0F B0 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] cmpxchg x:rv/mv, rv, <axv>" , "op": "[MR] 0F B1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cpuid X:<eax>, W:<ebx>, X:<ecx>, W:<edx>" , "op": "[OP] 0F A2" , "volatile": true},
+ {"any": "[lock|xacqrel] xadd x:r8/m8, x:r8" , "op": "[MR] 0F C0 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"any": "[lock|xacqrel] xadd x:rv/mv, x:rv" , "op": "[MR] 0F C1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "3DNOW", "volatile": true, "instructions": [
+ {"any": "prefetch R:mem" , "op": "0F 0D /0"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "ADX", "instructions": [
+ {"any": "adcx X:~ry, R:~ry/my" , "op": "[RM ] 66 0F 38 F6 /r" , "io": "CF=X"},
+ {"any": "adox X:~ry, R:~ry/my" , "op": "[RM ] F3 0F 38 F6 /r" , "io": "OF=X"},
+ {"apx": "adcx X:~ry, R:~ry/my" , "op": "[RM ] EVEX.ND=0.LLZ.66.MAP4.Wy 66 /r" , "io": "CF=X"},
+ {"apx": "adcx W:ry, R:~ry, R:~ry/my" , "op": "[VRM] EVEX.ND=1.LLZ.66.MAP4.Wy 66 /r" , "io": "CF=X"},
+ {"apx": "adox X:~ry, R:~ry/my" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.Wy 66 /r" , "io": "OF=X"},
+ {"apx": "adox W:ry, R:~ry, R:~ry/my" , "op": "[VRM] EVEX.ND=1.LLZ.F3.MAP4.Wy 66 /r" , "io": "OF=X"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "BMI", "instructions": [
+ {"any": "andn W:ry, R:ry, R:ry/my" , "op": "[RVM] VEX.LZ.0F38.Wy F2 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"},
+ {"apx": "andn{nf} W:ry, R:ry, R:my/ry" , "op": "[RVM] EVEX.128.NP.0F38.Wy F2 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"},
+ {"any": "bextr W:ry, R:ry/my, R:ry" , "op": "[RMV] VEX.LZ.0F38.Wy F7 /r" , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"},
+ {"apx": "bextr{nf} W:ry, R:my/ry, ry" , "op": "[RMV] EVEX.128.NP.0F38.Wy F7 /r" , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"},
+ {"any": "blsi W:ry, R:ry/my" , "op": "[VM ] VEX.LZ.0F38.Wy F3 /3" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+ {"apx": "blsi{nf} W:ry, R:my/ry" , "op": "[VM ] EVEX.128.NP.0F38.Wy F3 /3" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+ {"any": "blsmsk W:ry, R:ry/my" , "op": "[VM ] VEX.LZ.0F38.Wy F3 /2" , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"},
+ {"apx": "blsmsk{nf} W:ry, R:my/ry" , "op": "[VM ] EVEX.128.NP.0F38.Wy F3 /2" , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"},
+ {"any": "blsr W:ry, R:ry/my" , "op": "[VM ] VEX.LZ.0F38.Wy F3 /1" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+ {"apx": "blsr{nf} W:ry, R:my/ry" , "op": "[VM ] EVEX.128.NP.0F38.Wy F3 /1" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+ {"any": "tzcnt w:rv, rv/mv" , "op": "[RM ] F3 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
+ {"apx": "tzcnt{nf} w:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F4 /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "BMI2", "instructions": [
+ {"any": "bzhi W:ry, R:ry/my, R:ry" , "op": "[RMV] VEX.LZ.0F38.Wy F5 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+ {"apx": "bzhi{nf} W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.NP.0F38.Wy F5 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"},
+ {"any": "mulx W:ry, W:ry, ~ry/my, ~<dxy>" , "op": "[RVM] VEX.LZ.F2.0F38.Wy F6 /r"},
+ {"apx": "mulx W:ry, W:ry, R:~my/ry, R:~<dxy>" , "op": "[RVM] EVEX.128.F2.0F38.Wy F6 /r"},
+ {"any": "pdep W:ry, ry, ry/my" , "op": "[RVM] VEX.LZ.F2.0F38.Wy F5 /r"},
+ {"apx": "pdep W:ry, R:ry, R:my/ry" , "op": "[RVM] EVEX.128.F2.0F38.Wy F5 /r"},
+ {"any": "pext W:ry, ry, ry/my" , "op": "[RVM] VEX.LZ.F3.0F38.Wy F5 /r"},
+ {"apx": "pext W:ry, R:ry, R:my/ry" , "op": "[RVM] EVEX.128.F3.0F38.Wy F5 /r"},
+ {"any": "rorx W:ry, ry/my, imm8" , "op": "[RM ] VEX.LZ.F2.0F3A.Wy F0 /r ib"},
+ {"apx": "rorx W:ry, R:my/ry, imm8" , "op": "[RM ] EVEX.128.F2.0F3A.Wy F0 /r ib"},
+ {"any": "sarx W:ry, ry/my, ry" , "op": "[RMV] VEX.LZ.F3.0F38.Wy F7 /r"},
+ {"apx": "sarx W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.F3.0F38.Wy F7 /r"},
+ {"any": "shlx W:ry, ry/my, ry" , "op": "[RMV] VEX.LZ.66.0F38.Wy F7 /r"},
+ {"apx": "shlx W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.66.0F38.Wy F7 /r"},
+ {"any": "shrx W:ry, ry/my, ry" , "op": "[RMV] VEX.LZ.F2.0F38.Wy F7 /r"},
+ {"apx": "shrx W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.F2.0F38.Wy F7 /r"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CET_SS", "volatile": true, "instructions": [
+ {"any": "incsspd R:r32[7:0]" , "op": "F3 0F AE /5"},
+ {"x64": "incsspq R:r64[7:0]" , "op": "F3 REX.W 0F AE /5"},
+ {"any": "rdsspd W:r32" , "op": "F3 0F 1E /1"},
+ {"any": "rdsspq W:r64" , "op": "F3 REX.W 0F 1E /1"},
+ {"any": "rstorssp R:m64" , "op": "F3 0F 01 /5" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+ {"any": "saveprevssp" , "op": "F3 0F 01 EA" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLDEMOTE", "instructions": [
+ {"any": "cldemote R:mem" , "op": "[M ] NP 0F 1C /0"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLFLUSH", "instructions": [
+ {"any": "clflush R:mem" , "op": "[M ] NP 0F AE /7"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLFLUSHOPT", "instructions": [
+ {"any": "clflushopt R:mem" , "op": "[M ] NFx 66 0F AE /7"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLWB", "instructions": [
+ {"any": "clwb R:mem" , "op": "[M ] 66 0F AE /6"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CLZERO", "instructions": [
+ {"any": "clzero R:<m512(ds:zax)>" , "op": "[OP] NP 0F 01 FC"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CMOV", "instructions": [
+ {"any": "cmovb x:rv, rv/mv" , "op": "[RM] 0F 42 /r" , "io": "CF=R"},
+ {"any": "cmovbe x:rv, rv/mv" , "op": "[RM] 0F 46 /r" , "io": "CF=R ZF=R"},
+ {"any": "cmovl x:rv, rv/mv" , "op": "[RM] 0F 4C /r" , "io": "SF=R OF=R"},
+ {"any": "cmovle x:rv, rv/mv" , "op": "[RM] 0F 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"any": "cmovnb x:rv, rv/mv" , "op": "[RM] 0F 43 /r" , "io": "CF=R"},
+ {"any": "cmovnbe x:rv, rv/mv" , "op": "[RM] 0F 47 /r" , "io": "CF=R ZF=R"},
+ {"any": "cmovnl x:rv, rv/mv" , "op": "[RM] 0F 4D /r" , "io": "SF=R OF=R"},
+ {"any": "cmovnle x:rv, rv/mv" , "op": "[RM] 0F 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"any": "cmovno x:rv, rv/mv" , "op": "[RM] 0F 41 /r" , "io": "OF=R"},
+ {"any": "cmovnp x:rv, rv/mv" , "op": "[RM] 0F 4B /r" , "io": "PF=R"},
+ {"any": "cmovns x:rv, rv/mv" , "op": "[RM] 0F 49 /r" , "io": "SF=R"},
+ {"any": "cmovnz x:rv, rv/mv" , "op": "[RM] 0F 45 /r" , "io": "ZF=R"},
+ {"any": "cmovo x:rv, rv/mv" , "op": "[RM] 0F 40 /r" , "io": "OF=R"},
+ {"any": "cmovp x:rv, rv/mv" , "op": "[RM] 0F 4A /r" , "io": "PF=R"},
+ {"any": "cmovs x:rv, rv/mv" , "op": "[RM] 0F 48 /r" , "io": "SF=R"},
+ {"any": "cmovz x:rv, rv/mv" , "op": "[RM] 0F 44 /r" , "io": "ZF=R"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CMPCCXADD", "instructions": [
+ {"any": "cmpbxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E2 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpbxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E2 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpbexadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E6 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpbexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E6 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmplxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy EC !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmplxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EC !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmplexadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy EE !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmplexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EE !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnbxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E3 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnbxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E3 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnbexadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E7 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnbexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E7 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnlxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy ED !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnlxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy ED !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnlexadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy EF !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnlexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EF !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnoxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E1 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnoxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E1 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnpxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy EB !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnpxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EB !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnsxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E9 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnsxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E9 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpnzxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E5 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpnzxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E5 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpoxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E0 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpoxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E0 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmppxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy EA !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmppxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EA !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpsxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E8 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpsxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E8 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"},
+ {"any": "cmpzxadd X:my, X:ry, R:ry" , "op": "[MRV] VEX.128.66.0F38.Wy E4 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "cmpzxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E4 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CMPXCHG8B", "instructions": [
+ {"any": "[lock|xacqrel] cmpxchg8b X:m64,X:<edx>,X:<eax>,<ecx>,<ebx>" , "op": "[OP] 0F C7 /1" , "io": "ZF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CMPXCHG16B", "instructions": [
+ {"any": "[lock|xacqrel] cmpxchg16b X:m128,X:<rdx>,X:<rax>,<rcx>,<rbx>","op": "[OP] REX.W 0F C7 /1" , "io": "ZF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "FSGSBASE", "volatile": true, "instructions": [
+ {"x64": "rdfsbase W:ry" , "op": "[M ] F3 0F AE /0"},
+ {"x64": "rdgsbase W:ry" , "op": "[M ] F3 0F AE /1"},
+ {"x64": "wrfsbase R:ry" , "op": "[M ] F3 0F AE /2"},
+ {"x64": "wrgsbase R:ry" , "op": "[M ] F3 0F AE /3"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "FXSR", "volatile": true, "instructions": [
+ {"any": "fxrstor R:mem" , "op": "[M ] 0F AE /1" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fxrstor64 R:mem" , "op": "[M ] REX.W 0F AE /1" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fxsave W:mem" , "op": "[M ] 0F AE /0" , "io": "C0=R C1=R C2=R C3=R"},
+ {"any": "fxsave64 W:mem" , "op": "[M ] REX.W 0F AE /0" , "io": "C0=R C1=R C2=R C3=R"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LAHFSAHF", "instructions": [
+ {"any": "lahf w:<ah>" , "op": "[OP] 9F" , "io": "SF=R ZF=R AF=R PF=R CF=R"},
+ {"any": "sahf R:<ah>" , "op": "[OP] 9E" , "io": "SF=W ZF=W AF=W PF=W CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LWP", "volatile": true, "instructions": [
+ {"any": "llwpcb R:r32" , "op": "[M ] XOP.L0.P0.MAP9.W0 12 /0"},
+ {"any": "llwpcb R:r64" , "op": "[M ] XOP.L0.P0.MAP9.W1 12 /0"},
+ {"any": "lwpins R:r32, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W0 12 /0 id"},
+ {"any": "lwpins R:r64, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W1 12 /0 id"},
+ {"any": "lwpval R:r32, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W0 12 /1 id"},
+ {"any": "lwpval R:r64, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W1 12 /1 id"},
+ {"any": "slwpcb W:r32" , "op": "[M ] XOP.L0.P0.MAP9.W0 12 /1"},
+ {"any": "slwpcb W:r64" , "op": "[M ] XOP.L0.P0.MAP9.W1 12 /1"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "LZCNT", "instructions": [
+ {"any": "lzcnt w:rv, rv/mv" , "op": "[RM] F3 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"},
+ {"apx": "lzcnt{nf} w:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F5 /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MONITORX", "volatile": true, "instructions": [
+ {"any": "monitorx R:<mem(ds:zax)>, R:<ecx>, R:<edx>" , "op": "0F 01 FA"},
+ {"any": "mwaitx R:<eax>, R:<ecx>, R:<ebx>" , "op": "0F 01 FB"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MCOMMIT", "instructions": [
+ {"any": "mcommit" , "op": "F3 0F 01 FA" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MOVBE", "instructions": [
+ {"any": "movbe w:rv, R:mv" , "op": "[RM] 0F 38 F0 /r"},
+ {"any": "movbe W:mv, R:rv" , "op": "[MR] 0F 38 F1 /r"},
+ {"apx": "movbe w:rv, R:rv/mv" , "op": "[RM] EVEX.ND=0.LLZ.Pv.MAP4.Wv 60 /r"},
+ {"apx": "movbe w:rv/mv, R:rv" , "op": "[MR] EVEX.ND=0.LLZ.Pv.MAP4.Wv 61 /r"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MOVDIRI", "instructions": [
+ {"any": "movdiri W:my, R:ry" , "op": "[MR] 0F 38 F9 /r"},
+ {"apx": "movdiri W:my, R:ry" , "op": "[MR] EVEX.ND=0.LLZ.NP.MAP4.W0 F9 !(11):rrr:bbb"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MOVDIR64B", "instructions": [
+ {"any": "movdir64b W:m512(es:r32), m512" , "op": "[RM] 66 0F 38 F8 /r"},
+ {"any": "movdir64b W:m512(es:r64), m512" , "op": "[RM] 66 0F 38 F8 /r"},
+ {"apx": "movdir64b W:m512(es:r64), R:m512" , "op": "[RM] EVEX.LLZ.66.MAP4.W0 F8 !(11):rrr:bbb"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MOVRS", "instructions": [
+ {"x64": "movrs W:r8, R:m8" , "op": "[RM] NOREP 0F 38 8A !(11):rrr:bbb"},
+ {"x64": "movrs W:rv, R:mv" , "op": "[RM] NOREP 0F 38 8B !(11):rrr:bbb"},
+ {"any": "prefetchrst2 R:mem" , "op": "[M ] 0F 18 !(11):100:bbb"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PCONFIG", "volatile": true, "instructions": [
+ {"any": "pconfig" , "op": "[OP] NP 0F 01 C5"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "POPCNT", "instructions": [
+ {"any": "popcnt w:rv, rv/mv" , "op": "[RM] F3 0F B8 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"apx": "popcnt{nf} w:rv, R:rv/mv" , "op": "[RM] EVEX.ND=0.LLZ.Pv.MAP4.Wv 88 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "OSPKE", "instructions": [
+ {"any": "rdpkru W:<edx>, W:<eax>, R:<ecx>" , "op": "[OP] 0F 01 EE"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PREFETCHI", "volatile": true, "instructions": [
+ {"x64": "prefetchit0 R:mem" , "op": "[M ] 0F 18 /7"},
+ {"x64": "prefetchit1 R:mem" , "op": "[M ] 0F 18 /6"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PREFETCHW", "volatile": true, "instructions": [
+ {"any": "prefetchw R:mem" , "op": "[M ] 0F 0D /1" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PREFETCHWT1", "volatile": true, "instructions": [
+ {"any": "prefetchwt1 R:mem" , "op": "[M ] 0F 0D /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "PTWRITE", "volatile": true, "instructions": [
+ {"any": "ptwrite R:r32/m32" , "op": "[M ] F3 0F AE /4"},
+ {"any": "ptwrite R:r64/m64" , "op": "[M ] F3 REX.W 0F AE /4"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RAO_INT", "volatile": true, "instructions": [
+ {"any": "aadd X:my, R:ry" , "op": "[MR] NP 0F 38 FC !(11):rrr:bbb"},
+ {"apx": "aadd X:my, R:ry" , "op": "[MR] EVEX.ND=0.LLZ.NP.MAP4.Wy FC !(11):rrr:bbb"},
+ {"any": "aand X:my, R:ry" , "op": "[MR] 66 0F 38 FC !(11):rrr:bbb"},
+ {"apx": "aand X:my, R:ry" , "op": "[MR] EVEX.ND=0.LLZ.66.MAP4.Wy FC !(11):rrr:bbb"},
+ {"any": "aor X:my, R:ry" , "op": "[MR] F2 0F 38 FC !(11):rrr:bbb"},
+ {"apx": "aor X:my, R:ry" , "op": "[MR] EVEX.ND=0.LLZ.F2.MAP4.Wy FC !(11):rrr:bbb"},
+ {"any": "axor X:my, R:ry" , "op": "[MR] F3 0F 38 FC !(11):rrr:bbb"},
+ {"apx": "axor X:my, R:ry" , "op": "[MR] EVEX.ND=0.LLZ.F3.MAP4.Wy FC !(11):rrr:bbb"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RDPID", "instructions": [
+ {"x86": "rdpid W:r32" , "op": "[R ] F3 0F C7 /7"},
+ {"x64": "rdpid W:r64" , "op": "[R ] F3 0F C7 /7"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RDPRU", "instructions": [
+ {"any": "rdpru W:<edx>, W:<eax>, R:<ecx>" , "op": "0F 01 FD"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RDRAND", "instructions": [
+ {"any": "rdrand w:rv" , "op": "NFx 0F C7 /6" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RDSEED", "instructions": [
+ {"any": "rdseed w:rv" , "op": "NFx 0F C7 /7" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RDTSC", "instructions": [
+ {"any": "rdtsc W:<edx>, W:<eax>" , "op": "0F 31"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RDTSCP", "instructions": [
+ {"any": "rdtscp W:<edx>, W:<eax>, W:<ecx>" , "op": "0F 01 F9"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "RTM", "deprecated": true, "volatile": true, "instructions": [
+ {"any": "xabort imm8" , "op": "C6 /7 ib"},
+ {"any": "xbegin rel16" , "op": "66 C7 /7 cw"},
+ {"any": "xbegin rel32" , "op": "C7 /7 cd"},
+ {"any": "xend" , "op": "0F 01 D5"},
+ {"any": "xtest" , "op": "0F 01 D6" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SERIALIZE", "volatile": true, "instructions": [
+ {"any": "serialize" , "op": "0F 01 E8"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SSE", "volatile": true, "instructions": [
+ {"any": "prefetchnta R:mem" , "op": "[M ] 0F 18 /0"},
+ {"any": "prefetcht0 R:mem" , "op": "[M ] 0F 18 /1"},
+ {"any": "prefetcht1 R:mem" , "op": "[M ] 0F 18 /2"},
+ {"any": "prefetcht2 R:mem" , "op": "[M ] 0F 18 /3"},
+ {"any": "sfence" , "op": "[OP] NP 0F AE F8"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SSE2", "volatile": true, "instructions": [
+ {"any": "lfence" , "op": "[OP] NP 0F AE E8"},
+ {"any": "mfence" , "op": "[OP] NP 0F AE F0"},
+ {"any": "movnti W:my, ry" , "op": "[MR] NP 0F C3 /r"}
+ ]},
+
+ {"category": "GP GP_EXT CRYPTO_HASH", "ext": "SSE4_2", "instructions": [
+ {"any": "crc32 X:r32, R:r8/m8" , "op": "[RM] F2 0F 38 F0 /r"},
+ {"any": "crc32 X:r32, R:r16/m16" , "op": "[RM] 66 F2 0F 38 F1 /r"},
+ {"any": "crc32 X:r32, R:r32/m32" , "op": "[RM] F2 0F 38 F1 /r"},
+ {"any": "crc32 X:r64, R:r8/m8" , "op": "[RM] F2 REX.W 0F 38 F0 /r"},
+ {"any": "crc32 X:r64, R:r64/m64" , "op": "[RM] F2 REX.W 0F 38 F1 /r"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "TSE", "volatile": true, "instructions": [
+ {"x64": "pbndkb W:<rax>, R:<mem(ds:rbx)>, W:<mem(ds:rcx)>" , "op": "NP 0F 01 C7" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "TSXLDTRK", "volatile": true, "instructions": [
+ {"any": "xresldtrk" , "op": "F2 0F 01 E9"},
+ {"any": "xsusldtrk" , "op": "F2 0F 01 E8"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "UINTR", "volatile": true, "instructions": [
+ {"x64": "uiret" , "op": "F3 0F 01 EC"},
+ {"x64": "clui" , "op": "F3 0F 01 EE"},
+ {"x64": "stui" , "op": "F3 0F 01 EF"},
+ {"x64": "testui" , "op": "F3 0F 01 ED" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+ {"x64": "senduipi R:r64" , "op": "[R ] F3 0F C7 /6"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "WAITPKG", "volatile": true, "instructions": [
+ {"any": "tpause R:r32, <edx>, <eax>" , "op": "66 0F AE /6" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+ {"x86": "umonitor R:mem(ds:r32)" , "op": "F3 0F AE /6"},
+ {"x64": "umonitor R:mem(ds:r64)" , "op": "F3 0F AE /6"},
+ {"any": "umwait R:r32, <edx>, <eax>" , "op": "F2 0F AE /6" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "XSAVE", "volatile": true, "instructions": [
+ {"any": "xgetbv W:<edx>, W:<eax>, R:<ecx>" , "op": "NP 0F 01 D0" , "io": "XCR=R"},
+ {"any": "xrstor R:mem, <edx>, <eax>" , "op": "NP 0F AE /5" , "io": "XCR=R"},
+ {"any": "xrstor64 R:mem, <edx>, <eax>" , "op": "NP REX.W 0F AE /5" , "io": "XCR=R"},
+ {"any": "xsave W:mem, <edx>, <eax>" , "op": "NP 0F AE /4" , "io": "XCR=R"},
+ {"any": "xsave64 W:mem, <edx>, <eax>" , "op": "NP REX.W 0F AE /4" , "io": "XCR=R"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "XSAVEC", "volatile": true, "instructions": [
+ {"any": "xsavec W:mem, <edx>, <eax>" , "op": "NP 0F C7 /4" , "io": "XCR=R"},
+ {"any": "xsavec64 W:mem, <edx>, <eax>" , "op": "NP REX.W 0F C7 /4" , "io": "XCR=R"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "XSAVEOPT", "volatile": true, "instructions": [
+ {"any": "xsaveopt W:mem, <edx>, <eax>" , "op": "NP 0F AE /6" , "io": "XCR=R"},
+ {"any": "xsaveopt64 W:mem, <edx>, <eax>" , "op": "NP REX.W 0F AE /6" , "io": "XCR=R"}
+ ]},
+
+ {"category": "GP", "volatile": true, "instructions": [
+ {"any": "cli" , "op": "FA" , "io": "IF=W"},
+ {"any": "int imm8" , "op": "CD ib"},
+ {"any": "int3" , "op": "CC"},
+ {"any": "lar w:r16, R:r16/m16" , "op": "[RM] 66 0F 02 /r" , "io": "ZF=W"},
+ {"any": "lar W:r32, R:r32/m16" , "op": "[RM] 0F 02 /r" , "io": "ZF=W"},
+ {"x86": "lds x:r16, m16_16" , "op": "[RM] 66 C5 /r"},
+ {"x86": "lds X:r32, m16_32" , "op": "[RM] C5 /r"},
+ {"x86": "les x:r16, m16_16" , "op": "[RM] 66 C4 /r"},
+ {"x86": "les X:r32, m16_32" , "op": "[RM] C4 /r"},
+ {"any": "lfs x:r16, m16_16" , "op": "[RM] 66 0F B4 /r"},
+ {"any": "lfs X:r32, m16_32" , "op": "[RM] 0F B4 /r"},
+ {"x64": "lfs X:r64, m16_64" , "op": "[RM] REX.W 0F B4 /r"},
+ {"any": "lgs x:r16, m16_16" , "op": "[RM] 66 0F B5 /r"},
+ {"any": "lgs X:r32, m16_32" , "op": "[RM] 0F B5 /r"},
+ {"x64": "lgs X:r64, m16_64" , "op": "[RM] REX.W 0F B5 /r"},
+ {"any": "lsl w:r16, R:r16/m16" , "op": "[RM] 66 0F 03 /r" , "io": "ZF=W"},
+ {"any": "lsl W:r32, R:r32/m16" , "op": "[RM] 0F 03 /r" , "io": "ZF=W"},
+ {"x64": "lsl W:r64, R:r32/m16" , "op": "[RM] REX.W 0F 03 /r" , "io": "ZF=W"},
+ {"any": "lss x:r16, m16_16" , "op": "[RM] 66 0F B2 /r"},
+ {"any": "lss X:r32, m16_32" , "op": "[RM] 0F B2 /r"},
+ {"x64": "lss X:r64, m16_64" , "op": "[RM] REX.W 0F B2 /r"},
+ {"any": "pause" , "op": "F3 90"},
+ {"x86": "rsm" , "op": "0F AA" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "sgdt W:mem" , "op": "0F 01 /0"},
+ {"any": "sidt W:mem" , "op": "0F 01 /1"},
+ {"any": "sldt w:r16/m16" , "op": "66 0F 00 /0"},
+ {"any": "sldt W:r32/m16" , "op": "0F 00 /0"},
+ {"x64": "sldt W:r64/m16" , "op": "REX.W 0F 00 /0"},
+ {"any": "smsw w:r16/m16" , "op": "66 0F 01 /4"},
+ {"any": "smsw W:r32/m16" , "op": "0F 01 /4"},
+ {"x64": "smsw W:r64/m16" , "op": "REX.W 0F 01 /4"},
+ {"any": "sti" , "op": "FB" , "io": "IF=1"},
+ {"any": "str w:r16/m16" , "op": "66 0F 00 /1"},
+ {"any": "str W:r32/m16" , "op": "0F 00 /1"},
+ {"any": "str W:r64/m16" , "op": "REX.W 0F 00 /1"},
+ {"x64": "syscall" , "op": "0F 05"},
+ {"any": "sysenter" , "op": "0F 34"},
+ {"any": "verr R:r16/m16" , "op": "0F 00 /4" , "io": "ZF=W"},
+ {"any": "verw R:r16/m16" , "op": "0F 00 /5" , "io": "ZF=W"},
+ {"any": "xlatb" , "op": "D7"}
+ ]},
+
+ {"category": "GP", "deprecated": true, "instructions": [
+ {"x86": "aaa x:<ax>" , "op": "37" , "io": "OF=U SF=U ZF=U AF=W PF=U CF=W"},
+ {"x86": "aad x:<ax>, imm8" , "op": "D5 ib" , "io": "OF=U SF=W ZF=W AF=U PF=W CF=U"},
+ {"x86": "aam x:<ax>, imm8" , "op": "D4 ib" , "io": "OF=U SF=W ZF=W AF=U PF=W CF=U"},
+ {"x86": "aas x:<ax>" , "op": "3F" , "io": "OF=U SF=U ZF=U AF=W PF=U CF=W"},
+ {"x86": "arpl x:r16/m16, R:r16" , "op": "[MR] 63 /r" , "io": "ZF=W"},
+ {"x86": "bound R:r16, R:m32" , "op": "[RM] 66 62 /r"},
+ {"x86": "bound R:r32, R:m64" , "op": "[RM] 62 /r"},
+ {"x86": "daa x:<ax>" , "op": "27" , "io": "OF=U SF=W ZF=W AF=W PF=W CF=W"},
+ {"x86": "das x:<ax>" , "op": "2F" , "io": "OF=U SF=W ZF=W AF=W PF=W CF=W"},
+ {"x86": "into" , "op": "CE" , "io": "OF=R"},
+ {"x86": "popa" , "op": "66 61"},
+ {"x86": "popad" , "op": "61"},
+ {"x86": "pusha" , "op": "66 60"},
+ {"x86": "pushad" , "op": "60"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MPX", "deprecated": true, "instructions": [
+ {"x86": "bndcl R:bnd, r32/m32" , "op": "[RM] F3 0F 1A /r"},
+ {"x64": "bndcl R:bnd, r64/m64" , "op": "[RM] F3 0F 1A /r"},
+ {"x86": "bndcn R:bnd, r32/m32" , "op": "[RM] F2 0F 1B /r"},
+ {"x64": "bndcn R:bnd, r64/m64" , "op": "[RM] F2 0F 1B /r"},
+ {"x86": "bndcu R:bnd, r32/m32" , "op": "[RM] F2 0F 1A /r"},
+ {"x64": "bndcu R:bnd, r64/m64" , "op": "[RM] F2 0F 1A /r"},
+ {"any": "bndldx W:bnd, mib" , "op": "[RM] 0F 1A /r"},
+ {"any": "bndmk W:bnd, mem" , "op": "[RM] F3 0F 1B /r"},
+ {"any": "bndmov W:bnd, bnd/mem" , "op": "[RM] 66 0F 1A /r"},
+ {"any": "bndmov W:bnd/mem, bnd" , "op": "[MR] 66 0F 1B /r"},
+ {"any": "bndstx W:mib, bnd" , "op": "[MR] 0F 1B /r"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "TBM", "deprecated": true, "instructions": [
+ {"any": "blci W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 02 /6"},
+ {"any": "blcic W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /5"},
+ {"any": "blsic W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /6"},
+ {"any": "blcfill W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /1"},
+ {"any": "blsfill W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /2"},
+ {"any": "blcmsk W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 02 /1"},
+ {"any": "blcs W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /3"},
+ {"any": "tzmsk W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /4"},
+ {"any": "t1mskc W:ry, ry/my" , "op": "[VM ] XOP.LZ.MAP9.Wy 01 /7"}
+ ]},
+
+ {"category": "GP", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "clts" , "op": "0F 06"},
+ {"any": "hlt" , "op": "F4"},
+ {"any": "lgdt R:mem" , "op": "0F 01 /2"},
+ {"any": "lidt R:mem" , "op": "0F 01 /3"},
+ {"any": "lldt R:r16/m16" , "op": "0F 00 /2"},
+ {"any": "lmsw R:r16/m16" , "op": "0F 01 /6"},
+ {"any": "ltr R:r16/m16" , "op": "0F 00 /3"},
+ {"any": "rdpmc W:<edx>, W:<eax>, R:<ecx>" , "op": "0F 33"},
+ {"x64": "swapgs" , "op": "0F 01 F8"},
+ {"any": "sysexit" , "op": "0F 35"},
+ {"any": "sysexitq" , "op": "REX.W 0F 35"},
+ {"x64": "sysret" , "op": "0F 07"},
+ {"x64": "sysretq" , "op": "REX.W 0F 07"}
+ ]},
+
+ {"category": "GP", "ext": "I486", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "invd" , "op": "[OP] 0F 08"},
+ {"any": "invlpg R:mem" , "op": "[M ] 0F 01 /7"},
+ {"x86": "invpcid R:r32, R:m128" , "op": "[RM] 66 0F 38 82 /r"},
+ {"x64": "invpcid R:r64, R:m128" , "op": "[RM] 66 0F 38 82 /r"},
+ {"apx": "invpcid R:r64, R:m128" , "op": "[RM] EVEX.ND=0.LLZ.F3.MAP4.WIG F2 !(11):rrr:bbb"},
+ {"any": "wbinvd" , "op": "[OP] 0F 09"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CET_IBT", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "endbr32" , "op": "F3 0F 1E FB"},
+ {"any": "endbr64" , "op": "F3 0F 1E FA"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "CET_SS", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "clrssbsy R:m64" , "op": "F3 0F AE /6" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"},
+ {"any": "setssbsy" , "op": "F3 0F 01 E8"},
+ {"any": "wrssd W:m32, R:r32" , "op": "[MR] 0F 38 F6 !(11):rrr:bbb"},
+ {"apx": "wrssd W:m32, R:r32" , "op": "[MR] EVEX.ND=0.LLZ.NP.MAP4.W0 66 !(11):rrr:bbb"},
+ {"x64": "wrssq W:m64, R:r64" , "op": "[MR] REX.W 0F 38 F6 !(11):rrr:bbb"},
+ {"apx": "wrssq W:m64, R:r64" , "op": "[MR] EVEX.ND=0.LLZ.NP.MAP4.W1 66 !(11):rrr:bbb"},
+ {"any": "wrussd W:m32, R:r32" , "op": "[MR] 66 0F 38 F5 !(11):rrr:bbb"},
+ {"apx": "wrussd W:m32, R:r32" , "op": "[MR] EVEX.ND=0.LLZ.66.MAP4.W0 65 !(11):rrr:bbb"},
+ {"x64": "wrussq W:m64, R:r64" , "op": "[MR] REX.W 66 0F 38 F5 !(11):rrr:bbb"},
+ {"apx": "wrussq W:m64, R:r64" , "op": "[MR] EVEX.ND=0.LLZ.66.MAP4.W1 65 !(11):rrr:bbb"}
+
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "HRESET", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "hreset imm8, W:<eax>" , "op": "F3 0F 3A F0 /0 ib"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MONITOR", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "monitor R:<mem(ds:zax)>, R:<ecx>, R:<edx>" , "op": "0F 01 C8"},
+ {"any": "mwait R:<eax>, R:<ecx>" , "op": "0F 01 C9"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MSR", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "rdmsr W:<edx>, W:<eax>, R:<ecx>" , "op": "0F 32" , "io": "MSR=R"},
+ {"any": "wrmsr R:<edx>, R:<eax>, R:<ecx>" , "op": "0F 30" , "io": "MSR=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MSR_IMM", "volatile": true, "privilege": "L0", "instructions": [
+ {"x64": "rdmsr W:r64, R:imm32" , "op": "[M ] VEX.128.F2.MAP7.W0 F6 11:000:bbb id" , "io": "MSR=R"},
+ {"apx": "rdmsr W:r64, R:imm32" , "op": "[M ] EVEX.128.F2.MAP7.W0 F6 11:000:bbb id", "io": "MSR=R"},
+ {"x64": "wrmsrns imm32, R:r64" , "op": "[M ] VEX.128.F3.MAP7.W0 F6 11:000:bbb id" , "io": "MSR=W"},
+ {"apx": "wrmsrns imm32, R:r64" , "op": "[M ] EVEX.128.F3.MAP7.W0 F6 11:000:bbb id", "io": "MSR=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "MSRLIST", "volatile": true, "privilege": "L0", "instructions": [
+ {"x64": "rdmsrlist R:<mem(ds:rsi)>, W:<mem(ds:rdi)>, X:<rcx>" , "op": "[OP] F2 0F 01 C6" , "io": "MSR=R"},
+ {"x64": "wrmsrlist R:<mem(ds:rsi)>, R:<mem(ds:rdi)>, X:<rcx>" , "op": "[OP] F3 0F 01 C6" , "io": "MSR=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "SMX", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "getsec W:<eax>, R:<ebx>" , "op": "[OP] NP 0F 37"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "WBNOINVD", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "wbnoinvd" , "op": "[OP] F3 0F 09"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "WRMSRNS", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "wrmsrns R:<edx>, R:<eax>, R:<ecx>" , "op": "[OP] NP 0F 01 C6" , "io": "MSR=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "XSAVE", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "xsetbv R:<edx>, R:<eax>, R:<ecx>" , "op": "[OP] NP 0F 01 D1" , "io": "XCR=W"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "XSAVES", "volatile": true, "privilege": "L0", "instructions": [
+ {"any": "xrstors R:mem, <edx>, <eax>" , "op": "[M ] NP 0F C7 /3" , "io": "XCR=R"},
+ {"any": "xrstors64 R:mem, <edx>, <eax>" , "op": "[M ] NP REX.W 0F C7 /3" , "io": "XCR=R"},
+ {"any": "xsaves W:mem, <edx>, <eax>" , "op": "[M ] NP 0F C7 /5" , "io": "XCR=R"},
+ {"any": "xsaves64 W:mem, <edx>, <eax>" , "op": "[M ] NP REX.W 0F C7 /5" , "io": "XCR=R"}
+ ]},
+
+ {"category": "VIRTUALIZATION", "ext": "SMAP", "volatile": true, "instructions": [
+ {"any": "clac" , "op": "[OP] NP 0F 01 CA" , "ext": "SMAP" , "privilege": "L0", "io": "AC=0"},
+ {"any": "stac" , "op": "[OP] NP 0F 01 CB" , "ext": "SMAP" , "privilege": "L0", "io": "AC=1"}
+ ]},
+
+ {"category": "VIRTUALIZATION", "ext": "VMX", "volatile": true, "instructions": [
+ {"x86": "invept R:r32, R:m128" , "op": "[RM] 66 0F 38 80 /r" , "privilege": "L0"},
+ {"x64": "invept R:r64, R:m128" , "op": "[RM] 66 0F 38 80 /r" , "privilege": "L0"},
+ {"apx": "invept R:r64, R:m128" , "op": "[RM] EVEX.ND=0.LLZ.F3.MAP4.WIG F0 !(11):rrr:bbb" , "privilege": "L0"},
+ {"x86": "invvpid R:r32, R:m128" , "op": "[RM] 66 0F 38 81 /r" , "privilege": "L0"},
+ {"x64": "invvpid R:r64, R:m128" , "op": "[RM] 66 0F 38 81 /r" , "privilege": "L0"},
+ {"apx": "invvpid R:r64, R:m128" , "op": "[RM] EVEX.ND=0.LLZ.F3.MAP4.WIG F1 !(11):rrr:bbb" , "privilege": "L0"},
+ {"any": "vmcall" , "op": "[OP] 0F 01 C1" , "privilege": "L0"},
+ {"any": "vmclear R:m64" , "op": "[M ] 66 0F C7 /6" , "privilege": "L0"},
+ {"any": "vmfunc" , "op": "[OP] NP 0F 01 D4" , "privilege": "L0"},
+ {"any": "vmlaunch" , "op": "[OP] 0F 01 C2" , "privilege": "L0"},
+ {"any": "vmptrld R:m64" , "op": "[M ] NP 0F C7 /6" , "privilege": "L0"},
+ {"any": "vmptrst W:m64" , "op": "[M ] NP 0F C7 /7" , "privilege": "L0"},
+ {"x86": "vmread W:r32/m32, R:r32" , "op": "[MR] NP 0F 78 /r" , "privilege": "L0"},
+ {"x64": "vmread W:r64/m64, R:r64" , "op": "[MR] NP 0F 78 /r" , "privilege": "L0"},
+ {"any": "vmresume" , "op": "[OP] 0F 01 C3" , "privilege": "L0"},
+ {"x86": "vmwrite R:r32, R:r32/m32" , "op": "[RM] NP 0F 79 /r" , "privilege": "L0"},
+ {"x64": "vmwrite R:r64, R:r64/m64" , "op": "[RM] NP 0F 79 /r" , "privilege": "L0"},
+ {"any": "vmxoff" , "op": "[OP] 0F 01 C4" , "privilege": "L0"},
+ {"any": "vmxon R:m64" , "op": "[M ] F3 0F C7 /6" , "privilege": "L0"}
+ ]},
+
+ {"category": "VIRTUALIZATION", "ext": "SEAM", "volatile": true, "instructions": [
+ {"any": "seamcall" , "op": "[OP] 66 0F 01 CF" , "ext": "SEAM"},
+ {"any": "seamops" , "op": "[OP] 66 0F 01 CE" , "ext": "SEAM"},
+ {"any": "seamret" , "op": "[OP] 66 0F 01 CD" , "ext": "SEAM"},
+ {"any": "tdcall" , "op": "[OP] 66 0F 01 CC" , "ext": "SEAM"}
+ ]},
+
+ {"category": "VIRTUALIZATION", "ext": "ENQCMD", "volatile": true, "instructions": [
+ {"x86": "enqcmd W:m512(es:r32), m512" , "op": "[RM] F2 0F 38 F8 !(11):rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"x64": "enqcmd W:m512(es:r64), m512" , "op": "[RM] F2 0F 38 F8 !(11):rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"apx": "enqcmd W:m512(es:r64), R:m512" , "op": "[RM] EVEX.ND=0.LLZ.F2.MAP4.W? F8 !(11):rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"x86": "enqcmds W:m512(es:r32), m512" , "op": "[RM] F3 0F 38 F8 !(11):rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"x64": "enqcmds W:m512(es:r64), m512" , "op": "[RM] F3 0F 38 F8 !(11):rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"apx": "enqcmds W:m512(es:r64), R:m512" , "op": "[RM] EVEX.ND=0.LLZ.F3.MAP4.W? F8 !(11):rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+ ]},
+
+
+ {"category": "VIRTUALIZATION", "volatile": true, "instructions": [
+ {"any": "clgi" , "op": "0F 01 DD" , "ext": "SVM" , "privilege": "L0"},
+ {"x86": "invlpga R:<eax>, R:<ecx>" , "op": "0F 01 DF" , "ext": "SVM" , "privilege": "L0"},
+ {"x64": "invlpga R:<eax>, R:<ecx>" , "op": "67 0F 01 DF" , "ext": "SVM" , "privilege": "L0"},
+ {"x64": "invlpga R:<rax>, R:<ecx>" , "op": "0F 01 DF" , "ext": "SVM" , "privilege": "L0"},
+ {"x86": "invlpgb R:<eax>, R:<edx>, R:<ecx>" , "op": "0F 01 FE" , "ext": "INVLPGB" , "privilege": "L0"},
+ {"x64": "invlpgb R:<eax>, R:<edx>, R:<ecx>" , "op": "67 0F 01 FE" , "ext": "INVLPGB" , "privilege": "L0"},
+ {"x64": "invlpgb R:<rax>, R:<edx>, R:<ecx>" , "op": "0F 01 FE" , "ext": "INVLPGB" , "privilege": "L0"},
+ {"x64": "psmash" , "op": "F3 0F 01 FF" , "ext": "SEV_SNP" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "pvalidate" , "op": "F2 0F 01 FF" , "ext": "SEV_SNP" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"x64": "rmpadjust" , "op": "F3 0F 01 FE" , "ext": "SEV_SNP" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"x64": "rmpquery R:<rax>, W:<rcx>, W:<rdx>" , "op": "F3 0F 01 FD" , "ext": "RMPQUERY", "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"x64": "rmpupdate" , "op": "F2 0F 01 FE" , "ext": "SEV_SNP" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "skinit X:<eax>" , "op": "0F 01 DE" , "ext": "SKINIT"},
+ {"any": "stgi" , "op": "0F 01 DC" , "ext": "SKINIT"},
+ {"any": "tlbsync" , "op": "0F 01 FF" , "ext": "INVLPGB" , "privilege": "L0"},
+ {"any": "vmgexit" , "op": "F2 0F 01 D9" , "ext": "SEV_ES"},
+ {"x86": "vmload R:<eax>" , "op": "0F 01 DA" , "ext": "SVM" , "privilege": "L0"},
+ {"x64": "vmload R:<rax>" , "op": "0F 01 DA" , "ext": "SVM" , "privilege": "L0"},
+ {"any": "vmmcall" , "op": "0F 01 D9" , "ext": "SVM"},
+ {"x86": "vmrun X:<eax>" , "op": "0F 01 D8" , "ext": "SVM" , "privilege": "L0"},
+ {"x64": "vmrun X:<rax>" , "op": "0F 01 D8" , "ext": "SVM" , "privilege": "L0"},
+ {"x86": "vmsave R:<eax>" , "op": "0F 01 DB" , "ext": "SVM" , "privilege": "L0"},
+ {"x64": "vmsave R:<rax>" , "op": "0F 01 DB" , "ext": "SVM" , "privilege": "L0"}
+ ]},
+
+ {"category": "FPU", "ext": "FPU", "instructions": [
+ {"any": "f2xm1" , "op": "D9 F0" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fabs" , "op": "D9 E1" , "io": "C0=U C1=0 C2=U C3=U"},
+ {"any": "fadd R:m32fp" , "op": "D8 /0" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fadd R:m64fp" , "op": "DC /0" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fadd st(0), st(i)" , "op": "D8 C0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fadd st(i), st(0)" , "op": "DC C0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "faddp" , "op": "DE C1" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "faddp st(i)" , "op": "DE C0+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fbld R:m80dec" , "op": "DF /4" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fbstp W:m80bcd" , "op": "DF /6" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fchs" , "op": "D9 E0" , "io": "C0=U C1=0 C2=U C3=U"},
+ {"any": "fclex" , "op": "9B DB E2" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fcom" , "op": "D8 D1" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fcom R:m32fp" , "op": "D8 /2" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fcom R:m64fp" , "op": "DC /2" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fcom R:st(i)" , "op": "D8 D0+i" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fcomi R:st(i)" , "op": "DB F0+i" , "io": "C1=0 ZF=W PF=W CF=W"},
+ {"any": "fcomip R:st(i)" , "op": "DF F0+i" , "io": "C1=0 ZF=W PF=W CF=W", "fpuStack": "pop"},
+ {"any": "fcomp" , "op": "D8 D9" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"},
+ {"any": "fcomp R:m32fp" , "op": "D8 /3" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"},
+ {"any": "fcomp R:m64fp" , "op": "DC /3" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"},
+ {"any": "fcomp R:st(i)" , "op": "D8 D8+i" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"},
+ {"any": "fcompp" , "op": "DE D9" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop2x"},
+ {"any": "fcos" , "op": "D9 FF" , "io": "C0=U C1=W C2=W C3=U"},
+ {"any": "fdecstp" , "op": "D9 F6" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "dec"},
+ {"any": "fdiv R:m32fp" , "op": "D8 /6" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdiv R:m64fp" , "op": "DC /6" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdiv st(0), st(i)" , "op": "D8 F0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdiv st(i), st(0)" , "op": "DC F8+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdivp" , "op": "DE F9" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fdivp st(i)" , "op": "DE F8+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fdivr R:m32fp" , "op": "D8 /7" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdivr R:m64fp" , "op": "DC /7" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdivr st(0), st(i)" , "op": "D8 F8+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdivr st(i), st(0)" , "op": "DC F0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fdivrp" , "op": "DE F1" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fdivrp st(i)" , "op": "DE F0+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "ffree st(i)" , "op": "DD C0+i" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fiadd R:m16int" , "op": "DE /0" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fiadd R:m32int" , "op": "DA /0" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "ficom R:m16int" , "op": "DE /2" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "ficom R:m32int" , "op": "DA /2" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "ficomp R:m16int" , "op": "DE /3" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "ficomp R:m32int" , "op": "DA /3" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fidiv R:m16int" , "op": "DE /6" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fidiv R:m32int" , "op": "DA /6" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fidivr R:m16int" , "op": "DE /7" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fidivr R:m32int" , "op": "DA /7" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fild R:m16int" , "op": "DF /0" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fild R:m32int" , "op": "DB /0" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fild R:m64int" , "op": "DF /5" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fimul R:m16int" , "op": "DE /1" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fimul R:m32int" , "op": "DA /1" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fincstp" , "op": "D9 F7" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "inc"},
+ {"any": "finit" , "op": "9B DB E3" , "io": "C0=0 C1=0 C2=0 C3=0"},
+ {"any": "fist W:m16int" , "op": "DF /2" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fist W:m32int" , "op": "DB /2" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fistp W:m16int" , "op": "DF /3" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fistp W:m32int" , "op": "DB /3" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fistp W:m64int" , "op": "DF /7" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fisub R:m16int" , "op": "DE /4" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fisub R:m32int" , "op": "DA /4" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fisubr R:m16int" , "op": "DE /5" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fisubr R:m32int" , "op": "DA /5" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fld R:m32fp" , "op": "D9 /0" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fld R:m64fp" , "op": "DD /0" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fld R:m80fp" , "op": "DB /5" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fld R:st(i)" , "op": "D9 C0+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fld1" , "op": "D9 E8" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fldcw R:m16" , "op": "D9 /5" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fldenv R:mem" , "op": "D9 /4" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fldl2e" , "op": "D9 EA" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fldl2t" , "op": "D9 E9" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fldlg2" , "op": "D9 EC" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fldln2" , "op": "D9 ED" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fldpi" , "op": "D9 EB" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fldz" , "op": "D9 EE" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fmul R:m32fp" , "op": "D8 /1" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fmul R:m64fp" , "op": "DC /1" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fmul st(0), st(i)" , "op": "D8 C8+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fmul st(i), st(0)" , "op": "DC C8+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fmulp" , "op": "DE C9" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fmulp st(i)" , "op": "DE C8+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fnclex" , "op": "DB E2" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fninit" , "op": "DB E3" , "io": "C0=0 C1=0 C2=0 C3=0"},
+ {"any": "fnop" , "op": "D9 D0" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fnsave W:mem" , "op": "DD /6" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fnstcw W:m16" , "op": "D9 /7" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fnstenv W:mem" , "op": "D9 /6" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fnstsw w:ax" , "op": "DF E0" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fnstsw W:m16" , "op": "DD /7" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fpatan" , "op": "D9 F3" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fprem" , "op": "D9 F8" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fprem1" , "op": "D9 F5" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fptan" , "op": "D9 F2" , "io": "C0=U C1=W C2=W C3=U", "fpuStack": "pop"},
+ {"any": "frndint" , "op": "D9 FC" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "frstor R:mem" , "op": "DD /4" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fsave W:mem" , "op": "9B DD /6" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fscale" , "op": "D9 FD" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsin" , "op": "D9 FE" , "io": "C0=U C1=W C2=W C3=U"},
+ {"any": "fsincos" , "op": "D9 FB" , "io": "C0=U C1=W C2=W C3=U", "fpuStack": "push"},
+ {"any": "fsqrt" , "op": "D9 FE" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fst W:m32fp" , "op": "D9 /2" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fst W:m64fp" , "op": "DD /2" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fst W:st(i)" , "op": "DD D0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fstcw W:m16" , "op": "9B D9 /7" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fstenv W:mem" , "op": "9B D9 /6" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fstp W:m32fp" , "op": "D9 /3" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fstp W:m64fp" , "op": "DD /3" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fstp W:m80fp" , "op": "DB /7" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fstp W:st(i)" , "op": "DD D8+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fstsw w:ax" , "op": "9B DF E0" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fstsw W:m16" , "op": "9B DD /7" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fsub R:m32fp" , "op": "D8 /4" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsub R:m64fp" , "op": "DC /4" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsub st(0), st(i)" , "op": "D8 E0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsub st(i), st(0)" , "op": "DC E8+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsubp" , "op": "DE E9" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fsubp st(i)" , "op": "DE E8+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fsubr R:m32fp" , "op": "D8 /5" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsubr R:m64fp" , "op": "DC /5" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsubr st(0), st(i)" , "op": "D8 E8+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsubr st(i), st(0)" , "op": "DC E0+i" , "io": "C0=U C1=W C2=U C3=U"},
+ {"any": "fsubrp" , "op": "DE E1" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fsubrp st(i)" , "op": "DE E0+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "ftst" , "op": "D9 E4" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fucom" , "op": "DD E1" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fucom R:st(i)" , "op": "DD E0+i" , "io": "C0=W C1=0 C2=W C3=W"},
+ {"any": "fucomi R:st(i)" , "op": "DB E8+i" , "io": "C1=0 ZF=W PF=W CF=W"},
+ {"any": "fucomip R:st(i)" , "op": "DF E8+i" , "io": "C1=0 ZF=W PF=W CF=W", "fpuStack": "pop"},
+ {"any": "fucomp" , "op": "DD E9" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"},
+ {"any": "fucomp R:st(i)" , "op": "DD E8+i" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"},
+ {"any": "fucompp" , "op": "DA E9" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop2x"},
+ {"any": "fwait" , "op": "9B" , "io": "C0=U C1=U C2=U C3=U"},
+ {"any": "fxam" , "op": "D9 E5" , "io": "C0=W C1=W C2=W C3=W"},
+ {"any": "fxch" , "op": "D9 C9" , "io": "C0=U C1=0 C2=U C3=U"},
+ {"any": "fxch st(i)" , "op": "D9 C8+i" , "io": "C0=U C1=0 C2=U C3=U"},
+ {"any": "fxtract" , "op": "D9 F4" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"},
+ {"any": "fyl2x" , "op": "D9 F1" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fyl2xp1" , "op": "D9 F9" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"}
+ ]},
+
+ {"category": "FPU", "ext": "FPU CMOV", "instructions": [
+ {"any": "fcmovb st(i)" , "op": "DA C0+i" , "io": "C0=U C1=W C2=U C3=U CF=R" },
+ {"any": "fcmovbe st(i)" , "op": "DA D0+i" , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R"},
+ {"any": "fcmove st(i)" , "op": "DA C8+i" , "io": "C0=U C1=W C2=U C3=U ZF=R" },
+ {"any": "fcmovnb st(i)" , "op": "DB C0+i" , "io": "C0=U C1=W C2=U C3=U CF=R" },
+ {"any": "fcmovnbe st(i)" , "op": "DB D0+i" , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R"},
+ {"any": "fcmovne st(i)" , "op": "DB C8+i" , "io": "C0=U C1=W C2=U C3=U ZF=R" },
+ {"any": "fcmovnu st(i)" , "op": "DB D8+i" , "io": "C0=U C1=W C2=U C3=U PF=R" },
+ {"any": "fcmovu st(i)" , "op": "DA D8+i" , "io": "C0=U C1=W C2=U C3=U PF=R" }
+ ]},
+
+ {"category": "FPU", "ext": "FPU SSE3", "instructions": [
+ {"any": "fisttp W:m16int" , "op": "DF /1" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fisttp W:m32int" , "op": "DB /1" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"},
+ {"any": "fisttp W:m64int" , "op": "DD /1" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"}
+ ]},
+
+ {"category": "MMX STATE", "deprecated": true, "volatile": true, "instructions": [
+ {"any": "emms" , "op": "[OP] 0F 77" , "ext": "MMX"},
+ {"any": "femms" , "op": "[OP] 0F 0E" , "ext": "3DNOW"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "MMX", "deprecated": true, "instructions": [
+ {"any": "movd W:mm[31:0], R:r32[31:0]/m32" , "op": "[RM] NP 0F 6E /r"},
+ {"any": "movd W:r32[31:0]/m32, R:mm[31:0]" , "op": "[MR] NP 0F 7E /r"},
+ {"any": "movq W:mm, mm/m64" , "op": "[RM] NP 0F 6F /r"},
+ {"x64": "movq W:mm, r64/m64" , "op": "[RM] NP REX.W 0F 6E /r"},
+ {"any": "movq W:mm/m64, mm" , "op": "[MR] NP 0F 7F /r"},
+ {"x64": "movq W:r64/m64, mm" , "op": "[MR] NP REX.W 0F 7E /r"},
+ {"any": "packssdw X:mm, mm/m64" , "op": "[RM] NP 0F 6B /r"},
+ {"any": "packsswb X:mm, mm/m64" , "op": "[RM] NP 0F 63 /r"},
+ {"any": "packuswb X:mm, mm/m64" , "op": "[RM] NP 0F 67 /r"},
+ {"any": "paddb X:~mm, ~mm/m64" , "op": "[RM] NP 0F FC /r"},
+ {"any": "paddd X:~mm, ~mm/m64" , "op": "[RM] NP 0F FE /r"},
+ {"any": "paddsb X:~mm, ~mm/m64" , "op": "[RM] NP 0F EC /r"},
+ {"any": "paddsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F ED /r"},
+ {"any": "paddusb X:~mm, ~mm/m64" , "op": "[RM] NP 0F DC /r"},
+ {"any": "paddusw X:~mm, ~mm/m64" , "op": "[RM] NP 0F DD /r"},
+ {"any": "paddw X:~mm, ~mm/m64" , "op": "[RM] NP 0F FD /r"},
+ {"any": "pand X:~mm, ~mm/m64" , "op": "[RM] NP 0F DB /r"},
+ {"any": "pandn X:mm, mm/m64" , "op": "[RM] NP 0F DF /r"},
+ {"any": "pcmpeqb X:~mm, ~mm/m64" , "op": "[RM] NP 0F 74 /r"},
+ {"any": "pcmpeqd X:~mm, ~mm/m64" , "op": "[RM] NP 0F 76 /r"},
+ {"any": "pcmpeqw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 75 /r"},
+ {"any": "pcmpgtb X:mm, mm/m64" , "op": "[RM] NP 0F 64 /r"},
+ {"any": "pcmpgtd X:mm, mm/m64" , "op": "[RM] NP 0F 66 /r"},
+ {"any": "pcmpgtw X:mm, mm/m64" , "op": "[RM] NP 0F 65 /r"},
+ {"any": "pmaddwd X:~mm, ~mm/m64" , "op": "[RM] NP 0F F5 /r"},
+ {"any": "pmulhw X:~mm, ~mm/m64" , "op": "[RM] NP 0F E5 /r"},
+ {"any": "pmullw X:~mm, ~mm/m64" , "op": "[RM] NP 0F D5 /r"},
+ {"any": "por X:~mm, ~mm/m64" , "op": "[RM] NP 0F EB /r"},
+ {"any": "pslld X:mm, mm/m64" , "op": "[RM] NP 0F F2 /r"},
+ {"any": "pslld X:mm, imm8" , "op": "[M ] NP 0F 72 /6 ib"},
+ {"any": "psllq X:mm, mm/m64" , "op": "[RM] NP 0F F3 /r"},
+ {"any": "psllq X:mm, imm8" , "op": "[M ] NP 0F 73 /6 ib"},
+ {"any": "psllw X:mm, mm/m64" , "op": "[RM] NP 0F F1 /r"},
+ {"any": "psllw X:mm, imm8" , "op": "[M ] NP 0F 71 /6 ib"},
+ {"any": "psrad X:mm, mm/m64" , "op": "[RM] NP 0F E2 /r"},
+ {"any": "psrad X:mm, imm8" , "op": "[M ] NP 0F 72 /4 ib"},
+ {"any": "psraw X:mm, mm/m64" , "op": "[RM] NP 0F E1 /r"},
+ {"any": "psraw X:mm, imm8" , "op": "[M ] NP 0F 71 /4 ib"},
+ {"any": "psrld X:mm, mm/m64" , "op": "[RM] NP 0F D2 /r"},
+ {"any": "psrld X:mm, imm8" , "op": "[M ] NP 0F 72 /2 ib"},
+ {"any": "psrlq X:mm, mm/m64" , "op": "[RM] NP 0F D3 /r"},
+ {"any": "psrlq X:mm, imm8" , "op": "[M ] NP 0F 73 /2 ib"},
+ {"any": "psrlw X:mm, mm/m64" , "op": "[RM] NP 0F D1 /r"},
+ {"any": "psrlw X:mm, imm8" , "op": "[M ] NP 0F 71 /2 ib"},
+ {"any": "psubb X:mm, mm/m64" , "op": "[RM] NP 0F F8 /r"},
+ {"any": "psubd X:mm, mm/m64" , "op": "[RM] NP 0F FA /r"},
+ {"any": "psubsb X:mm, mm/m64" , "op": "[RM] NP 0F E8 /r"},
+ {"any": "psubsw X:mm, mm/m64" , "op": "[RM] NP 0F E9 /r"},
+ {"any": "psubusb X:mm, mm/m64" , "op": "[RM] NP 0F D8 /r"},
+ {"any": "psubusw X:mm, mm/m64" , "op": "[RM] NP 0F D9 /r"},
+ {"any": "psubw X:mm, mm/m64" , "op": "[RM] NP 0F F9 /r"},
+ {"any": "punpckhbw X:mm, mm/m64" , "op": "[RM] NP 0F 68 /r"},
+ {"any": "punpckhdq X:mm, mm/m64" , "op": "[RM] NP 0F 6A /r"},
+ {"any": "punpckhwd X:mm, mm/m64" , "op": "[RM] NP 0F 69 /r"},
+ {"any": "punpcklbw X:mm, mm/m32" , "op": "[RM] NP 0F 60 /r"},
+ {"any": "punpckldq X:mm, mm/m32" , "op": "[RM] NP 0F 62 /r"},
+ {"any": "punpcklwd X:mm, mm/m32" , "op": "[RM] NP 0F 61 /r"},
+ {"any": "pxor X:~mm, ~mm/m64" , "op": "[RM] NP 0F EF /r"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "MMX2", "deprecated": true, "instructions": [
+ {"any": "maskmovq R:mm, mm, X:<m64(ds:zdi)>" , "op": "[RM] NP 0F F7 /r"},
+ {"any": "movntq W:m64, mm" , "op": "[MR] NP 0F E7 /r"},
+ {"any": "pavgb X:~mm, ~mm/m64" , "op": "[RM] NP 0F E0 /r"},
+ {"any": "pavgw X:~mm, ~mm/m64" , "op": "[RM] NP 0F E3 /r"},
+ {"any": "pextrw W:r32[15:0], mm, imm8" , "op": "[RM] NP 0F C5 /r ib"},
+ {"any": "pinsrw X:mm, r32[15:0]/m16, imm8" , "op": "[RM] NP 0F C4 /r ib"},
+ {"any": "pmaxsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F EE /r"},
+ {"any": "pmaxub X:~mm, ~mm/m64" , "op": "[RM] NP 0F DE /r"},
+ {"any": "pminsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F EA /r"},
+ {"any": "pminub X:~mm, ~mm/m64" , "op": "[RM] NP 0F DA /r"},
+ {"any": "pmovmskb W:r32[7:0], mm" , "op": "[RM] NP 0F D7 /r"},
+ {"any": "pmulhuw X:~mm, ~mm/m64" , "op": "[RM] NP 0F E4 /r"},
+ {"any": "psadbw X:~mm, ~mm/m64" , "op": "[RM] NP 0F F6 /r"},
+ {"any": "pshufw W:mm, mm/m64, imm8" , "op": "[RM] NP 0F 70 /r ib"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "3DNOW", "deprecated": true, "instructions": [
+ {"any": "pavgusb X:mm, mm/m64" , "op": "[RM] 0F 0F /r BF"},
+ {"any": "pf2id W:mm, mm/m64" , "op": "[RM] 0F 0F /r 1D"},
+ {"any": "pfacc X:mm, mm/m64" , "op": "[RM] 0F 0F /r AE"},
+ {"any": "pfadd X:mm, mm/m64" , "op": "[RM] 0F 0F /r 9E"},
+ {"any": "pfcmpeq X:mm, mm/m64" , "op": "[RM] 0F 0F /r B0"},
+ {"any": "pfcmpge X:mm, mm/m64" , "op": "[RM] 0F 0F /r 90"},
+ {"any": "pfcmpgt X:mm, mm/m64" , "op": "[RM] 0F 0F /r A0"},
+ {"any": "pfmax X:mm, mm/m64" , "op": "[RM] 0F 0F /r A4"},
+ {"any": "pfmin X:mm, mm/m64" , "op": "[RM] 0F 0F /r 94"},
+ {"any": "pfmul X:mm, mm/m64" , "op": "[RM] 0F 0F /r B4"},
+ {"any": "pfrcp W:mm, mm/m64" , "op": "[RM] 0F 0F /r 96"},
+ {"any": "pfrcpit1 X:mm, mm/m64" , "op": "[RM] 0F 0F /r A6"},
+ {"any": "pfrcpit2 X:mm, mm/m64" , "op": "[RM] 0F 0F /r B6"},
+ {"any": "pfrsqit1 W:mm, mm/m64" , "op": "[RM] 0F 0F /r A7"},
+ {"any": "pfrsqrt W:mm, mm/m64" , "op": "[RM] 0F 0F /r 97"},
+ {"any": "pfsub X:mm, mm/m64" , "op": "[RM] 0F 0F /r 9A"},
+ {"any": "pfsubr X:mm, mm/m64" , "op": "[RM] 0F 0F /r AA"},
+ {"any": "pi2fd W:mm, mm/m64" , "op": "[RM] 0F 0F /r 0D"},
+ {"any": "pmulhrw X:mm, mm/m64" , "op": "[RM] 0F 0F /r B7"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "3DNOW2", "deprecated": true, "instructions": [
+ {"any": "pf2iw W:mm, mm/m64" , "op": "[RM] 0F 0F /r 1C"},
+ {"any": "pfnacc X:mm, mm/m64" , "op": "[RM] 0F 0F /r 8A"},
+ {"any": "pfpnacc X:mm, mm/m64" , "op": "[RM] 0F 0F /r 8E"},
+ {"any": "pi2fw W:mm, mm/m64" , "op": "[RM] 0F 0F /r 0C"},
+ {"any": "pswapd W:mm, mm/m64" , "op": "[RM] 0F 0F /r BB"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "GEODE", "deprecated": true, "instructions": [
+ {"any": "pfrcpv X:mm, mm/m64" , "op": "[RM] 0F 0F /r 86"},
+ {"any": "pfrsqrtv X:mm, mm/m64" , "op": "[RM] 0F 0F /r 87"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "SSE", "deprecated": true, "instructions": [
+ {"any": "cvtpi2ps w:xmm[63:0], mm/m64" , "op": "[RM] NP 0F 2A /r"},
+ {"any": "cvtps2pi W:mm, xmm[63:0]/m64" , "op": "[RM] NP 0F 2D /r"},
+ {"any": "cvttps2pi W:mm, xmm[63:0]/m64" , "op": "[RM] NP 0F 2C /r"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "SSE2", "deprecated": true, "instructions": [
+ {"any": "cvtpd2pi W:mm, xmm/m128" , "op": "[RM] 66 0F 2D /r"},
+ {"any": "cvtpi2pd W:xmm, R:mm[63:0]/m64" , "op": "[RM] 66 0F 2A /r"},
+ {"any": "cvttpd2pi W:mm, xmm/m128" , "op": "[RM] 66 0F 2C /r"},
+ {"any": "movdq2q W:mm, xmm[63:0]" , "op": "[RM] F2 0F D6 /r"},
+ {"any": "movq2dq W:xmm[63:0], mm" , "op": "[RM] F3 0F D6 /r"},
+ {"any": "paddq X:~mm, ~mm/m64" , "op": "[RM] NP 0F D4 /r"},
+ {"any": "pmuludq X:~mm, ~mm/m64" , "op": "[RM] NP 0F F4 /r"},
+ {"any": "psubq X:mm, mm/m64" , "op": "[RM] NP 0F FB /r"}
+ ]},
+
+ {"category": "MMX SIMD", "ext": "SSSE3", "deprecated": true, "instructions": [
+ {"any": "pabsb W:mm, mm/m64" , "op": "[RM] NP 0F 38 1C /r"},
+ {"any": "pabsd W:mm, mm/m64" , "op": "[RM] NP 0F 38 1E /r"},
+ {"any": "pabsw W:mm, mm/m64" , "op": "[RM] NP 0F 38 1D /r"},
+ {"any": "palignr X:mm, mm/m64, imm8" , "op": "[RM] NP 0F 3A 0F /r ib"},
+ {"any": "phaddd X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 02 /r"},
+ {"any": "phaddsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 03 /r"},
+ {"any": "phaddw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 01 /r"},
+ {"any": "phsubd X:mm, mm/m64" , "op": "[RM] NP 0F 38 06 /r"},
+ {"any": "phsubsw X:mm, mm/m64" , "op": "[RM] NP 0F 38 07 /r"},
+ {"any": "phsubw X:mm, mm/m64" , "op": "[RM] NP 0F 38 05 /r"},
+ {"any": "pmaddubsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 04 /r"},
+ {"any": "pmulhrsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 0B /r"},
+ {"any": "pshufb X:mm, mm/m64" , "op": "[RM] NP 0F 38 00 /r"},
+ {"any": "psignb X:mm, mm/m64" , "op": "[RM] NP 0F 38 08 /r"},
+ {"any": "psignd X:mm, mm/m64" , "op": "[RM] NP 0F 38 0A /r"},
+ {"any": "psignw X:mm, mm/m64" , "op": "[RM] NP 0F 38 09 /r"}
+ ]},
+
+ {"category": "SSE STATE", "ext": "SSE", "instructions": [
+ {"any": "ldmxcsr R:m32" , "op": "[M ] NP 0F AE /2", "io": "MXCSR=W"},
+ {"any": "stmxcsr W:m32" , "op": "[M ] NP 0F AE /3", "io": "MXCSR=R"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSE", "instructions": [
+ {"any": "addps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 58 /r"},
+ {"any": "addss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 58 /r"},
+ {"any": "andnps X:xmm, xmm/m128" , "op": "[RM] NP 0F 55 /r"},
+ {"any": "andps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 54 /r"},
+ {"any": "cmpps X:xmm, xmm/m128, imm8" , "op": "[RM] NP 0F C2 /r ib"},
+ {"any": "cmpss x:xmm[31:0], xmm[31:0]/m32, imm8" , "op": "[RM] F3 0F C2 /r ib"},
+ {"any": "comiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] NP 0F 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "cvtsi2ss w:xmm[31:0], ry/my" , "op": "[RM] F3 0F 2A /r"},
+ {"any": "cvtss2si W:ry, xmm[31:0]/m32" , "op": "[RM] F3 0F 2D /r"},
+ {"any": "cvttss2si W:ry, xmm[31:0]/m32" , "op": "[RM] F3 0F 2C /r"},
+ {"any": "divps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5E /r"},
+ {"any": "divss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5E /r"},
+ {"any": "maxps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5F /r"},
+ {"any": "maxss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5F /r"},
+ {"any": "minps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5D /r"},
+ {"any": "minss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5D /r"},
+ {"any": "movaps W:xmm, xmm/m128" , "op": "[RM] NP 0F 28 /r"},
+ {"any": "movaps W:xmm/m128, xmm" , "op": "[MR] NP 0F 29 /r"},
+ {"any": "movhlps w:xmm[63:0], xmm[127:64]" , "op": "[RM] NP 0F 12 /r"},
+ {"any": "movhps W:m64, xmm[127:64]" , "op": "[MR] NP 0F 17 /r"},
+ {"any": "movhps w:xmm[127:64], m64" , "op": "[RM] NP 0F 16 /r"},
+ {"any": "movlhps w:xmm[127:64], xmm[63:0]" , "op": "[RM] NP 0F 16 /r"},
+ {"any": "movlps W:m64, xmm[63:0]" , "op": "[MR] NP 0F 13 /r"},
+ {"any": "movlps w:xmm[63:0], m64" , "op": "[RM] NP 0F 12 /r"},
+ {"any": "movmskps W:r32[3:0], xmm" , "op": "[RM] NP 0F 50 /r"},
+ {"any": "movntps W:m128, xmm" , "op": "[MR] NP 0F 2B /r"},
+ {"any": "movss w:xmm[31:0], xmm[31:0]" , "op": "[RM] F3 0F 10 /r"},
+ {"any": "movss W:xmm[31:0], m32" , "op": "[RM] F3 0F 10 /r"},
+ {"any": "movss W:m32, xmm[31:0]" , "op": "[MR] F3 0F 11 /r"},
+ {"any": "movups W:xmm, xmm/m128" , "op": "[RM] NP 0F 10 /r"},
+ {"any": "movups W:xmm/m128, xmm" , "op": "[MR] NP 0F 11 /r"},
+ {"any": "mulps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 59 /r"},
+ {"any": "mulss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 59 /r"},
+ {"any": "orps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 56 /r"},
+ {"any": "rcpps W:xmm, xmm/m128" , "op": "[RM] NP 0F 53 /r"},
+ {"any": "rcpss w:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 53 /r"},
+ {"any": "rsqrtps W:xmm, xmm/m128" , "op": "[RM] NP 0F 52 /r"},
+ {"any": "rsqrtss w:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 52 /r"},
+ {"any": "shufps X:xmm, xmm/m128, imm8" , "op": "[RM] NP 0F C6 /r ib"},
+ {"any": "sqrtps W:xmm, xmm/m128" , "op": "[RM] NP 0F 51 /r"},
+ {"any": "sqrtss w:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 51 /r"},
+ {"any": "subps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5C /r"},
+ {"any": "subss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5C /r"},
+ {"any": "ucomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] NP 0F 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "unpckhps X:xmm, xmm/m128" , "op": "[RM] NP 0F 15 /r"},
+ {"any": "unpcklps X:xmm, xmm/m128" , "op": "[RM] NP 0F 14 /r"},
+ {"any": "xorps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 57 /r"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSE2", "instructions": [
+ {"any": "addpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 58 /r"},
+ {"any": "addsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 58 /r"},
+ {"any": "andnpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 55 /r"},
+ {"any": "andpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 54 /r"},
+ {"any": "cmppd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F C2 /r ib"},
+ {"any": "cmpsd x:xmm[63:0], xmm[63:0]/m64, imm8" , "op": "[RM] F2 0F C2 /r ib"},
+ {"any": "comisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] 66 0F 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "cvtdq2pd W:xmm, xmm[63:0]/m64" , "op": "[RM] F3 0F E6 /r"},
+ {"any": "cvtdq2ps W:xmm, xmm/m128" , "op": "[RM] NP 0F 5B /r"},
+ {"any": "cvtpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM] F2 0F E6 /r"},
+ {"any": "cvtpd2ps W:xmm[63:0], xmm/m128" , "op": "[RM] 66 0F 5A /r"},
+ {"any": "cvtps2dq W:xmm, xmm/m128" , "op": "[RM] 66 0F 5B /r"},
+ {"any": "cvtps2pd W:xmm, xmm[63:0]/m64" , "op": "[RM] NP 0F 5A /r"},
+ {"any": "cvtsd2si W:ry, xmm[63:0]/m64" , "op": "[RM] F2 0F 2D /r"},
+ {"any": "cvtsd2ss w:xmm[31:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5A /r"},
+ {"any": "cvtsi2sd w:xmm[63:0], ry/my" , "op": "[RM] F2 0F 2A /r"},
+ {"any": "cvtss2sd w:xmm[63:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5A /r"},
+ {"any": "cvttpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM] 66 0F E6 /r"},
+ {"any": "cvttps2dq W:xmm, xmm/m128" , "op": "[RM] F3 0F 5B /r"},
+ {"any": "cvttsd2si W:ry, xmm[63:0]/m64" , "op": "[RM] F2 0F 2C /r"},
+ {"any": "divpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5E /r"},
+ {"any": "divsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5E /r"},
+ {"any": "maskmovdqu R:xmm, xmm, X:<m128(ds:zdi)>" , "op": "[RM] 66 0F F7 /r"},
+ {"any": "maxpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5F /r"},
+ {"any": "maxsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5F /r"},
+ {"any": "minpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5D /r"},
+ {"any": "minsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5D /r"},
+ {"any": "movapd W:xmm, xmm/m128" , "op": "[RM] 66 0F 28 /r"},
+ {"any": "movapd W:xmm/m128, xmm" , "op": "[MR] 66 0F 29 /r"},
+ {"any": "movd W:r32[31:0]/m32, xmm[31:0]" , "op": "[MR] 66 0F 7E /r"},
+ {"any": "movd W:xmm[31:0], R:r32[31:0]/m32" , "op": "[RM] 66 0F 6E /r"},
+ {"any": "movdqa W:xmm, xmm/m128" , "op": "[RM] 66 0F 6F /r"},
+ {"any": "movdqa W:xmm/m128, xmm" , "op": "[MR] 66 0F 7F /r"},
+ {"any": "movdqu W:xmm, xmm/m128" , "op": "[RM] F3 0F 6F /r"},
+ {"any": "movdqu W:xmm/m128, xmm" , "op": "[MR] F3 0F 7F /r"},
+ {"any": "movhpd W:m64, xmm[127:64]" , "op": "[MR] 66 0F 17 /r"},
+ {"any": "movhpd w:xmm[127:64], m64" , "op": "[RM] 66 0F 16 /r"},
+ {"any": "movlpd W:m64, xmm[63:0]" , "op": "[MR] 66 0F 13 /r"},
+ {"any": "movlpd w:xmm[63:0], m64" , "op": "[RM] 66 0F 12 /r"},
+ {"any": "movmskpd W:r32[1:0], xmm" , "op": "[RM] 66 0F 50 /r"},
+ {"any": "movntdq W:m128, xmm" , "op": "[MR] 66 0F E7 /r"},
+ {"any": "movntpd W:m128, xmm" , "op": "[MR] 66 0F 2B /r"},
+ {"x64": "movq W:r64/m64, xmm[63:0]" , "op": "[MR] REX.W 66 0F 7E /r"},
+ {"x64": "movq W:xmm[63:0], r64[63:0]/m64" , "op": "[RM] REX.W 66 0F 6E /r"},
+ {"any": "movq W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F3 0F 7E /r"},
+ {"any": "movq W:xmm[63:0]/m64, xmm[63:0]" , "op": "[MR] 66 0F D6 /r"},
+ {"any": "movsd w:xmm[63:0], xmm[63:0]" , "op": "[RM] F2 0F 10 /r"},
+ {"any": "movsd W:xmm[63:0], m64" , "op": "[RM] F2 0F 10 /r"},
+ {"any": "movsd W:m64, xmm[63:0]" , "op": "[MR] F2 0F 11 /r"},
+ {"any": "movupd W:xmm, xmm/m128" , "op": "[RM] 66 0F 10 /r"},
+ {"any": "movupd W:xmm/m128, xmm" , "op": "[MR] 66 0F 11 /r"},
+ {"any": "mulpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 59 /r"},
+ {"any": "mulsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 59 /r"},
+ {"any": "orpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 56 /r"},
+ {"any": "packssdw X:xmm, xmm/m128" , "op": "[RM] 66 0F 6B /r"},
+ {"any": "packsswb X:xmm, xmm/m128" , "op": "[RM] 66 0F 63 /r"},
+ {"any": "packuswb X:xmm, xmm/m128" , "op": "[RM] 66 0F 67 /r"},
+ {"any": "paddb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F FC /r"},
+ {"any": "paddd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F FE /r"},
+ {"any": "paddq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F D4 /r"},
+ {"any": "paddsb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EC /r"},
+ {"any": "paddsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F ED /r"},
+ {"any": "paddusb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DC /r"},
+ {"any": "paddusw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DD /r"},
+ {"any": "paddw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F FD /r"},
+ {"any": "pand X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DB /r"},
+ {"any": "pandn X:xmm, xmm/m128" , "op": "[RM] 66 0F DF /r"},
+ {"any": "pavgb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E0 /r"},
+ {"any": "pavgw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E3 /r"},
+ {"any": "pcmpeqb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 74 /r"},
+ {"any": "pcmpeqd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 76 /r"},
+ {"any": "pcmpeqw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 75 /r"},
+ {"any": "pcmpgtb X:xmm, xmm/m128" , "op": "[RM] 66 0F 64 /r"},
+ {"any": "pcmpgtd X:xmm, xmm/m128" , "op": "[RM] 66 0F 66 /r"},
+ {"any": "pcmpgtw X:xmm, xmm/m128" , "op": "[RM] 66 0F 65 /r"},
+ {"any": "pextrw W:r32[15:0], xmm, imm8" , "op": "[RM] 66 0F C5 /r ib"},
+ {"any": "pinsrw X:xmm, r32[15:0]/m16, imm8" , "op": "[RM] 66 0F C4 /r ib"},
+ {"any": "pmaddwd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F F5 /r"},
+ {"any": "pmaxsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EE /r"},
+ {"any": "pmaxub X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DE /r"},
+ {"any": "pminsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EA /r"},
+ {"any": "pminub X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DA /r"},
+ {"any": "pmovmskb W:r32[15:0], xmm" , "op": "[RM] 66 0F D7 /r"},
+ {"any": "pmulhuw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E4 /r"},
+ {"any": "pmulhw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E5 /r"},
+ {"any": "pmullw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F D5 /r"},
+ {"any": "pmuludq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F F4 /r"},
+ {"any": "por X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EB /r"},
+ {"any": "psadbw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F F6 /r"},
+ {"any": "pshufd W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 70 /r ib"},
+ {"any": "pshufhw W:xmm, xmm/m128, imm8" , "op": "[RM] F3 0F 70 /r ib"},
+ {"any": "pshuflw W:xmm, xmm/m128, imm8" , "op": "[RM] F2 0F 70 /r ib"},
+ {"any": "pslld X:xmm, xmm/m128" , "op": "[RM] 66 0F F2 /r"},
+ {"any": "pslld X:xmm, imm8" , "op": "[M ] 66 0F 72 /6 ib"},
+ {"any": "pslldq X:xmm, imm8" , "op": "[M ] 66 0F 73 /7 ib"},
+ {"any": "psllq X:xmm, xmm/m128" , "op": "[RM] 66 0F F3 /r"},
+ {"any": "psllq X:xmm, imm8" , "op": "[M ] 66 0F 73 /6 ib"},
+ {"any": "psllw X:xmm, xmm/m128" , "op": "[RM] 66 0F F1 /r"},
+ {"any": "psllw X:xmm, imm8" , "op": "[M ] 66 0F 71 /6 ib"},
+ {"any": "psrad X:xmm, xmm/m128" , "op": "[RM] 66 0F E2 /r"},
+ {"any": "psrad X:xmm, imm8" , "op": "[M ] 66 0F 72 /4 ib"},
+ {"any": "psraw X:xmm, xmm/m128" , "op": "[RM] 66 0F E1 /r"},
+ {"any": "psraw X:xmm, imm8" , "op": "[M ] 66 0F 71 /4 ib"},
+ {"any": "psrld X:xmm, xmm/m128" , "op": "[RM] 66 0F D2 /r"},
+ {"any": "psrld X:xmm, imm8" , "op": "[M ] 66 0F 72 /2 ib"},
+ {"any": "psrldq X:xmm, imm8" , "op": "[M ] 66 0F 73 /3 ib"},
+ {"any": "psrlq X:xmm, xmm/m128" , "op": "[RM] 66 0F D3 /r"},
+ {"any": "psrlq X:xmm, imm8" , "op": "[M ] 66 0F 73 /2 ib"},
+ {"any": "psrlw X:xmm, imm8" , "op": "[M ] 66 0F 71 /2 ib"},
+ {"any": "psrlw X:xmm, xmm/m128" , "op": "[RM] 66 0F D1 /r"},
+ {"any": "psubb X:xmm, xmm/m128" , "op": "[RM] 66 0F F8 /r"},
+ {"any": "psubd X:xmm, xmm/m128" , "op": "[RM] 66 0F FA /r"},
+ {"any": "psubq X:xmm, xmm/m128" , "op": "[RM] 66 0F FB /r"},
+ {"any": "psubsb X:xmm, xmm/m128" , "op": "[RM] 66 0F E8 /r"},
+ {"any": "psubsw X:xmm, xmm/m128" , "op": "[RM] 66 0F E9 /r"},
+ {"any": "psubusb X:xmm, xmm/m128" , "op": "[RM] 66 0F D8 /r"},
+ {"any": "psubusw X:xmm, xmm/m128" , "op": "[RM] 66 0F D9 /r"},
+ {"any": "psubw X:xmm, xmm/m128" , "op": "[RM] 66 0F F9 /r"},
+ {"any": "punpckhbw X:xmm, xmm/m128" , "op": "[RM] 66 0F 68 /r"},
+ {"any": "punpckhdq X:xmm, xmm/m128" , "op": "[RM] 66 0F 6A /r"},
+ {"any": "punpckhqdq X:xmm, xmm/m128" , "op": "[RM] 66 0F 6D /r"},
+ {"any": "punpckhwd X:xmm, xmm/m128" , "op": "[RM] 66 0F 69 /r"},
+ {"any": "punpcklbw X:xmm, xmm/m128" , "op": "[RM] 66 0F 60 /r"},
+ {"any": "punpckldq X:xmm, xmm/m128" , "op": "[RM] 66 0F 62 /r"},
+ {"any": "punpcklqdq X:xmm, xmm/m128" , "op": "[RM] 66 0F 6C /r"},
+ {"any": "punpcklwd X:xmm, xmm/m128" , "op": "[RM] 66 0F 61 /r"},
+ {"any": "pxor X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EF /r"},
+ {"any": "shufpd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F C6 /r ib"},
+ {"any": "sqrtpd W:xmm, xmm/m128" , "op": "[RM] 66 0F 51 /r"},
+ {"any": "sqrtsd w:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 51 /r"},
+ {"any": "subpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5C /r"},
+ {"any": "subsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5C /r"},
+ {"any": "ucomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] 66 0F 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "unpckhpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 15 /r"},
+ {"any": "unpcklpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 14 /r"},
+ {"any": "xorpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 57 /r"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSE3", "instructions": [
+ {"any": "addsubpd X:xmm, xmm/m128" , "op": "[RM] 66 0F D0 /r"},
+ {"any": "addsubps X:xmm, xmm/m128" , "op": "[RM] F2 0F D0 /r"},
+ {"any": "haddpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 7C /r"},
+ {"any": "haddps X:~xmm, ~xmm/m128" , "op": "[RM] F2 0F 7C /r"},
+ {"any": "hsubpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 7D /r"},
+ {"any": "hsubps X:xmm, xmm/m128" , "op": "[RM] F2 0F 7D /r"},
+ {"any": "lddqu W:xmm, m128" , "op": "[RM] F2 0F F0 /r"},
+ {"any": "movddup W:xmm, xmm[63:0]/m64" , "op": "[RM] F2 0F 12 /r"},
+ {"any": "movshdup W:xmm, xmm/m128" , "op": "[RM] F3 0F 16 /r"},
+ {"any": "movsldup W:xmm, xmm/m128" , "op": "[RM] F3 0F 12 /r"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSSE3", "instructions": [
+ {"any": "pabsb W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 1C /r"},
+ {"any": "pabsd W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 1E /r"},
+ {"any": "pabsw W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 1D /r"},
+ {"any": "palignr X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0F /r ib"},
+ {"any": "phaddd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 02 /r"},
+ {"any": "phaddsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 03 /r"},
+ {"any": "phaddw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 01 /r"},
+ {"any": "phsubd X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 06 /r"},
+ {"any": "phsubsw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 07 /r"},
+ {"any": "phsubw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 05 /r"},
+ {"any": "pmaddubsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 04 /r"},
+ {"any": "pmulhrsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 0B /r"},
+ {"any": "pshufb X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 00 /r"},
+ {"any": "psignb X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 08 /r"},
+ {"any": "psignd X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 0A /r"},
+ {"any": "psignw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 09 /r"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSE4_1", "instructions": [
+ {"any": "blendpd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0D /r ib"},
+ {"any": "blendps X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0C /r ib"},
+ {"any": "blendvpd X:xmm, xmm/m128, <xmm0>" , "op": "[RM] 66 0F 38 15 /r"},
+ {"any": "blendvps X:xmm, xmm/m128, <xmm0>" , "op": "[RM] 66 0F 38 14 /r"},
+ {"any": "dppd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 41 /r ib"},
+ {"any": "dpps X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 40 /r ib"},
+ {"any": "extractps W:r32/m32, xmm, imm8" , "op": "[MR] 66 0F 3A 17 /r ib"},
+ {"any": "insertps X:xmm, xmm[31:0]/m32, imm8" , "op": "[RM] 66 0F 3A 21 /r ib"},
+ {"any": "movntdqa W:xmm, m128" , "op": "[RM] 66 0F 38 2A /r"},
+ {"any": "mpsadbw X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 42 /r ib"},
+ {"any": "packusdw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 2B /r"},
+ {"any": "pblendvb X:xmm, xmm/m128, <xmm0>" , "op": "[RM] 66 0F 38 10 /r"},
+ {"any": "pblendw X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0E /r ib"},
+ {"any": "pcmpeqq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 29 /r"},
+ {"any": "pextrb W:r32[7:0]/m8, xmm, imm8" , "op": "[MR] 66 0F 3A 14 /r ib"},
+ {"any": "pextrd W:r32[31:0]/m32, xmm, imm8" , "op": "[MR] 66 0F 3A 16 /r ib"},
+ {"any": "pextrq W:r64/m64, xmm, imm8" , "op": "[MR] REX.W 66 0F 3A 16 /r ib"},
+ {"any": "pextrw W:r32[15:0]/m16, xmm, imm8" , "op": "[MR] 66 0F 3A 15 /r ib"},
+ {"any": "phminposuw W:xmm[18:0], xmm/m128" , "op": "[RM] 66 0F 38 41 /r"},
+ {"any": "pinsrb X:xmm, r32[7:0]/m8, imm8" , "op": "[RM] 66 0F 3A 20 /r ib"},
+ {"any": "pinsrd X:xmm, r32[31:0]/m32, imm8" , "op": "[RM] 66 0F 3A 22 /r ib"},
+ {"any": "pinsrq X:xmm, r64/m64, imm8" , "op": "[RM] REX.W 66 0F 3A 22 /r ib"},
+ {"any": "pmaxsb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3C /r"},
+ {"any": "pmaxsd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3D /r"},
+ {"any": "pmaxud X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3F /r"},
+ {"any": "pmaxuw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3E /r"},
+ {"any": "pminsb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 38 /r"},
+ {"any": "pminsd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 39 /r"},
+ {"any": "pminud X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3B /r"},
+ {"any": "pminuw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3A /r"},
+ {"any": "pmovsxbd W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 21 /r"},
+ {"any": "pmovsxbq W:xmm, xmm[15:0]/m16" , "op": "[RM] 66 0F 38 22 /r"},
+ {"any": "pmovsxbw W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 20 /r"},
+ {"any": "pmovsxdq W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 25 /r"},
+ {"any": "pmovsxwd W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 23 /r"},
+ {"any": "pmovsxwq W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 24 /r"},
+ {"any": "pmovzxbd W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 31 /r"},
+ {"any": "pmovzxbq W:xmm, xmm[15:0]/m16" , "op": "[RM] 66 0F 38 32 /r"},
+ {"any": "pmovzxbw W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 30 /r"},
+ {"any": "pmovzxdq W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 35 /r"},
+ {"any": "pmovzxwd W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 33 /r"},
+ {"any": "pmovzxwq W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 34 /r"},
+ {"any": "pmuldq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 28 /r"},
+ {"any": "pmulld X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 40 /r"},
+ {"any": "ptest R:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "roundpd W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 09 /r ib"},
+ {"any": "roundps W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 08 /r ib"},
+ {"any": "roundsd w:xmm[63:0], xmm[63:0]/m64, imm8" , "op": "[RM] 66 0F 3A 0B /r ib"},
+ {"any": "roundss w:xmm[31:0], xmm[31:0]/m32, imm8" , "op": "[RM] 66 0F 3A 0A /r ib"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSE4_2", "instructions": [
+ {"any": "pcmpestri R:xmm, xmm/m128, imm8, W:<ecx>, <eax>, <edx>" , "op": "[RM] 66 0F 3A 61 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "pcmpestrm R:xmm, xmm/m128, imm8, W:<xmm0>, <eax>, <edx>" , "op": "[RM] 66 0F 3A 60 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "pcmpgtq X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 37 /r"},
+ {"any": "pcmpistri R:xmm, xmm/m128, imm8, W:<ecx>" , "op": "[RM] 66 0F 3A 63 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "pcmpistrm R:xmm, xmm/m128, imm8, W:<xmm0>" , "op": "[RM] 66 0F 3A 62 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "SSE4A", "instructions": [
+ {"any": "extrq X:xmm, imm8, imm8" , "op": "[R ] 66 0F 78 /0 ib ib"},
+ {"any": "extrq X:xmm, xmm" , "op": "[RM] 66 0F 79 /r"},
+ {"any": "insertq X:xmm, xmm" , "op": "[RM] F2 0F 79 /r"},
+ {"any": "insertq X:xmm, xmm, imm8, imm8" , "op": "[RM] F2 0F 78 /r ib ib"},
+ {"any": "movntsd W:m64, xmm[63:0]" , "op": "[RM] F2 0F 2B /r"},
+ {"any": "movntss W:m32, xmm[31:0]" , "op": "[RM] F3 0F 2B /r"}
+ ]},
+
+ {"category": "SSE SIMD CRYPTO_HASH", "ext": "KL", "instructions": [
+ {"any": "loadiwkey R:xmm, R:xmm, R:<eax>, R:<xmm0>" , "op": "[RM] F3 0F 38 DC 11:rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+ ]},
+
+ {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESKLE", "instructions": [
+ {"any": "aesdec128kl X:xmm, R:m384" , "op": "[RM] F3 0F 38 DD !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"any": "aesdec256kl X:xmm, R:m512" , "op": "[RM] F3 0F 38 DF !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"any": "aesenc128kl X:xmm, R:m384" , "op": "[RM] F3 0F 38 DC !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"any": "aesenc256kl X:xmm, R:m512" , "op": "[RM] F3 0F 38 DE !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"___": "encodekey128 W:r32, R:r32, X:<xmm0>, W:<xmm1-6>" , "op": "[RM] F3 0F 38 FA 11:rrr:bbb" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=0"},
+ {"___": "encodekey256 W:r32, R:r32, X:<xmm0-1>, W:<xmm2-6>" , "op": "[RM] F3 0F 38 FB 11:rrr:bbb" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=0"}
+ ]},
+
+ {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESKLEWIDE_KL", "instructions": [
+ {"___": "aesdecwide128kl R:m384, X:<xmm0-7>" , "op": "[RM] F3 0F 38 D8 !(11):001:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"___": "aesdecwide256kl R:m512, X:<xmm0-7>" , "op": "[RM] F3 0F 38 D8 !(11):011:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"___": "aesencwide128kl R:m384, X:<xmm0-7>" , "op": "[RM] F3 0F 38 D8 !(11):000:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"},
+ {"___": "aesencwide256kl R:m512, X:<xmm0-7>" , "op": "[RM] F3 0F 38 D8 !(11):010:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}
+ ]},
+
+ {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESNI", "instructions": [
+ {"any": "aesdec X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DE /r"},
+ {"any": "aesdeclast X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DF /r"},
+ {"any": "aesenc X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DC /r"},
+ {"any": "aesenclast X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DD /r"},
+ {"any": "aesimc W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DB /r"},
+ {"any": "aeskeygenassist W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A DF /r ib"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "GFNI", "instructions": [
+ {"any": "gf2p8affineinvqb X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A CF /r ib"},
+ {"any": "gf2p8affineqb X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A CE /r ib"},
+ {"any": "gf2p8mulb X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 CF /r"}
+ ]},
+
+ {"category": "SSE SIMD", "ext": "PCLMULQDQ", "instructions": [
+ {"any": "pclmulqdq X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 44 /r ib"}
+ ]},
+
+ {"category": "SSE SIMD CRYPTO_HASH", "ext": "SHA", "instructions": [
+ {"any": "sha1msg1 xmm, xmm/m128" , "op": "[RM] NP 0F 38 C9 /r"},
+ {"any": "sha1msg2 xmm, xmm/m128" , "op": "[RM] NP 0F 38 CA /r"},
+ {"any": "sha1nexte xmm, xmm/m128" , "op": "[RM] NP 0F 38 C8 /r"},
+ {"any": "sha1rnds4 xmm, xmm/m128, imm8" , "op": "[RM] NP 0F 3A CC /r ib"},
+ {"any": "sha256msg1 xmm, xmm/m128" , "op": "[RM] NP 0F 38 CC /r"},
+ {"any": "sha256msg2 xmm, xmm/m128" , "op": "[RM] NP 0F 38 CD /r"},
+ {"any": "sha256rnds2 xmm, xmm/m128, <xmm0>" , "op": "[RM] NP 0F 38 CB /r"}
+ ]},
+
+ {"category": "AVX STATE", "ext": "AVX", "instructions": [
+ {"any": "vldmxcsr R:m32" , "op": "[M ] VEX.LZ.NP.0F.WIG AE /2", "io": "MXCSR=W"},
+ {"any": "vstmxcsr W:m32" , "op": "[M ] VEX.LZ.NP.0F.WIG AE /3", "io": "MXCSR=R"},
+ {"any": "vzeroall" , "op": "[OP ] VEX.256.NP.0F.WIG 77", "volatile": true},
+ {"any": "vzeroupper" , "op": "[OP ] VEX.128.NP.0F.WIG 77", "volatile": true}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX", "instructions": [
+ {"any": "vaddpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 58 /r"},
+ {"any": "vaddps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 58 /r"},
+ {"any": "vaddsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 58 /r"},
+ {"any": "vaddss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 58 /r"},
+ {"any": "vaddsubpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG D0 /r"},
+ {"any": "vaddsubps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F.WIG D0 /r"},
+ {"any": "vandnpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 55 /r"},
+ {"any": "vandnps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 55 /r"},
+ {"any": "vandpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 54 /r"},
+ {"any": "vandps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 54 /r"},
+ {"any": "vblendpd W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.WIG 0D /r ib"},
+ {"any": "vblendps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.WIG 0C /r ib"},
+ {"any": "vblendvpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS]VEX.Lxy.66.0F3A.W0 4B /r /is4"},
+ {"any": "vblendvps W:xy, xy, xy/mxy, xy" , "op": "[RVMS]VEX.Lxy.66.0F3A.W0 4A /r /is4"},
+ {"any": "vbroadcastf128 W:ymm, m128" , "op": "[RM ] VEX.256.66.0F38.W0 1A /r"},
+ {"any": "vbroadcastsd W:ymm, m64" , "op": "[RM ] VEX.256.66.0F38.W0 19 /r"},
+ {"any": "vbroadcastss W:xy, m32" , "op": "[RM ] VEX.Lxy.66.0F38.W0 18 /r"},
+ {"any": "vcmppd W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F.WIG C2 /r ib"},
+ {"any": "vcmpps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.NP.0F.WIG C2 /r ib"},
+ {"any": "vcmpsd W:xmm, xmm, xmm[63:0]/m64, imm8" , "op": "[RVM] VEX.LIG.F2.0F.WIG C2 /r ib"},
+ {"any": "vcmpss W:xmm, xmm, xmm[31:0]/m32, imm8" , "op": "[RVM] VEX.LIG.F3.0F.WIG C2 /r ib"},
+ {"any": "vcomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.66.0F.WIG 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.NP.0F.WIG 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcvtdq2pd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.F3.0F.WIG E6 /r"},
+ {"any": "vcvtdq2pd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.F3.0F.WIG E6 /r"},
+ {"any": "vcvtdq2ps W:xmm, xmm/m128" , "op": "[RM ] VEX.128.NP.0F.WIG 5B /r"},
+ {"any": "vcvtdq2ps W:ymm, ymm/m256" , "op": "[RM ] VEX.256.NP.0F.WIG 5B /r"},
+ {"any": "vcvtpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.F2.0F.WIG E6 /r"},
+ {"any": "vcvtpd2dq W:xmm, ymm/m256" , "op": "[RM ] VEX.256.F2.0F.WIG E6 /r"},
+ {"any": "vcvtpd2ps W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.66.0F.WIG 5A /r"},
+ {"any": "vcvtpd2ps W:xmm, ymm/m256" , "op": "[RM ] VEX.256.66.0F.WIG 5A /r"},
+ {"any": "vcvtps2dq W:xmm, xmm/m128" , "op": "[RM ] VEX.128.66.0F.WIG 5B /r"},
+ {"any": "vcvtps2dq W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F.WIG 5B /r"},
+ {"any": "vcvtps2pd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.NP.0F.WIG 5A /r"},
+ {"any": "vcvtps2pd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.NP.0F.WIG 5A /r"},
+ {"any": "vcvtsd2si W:ry, xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.F2.0F.Wy 2D /r"},
+ {"any": "vcvtsd2ss W:xmm, xmm[127:32], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5A /r"},
+ {"any": "vcvtsi2sd W:xmm, xmm[127:64], ry/my" , "op": "[RVM] VEX.LIG.F2.0F.Wy 2A /r"},
+ {"any": "vcvtsi2ss W:xmm, xmm[127:32], ry/my" , "op": "[RVM] VEX.LIG.F3.0F.Wy 2A /r"},
+ {"any": "vcvtss2sd W:xmm, xmm[127:64], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5A /r"},
+ {"any": "vcvtss2si W:ry, xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.F3.0F.Wy 2D /r"},
+ {"any": "vcvttpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.66.0F.WIG E6 /r"},
+ {"any": "vcvttpd2dq W:xmm, ymm/m256" , "op": "[RM ] VEX.256.66.0F.WIG E6 /r"},
+ {"any": "vcvttps2dq W:xmm, xmm/m128" , "op": "[RM ] VEX.128.F3.0F.WIG 5B /r"},
+ {"any": "vcvttps2dq W:ymm, ymm/m256" , "op": "[RM ] VEX.256.F3.0F.WIG 5B /r"},
+ {"any": "vcvttsd2si W:ry, xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.F2.0F.Wy 2C /r"},
+ {"any": "vcvttss2si W:ry, xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.F3.0F.Wy 2C /r"},
+ {"any": "vdivpd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 5E /r"},
+ {"any": "vdivpd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 5E /r"},
+ {"any": "vdivps W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.NP.0F.WIG 5E /r"},
+ {"any": "vdivps W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.NP.0F.WIG 5E /r"},
+ {"any": "vdivsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5E /r"},
+ {"any": "vdivss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5E /r"},
+ {"any": "vdppd W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 41 /r ib"},
+ {"any": "vdpps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.WIG 40 /r ib"},
+ {"any": "vextractps W:r32[31:0]/m32, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.WIG 17 /r ib"},
+ {"any": "vextractf128 W:xmm/m128, ymm, imm8" , "op": "[MR ] VEX.256.66.0F3A.W0 19 /r ib"},
+ {"any": "vhaddpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 7C /r"},
+ {"any": "vhaddps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F.WIG 7C /r"},
+ {"any": "vhsubpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 7D /r"},
+ {"any": "vhsubps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F.WIG 7D /r"},
+ {"any": "vinsertf128 W:ymm, ymm, xmm/m128, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 18 /r ib"},
+ {"any": "vinsertps W:xmm, xmm, xmm[31:0]/m32, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 21 /r ib"},
+ {"any": "vlddqu W:xy, mxy" , "op": "[RM ] VEX.Lxy.F2.0F.WIG F0 /r"},
+ {"any": "vmaskmovdqu R:xmm, xmm, X:<m128(ds:zdi)>" , "op": "[RM ] VEX.128.66.0F.WIG F7 /r"},
+ {"any": "vmaskmovpd X:mxy, xy, xy" , "op": "[MVR] VEX.Lxy.66.0F38.W0 2F /r"},
+ {"any": "vmaskmovpd W:xy, xy, mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 2D /r"},
+ {"any": "vmaskmovps X:mxy, xy, xy" , "op": "[MVR] VEX.Lxy.66.0F38.W0 2E /r"},
+ {"any": "vmaskmovps W:xy, xy, mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 2C /r"},
+ {"any": "vmaxpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 5F /r"},
+ {"any": "vmaxps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 5F /r"},
+ {"any": "vmaxsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5F /r"},
+ {"any": "vmaxss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5F /r"},
+ {"any": "vminpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 5D /r"},
+ {"any": "vminps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 5D /r"},
+ {"any": "vminsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5D /r"},
+ {"any": "vminss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5D /r"},
+ {"any": "vmovapd W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 28 /r"},
+ {"any": "vmovapd W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 29 /r"},
+ {"any": "vmovaps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 28 /r"},
+ {"any": "vmovaps W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.NP.0F.WIG 29 /r"},
+ {"any": "vmovd W:r32[31:0]/m32, xmm[31:0]" , "op": "[MR ] VEX.128.66.0F.W0 7E /r"},
+ {"any": "vmovd W:xmm[31:0], r32[31:0]/m32" , "op": "[RM ] VEX.128.66.0F.W0 6E /r"},
+ {"any": "vmovddup W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.F2.0F.WIG 12 /r"},
+ {"any": "vmovddup W:ymm, ymm/m256" , "op": "[RM ] VEX.256.F2.0F.WIG 12 /r"},
+ {"any": "vmovdqa W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 6F /r"},
+ {"any": "vmovdqa W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 7F /r"},
+ {"any": "vmovdqu W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.F3.0F.WIG 6F /r"},
+ {"any": "vmovdqu W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.F3.0F.WIG 7F /r"},
+ {"any": "vmovhlps W:xmm, xmm[127:64], xmm[127:64]" , "op": "[RVM] VEX.128.NP.0F.WIG 12 /r"},
+ {"any": "vmovhpd W:m64, xmm[127:64]" , "op": "[MR ] VEX.128.66.0F.WIG 17 /r"},
+ {"any": "vmovhpd W:xmm, xmm[63:0], m64" , "op": "[RVM] VEX.128.66.0F.WIG 16 /r"},
+ {"any": "vmovhps W:m64, xmm[127:64]" , "op": "[MR ] VEX.128.NP.0F.WIG 17 /r"},
+ {"any": "vmovhps W:xmm, xmm[63:0], m64" , "op": "[RVM] VEX.128.NP.0F.WIG 16 /r"},
+ {"any": "vmovlhps W:xmm, xmm[63:0], xmm[63:0]" , "op": "[RVM] VEX.128.NP.0F.WIG 16 /r"},
+ {"any": "vmovlpd W:m64, xmm[63:0]" , "op": "[MR ] VEX.128.66.0F.WIG 13 /r"},
+ {"any": "vmovlpd W:xmm, xmm[127:64], m64" , "op": "[RVM] VEX.128.66.0F.WIG 12 /r"},
+ {"any": "vmovlps W:m64, xmm[63:0]" , "op": "[MR ] VEX.128.NP.0F.WIG 13 /r"},
+ {"any": "vmovlps W:xmm, xmm[127:64], m64" , "op": "[RVM] VEX.128.NP.0F.WIG 12 /r"},
+ {"any": "vmovmskpd W:r32[1:0], xmm" , "op": "[RM ] VEX.128.66.0F.WIG 50 /r"},
+ {"any": "vmovmskpd W:r32[3:0], ymm" , "op": "[RM ] VEX.256.66.0F.WIG 50 /r"},
+ {"any": "vmovmskps W:r32[3:0], xmm" , "op": "[RM ] VEX.128.NP.0F.WIG 50 /r"},
+ {"any": "vmovmskps W:r32[7:0], ymm" , "op": "[RM ] VEX.256.NP.0F.WIG 50 /r"},
+ {"any": "vmovntdq W:mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG E7 /r"},
+ {"any": "vmovntdqa W:xmm, m128" , "op": "[RM ] VEX.128.66.0F38.WIG 2A /r"},
+ {"any": "vmovntpd W:mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 2B /r"},
+ {"any": "vmovntps W:mxy, xy" , "op": "[MR ] VEX.Lxy.NP.0F.WIG 2B /r"},
+ {"any": "vmovq W:r64/m64, xmm[63:0]" , "op": "[MR ] VEX.128.66.0F.W1 7E /r"},
+ {"any": "vmovq W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] VEX.128.F3.0F.WIG 7E /r"},
+ {"any": "vmovq W:xmm[63:0], r64/m64" , "op": "[RM ] VEX.128.66.0F.W1 6E /r"},
+ {"any": "vmovq W:xmm[63:0]/m64, xmm[63:0]" , "op": "[MR ] VEX.128.66.0F.WIG D6 /r"},
+ {"any": "vmovsd W:m64, xmm[63:0]" , "op": "[MR ] VEX.LIG.F2.0F.WIG 11 /r"},
+ {"any": "vmovsd W:xmm[63:0], m64" , "op": "[RM ] VEX.LIG.F2.0F.WIG 10 /r"},
+ {"any": "vmovsd W:xmm, xmm[127:64], xmm[63:0]" , "op": "[MVR] VEX.LIG.F2.0F.WIG 11 /r"},
+ {"any": "vmovsd W:xmm, xmm[127:64], xmm[63:0]" , "op": "[RVM] VEX.LIG.F2.0F.WIG 10 /r"},
+ {"any": "vmovshdup W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.F3.0F.WIG 16 /r"},
+ {"any": "vmovsldup W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.F3.0F.WIG 12 /r"},
+ {"any": "vmovss W:m32, xmm[31:0]" , "op": "[MR ] VEX.LIG.F3.0F.WIG 11 /r"},
+ {"any": "vmovss W:xmm[31:0], m32" , "op": "[RM ] VEX.LIG.F3.0F.WIG 10 /r"},
+ {"any": "vmovss W:xmm, xmm[127:32], xmm[31:0]" , "op": "[MVR] VEX.LIG.F3.0F.WIG 11 /r"},
+ {"any": "vmovss W:xmm, xmm[127:32], xmm[31:0]" , "op": "[RVM] VEX.LIG.F3.0F.WIG 10 /r"},
+ {"any": "vmovupd W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 10 /r"},
+ {"any": "vmovupd W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.NP.0F.WIG 11 /r"},
+ {"any": "vmovups W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 10 /r"},
+ {"any": "vmovups W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 11 /r"},
+ {"any": "vmpsadbw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 42 /r ib"},
+ {"any": "vmulpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 59 /r"},
+ {"any": "vmulps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 59 /r"},
+ {"any": "vmulsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 59 /r"},
+ {"any": "vmulss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 59 /r"},
+ {"any": "vorpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 56 /r"},
+ {"any": "vorps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 56 /r"},
+ {"any": "vpabsb W:xmm, xmm/m128" , "op": "[RM ] VEX.128.66.0F38.WIG 1C /r"},
+ {"any": "vpabsd W:xmm, xmm/m128" , "op": "[RM_] VEX.128.66.0F38.WIG 1E /r"},
+ {"any": "vpabsw W:xmm, xmm/m128" , "op": "[RM ] VEX.128.66.0F38.WIG 1D /r"},
+ {"any": "vpackssdw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6B /r"},
+ {"any": "vpacksswb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 63 /r"},
+ {"any": "vpackusdw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 2B /r"},
+ {"any": "vpackuswb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 67 /r"},
+ {"any": "vpaddb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FC /r"},
+ {"any": "vpaddd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FE /r"},
+ {"any": "vpaddq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D4 /r"},
+ {"any": "vpaddsb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EC /r"},
+ {"any": "vpaddsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG ED /r"},
+ {"any": "vpaddusb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DC /r"},
+ {"any": "vpaddusw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DD /r"},
+ {"any": "vpaddw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FD /r"},
+ {"any": "vpalignr W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 0F /r ib"},
+ {"any": "vpand W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DB /r"},
+ {"any": "vpandn W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DF /r"},
+ {"any": "vpavgb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E0 /r"},
+ {"any": "vpavgw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E3 /r"},
+ {"any": "vpblendvb W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]VEX.128.66.0F3A.W0 4C /r /is4"},
+ {"any": "vpblendw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 0E /r ib"},
+ {"any": "vpcmpeqb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 74 /r"},
+ {"any": "vpcmpeqd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 76 /r"},
+ {"any": "vpcmpeqq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 29 /r"},
+ {"any": "vpcmpeqw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 75 /r"},
+ {"any": "vpcmpestri R:xmm, xmm/m128, imm8, W:<ecx>, <eax>, <edx>" , "op": "[RM ] VEX.128.66.0F3A.WIG 61 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vpcmpestrm R:xmm, xmm/m128, imm8, W:<xmm0>, <eax>, <edx>" , "op": "[RM ] VEX.128.66.0F3A.WIG 60 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vpcmpgtb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 64 /r"},
+ {"any": "vpcmpgtd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 66 /r"},
+ {"any": "vpcmpgtq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 37 /r"},
+ {"any": "vpcmpgtw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 65 /r"},
+ {"any": "vpcmpistri R:xmm, xmm/m128, imm8, W:<ecx>" , "op": "[RM ] VEX.128.66.0F3A.WIG 63 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vpcmpistrm R:xmm, xmm/m128, imm8, W:<xmm0>" , "op": "[RM ] VEX.128.66.0F3A.WIG 62 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vperm2f128 W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 06 /r ib"},
+ {"any": "vpermilpd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 0D /r"},
+ {"any": "vpermilpd W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.66.0F3A.W0 05 /r ib"},
+ {"any": "vpermilpd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 0D /r"},
+ {"any": "vpermilpd W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W0 05 /r ib"},
+ {"any": "vpermilps W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 0C /r"},
+ {"any": "vpermilps W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.66.0F3A.W0 04 /r ib"},
+ {"any": "vpermilps W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 0C /r"},
+ {"any": "vpermilps W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W0 04 /r ib"},
+ {"any": "vpextrb W:r32[7:0]/m8, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 14 /r ib"},
+ {"any": "vpextrd W:r32/m32, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 16 /r ib"},
+ {"any": "vpextrq W:r64/m64, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W1 16 /r ib"},
+ {"any": "vpextrw W:r32[15:0], xmm, imm8" , "op": "[RM ] VEX.128.66.0F.W0 C5 /r ib"},
+ {"any": "vpextrw W:r32[15:0]/m16, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 15 /r ib"},
+ {"any": "vphaddd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 02 /r"},
+ {"any": "vphaddsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 03 /r"},
+ {"any": "vphaddw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 01 /r"},
+ {"any": "vphminposuw W:xmm[18:0], xmm/m128" , "op": "[RM ] VEX.128.66.0F38.WIG 41 /r"},
+ {"any": "vphsubd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 06 /r"},
+ {"any": "vphsubsw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 07 /r"},
+ {"any": "vphsubw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 05 /r"},
+ {"any": "vpinsrb W:xmm, xmm, r32[7:0]/m8, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 20 /r ib"},
+ {"any": "vpinsrd W:xmm, xmm, r32/m32, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 22 /r ib"},
+ {"any": "vpinsrq W:xmm, xmm, r64/m64, imm8" , "op": "[RVM] VEX.128.66.0F3A.W1 22 /r ib"},
+ {"any": "vpinsrw W:xmm, xmm, r32[15:0]/m16, imm8" , "op": "[RVM] VEX.128.66.0F.W0 C4 /r ib"},
+ {"any": "vpmaddubsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 04 /r"},
+ {"any": "vpmaddwd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F5 /r"},
+ {"any": "vpmaxsb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3C /r"},
+ {"any": "vpmaxsd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3D /r"},
+ {"any": "vpmaxsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EE /r"},
+ {"any": "vpmaxub W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DE /r"},
+ {"any": "vpmaxud W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3F /r"},
+ {"any": "vpmaxuw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3E /r"},
+ {"any": "vpminsb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 38 /r"},
+ {"any": "vpminsd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 39 /r"},
+ {"any": "vpminsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EA /r"},
+ {"any": "vpminub W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DA /r"},
+ {"any": "vpminud W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3B /r"},
+ {"any": "vpminuw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3A /r"},
+ {"any": "vpmovmskb W:r32[15:0], xmm" , "op": "[RVM] VEX.128.66.0F.WIG D7 /r"},
+ {"any": "vpmovsxwq W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 24 /r"},
+ {"any": "vpmovsxbd W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 21 /r"},
+ {"any": "vpmovsxbq W:xmm, xmm[15:0]/m16" , "op": "[RM ] VEX.128.66.0F38.WIG 22 /r"},
+ {"any": "vpmovsxbw W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 20 /r"},
+ {"any": "vpmovsxdq W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 25 /r"},
+ {"any": "vpmovsxwd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 23 /r"},
+ {"any": "vpmovzxbd W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 31 /r"},
+ {"any": "vpmovzxbq W:xmm, xmm[15:0]/m16" , "op": "[RM ] VEX.128.66.0F38.WIG 32 /r"},
+ {"any": "vpmovzxbw W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 30 /r"},
+ {"any": "vpmovzxdq W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 35 /r"},
+ {"any": "vpmovzxwd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 33 /r"},
+ {"any": "vpmovzxwq W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 34 /r"},
+ {"any": "vpmuldq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 28 /r"},
+ {"any": "vpmulhrsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 0B /r"},
+ {"any": "vpmulhuw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E4 /r"},
+ {"any": "vpmulhw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E5 /r"},
+ {"any": "vpmulld W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 40 /r"},
+ {"any": "vpmullw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D5 /r"},
+ {"any": "vpmuludq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F4 /r"},
+ {"any": "vpor W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EB /r"},
+ {"any": "vpsadbw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F6 /r"},
+ {"any": "vpshufb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 00 /r"},
+ {"any": "vpshufd W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.66.0F.WIG 70 /r ib"},
+ {"any": "vpshufhw W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.F3.0F.WIG 70 /r ib"},
+ {"any": "vpshuflw W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.F2.0F.WIG 70 /r ib"},
+ {"any": "vpsignb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 08 /r"},
+ {"any": "vpsignd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 0A /r"},
+ {"any": "vpsignw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 09 /r"},
+ {"any": "vpslld W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F2 /r"},
+ {"any": "vpslld W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 72 /6 ib"},
+ {"any": "vpslldq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /7 ib"},
+ {"any": "vpsllq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F3 /r"},
+ {"any": "vpsllq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /6 ib"},
+ {"any": "vpsllw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F1 /r"},
+ {"any": "vpsllw W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 71 /6 ib"},
+ {"any": "vpsrad W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E2 /r"},
+ {"any": "vpsrad W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 72 /4 ib"},
+ {"any": "vpsraw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E1 /r"},
+ {"any": "vpsraw W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 71 /4 ib"},
+ {"any": "vpsrld W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D2 /r"},
+ {"any": "vpsrld W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 72 /2 ib"},
+ {"any": "vpsrldq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /3 ib"},
+ {"any": "vpsrlq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D3 /r"},
+ {"any": "vpsrlq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /2 ib"},
+ {"any": "vpsrlw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D1 /r"},
+ {"any": "vpsrlw W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 71 /2 ib"},
+ {"any": "vpsubb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F8 /r"},
+ {"any": "vpsubd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FA /r"},
+ {"any": "vpsubq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FB /r"},
+ {"any": "vpsubsb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E8 /r"},
+ {"any": "vpsubsw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E9 /r"},
+ {"any": "vpsubusb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D8 /r"},
+ {"any": "vpsubusw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D9 /r"},
+ {"any": "vpsubw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F9 /r"},
+ {"any": "vptest R:~xy, ~xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F38.WIG 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vpunpckhbw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 68 /r"},
+ {"any": "vpunpckhdq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6A /r"},
+ {"any": "vpunpckhqdq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6D /r"},
+ {"any": "vpunpckhwd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 69 /r"},
+ {"any": "vpunpcklbw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 60 /r"},
+ {"any": "vpunpckldq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 62 /r"},
+ {"any": "vpunpcklqdq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6C /r"},
+ {"any": "vpunpcklwd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 61 /r"},
+ {"any": "vpxor W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EF /r"},
+ {"any": "vrcpps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 53 /r"},
+ {"any": "vrcpss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 53 /r"},
+ {"any": "vroundpd W:xy, xy/mxy, imm8" , "op": "[RM ] VEX.Lxy.66.0F3A.WIG 09 /r ib"},
+ {"any": "vroundps W:xy, xy/mxy, imm8" , "op": "[RM ] VEX.Lxy.66.0F3A.WIG 08 /r ib"},
+ {"any": "vroundsd W:xmm, xmm[127:64], xmm[63:0]/m64, imm8" , "op": "[RVM] VEX.LIG.66.0F3A.WIG 0B /r ib"},
+ {"any": "vroundss W:xmm, xmm[127:32], xmm[31:0]/m32, imm8" , "op": "[RVM] VEX.LIG.66.0F3A.WIG 0A /r ib"},
+ {"any": "vrsqrtps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 52 /r"},
+ {"any": "vrsqrtss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 52 /r"},
+ {"any": "vshufpd W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F.WIG C6 /r ib"},
+ {"any": "vshufps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.NP.0F.WIG C6 /r ib"},
+ {"any": "vsqrtpd W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 51 /r"},
+ {"any": "vsqrtps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 51 /r"},
+ {"any": "vsqrtsd W:xmm, xmm[127:64], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 51 /r"},
+ {"any": "vsqrtss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 51 /r"},
+ {"any": "vsubpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 5C /r"},
+ {"any": "vsubps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 5C /r"},
+ {"any": "vsubsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5C /r"},
+ {"any": "vsubss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5C /r"},
+ {"any": "vtestpd R:~xy, ~xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F38.W0 0F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vtestps R:~xy, ~xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F38.W0 0E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "vucomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.66.0F.WIG 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vucomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.NP.0F.WIG 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vunpckhpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 15 /r"},
+ {"any": "vunpckhps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 15 /r"},
+ {"any": "vunpcklpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 14 /r"},
+ {"any": "vunpcklps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 14 /r"},
+ {"any": "vxorpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 57 /r"},
+ {"any": "vxorps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 57 /r"}
+ ]},
+
+ {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX AESNI", "instructions": [
+ {"any": "vaesdec W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DE /r"},
+ {"any": "vaesdeclast W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DF /r"},
+ {"any": "vaesenc W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DC /r"},
+ {"any": "vaesenclast W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DD /r"},
+ {"any": "vaesimc W:xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DB /r"},
+ {"any": "vaeskeygenassist W:xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG DF /r ib"}
+ ]},
+
+ {"category": "AVX SIMD CRYPTO_HASH", "ext": "VAES", "instructions": [
+ {"any": "vaesdec W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DE /r"},
+ {"any": "vaesdeclast W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DF /r"},
+ {"any": "vaesenc W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DC /r"},
+ {"any": "vaesenclast W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DD /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX GFNI", "instructions": [
+ {"any": "vgf2p8affineinvqb W:xy, R:xy, R:xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.W1 CF /r ib"},
+ {"any": "vgf2p8affineqb W:xy, R:xy, R:xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.W1 CE /r ib"},
+ {"any": "vgf2p8mulb W:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 CF /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX2", "instructions": [
+ {"any": "vbroadcasti128 W:ymm, m128" , "op": "[RM ] VEX.256.66.0F38.W0 5A /r"},
+ {"any": "vbroadcastsd W:ymm, xmm[63:0]" , "op": "[RM ] VEX.256.66.0F38.W0 19 /r"},
+ {"any": "vbroadcastss W:xmm, xmm[31:0]" , "op": "[RM ] VEX.128.66.0F38.W0 18 /r"},
+ {"any": "vbroadcastss W:ymm, xmm[31:0]" , "op": "[RM ] VEX.256.66.0F38.W0 18 /r"},
+ {"any": "vextracti128 W:xmm/m128, ymm, imm8" , "op": "[MR ] VEX.256.66.0F3A.W0 39 /r ib"},
+ {"any": "vgatherdpd X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 92 /r"},
+ {"any": "vgatherdpd X:ymm, vm32x, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 92 /r"},
+ {"any": "vgatherdps X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 92 /r"},
+ {"any": "vgatherdps X:ymm, vm32y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W0 92 /r"},
+ {"any": "vgatherqpd X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 93 /r"},
+ {"any": "vgatherqpd X:ymm, vm64y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 93 /r"},
+ {"any": "vgatherqps X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 93 /r"},
+ {"any": "vgatherqps X:xmm, vm64y, X:xmm" , "op": "[RMV] VEX.256.66.0F38.W0 93 /r"},
+ {"any": "vinserti128 W:ymm, ymm, xmm/m128, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 38 /r ib"},
+ {"any": "vmovntdqa W:ymm, m256" , "op": "[RM ] VEX.256.66.0F38.WIG 2A /r"},
+ {"any": "vmpsadbw W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 42 /r ib"},
+ {"any": "vpabsb W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F38.WIG 1C /r"},
+ {"any": "vpabsd W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F38.WIG 1E /r"},
+ {"any": "vpabsw W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F38.WIG 1D /r"},
+ {"any": "vpackssdw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6B /r"},
+ {"any": "vpacksswb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 63 /r"},
+ {"any": "vpackusdw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 2B /r"},
+ {"any": "vpackuswb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 67 /r"},
+ {"any": "vpaddb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FC /r"},
+ {"any": "vpaddd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FE /r"},
+ {"any": "vpaddq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D4 /r"},
+ {"any": "vpaddsb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EC /r"},
+ {"any": "vpaddsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG ED /r"},
+ {"any": "vpaddusb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DC /r"},
+ {"any": "vpaddusw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DD /r"},
+ {"any": "vpaddw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FD /r"},
+ {"any": "vpalignr W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 0F /r ib"},
+ {"any": "vpand W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DB /r"},
+ {"any": "vpandn W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DF /r"},
+ {"any": "vpavgb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E0 /r"},
+ {"any": "vpavgw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E3 /r"},
+ {"any": "vpblendd W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 02 /r ib"},
+ {"any": "vpblendd W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 02 /r ib"},
+ {"any": "vpblendvb W:ymm, ymm, ymm/m256, ymm" , "op": "[RVMS]VEX.256.66.0F3A.W0 4C /r /is4"},
+ {"any": "vpblendw W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 0E /r ib"},
+ {"any": "vpbroadcastb W:xmm, xmm[7:0]/m8" , "op": "[RM ] VEX.128.66.0F38.W0 78 /r"},
+ {"any": "vpbroadcastb W:ymm, xmm[7:0]/m8" , "op": "[RM ] VEX.256.66.0F38.W0 78 /r"},
+ {"any": "vpbroadcastd W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.W0 58 /r"},
+ {"any": "vpbroadcastd W:ymm, xmm[31:0]/m32" , "op": "[RM ] VEX.256.66.0F38.W0 58 /r"},
+ {"any": "vpbroadcastq W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.W0 59 /r"},
+ {"any": "vpbroadcastq W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.W0 59 /r"},
+ {"any": "vpbroadcastw W:xmm, xmm[15:0]/m16" , "op": "[RM ] VEX.128.66.0F38.W0 79 /r"},
+ {"any": "vpbroadcastw W:ymm, xmm[15:0]/m16" , "op": "[RM ] VEX.256.66.0F38.W0 79 /r"},
+ {"any": "vpcmpeqb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 74 /r"},
+ {"any": "vpcmpeqd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 76 /r"},
+ {"any": "vpcmpeqq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 29 /r"},
+ {"any": "vpcmpeqw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 75 /r"},
+ {"any": "vpcmpgtb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 64 /r"},
+ {"any": "vpcmpgtd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 66 /r"},
+ {"any": "vpcmpgtq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 37 /r"},
+ {"any": "vpcmpgtw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 65 /r"},
+ {"any": "vperm2i128 W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 46 /r ib"},
+ {"any": "vpermd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 36 /r"},
+ {"any": "vpermpd W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W1 01 /r ib"},
+ {"any": "vpermps W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 16 /r"},
+ {"any": "vpermq W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W1 00 /r ib"},
+ {"any": "vpgatherdd X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 90 /r"},
+ {"any": "vpgatherdd X:ymm, vm32y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W0 90 /r"},
+ {"any": "vpgatherdq X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 90 /r"},
+ {"any": "vpgatherdq X:ymm, vm32x, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 90 /r"},
+ {"any": "vpgatherqd X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 91 /r"},
+ {"any": "vpgatherqd X:xmm, vm64y, X:xmm" , "op": "[RMV] VEX.256.66.0F38.W0 91 /r"},
+ {"any": "vpgatherqq X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 91 /r"},
+ {"any": "vpgatherqq X:ymm, vm64y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 91 /r"},
+ {"any": "vphaddd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 02 /r"},
+ {"any": "vphaddsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 03 /r"},
+ {"any": "vphaddw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 01 /r"},
+ {"any": "vphsubd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 06 /r"},
+ {"any": "vphsubsw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 07 /r"},
+ {"any": "vphsubw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 05 /r"},
+ {"any": "vpmaddubsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 04 /r"},
+ {"any": "vpmaddwd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F5 /r"},
+ {"any": "vpmaskmovd X:m128, xmm, xmm" , "op": "[MVR] VEX.128.66.0F38.W0 8E /r"},
+ {"any": "vpmaskmovd X:m256, ymm, ymm" , "op": "[MVR] VEX.256.66.0F38.W0 8E /r"},
+ {"any": "vpmaskmovd W:xmm, xmm, m128" , "op": "[RVM] VEX.128.66.0F38.W0 8C /r"},
+ {"any": "vpmaskmovd W:ymm, ymm, m256" , "op": "[RVM] VEX.256.66.0F38.W0 8C /r"},
+ {"any": "vpmaskmovq X:m128, xmm, xmm" , "op": "[MVR] VEX.128.66.0F38.W1 8E /r"},
+ {"any": "vpmaskmovq X:m256, ymm, ymm" , "op": "[MVR] VEX.256.66.0F38.W1 8E /r"},
+ {"any": "vpmaskmovq W:xmm, xmm, m128" , "op": "[RVM] VEX.128.66.0F38.W1 8C /r"},
+ {"any": "vpmaskmovq W:ymm, ymm, m256" , "op": "[RVM] VEX.256.66.0F38.W1 8C /r"},
+ {"any": "vpmaxsb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3C /r"},
+ {"any": "vpmaxsd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3D /r"},
+ {"any": "vpmaxsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EE /r"},
+ {"any": "vpmaxub W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DE /r"},
+ {"any": "vpmaxud W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3F /r"},
+ {"any": "vpmaxuw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3E /r"},
+ {"any": "vpminsb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 38 /r"},
+ {"any": "vpminsd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 39 /r"},
+ {"any": "vpminsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EA /r"},
+ {"any": "vpminub W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DA /r"},
+ {"any": "vpminud W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3B /r"},
+ {"any": "vpminuw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3A /r"},
+ {"any": "vpmovmskb W:r32[31:0], ymm" , "op": "[RVM] VEX.256.66.0F.WIG D7 /r"},
+ {"any": "vpmovsxbd W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 21 /r"},
+ {"any": "vpmovsxbq W:ymm, xmm[31:0]/m32" , "op": "[RM ] VEX.256.66.0F38.WIG 22 /r"},
+ {"any": "vpmovsxbw W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 20 /r"},
+ {"any": "vpmovsxdq W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 25 /r"},
+ {"any": "vpmovsxwd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 23 /r"},
+ {"any": "vpmovsxwq W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 24 /r"},
+ {"any": "vpmovzxbd W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 31 /r"},
+ {"any": "vpmovzxbq W:ymm, xmm[31:0]/m32" , "op": "[RM ] VEX.256.66.0F38.WIG 32 /r"},
+ {"any": "vpmovzxbw W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 30 /r"},
+ {"any": "vpmovzxdq W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 35 /r"},
+ {"any": "vpmovzxwd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 33 /r"},
+ {"any": "vpmovzxwq W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 34 /r"},
+ {"any": "vpmuldq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 28 /r"},
+ {"any": "vpmulhrsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 0B /r"},
+ {"any": "vpmulhuw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E4 /r"},
+ {"any": "vpmulhw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E5 /r"},
+ {"any": "vpmulld W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 40 /r"},
+ {"any": "vpmullw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D5 /r"},
+ {"any": "vpmuludq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F4 /r"},
+ {"any": "vpor W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EB /r"},
+ {"any": "vpsadbw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F6 /r"},
+ {"any": "vpshufb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 00 /r"},
+ {"any": "vpshufd W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F.WIG 70 /r ib"},
+ {"any": "vpshufhw W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.F3.0F.WIG 70 /r ib"},
+ {"any": "vpshuflw W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.F2.0F.WIG 70 /r ib"},
+ {"any": "vpsignb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 08 /r"},
+ {"any": "vpsignd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 0A /r"},
+ {"any": "vpsignw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 09 /r"},
+ {"any": "vpslld W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG F2 /r"},
+ {"any": "vpslld W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 72 /6 ib"},
+ {"any": "vpslldq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /7 ib"},
+ {"any": "vpsllq W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG F3 /r"},
+ {"any": "vpsllq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /6 ib"},
+ {"any": "vpsllvd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 47 /r"},
+ {"any": "vpsllvd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 47 /r"},
+ {"any": "vpsllvq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W1 47 /r"},
+ {"any": "vpsllvq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W1 47 /r"},
+ {"any": "vpsllw W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG F1 /r"},
+ {"any": "vpsllw W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 71 /6 ib"},
+ {"any": "vpsrad W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG E2 /r"},
+ {"any": "vpsrad W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 72 /4 ib"},
+ {"any": "vpsravd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 46 /r"},
+ {"any": "vpsravd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 46 /r"},
+ {"any": "vpsraw W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG E1 /r"},
+ {"any": "vpsraw W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 71 /4 ib"},
+ {"any": "vpsrld W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG D2 /r"},
+ {"any": "vpsrld W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 72 /2 ib"},
+ {"any": "vpsrldq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /3 ib"},
+ {"any": "vpsrlq W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG D3 /r"},
+ {"any": "vpsrlq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /2 ib"},
+ {"any": "vpsrlvd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 45 /r"},
+ {"any": "vpsrlvd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 45 /r"},
+ {"any": "vpsrlvq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W1 45 /r"},
+ {"any": "vpsrlvq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W1 45 /r"},
+ {"any": "vpsrlw W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG D1 /r"},
+ {"any": "vpsrlw W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 71 /2 ib"},
+ {"any": "vpsubb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F8 /r"},
+ {"any": "vpsubd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FA /r"},
+ {"any": "vpsubq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FB /r"},
+ {"any": "vpsubsb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E8 /r"},
+ {"any": "vpsubsw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E9 /r"},
+ {"any": "vpsubusb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D8 /r"},
+ {"any": "vpsubusw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D9 /r"},
+ {"any": "vpsubw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F9 /r"},
+ {"any": "vpunpckhbw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 68 /r"},
+ {"any": "vpunpckhdq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6A /r"},
+ {"any": "vpunpckhqdq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6D /r"},
+ {"any": "vpunpckhwd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 69 /r"},
+ {"any": "vpunpcklbw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 60 /r"},
+ {"any": "vpunpckldq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 62 /r"},
+ {"any": "vpunpcklqdq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6C /r"},
+ {"any": "vpunpcklwd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 61 /r"},
+ {"any": "vpxor W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EF /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "F16C", "instructions": [
+ {"any": "vcvtph2ps W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.W0 13 /r"},
+ {"any": "vcvtph2ps W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.W0 13 /r"},
+ {"any": "vcvtps2ph W:xmm[63:0]/m64, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 1D /r ib"},
+ {"any": "vcvtps2ph W:xmm/m128, ymm, imm8" , "op": "[MR ] VEX.256.66.0F3A.W0 1D /r ib"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "FMA", "instructions": [
+ {"any": "vfmadd132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 98 /r"},
+ {"any": "vfmadd132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 98 /r"},
+ {"any": "vfmadd132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 99 /r"},
+ {"any": "vfmadd132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 99 /r"},
+ {"any": "vfmadd213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 A8 /r"},
+ {"any": "vfmadd213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 A8 /r"},
+ {"any": "vfmadd213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 A9 /r"},
+ {"any": "vfmadd213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 A9 /r"},
+ {"any": "vfmadd231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B8 /r"},
+ {"any": "vfmadd231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 B8 /r"},
+ {"any": "vfmadd231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 B9 /r"},
+ {"any": "vfmadd231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 B9 /r"},
+ {"any": "vfmaddsub132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 96 /r"},
+ {"any": "vfmaddsub132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 96 /r"},
+ {"any": "vfmaddsub213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 A6 /r"},
+ {"any": "vfmaddsub213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 A6 /r"},
+ {"any": "vfmaddsub231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B6 /r"},
+ {"any": "vfmaddsub231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 B6 /r"},
+ {"any": "vfmsub132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 9A /r"},
+ {"any": "vfmsub132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 9A /r"},
+ {"any": "vfmsub132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 9B /r"},
+ {"any": "vfmsub132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 9B /r"},
+ {"any": "vfmsub213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 AA /r"},
+ {"any": "vfmsub213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 AA /r"},
+ {"any": "vfmsub213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 AB /r"},
+ {"any": "vfmsub213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 AB /r"},
+ {"any": "vfmsub231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 BA /r"},
+ {"any": "vfmsub231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 BA /r"},
+ {"any": "vfmsub231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 BB /r"},
+ {"any": "vfmsub231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 BB /r"},
+ {"any": "vfmsubadd132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 97 /r"},
+ {"any": "vfmsubadd132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 97 /r"},
+ {"any": "vfmsubadd213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 A7 /r"},
+ {"any": "vfmsubadd213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 A7 /r"},
+ {"any": "vfmsubadd231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B7 /r"},
+ {"any": "vfmsubadd231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 B7 /r"},
+ {"any": "vfnmadd132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 9C /r"},
+ {"any": "vfnmadd132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 9C /r"},
+ {"any": "vfnmadd132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 9D /r"},
+ {"any": "vfnmadd132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 9D /r"},
+ {"any": "vfnmadd213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 AC /r"},
+ {"any": "vfnmadd213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 AC /r"},
+ {"any": "vfnmadd213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 AD /r"},
+ {"any": "vfnmadd213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 AD /r"},
+ {"any": "vfnmadd231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 BC /r"},
+ {"any": "vfnmadd231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 BC /r"},
+ {"any": "vfnmadd231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 BD /r"},
+ {"any": "vfnmadd231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 BD /r"},
+ {"any": "vfnmsub132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 9E /r"},
+ {"any": "vfnmsub132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 9E /r"},
+ {"any": "vfnmsub132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 9F /r"},
+ {"any": "vfnmsub132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 9F /r"},
+ {"any": "vfnmsub213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 AE /r"},
+ {"any": "vfnmsub213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 AE /r"},
+ {"any": "vfnmsub213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 AF /r"},
+ {"any": "vfnmsub213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 AF /r"},
+ {"any": "vfnmsub231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 BE /r"},
+ {"any": "vfnmsub231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 BE /r"},
+ {"any": "vfnmsub231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 BF /r"},
+ {"any": "vfnmsub231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 BF /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "FMA4", "deprecated": true, "instructions": [
+ {"any": "vfmaddpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 69 /r /is4"},
+ {"any": "vfmaddpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 69 /r /is4"},
+ {"any": "vfmaddps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 68 /r /is4"},
+ {"any": "vfmaddps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 68 /r /is4"},
+ {"any": "vfmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 6b /r /is4"},
+ {"any": "vfmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6b /r /is4"},
+ {"any": "vfmaddss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 6a /r /is4"},
+ {"any": "vfmaddss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6a /r /is4"},
+ {"any": "vfmaddsubpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5D /r /is4"},
+ {"any": "vfmaddsubpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5D /r /is4"},
+ {"any": "vfmaddsubps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5C /r /is4"},
+ {"any": "vfmaddsubps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5C /r /is4"},
+ {"any": "vfmsubaddpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5F /r /is4"},
+ {"any": "vfmsubaddpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5F /r /is4"},
+ {"any": "vfmsubaddps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5E /r /is4"},
+ {"any": "vfmsubaddps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5E /r /is4"},
+ {"any": "vfmsubpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 6D /r /is4"},
+ {"any": "vfmsubpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 6D /r /is4"},
+ {"any": "vfmsubps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 6C /r /is4"},
+ {"any": "vfmsubps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 6C /r /is4"},
+ {"any": "vfmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 6F /r /is4"},
+ {"any": "vfmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6F /r /is4"},
+ {"any": "vfmsubss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 6E /r /is4"},
+ {"any": "vfmsubss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6E /r /is4"},
+ {"any": "vfnmaddpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 79 /r /is4"},
+ {"any": "vfnmaddpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 79 /r /is4"},
+ {"any": "vfnmaddps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 78 /r /is4"},
+ {"any": "vfnmaddps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 78 /r /is4"},
+ {"any": "vfnmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 7B /r /is4"},
+ {"any": "vfnmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7B /r /is4"},
+ {"any": "vfnmaddss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 7A /r /is4"},
+ {"any": "vfnmaddss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7A /r /is4"},
+ {"any": "vfnmsubpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 7D /r /is4"},
+ {"any": "vfnmsubpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 7D /r /is4"},
+ {"any": "vfnmsubps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 7C /r /is4"},
+ {"any": "vfnmsubps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 7C /r /is4"},
+ {"any": "vfnmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 7F /r /is4"},
+ {"any": "vfnmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7F /r /is4"},
+ {"any": "vfnmsubss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 7E /r /is4"},
+ {"any": "vfnmsubss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7E /r /is4"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "XOP", "deprecated": true, "instructions": [
+ {"any": "vfrczpd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 81 /r"},
+ {"any": "vfrczpd W:ymm, ymm/m256" , "op": "[RM ] XOP.256.P0.MAP9.W0 81 /r"},
+ {"any": "vfrczps W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 80 /r"},
+ {"any": "vfrczps W:ymm, ymm/m256" , "op": "[RM ] XOP.256.P0.MAP9.W0 80 /r"},
+ {"any": "vfrczsd W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] XOP.128.P0.MAP9.W0 83 /r"},
+ {"any": "vfrczss W:xmm[31:0], xmm[31:0]/m32" , "op": "[RM ] XOP.128.P0.MAP9.W0 82 /r"},
+ {"any": "vpcmov W:xmm, xmm, xmm, xmm/m128" , "op": "[RVSM]XOP.128.P0.MAP8.W1 A2 /r /is4"},
+ {"any": "vpcmov W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 A2 /r /is4"},
+ {"any": "vpcmov W:ymm, ymm, ymm, ymm/m256" , "op": "[RVSM]XOP.256.P0.MAP8.W1 A2 /r /is4"},
+ {"any": "vpcmov W:ymm, ymm, ymm/m256, ymm" , "op": "[RVMS]XOP.256.P0.MAP8.W0 A2 /r /is4"},
+ {"any": "vpcomb W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CC /r ib"},
+ {"any": "vpcomd W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CE /r ib"},
+ {"any": "vpcomq W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CF /r ib"},
+ {"any": "vpcomub W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 EC /r ib"},
+ {"any": "vpcomud W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 EE /r ib"},
+ {"any": "vpcomuq W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 EF /r ib"},
+ {"any": "vpcomuw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 ED /r ib"},
+ {"any": "vpcomw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CD /r ib"},
+ {"any": "vpermil2pd W:xmm, xmm, xmm/m128, xmm, imm4" , "op": "[RVMS]VEX.128.66.0F3A.W0 49 /r /is4"},
+ {"any": "vpermil2pd W:xmm, xmm, xmm, xmm/m128, imm4" , "op": "[RVSM]VEX.128.66.0F3A.W1 49 /r /is4"},
+ {"any": "vpermil2pd W:ymm, ymm, ymm/m256, ymm, imm4" , "op": "[RVMS]VEX.256.66.0F3A.W0 49 /r /is4"},
+ {"any": "vpermil2pd W:ymm, ymm, ymm, ymm/m256, imm4" , "op": "[RVSM]VEX.256.66.0F3A.W1 49 /r /is4"},
+ {"any": "vpermil2ps W:xmm, xmm, xmm/m128, xmm, imm4" , "op": "[RVMS]VEX.128.66.0F3A.W0 48 /r /is4"},
+ {"any": "vpermil2ps W:xmm, xmm, xmm, xmm/m128, imm4" , "op": "[RVSM]VEX.128.66.0F3A.W1 48 /r /is4"},
+ {"any": "vpermil2ps W:ymm, ymm, ymm/m256, ymm, imm4" , "op": "[RVMS]VEX.256.66.0F3A.W0 48 /r /is4"},
+ {"any": "vpermil2ps W:ymm, ymm, ymm, ymm/m256, imm4" , "op": "[RVSM]VEX.256.66.0F3A.W1 48 /r /is4"},
+ {"any": "vphaddbd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C2 /r"},
+ {"any": "vphaddbq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C3 /r"},
+ {"any": "vphaddbw W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C1 /r"},
+ {"any": "vphadddq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 CB /r"},
+ {"any": "vphaddubd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D2 /r"},
+ {"any": "vphaddubq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D3 /r"},
+ {"any": "vphaddubw W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D1 /r"},
+ {"any": "vphaddudq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 DB /r"},
+ {"any": "vphadduwd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D6 /r"},
+ {"any": "vphadduwq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D7 /r"},
+ {"any": "vphaddwd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C6 /r"},
+ {"any": "vphaddwq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C7 /r"},
+ {"any": "vphsubbw W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 E1 /r"},
+ {"any": "vphsubdq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 E3 /r"},
+ {"any": "vphsubwd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 E2 /r"},
+ {"any": "vpmacsdd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 9E /r /is4"},
+ {"any": "vpmacsdqh W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 9F /r /is4"},
+ {"any": "vpmacsdql W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 97 /r /is4"},
+ {"any": "vpmacssdd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 8E /r /is4"},
+ {"any": "vpmacssdqh W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 8F /r /is4"},
+ {"any": "vpmacssdql W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 87 /r /is4"},
+ {"any": "vpmacsswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 86 /r /is4"},
+ {"any": "vpmacssww W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 85 /r /is4"},
+ {"any": "vpmacswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 96 /r /is4"},
+ {"any": "vpmacsww W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 95 /r /is4"},
+ {"any": "vpmadcsswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 A6 /r /is4"},
+ {"any": "vpmadcswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 B6 /r /is4"},
+ {"any": "vpperm W:xmm, xmm, xmm, xmm/m128" , "op": "[RVSM]XOP.128.P0.MAP8.W1 A3 /r /is4"},
+ {"any": "vpperm W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 A3 /r /is4"},
+ {"any": "vprotb W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 90 /r"},
+ {"any": "vprotb W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C0 /r ib"},
+ {"any": "vprotb W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 90 /r"},
+ {"any": "vprotd W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 92 /r"},
+ {"any": "vprotd W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C2 /r ib"},
+ {"any": "vprotd W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 92 /r"},
+ {"any": "vprotq W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 93 /r"},
+ {"any": "vprotq W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C3 /r ib"},
+ {"any": "vprotq W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 93 /r"},
+ {"any": "vprotw W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 91 /r"},
+ {"any": "vprotw W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C1 /r ib"},
+ {"any": "vprotw W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 91 /r"},
+ {"any": "vpshab W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 98 /r"},
+ {"any": "vpshab W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 98 /r"},
+ {"any": "vpshad W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 9A /r"},
+ {"any": "vpshad W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 9A /r"},
+ {"any": "vpshaq W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 9B /r"},
+ {"any": "vpshaq W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 9B /r"},
+ {"any": "vpshaw W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 99 /r"},
+ {"any": "vpshaw W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 99 /r"},
+ {"any": "vpshlb W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 94 /r"},
+ {"any": "vpshlb W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 94 /r"},
+ {"any": "vpshld W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 96 /r"},
+ {"any": "vpshld W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 96 /r"},
+ {"any": "vpshlq W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 97 /r"},
+ {"any": "vpshlq W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 97 /r"},
+ {"any": "vpshlw W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 95 /r"},
+ {"any": "vpshlw W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 95 /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX PCLMULQDQ", "instructions": [
+ {"any": "vpclmulqdq W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 44 /r ib"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "VPCLMULQDQ", "instructions": [
+ {"any": "vpclmulqdq W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 44 /r ib"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX_IFMA", "instructions": [
+ {"any": "vpmadd52huq X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B5 /r"},
+ {"any": "vpmadd52luq X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B4 /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX_NE_CONVERT", "instructions": [
+ {"any": "vbcstnebf162ps W:xy, m16" , "op": "[RM ] VEX.Lxy.F3.0F38.W0 B1 !(11):rrr:bbb"},
+ {"any": "vbcstnesh2ps W:xy, m16" , "op": "[RM ] VEX.Lxy.66.0F38.W0 B1 !(11):rrr:bbb"},
+ {"any": "vcvtneebf162ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.F3.0F38.W0 B0 !(11):rrr:bbb"},
+ {"any": "vcvtneeph2ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.66.0F38.W0 B0 !(11):rrr:bbb"},
+ {"any": "vcvtneobf162ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.F2.0F38.W0 B0 !(11):rrr:bbb"},
+ {"any": "vcvtneoph2ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.NP.0F38.W0 B0 !(11):rrr:bbb"},
+ {"any": "vcvtneps2bf16 W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.F3.0F38.W0 72 /r"},
+ {"any": "vcvtneps2bf16 W:xmm, ymm/m256" , "op": "[RM ] VEX.256.F3.0F38.W0 72 /r"}
+ ]},
+
+ {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX SHA512", "instructions": [
+ {"any": "vsha512msg1 X:ymm, R:xmm" , "op": "[RM ] VEX.256.F2.0F38.W0 CC 11:rrr:bbb"},
+ {"any": "vsha512msg2 X:ymm, R:ymm" , "op": "[RM ] VEX.256.F2.0F38.W0 CD 11:rrr:bbb"},
+ {"any": "vsha512rnds2 X:ymm, R:ymm, R:xmm" , "op": "[RVM] VEX.256.F2.0F38.W0 CB 11:rrr:bbb"}
+ ]},
+
+ {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX SM3", "instructions": [
+ {"any": "vsm3msg1 X:xmm, R:xmm, R:xmm/m128" , "op": "[RVM] VEX.128.NP.0F38.W0 DA /r"},
+ {"any": "vsm3msg2 X:xmm, R:xmm, R:xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 DA /r"},
+ {"any": "vsm3rnds2 X:xmm, R:xmm, R:xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 DE /r ib"}
+ ]},
+
+ {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX SM4", "instructions": [
+ {"any": "vsm4key4 W:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 DA /r"},
+ {"any": "vsm4rnds4 W:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F38.W0 DA /r"}
+ ]},
+
+ {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX10_2 SM4", "instructions": [
+ {"any": "vsm4key4 W:xyz, R:xyz, R:xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 DA /r"},
+ {"any": "vsm4rnds4 W:xyz, R:xyz, R:xyz/mxyz" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 DA /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX_VNNI", "instructions": [
+ {"any": "vpdpbusd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 50 /r"},
+ {"any": "vpdpbusds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 51 /r"},
+ {"any": "vpdpwssd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 52 /r"},
+ {"any": "vpdpwssds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 53 /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX_VNNI_INT8", "instructions": [
+ {"any": "vpdpbssd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F38.W0 50 /r"},
+ {"any": "vpdpbssds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F38.W0 51 /r"},
+ {"any": "vpdpbsud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 50 /r"},
+ {"any": "vpdpbsuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 51 /r"},
+ {"any": "vpdpbuud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 50 /r"},
+ {"any": "vpdpbuuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 51 /r"}
+ ]},
+
+ {"category": "AVX SIMD", "ext": "AVX_VNNI_INT16", "instructions": [
+ {"any": "vpdpwsud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 D2 /r"},
+ {"any": "vpdpwsuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 D3 /r"},
+ {"any": "vpdpwusd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 D2 /r"},
+ {"any": "vpdpwusds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 D3 /r"},
+ {"any": "vpdpwuud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 D2 /r"},
+ {"any": "vpdpwuuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 D3 /r"}
+ ]},
+
+ {"category": "AVX512 MASK", "ext": "AVX512_F", "instructions": [
+ {"any": "kandnw W:k[15:0], k[15:0], k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 42 /r"},
+ {"any": "kandw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 41 /r"},
+ {"any": "kmovw W:k[15:0], k[15:0]/m16" , "op": "[RM ] VEX.L0.0F.W0 90 /r"},
+ {"apx": "kmovw W:k[15:0], k[15:0]/m16" , "op": "[RM ] EVEX.128.NP.0F.W0 90 /r"},
+ {"any": "kmovw W:k[15:0], r32[15:0]" , "op": "[RM ] VEX.L0.0F.W0 92 /r"},
+ {"apx": "kmovw W:k[15:0], r32[15:0]" , "op": "[RM ] EVEX.128.NP.0F.W0 92 11:rrr:bbb"},
+ {"any": "kmovw W:m16, k[15:0]" , "op": "[MR ] VEX.L0.0F.W0 91 /r"},
+ {"apx": "kmovw W:m16, k[15:0]" , "op": "[MR ] EVEX.128.NP.0F.W0 91 !(11):rrr:bbb"},
+ {"any": "kmovw W:r32[15:0], k[15:0]" , "op": "[RM ] VEX.L0.0F.W0 93 /r"},
+ {"apx": "kmovw W:r32[15:0], k[15:0]" , "op": "[RM ] EVEX.128.NP.0F.W0 93 11:rrr:bbb"},
+ {"any": "knotw W:k[15:0], k[15:0]" , "op": "[RM ] VEX.L0.0F.W0 44 /r"},
+ {"any": "kortestw R:~k[15:0], ~k[15:0]" , "op": "[RM ] VEX.L0.0F.W0 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "korw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 45 /r"},
+ {"any": "kshiftlw W:k[15:0], k[15:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W1 32 /r ib"},
+ {"any": "kshiftrw W:k[15:0], k[15:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W1 30 /r ib"},
+ {"any": "kunpckbw W:k[15:0], k[7:0], k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 4B /r"},
+ {"any": "kxnorw W:k[15:0], k[15:0], k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 46 /r"},
+ {"any": "kxorw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 47 /r"}
+ ]},
+
+ {"category": "AVX512 MASK", "ext": "AVX512_DQ", "instructions": [
+ {"any": "kaddb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 4A /r"},
+ {"any": "kaddw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.NP.0F.W0 4A /r"},
+ {"any": "kandb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 41 /r"},
+ {"any": "kandnb W:k[7:0], k[7:0], k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 42 /r"},
+ {"any": "kmovb W:k[7:0], k[7:0]/m8" , "op": "[RM ] VEX.L0.66.0F.W0 90 /r"},
+ {"apx": "kmovb W:k[7:0], k[7:0]/m8" , "op": "[RM ] EVEX.128.66.0F.W0 90 /r"},
+ {"any": "kmovb W:k[7:0], r32[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 92 /r"},
+ {"apx": "kmovb W:k[7:0], r32[7:0]" , "op": "[RM ] EVEX.128.66.0F.W0 92 11:rrr:bbb"},
+ {"any": "kmovb W:m8, k[7:0]" , "op": "[MR ] VEX.L0.66.0F.W0 91 /r"},
+ {"apx": "kmovb W:m8, k[7:0]" , "op": "[MR ] EVEX.128.66.0F.W0 91 !(11):rrr:bbb"},
+ {"any": "kmovb W:r32[7:0], k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 93 /r"},
+ {"apx": "kmovb W:r32[7:0], k[7:0]" , "op": "[RM ] EVEX.128.66.0F.W0 93 11:rrr:bbb"},
+ {"any": "knotb W:k[7:0], k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 44 /r"},
+ {"any": "korb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 45 /r"},
+ {"any": "kortestb R:~k[7:0], ~k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "kshiftlb W:k[7:0], k[7:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W0 32 /r ib"},
+ {"any": "kshiftrb W:k[7:0], k[7:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W0 30 /r ib"},
+ {"any": "ktestb R:~k[7:0], ~k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "ktestw R:~k[15:0], ~k[15:0]" , "op": "[RM ] VEX.L0.NP.0F.W0 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "kxnorb W:k[7:0], k[7:0], k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 46 /r"},
+ {"any": "kxorb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 47 /r"}
+ ]},
+
+ {"category": "AVX512 MASK", "ext": "AVX512_BW", "instructions": [
+ {"any": "kaddd W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "[RVM] VEX.L1.66.0F.W1 4A /r"},
+ {"any": "kaddq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 4A /r"},
+ {"any": "kandd W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "[RVM] VEX.L1.66.0F.W1 41 /r"},
+ {"any": "kandnd W:k[31:0], k[31:0], k[31:0]" , "op": "[RVM] VEX.L1.66.0F.W1 42 /r"},
+ {"any": "kandnq W:k[63:0], k[63:0], k[63:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 42 /r"},
+ {"any": "kandq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 41 /r"},
+ {"any": "kmovd W:k[31:0], k[31:0]/m32" , "op": "[RM ] VEX.L0.66.0F.W1 90 /r"},
+ {"apx": "kmovd W:k[31:0], k[31:0]/m32" , "op": "[RM ] EVEX.128.66.0F.W1 90 /r"},
+ {"any": "kmovd W:k[31:0], r32" , "op": "[RM ] VEX.L0.F2.0F.W0 92 /r"},
+ {"apx": "kmovd W:k[31:0], r32" , "op": "[RM ] EVEX.128.F2.0F.W0 92 11:rrr:bbb"},
+ {"any": "kmovd W:m32, k[31:0]" , "op": "[MR ] VEX.L0.66.0F.W1 91 /r"},
+ {"apx": "kmovd W:m32, k[31:0]" , "op": "[MR ] EVEX.128.66.0F.W1 91 !(11):rrr:bbb"},
+ {"any": "kmovd W:r32, k[31:0]" , "op": "[RM ] VEX.L0.F2.0F.W0 93 /r"},
+ {"apx": "kmovd W:r32, k[31:0]" , "op": "[RM ] EVEX.128.F2.0F.W0 93 11:rrr:bbb"},
+ {"any": "kmovq W:k[63:0], k[63:0]/m64" , "op": "[RM ] VEX.L0.NP.0F.W1 90 /r"},
+ {"apx": "kmovq W:k[63:0], k[63:0]/m64" , "op": "[RM ] EVEX.128.NP.0F.W1 90 /r"},
+ {"any": "kmovq W:k[63:0], r64" , "op": "[RM ] VEX.L0.F2.0F.W1 92 /r"},
+ {"apx": "kmovq W:k[63:0], r64" , "op": "[RM ] EVEX.128.F2.0F.W1 92 11:rrr:bbb"},
+ {"any": "kmovq W:m64, k[63:0]" , "op": "[MR ] VEX.L0.NP.0F.W1 91 /r"},
+ {"apx": "kmovq W:m64, k[63:0]" , "op": "[MR ] EVEX.128.NP.0F.W1 91 !(11):rrr:bbb"},
+ {"any": "kmovq W:r64, k[63:0]" , "op": "[RM ] VEX.L0.F2.0F.W1 93 /r"},
+ {"apx": "kmovq W:r64, k[63:0]" , "op": "[RM ] EVEX.128.F2.0F.W1 93 11:rrr:bbb"},
+ {"any": "knotd W:k[31:0], k[31:0]" , "op": "[RM ] VEX.L0.66.0F.W1 44 /r"},
+ {"any": "knotq W:k[63:0], k[63:0]" , "op": "[RM ] VEX.L0.NP.0F.W1 44 /r"},
+ {"any": "kord W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "[RVM] VEX.L1.66.0F.W1 45 /r"},
+ {"any": "korq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 45 /r"},
+ {"any": "kortestd R:~k[31:0], ~k[31:0]" , "op": "[RM ] VEX.L0.66.0F.W1 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "kortestq R:~k[63:0], ~k[63:0]" , "op": "[RM ] VEX.L0.NP.0F.W1 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "kshiftld W:k[31:0], k[31:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W0 33 /r ib"},
+ {"any": "kshiftlq W:k[63:0], k[63:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W1 33 /r ib"},
+ {"any": "kshiftrd W:k[31:0], k[31:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W0 31 /r ib"},
+ {"any": "kshiftrq W:k[63:0], k[63:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W1 31 /r ib"},
+ {"any": "ktestd R:~k[31:0], ~k[31:0]" , "op": "[RM ] VEX.L0.66.0F.W1 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "ktestq R:~k[63:0], ~k[63:0]" , "op": "[RM ] VEX.L0.NP.0F.W1 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"},
+ {"any": "kunpckdq W:k[63:0], k[31:0], k[31:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 4B /r"},
+ {"any": "kunpckwd W:k[31:0], k[15:0], k[15:0]" , "op": "[RVM] VEX.L1.NP.0F.W0 4B /r"},
+ {"any": "kxnord W:k[31:0], k[31:0], k[31:0]" , "op": "[RVM] VEX.L1.66.0F.W1 46 /r"},
+ {"any": "kxnorq W:k[63:0], k[63:0], k[63:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 46 /r"},
+ {"any": "kxord W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "[RVM] VEX.L1.66.0F.W1 47 /r"},
+ {"any": "kxorq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "[RVM] VEX.L1.NP.0F.W1 47 /r"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_F", "instructions": [
+ {"any": "vaddpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 58 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vaddps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 58 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vaddsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 58 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vaddss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 58 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "valignd W:xyz {kz}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 03 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "valignq W:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 03 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vblendmpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 65 /r" , "tt": "fv" , "vl": "xy", "k": "blend"},
+ {"any": "vblendmps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 65 /r" , "tt": "fv" , "vl": "xy", "k": "blend"},
+ {"any": "vbroadcastf32x4 W:ymm {kz}, m128" , "op": "[RM ] EVEX.256.66.0F38.W0 1A /r" , "tt": "t4" , "vl": "xy"},
+ {"any": "vbroadcastf32x4 W:zmm {kz}, m128" , "op": "[RM ] EVEX.512.66.0F38.W0 1A /r" , "tt": "t4" , "vl": "xy"},
+ {"any": "vbroadcastf64x4 W:zmm {kz}, m256" , "op": "[RM ] EVEX.512.66.0F38.W1 1B /r" , "tt": "t4" , "vl": "xy"},
+ {"any": "vbroadcasti32x4 W:ymm {kz}, m128" , "op": "[RM ] EVEX.256.66.0F38.W0 5A /r" , "tt": "t4" , "vl": "xy"},
+ {"any": "vbroadcasti32x4 W:zmm {kz}, m128" , "op": "[RM ] EVEX.512.66.0F38.W0 5A /r" , "tt": "t4" , "vl": "xy"},
+ {"any": "vbroadcasti64x4 W:zmm {kz}, m256" , "op": "[RM ] EVEX.512.66.0F38.W1 5B /r" , "tt": "t4" , "vl": "xy"},
+ {"any": "vbroadcastsd W:ymm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.256.66.0F38.W1 19 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vbroadcastsd W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.W1 19 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vbroadcastss W:xyz {kz}, xmm[31:0]/m32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 18 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vcmppd W:k {k}, xyz, xyz/mxyz/b64, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F.W1 C2 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vcmpps W:k {k}, xyz, xyz/mxyz/b32, imm8 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 C2 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vcmpsd W:k {k}, xmm, xmm[63:0]/m64, imm8 {sae}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 C2 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"},
+ {"any": "vcmpss W:k {k}, xmm, xmm[31:0]/m32, imm8 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 C2 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"},
+ {"any": "vcomisd R:xmm[63:0], xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.66.0F.W1 2F /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcomiss R:xmm[31:0], xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.NP.0F.W0 2F /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcompresspd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F38.W1 8A /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vcompressps W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F38.W0 8A /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vcvtdq2pd W:xyz {kz}, xxy/mxxy/b32" , "op": "[RM ] EVEX.xyz.F3.0F.W0 E6 /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtdq2ps W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.NP.0F.W0 5B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtpd2ps W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 5A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtpd2dq W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F2.0F.W1 E6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtpd2udq W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.NP.0F.W1 79 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtph2ps W:xyz {kz}, xxy/mxxy {sae}" , "op": "[RM ] EVEX.xyz.66.0F38.W0 13 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vcvtps2dq W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W0 5B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtps2pd W:xyz {kz}, xxy/mxxy/b32 {er}" , "op": "[RM ] EVEX.xyz.NP.0F.W0 5A /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtps2ph W:xxy/mxxy {kz}, xyz, imm8 {sae}" , "op": "[MR ] EVEX.xyz.66.0F3A.W0 1D /r ib" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vcvtps2udq W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.NP.0F.W0 79 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtsd2si W:ry, xmm[63:0]/m64 {er}" , "op": "[RM ] EVEX.LIG.F2.0F.Wy 2D /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvtsd2ss W:xmm {kz}, xmm[127:32], xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsd2usi W:ry, xmm[63:0]/m64 {er}" , "op": "[RM ] EVEX.LIG.F2.0F.Wy 79 /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvtsi2sd W:xmm, xmm[127:64], ry/my {er}" , "op": "[RVM] EVEX.LIG.F2.0F.Wy 2A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsi2ss W:xmm, xmm[127:32], ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.0F.Wy 2A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtss2sd W:xmm {kz}, xmm[127:64], xmm[31:0]/m32 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtss2si W:ry, xmm[31:0]/m32 {er}" , "op": "[RM ] EVEX.LIG.F3.0F.Wy 2D /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvtss2usi W:ry, xmm[31:0]/m32 {er}" , "op": "[RM ] EVEX.LIG.F3.0F.Wy 79 /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvttpd2dq W:xxy {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W1 E6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttpd2qq W:xyz {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W1 7A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttpd2udq W:xxy {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F.W1 78 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttps2dq W:xyz {kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.F3.0F.W0 5B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttps2udq W:xyz {kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F.W0 78 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttsd2si W:ry, xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F2.0F.Wy 2C /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvttsd2usi W:ry, xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F2.0F.Wy 78 /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvttss2si W:ry, xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F3.0F.Wy 2C /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvttss2usi W:ry, xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F3.0F.Wy 78 /r" , "tt": "t1f" , "vl": "no"},
+ {"any": "vcvtudq2pd W:xyz {kz}, xxy/mxxy/b32 {er}" , "op": "[RM ] EVEX.xyz.F3.0F.W0 7A /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtudq2ps W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.F2.0F.W0 7A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtusi2sd W:xmm, xmm[127:64], ry/my {er}" , "op": "[RVM] EVEX.LIG.F2.0F.Wy 7B /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtusi2ss W:xmm, xmm[127:32], ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.0F.Wy 7B /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vdivpd W:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vdivps W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 5E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vdivsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vdivss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vexpandpd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 88 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vexpandps W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 88 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vextractf32x4 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W0 19 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vextractf32x4 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 19 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vextractf64x4 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 1B /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vextracti32x4 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W0 39 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vextracti32x4 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 39 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vextracti64x4 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 3B /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vextractps W:r32[31:0]/m32, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.WIG 17 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfixupimmpd X:xyz {kz}, xyz, xyz/mxyz/b64, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 54 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfixupimmps X:xyz {kz}, xyz, xyz/mxyz/b32, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 54 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfixupimmsd X:xmm {kz},xmm[127:64],xmm[63:0]/m64,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W1 55 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfixupimmss X:xmm {kz},xmm[127:32],xmm[31:0]/m32,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W0 55 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 98 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 98 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd132sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 99 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd132ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 99 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 A8 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 A8 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd213sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 A9 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd213ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 A9 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B8 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 B8 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd231sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 B9 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd231ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 B9 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmaddsub132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 96 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 96 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 A6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 A6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 B6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 9A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 9A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub132sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 9B /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub132ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 9B /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 AA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 AA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub213sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 AB /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub213ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 AB /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 BA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 BA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub231sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 BB /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub231ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 BB /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsubadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 97 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 97 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 A7 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 A7 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B7 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 B7 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 9C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 9C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd132sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 9D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd132ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 9D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 AC /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 AC /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd213sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 AD /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd213ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 AD /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 BC /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 BC /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd231sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 BD /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd231ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 BD /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 9E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 9E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub132sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 9F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub132ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 9F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 AE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 AE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub213sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 AF /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub213ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 AF /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 BE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 BE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub231sd X:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 BF /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub231ss X:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 BF /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vgatherdpd X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W1 92 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherdpd X:ymm {k}, vm32x" , "op": "[RM ] EVEX.256.66.0F38.W1 92 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherdpd X:zmm {k}, vm32y" , "op": "[RM ] EVEX.512.66.0F38.W1 92 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherdps X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W0 92 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherdps X:ymm {k}, vm32y" , "op": "[RM ] EVEX.256.66.0F38.W0 92 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherdps X:zmm {k}, vm32z" , "op": "[RM ] EVEX.512.66.0F38.W0 92 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherqpd X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W1 93 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherqpd X:ymm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W1 93 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherqpd X:zmm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W1 93 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherqps X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W0 93 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherqps X:xmm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W0 93 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgatherqps X:ymm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W0 93 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vgetexppd W:xyz {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.0F38.W1 42 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vgetexpps W:xyz {kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.0F38.W0 42 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vgetexpsd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.66.0F38.W1 43 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vgetexpss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.66.0F38.W0 43 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vgetmantpd W:xyz {kz}, xyz/mxyz/b64, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 26 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vgetmantps W:xyz {kz}, xyz/mxyz/b32, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 26 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vgetmantsd W:xmm {kz}, xmm[127:64],xmm[63:0]/m64,imm8 {sae}", "op": "[RM ] EVEX.LIG.66.0F3A.W1 27 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vgetmantss W:xmm {kz}, xmm[127:32],xmm[31:0]/m32,imm8 {sae}", "op": "[RM ] EVEX.LIG.66.0F3A.W0 27 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vinsertf32x4 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 18 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vinsertf32x4 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 18 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vinsertf64x4 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 1A /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vinserti32x4 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 38 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vinserti32x4 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 38 /r ib" , "tt": "t4" , "vl": "xy"},
+ {"any": "vinserti64x4 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 3A /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vinsertps W:xmm, xmm, xmm[31:0]/m32, imm8" , "op": "[RVM] EVEX.128.66.0F3A.W0 21 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmaxpd W:xyz {kz}, xyz, xyz/mxyz/b64 {sae}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vmaxps W:xyz {kz}, xyz, xyz/mxyz/b32 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 5F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vmaxsd W:xmm {kz}, xmm, xmm[63:0]/m64 {sae}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmaxss W:xmm {kz}, xmm, xmm[31:0]/m32 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vminpd W:xyz {kz}, xyz, xyz/mxyz/b64 {sae}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vminps W:xyz {kz}, xyz, xyz/mxyz/b32 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 5D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vminsd W:xmm {kz}, xmm, xmm[63:0]/m64 {sae}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vminss W:xmm {kz}, xmm, xmm[31:0]/m32 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovapd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W1 28 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovapd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 29 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovaps W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.NP.0F.W0 28 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovaps W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.NP.0F.W0 29 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovd W:r32/m32, xmm[31:0]" , "op": "[MR ] EVEX.128.66.0F.W0 7E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovd W:xmm[31:0], r32/m32" , "op": "[RM ] EVEX.128.66.0F.W0 6E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovddup W:xmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.128.F2.0F.W1 12 /r" , "tt": "movddup", "vl": "xy"},
+ {"any": "vmovddup W:ymm {kz}, ymm/m256" , "op": "[RM ] EVEX.256.F2.0F.W1 12 /r" , "tt": "movddup", "vl": "xy"},
+ {"any": "vmovddup W:zmm {kz}, zmm/m512" , "op": "[RM ] EVEX.512.F2.0F.W1 12 /r" , "tt": "movddup", "vl": "xy"},
+ {"any": "vmovdqa32 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W0 6F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqa32 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W0 7F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqa64 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W1 6F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqa64 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 7F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu32 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F3.0F.W0 6F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu32 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F.W0 7F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu64 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F3.0F.W1 6F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu64 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F.W1 7F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovhlps W:xmm, xmm[127:64], xmm[127:64]" , "op": "[RVM] EVEX.128.NP.0F.W0 12 /r" , "tt": "none" , "vl": "no"},
+ {"any": "vmovhpd W:m64, xmm[127:64]" , "op": "[MR ] EVEX.128.66.0F.W1 17 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovhpd W:xmm, xmm[63:0], m64" , "op": "[RVM] EVEX.128.66.0F.W1 16 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovhps W:m64, xmm[127:64]" , "op": "[MR ] EVEX.128.NP.0F.W0 17 /r" , "tt": "t2" , "vl": "no"},
+ {"any": "vmovhps W:xmm, xmm[63:0], m64" , "op": "[RVM] EVEX.128.NP.0F.W0 16 /r" , "tt": "t2" , "vl": "no"},
+ {"any": "vmovlhps W:xmm, xmm[63:0], xmm[63:0]" , "op": "[RVM] EVEX.128.NP.0F.W0 16 /r" , "tt": "none" , "vl": "no"},
+ {"any": "vmovlpd W:m64, xmm[63:0]" , "op": "[MR ] EVEX.128.66.0F.W1 13 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovlpd W:xmm, xmm[127:64], m64" , "op": "[RVM] EVEX.128.66.0F.W1 12 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovlps W:m64, xmm[63:0]" , "op": "[MR ] EVEX.128.NP.0F.W0 13 /r" , "tt": "t2" , "vl": "no"},
+ {"any": "vmovlps W:xmm, xmm[127:64], m64" , "op": "[RVM] EVEX.128.NP.0F.W0 12 /r" , "tt": "t2" , "vl": "no"},
+ {"any": "vmovntdq W:mxyz, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W0 E7 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovntdqa W:xyz, mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 2A /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovntpd W:mxyz, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 2B /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovntps W:mxyz, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W0 2B /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovq W:r64/m64, xmm[63:0]" , "op": "[MR ] EVEX.128.66.0F.W1 7E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovq W:xmm[63:0], r64/m64" , "op": "[RM ] EVEX.128.66.0F.W1 6E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovq W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] EVEX.128.F3.0F.W1 7E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovq W:xmm[63:0]/m64, xmm[63:0]" , "op": "[MR ] EVEX.128.66.0F.W1 D6 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsd W:m64, xmm[63:0]" , "op": "[MR ] EVEX.LIG.F2.0F.W1 11 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsd W:xmm[63:0] {kz}, m64" , "op": "[MR ] EVEX.LIG.F2.0F.W1 10 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsd W:xmm {kz}, xmm[127:64], xmm[63:0]" , "op": "[MVR] EVEX.LIG.F2.0F.W1 11 /r" , "tt": "none" , "vl": "no"},
+ {"any": "vmovsd W:xmm {kz}, xmm[127:64], xmm[63:0]" , "op": "[RVM] EVEX.LIG.F2.0F.W1 10 /r" , "tt": "none" , "vl": "no"},
+ {"any": "vmovshdup W:xyz {kz}, xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F.W0 16 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovsldup W:xyz {kz}, xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F.W0 12 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovss W:m32, xmm[31:0]" , "op": "[MR ] EVEX.LIG.F3.0F.W0 11 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovss W:xmm[31:0] {kz}, m32" , "op": "[MR ] EVEX.LIG.F3.0F.W0 10 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovss W:xmm {kz}, xmm[127:32], xmm[31:0]" , "op": "[MVR] EVEX.LIG.F3.0F.W0 11 /r" , "tt": "none" , "vl": "no"},
+ {"any": "vmovss W:xmm {kz}, xmm[127:32], xmm[31:0]" , "op": "[RVM] EVEX.LIG.F3.0F.W0 10 /r" , "tt": "none" , "vl": "no"},
+ {"any": "vmovupd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W1 10 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovupd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 11 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovups W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.0F.W0 10 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovups W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.0F.W0 11 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmulpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 59 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vmulps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.0F.W0 59 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vmulsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 59 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmulss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 59 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpabsd W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 1E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpabsq W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 1F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpaddd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 FE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpaddq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 D4 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpandd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 DB /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpandnd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 DF /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpandnq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 DF /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpandq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 DB /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpblendmd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 64 /r" , "tt": "fv" , "vl": "xy", "k": "blend"},
+ {"any": "vpblendmq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 64 /r" , "tt": "fv" , "vl": "xy", "k": "blend"},
+ {"any": "vpbroadcastd W:xyz {kz}, r32[31:0]" , "op": "[RM ] EVEX.xyz.66.0F38.W0 7C /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpbroadcastd W:xyz {kz}, xmm[31:0]/m32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 58 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpbroadcastq W:xyz {kz}, r64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 7C /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpbroadcastq W:xyz {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 59 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpcmpd W:k {k}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 1F /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpeqd W:k {k}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 76 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpeqq W:k {k}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 29 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpgtd W:k {k}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 66 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpgtq W:k {k}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 37 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpq W:k {k}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 1F /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpud W:k {k}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 1E /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpuq W:k {k}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 1E /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcompressd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F38.W0 8B /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpcompressq W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F38.W1 8B /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpermd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "[RVM] EVEX.256.66.0F38.W0 36 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "[RVM] EVEX.512.66.0F38.W0 36 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermi2d X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 76 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermi2pd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 77 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermi2ps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 77 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermi2q X:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 76 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermilpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 0D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermilpd W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 05 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermilps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 0C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermilps W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 04 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "[RVM] EVEX.256.66.0F38.W1 16 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "[RVM] EVEX.512.66.0F38.W1 16 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermpd W:ymm {kz}, ymm/m256/b64, imm8" , "op": "[RM ] EVEX.256.66.0F3A.W1 01 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermpd W:zmm {kz}, zmm/m512/b64, imm8" , "op": "[RM ] EVEX.512.66.0F3A.W1 01 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "[RVM] EVEX.256.66.0F38.W0 16 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "[RVM] EVEX.512.66.0F38.W0 16 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "[RVM] EVEX.256.66.0F38.W1 36 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "[RVM] EVEX.512.66.0F38.W1 36 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermq W:ymm {kz}, ymm/m256/b64, imm8" , "op": "[RM ] EVEX.256.66.0F3A.W1 00 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermq W:zmm {kz}, zmm/m512/b64, imm8" , "op": "[RM ] EVEX.512.66.0F3A.W1 00 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermt2d X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 7E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermt2pd X:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 7F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermt2ps X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 7F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpermt2q X:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 7E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpexpandd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 89 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpexpandq W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 89 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherdd X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W0 90" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherdd X:ymm {k}, vm32y" , "op": "[RM ] EVEX.256.66.0F38.W0 90" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherdd X:zmm {k}, vm32z" , "op": "[RM ] EVEX.512.66.0F38.W0 90" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherdq X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W1 90" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherdq X:ymm {k}, vm32x" , "op": "[RM ] EVEX.256.66.0F38.W1 90" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherdq X:zmm {k}, vm32y" , "op": "[RM ] EVEX.512.66.0F38.W1 90" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherqd X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W0 91" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherqd X:xmm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W0 91" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherqd X:ymm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W0 91" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherqq X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W1 91" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherqq X:ymm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W1 91" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpgatherqq X:zmm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W1 91" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpmaxsd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 3D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmaxsq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 3D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmaxud W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 3F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmaxuq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 3F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpminsd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 39 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpminsq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 39 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpminud W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 3B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpminuq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 3B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmovdb W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 31 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovdw W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 33 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 32 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "[MR ] EVEX.256.F3.0F38.W0 32 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "[MR ] EVEX.512.F3.0F38.W0 32 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovqd W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 35 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovqw W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 34 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovsdb W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 21 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovsdw W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 23 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovsqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 22 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovsqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "[MR ] EVEX.256.F3.0F38.W0 22 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovsqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "[MR ] EVEX.512.F3.0F38.W0 22 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovsqd W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 25 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovsqw W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 24 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovsxbd W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 21 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovsxbq W:xmm {kz}, xmm[15:0]/m16" , "op": "[RM ] EVEX.128.66.0F38.WIG 22 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovsxbq W:ymm {kz}, xmm[31:0]/m32" , "op": "[RM ] EVEX.256.66.0F38.WIG 22 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovsxbq W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.WIG 22 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovsxdq W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.W0 25 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovsxwd W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 23 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovsxwq W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 24 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovusdb W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 11 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovusdw W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 13 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovusqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 12 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovusqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "[MR ] EVEX.256.F3.0F38.W0 12 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovusqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "[MR ] EVEX.512.F3.0F38.W0 12 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovusqd W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 15 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovusqw W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 14 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovzxbd W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 31 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmovzxbq W:xmm {kz}, xmm[15:0]/m16" , "op": "[RM ] EVEX.128.66.0F38.WIG 32 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovzxbq W:ymm {kz}, xmm[31:0]/m32" , "op": "[RM ] EVEX.256.66.0F38.WIG 32 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovzxbq W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.WIG 32 /r" , "tt": "ovm" , "vl": "xy"},
+ {"any": "vpmovzxdq W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.W0 35 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovzxwd W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 33 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovzxwq W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 34 /r" , "tt": "qvm" , "vl": "xy"},
+ {"any": "vpmuldq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 28 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmulld W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 40 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmuludq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 F4 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpord W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 EB /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vporq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 EB /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprold W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /1 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprolq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 72 /1 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprolvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 15 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprolvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 15 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprord W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /0 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprorq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 72 /0 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprorvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 14 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vprorvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 14 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpscatterdd W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A0 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterdd W:vm32y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W0 A0 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterdd W:vm32z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W0 A0 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterdq W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A0 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterdq W:vm32x {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A0 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterdq W:vm32y {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A0 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterqd W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A1 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterqd W:vm64y {k}, xmm" , "op": "[MR ] EVEX.256.66.0F38.W0 A1 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterqd W:vm64z {k}, ymm" , "op": "[MR ] EVEX.512.66.0F38.W0 A1 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterqq W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A1 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterqq W:vm64y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A1 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpscatterqq W:vm64z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A1 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpshufd W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F.W0 70 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpslld W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W0 F2 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpslld W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /6 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsllq W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W1 F3 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsllq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 73 /6 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsllvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 47 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsllvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 47 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsrad W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W0 E2 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsrad W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /4 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsraq W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W1 E2 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsraq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 72 /4 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsravd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 46 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsravq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 46 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsrld W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W0 D2 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsrld W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /2 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsrlq W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W1 D3 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsrlq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 73 /2 ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsrlvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 45 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsrlvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 45 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsubd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 FA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpsubq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 FB /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpternlogd X:xyz {kz}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 25 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpternlogq X:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 25 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vptestmd W:k {k}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vptestmq W:k {k}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vptestnmd W:k {k}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vptestnmq W:k {k}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.F3.0F38.W1 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpunpckhdq W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 6A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpunpckhqdq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 6D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpunpckldq W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 62 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpunpcklqdq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 6C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpxord W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 EF /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpxorq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 EF /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrcp14pd W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 4C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrcp14ps W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 4C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrcp14sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64" , "op": "[RVM] EVEX.LIG.66.0F38.W1 4D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrcp14ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] EVEX.LIG.66.0F38.W0 4D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrndscalepd W:xyz {kz}, xyz/mxyz/b64, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 09 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrndscaleps W:xyz {kz}, xyz/mxyz/b32, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 08 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrndscalesd W:xmm {kz},xmm[127:64],xmm[63:0]/m64,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W1 0B /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrndscaless W:xmm {kz},xmm[127:32],xmm[31:0]/m32,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W0 0A /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrsqrt14pd W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 4E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrsqrt14ps W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 4E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrsqrt14sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64" , "op": "[RVM] EVEX.LIG.66.0F38.W1 4F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrsqrt14ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] EVEX.LIG.66.0F38.W0 4F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vscalefpd W:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 2C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vscalefps W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 2C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vscalefsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.66.0F38.W1 2D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vscalefss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.66.0F38.W0 2D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vscatterdpd W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A2 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterdpd W:vm32x {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A2 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterdpd W:vm32y {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A2 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterdps W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A2 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterdps W:vm32y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W0 A2 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterdps W:vm32z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W0 A2 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterqpd W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A3" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterqpd W:vm64y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A3" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterqpd W:vm64z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A3" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterqps W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A3" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterqps W:vm64y {k}, xmm" , "op": "[MR ] EVEX.256.66.0F38.W0 A3" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vscatterqps W:vm64z {k}, ymm" , "op": "[MR ] EVEX.512.66.0F38.W0 A3" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vshuff32x4 W:ymm {kz}, ymm, ymm/m256/b32, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 23 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshuff32x4 W:zmm {kz}, zmm, zmm/m512/b32, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 23 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshuff64x2 W:ymm {kz}, ymm, ymm/m256/b64, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 23 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshuff64x2 W:zmm {kz}, zmm, zmm/m512/b64, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 23 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshufi32x4 W:ymm {kz}, ymm, ymm/m256/b32, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 43 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshufi32x4 W:zmm {kz}, zmm, zmm/m512/b32, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 43 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshufi64x2 W:ymm {kz}, ymm, ymm/m256/b64, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 43 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshufi64x2 W:zmm {kz}, zmm, zmm/m512/b64, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 43 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshufpd W:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F.W1 C6 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vshufps W:xyz {kz}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.0F.W0 C6 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsqrtpd W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 51 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsqrtps W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.0F.W0 51 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsqrtsd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 51 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vsqrtss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 51 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vsubpd W:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsubps W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.0F.W0 5C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsubsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5C /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vsubss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5C /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vucomisd R:xmm[63:0], xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.66.0F.W1 2E /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vucomiss R:xmm[31:0], xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.NP.0F.W0 2E /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vunpckhpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 15 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vunpckhps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 15 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vunpcklpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 14 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vunpcklps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 14 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD CRYPTO_HASH", "ext": "AVX512_F VAES", "instructions": [
+ {"any": "vaesdec W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DE /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vaesdeclast W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DF /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vaesenc W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DC /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vaesenclast W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DD /r" , "tt": "fvm" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_F GFNI", "instructions": [
+ {"any": "vgf2p8affineinvqb W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 CF /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vgf2p8affineqb W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 CE /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vgf2p8mulb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 CF /r" , "tt": "fvm" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_F VPCLMULQDQ", "instructions": [
+ {"any": "vpclmulqdq W:xyz, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.WIG 44 /r ib" , "tt": "fvm" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_DQ", "instructions": [
+ {"any": "vandnpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 55 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vandnps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.W0 55 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vandpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 54 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vandps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 54 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vbroadcastf32x2 W:ymm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.256.66.0F38.W0 19 /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcastf32x2 W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.W0 19 /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcastf32x8 W:zmm {kz}, m256" , "op": "[RM ] EVEX.512.66.0F38.W0 1B /r" , "tt": "t8" , "vl": "xy"},
+ {"any": "vbroadcastf64x2 W:ymm {kz}, m128" , "op": "[RM ] EVEX.256.66.0F38.W1 1A /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcastf64x2 W:zmm {kz}, m128" , "op": "[RM ] EVEX.512.66.0F38.W1 1A /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcasti32x2 W:xmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.128.66.0F38.W0 59 /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcasti32x2 W:ymm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.256.66.0F38.W0 59 /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcasti32x2 W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.W0 59 /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcasti32x8 W:zmm {kz}, m256" , "op": "[RM ] EVEX.512.66.0F38.W0 5B /r" , "tt": "t8" , "vl": "xy"},
+ {"any": "vbroadcasti64x2 W:ymm {kz}, m128" , "op": "[RM ] EVEX.256.66.0F38.W1 5A /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vbroadcasti64x2 W:zmm {kz}, m128" , "op": "[RM ] EVEX.512.66.0F38.W1 5A /r" , "tt": "t2" , "vl": "xy"},
+ {"any": "vcvtpd2qq W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 7B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtpd2uqq W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 79 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtps2qq W:xyz {kz}, xxy/mxxy/b32 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W0 7B /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtps2uqq W:xyz {kz}, xxy/mxxy/b32 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W0 79 /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtqq2pd W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F3.0F.W1 E6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtqq2ps W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.NP.0F.W1 5B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttpd2uqq W:xyz {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W1 78 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttps2qq W:xyz {kz}, xxy/mxxy/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W0 7A /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvttps2uqq W:xyz {kz}, xxy/mxxy/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W0 78 /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtuqq2pd W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F3.0F.W1 7A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtuqq2ps W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F2.0F.W1 7A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vextractf32x8 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 1B /r ib" , "tt": "t8" , "vl": "xy"},
+ {"any": "vextractf64x2 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W1 19 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vextractf64x2 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 19 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vextracti32x8 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 3B /r ib" , "tt": "t8" , "vl": "xy"},
+ {"any": "vextracti64x2 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W1 39 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vextracti64x2 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 39 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vfpclasspd W:k {k}, xyz/mxyz/b64, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 66 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vfpclassps W:k {k}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 66 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vfpclasssd W:k {k}, xmm[63:0]/m64, imm8" , "op": "[RM ] EVEX.LIG.66.0F3A.W1 67 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"},
+ {"any": "vfpclassss W:k {k}, xmm[31:0]/m32, imm8" , "op": "[RM ] EVEX.LIG.66.0F3A.W0 67 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"},
+ {"any": "vinsertf32x8 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 1A /r ib" , "tt": "t8" , "vl": "xy"},
+ {"any": "vinsertf64x2 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 18 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vinsertf64x2 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 18 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vinserti32x8 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 3A /r ib" , "tt": "t8" , "vl": "xy"},
+ {"any": "vinserti64x2 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 38 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vinserti64x2 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 38 /r ib" , "tt": "t2" , "vl": "xy"},
+ {"any": "vorpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 56 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vorps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F.W0 56 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpextrd W:r32/m32, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.W0 16 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpextrq W:r64/m64, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.W1 16 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpinsrd W:xmm {kz}, xmm, r32/m32, imm8" , "op": "[RVM] EVEX.128.66.0F3A.W0 22 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpinsrq W:xmm {kz}, xmm, r64/m64, imm8" , "op": "[RVM] EVEX.128.66.0F3A.W1 22 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpmovd2m W:k, xyz" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 39 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovm2d W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 38 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovm2q W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 38 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovq2m W:k, xyz" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 39 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmullq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 40 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrangepd W:xyz {kz}, xyz, xyz/mxyz/b64, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 50 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrangeps W:xyz {kz}, xyz, xyz/mxyz/b32, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 50 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrangesd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64,imm8 {sae}" , "op": "[RVM] EVEX.LIG.66.0F3A.W1 51 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrangess W:xmm {kz}, xmm[127:32], xmm[31:0]/m32,imm8 {sae}" , "op": "[RVM] EVEX.LIG.66.0F3A.W0 51 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vreducepd W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 56 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vreduceps W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 56 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vreducesd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W1 57 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vreducess W:xmm {kz}, xmm[127:32], xmm[31:0]/m32, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W0 57 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vxorpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 57 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vxorps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 57 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_BW", "instructions": [
+ {"any": "vdbpsadbw W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 42 /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu16 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F2.0F.W1 6F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu16 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F2.0F.W1 7F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu8 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F2.0F.W0 6F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vmovdqu8 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F2.0F.W0 7F /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpabsb W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38 1C /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpabsw W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38 1D /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpackssdw W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 6B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpacksswb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 63 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpackusdw W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 2B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpackuswb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 67 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpaddb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG FC /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpaddsb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG EC /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpaddsw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG ED /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpaddusb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG DC /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpaddusw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG DD /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpaddw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG FD /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpalignr W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.WIG 0F /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpavgb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E0 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpavgw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E3 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpblendmb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 66 /r" , "tt": "fvm" , "vl": "xy", "k": "blend"},
+ {"any": "vpblendmw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 66 /r" , "tt": "fvm" , "vl": "xy", "k": "blend"},
+ {"any": "vpbroadcastb W:xyz {kz}, r32[7:0]" , "op": "[RM ] EVEX.xyz.66.0F38.W0 7A /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpbroadcastb W:xyz {kz}, xmm[7:0]/m8" , "op": "[RM ] EVEX.xyz.66.0F38.W0 78 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpbroadcastw W:xyz {kz}, r32[15:0]" , "op": "[RM ] EVEX.xyz.66.0F38.W0 7B /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpbroadcastw W:xyz {kz}, xmm[15:0]/m16" , "op": "[RM ] EVEX.xyz.66.0F38.W0 79 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpcmpb W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 3F /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpeqb W:k {k}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 74 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpeqw W:k {k}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 75 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpgtb W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 64 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpgtw W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 65 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpub W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 3E /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpuw W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 3E /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpcmpw W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 3F /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpermi2w X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 75 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpermt2w X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 7D /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpermw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 8D /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpextrb W:r32[7:0]/m8 , xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.WIG 14 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpextrw W:r32[15:0], xmm, imm8" , "op": "[RM ] EVEX.128.66.0F.WIG C5 /r ib" , "tt": "none" , "vl": "no"},
+ {"any": "vpextrw W:r32[15:0]/m16, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.WIG 15 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpinsrb W:xmm {kz}, xmm, r32[7:0]/m8, imm8" , "op": "[RVM] EVEX.128.66.0F3A.WIG 20 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpinsrw W:xmm {kz}, xmm, r32[15:0]/m16, imm8" , "op": "[RVM] EVEX.128.66.0F.WIG C4 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vpmaddubsw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG 04 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmaddwd W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG F5 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmaxsb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG 3C /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmaxsw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG EE /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmaxub W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG DE /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmaxuw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG 3E /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpminsb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG 38 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpminsw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG EA /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpminub W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F DA /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpminuw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38 3A /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmovb2m W:k, xyz" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 29 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovm2b W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 28 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovm2w W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 28 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovswb W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 20 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovsxbw W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 20 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovuswb W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 10 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovw2m W:k, xyz" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 29 /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpmovwb W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 30 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmovzxbw W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 30 /r" , "tt": "hvm" , "vl": "xy"},
+ {"any": "vpmulhrsw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG 0B /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmulhuw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E4 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmulhw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E5 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmullw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG D5 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsadbw W:xyz, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG F6 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshufb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG 00 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshufhw W:xyz {kz}, xyz/mxyz, imm8" , "op": "[RM ] EVEX.xyz.F3.0F.WIG 70 /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshuflw W:xyz {kz}, xyz/mxyz, imm8" , "op": "[RM ] EVEX.xyz.F2.0F.WIG 70 /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpslldq W:xyz, xyz/mxyz, imm8" , "op": "[VM ] EVEX.xyz.66.0F.WIG 73 /7 ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsllvw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 12 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsllw W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.WIG F1 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsllw W:xyz {kz}, xyz/mxyz, imm8" , "op": "[VM ] EVEX.xyz.66.0F.WIG 71 /6 ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsravw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 11 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsraw W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.WIG E1 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsraw W:xyz {kz}, xyz/mxyz, imm8" , "op": "[VM ] EVEX.xyz.66.0F.WIG 71 /4 ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsrldq W:xyz, xyz/mxyz, imm8" , "op": "[VM ] EVEX.xyz.66.0F.WIG 73 /3 ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsrlvw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 10 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsrlw W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.WIG D1 /r" , "tt": "m128" , "vl": "xy"},
+ {"any": "vpsrlw W:xyz {kz}, xyz/mxyz, imm8" , "op": "[VM ] EVEX.xyz.66.0F.WIG 71 /2 ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsubb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG F8 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsubsb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E8 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsubsw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E9 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsubusb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG D8 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsubusw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG D9 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpsubw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG F9 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vptestmb W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 26 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vptestmw W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 26 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vptestnmb W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 26 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vptestnmw W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F38.W1 26 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"},
+ {"any": "vpunpckhbw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 68 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpunpckhwd W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 69 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpunpcklbw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 60 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpunpcklwd W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 61 /r" , "tt": "fvm" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_CD", "instructions": [
+ {"any": "vpbroadcastmb2q W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 2A /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpbroadcastmw2d W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 3A /r" , "tt": "none" , "vl": "xy"},
+ {"any": "vpconflictd W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 C4 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpconflictq W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W1 C4 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vplzcntd W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 44 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vplzcntq W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 44 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_IFMA", "instructions": [
+ {"any": "vpmadd52luq X:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B4 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpmadd52huq X:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B5 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_VPOPCNTDQ", "instructions": [
+ {"any": "vpopcntd W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 55 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpopcntq W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 55 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_VBMI", "instructions": [
+ {"any": "vpermb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 8D /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpermi2b X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 75 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpermt2b X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 7D /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpmultishiftqb W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 83 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_VBMI2", "instructions": [
+ {"any": "vpcompressb W:xyz/mxyz {kz}, xyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 63 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpcompressw W:xyz/mxyz {kz}, xyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 63 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpexpandb W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 62 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpexpandw W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 62 /r" , "tt": "t1s" , "vl": "xy"},
+ {"any": "vpshldd W:xyz {kz}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 71 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshldq W:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 71 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshldvd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 71 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshldvq X:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 71 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshldvw X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 70 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshldw W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 70 /r ib" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshrdd W:xyz {kz}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 73 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshrdq W:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 73 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshrdvd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 73 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshrdvq X:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 73 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpshrdvw X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 72 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshrdw W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 72 /r ib" , "tt": "fvm" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_VNNI", "instructions": [
+ {"any": "vpdpbusd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 50 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpdpbusds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 51 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpdpwssd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 52 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vpdpwssds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 53 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_BITALG", "instructions": [
+ {"any": "vpopcntb W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 54 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpopcntw W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 54 /r" , "tt": "fvm" , "vl": "xy"},
+ {"any": "vpshufbitqmb W:k {k}, xyz, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 8F /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_VP2INTERSECT", "instructions": [
+ {"any": "vp2intersectd W:k, W:k+1, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 68 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vp2intersectq W:k, W:k+1, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.F2.0F38.W1 68 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_BF16", "instructions": [
+ {"any": "vcvtne2ps2bf16 W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 72 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtneps2bf16 W:xxy {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 72 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vdpbf16ps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 52 /r" , "tt": "fv" , "vl": "xy"}
+ ]},
+
+ {"category": "AVX512 SIMD", "ext": "AVX512_FP16", "instructions": [
+ {"any": "vaddph W:xyz {kz}, ~xyz, ~xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 58 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vaddsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 58 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcmpph W:k {k}, xyz, xyz/mxyz/b16, imm8 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F3A.W0 C2 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vcmpsh W:k {k}, xmm[15:0], xmm[15:0]/m16, imm8 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F3A.W0 C2 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"},
+ {"any": "vcomish R:xmm[15:0], xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.NP.MAP5.W0 2F /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcvtdq2ph W:xxy {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 5B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtpd2ph W:xxx {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W1 5A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtph2dq W:xyz {kz}, xxy/mxxy/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 5B /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtph2pd W:xyz {kz}, xxx/mxxx/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 5A /r" , "tt": "qv" , "vl": "xy"},
+ {"any": "vcvtph2psx W:xyz {kz}, xxy/mxxy/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 13 /r" , "tt": "qv" , "vl": "xy"},
+ {"any": "vcvtph2qq W:xyz {kz}, xxx/mxxx/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7B /r" , "tt": "qv" , "vl": "xy"},
+ {"any": "vcvtph2udq W:xyz {kz}, xxy/mxxy/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 79 /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvtph2uqq W:xyz {kz}, xxx/mxxx/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 79 /r" , "tt": "qv" , "vl": "xy"},
+ {"any": "vcvtph2uw W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtph2w W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtps2phx W:xxy {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 1D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtqq2ph W:xmm {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W1 5B /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtsd2sh W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.MAP5.W1 5A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsh2sd W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsh2si W:ry, xmm[15:0]/m16 {er}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 2D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsh2ss W:xmm {kz}, xmm, xmm/m16 {sae}" , "op": "[RVM] EVEX.LIG.NP.MAP6.W0 13 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsh2usi W:ry, xmm[15:0]/m16 {er}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 79 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtsi2sh W:xmm, xmm, ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.Wy 2A /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtss2sh W:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.NP.MAP5.W0 1D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvttph2dq W:xyz {kz}, xxy/mxxy/b16 {sae}" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 5B /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvttph2qq W:xyz {kz}, xxx/mxxx/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7A /r" , "tt": "qv" , "vl": "xy"},
+ {"any": "vcvttph2udq W:xyz {kz}, xxy/mxxy/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 78 /r" , "tt": "hv" , "vl": "xy"},
+ {"any": "vcvttph2uqq W:xyz {kz}, xxx/mxxx/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 78 /r" , "tt": "qv" , "vl": "xy"},
+ {"any": "vcvttph2uw W:xyz {kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 7C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttph2w W:xyz {kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvttsh2si W:ry, xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 2C /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvttsh2usi W:ry, xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 78 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtudq2ph W:xxy {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 7A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtuqq2ph W:xxx {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F2.MAP5.W1 7A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtusi2sh W:xmm, xmm, ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.Wy 7B /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vcvtuw2ph W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vcvtw2ph W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vdivph W:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vdivsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfcmaddcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F2.MAP6.W0 56 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfcmaddcsh x:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F2.MAP6.W0 57 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfcmulcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F2.MAP6.W0 D6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfcmulcsh x:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F2.MAP6.W0 D7 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 98 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd132sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 99 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 A8 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd213sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 A9 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmadd231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 B8 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmadd231sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 B9 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmaddcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F3.MAP6.W0 56 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddcsh x:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP6.W0 57 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmaddsub132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 96 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 A6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmaddsub231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 B6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 9A /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub132sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 9B /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 AA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub213sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 AB /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsub231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 BA /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsub231sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 BB /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfmsubadd132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 97 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 A7 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmsubadd231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 B7 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmulcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F3.MAP6.W0 D6 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfmulcsh X:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP6.W0 D7 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 9C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd132sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 9D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 AC /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd213sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 AD /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmadd231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 BC /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmadd231sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 BD /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 9E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub132sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 9F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 AE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub213sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 AF /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfnmsub231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 BE /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vfnmsub231sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 BF /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vfpclassph W:k {k}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 66 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"},
+ {"any": "vfpclasssh W:k {k}, xmm[15:0]/m16, imm8" , "op": "[RM ] EVEX.LIG.NP.0F3A.W0 67 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"},
+ {"any": "vgetexpph W:xyz {kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 42 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vgetexpsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.66.MAP6.W0 43 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vgetmantph W:xyz {kz}, xyz/mxyz/b16, imm8 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 26 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vgetmantsh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,imm8 {sae}" , "op": "[RM ] EVEX.LIG.NP.0F3A.W0 27 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmaxph W:xyz {kz}, xyz, xyz/mxyz/b16 {sae}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5F /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vmaxsh W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vminph W:xyz {kz}, xyz, xyz/mxyz/b16 {sae}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5D /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vminsh W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsh W:m16, xmm[15:0]" , "op": "[MR ] EVEX.LIG.F3.MAP5.W0 11 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsh W:xmm[15:0] {kz}, m16" , "op": "[RM ] EVEX.LIG.F3.MAP5.W0 10 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsh W:xmm {kz}, xmm[127:16], xmm[15:0]" , "op": "[MVR] EVEX.LIG.F3.MAP5.W0 11 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovsh W:xmm {kz}, xmm[127:16], xmm[15:0]" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 10 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovw W:r32[15:0]/m16, xmm[15:0]" , "op": "[MR ] EVEX.128.66.MAP5.WIG 7E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmovw W:xmm[15:0] {kz}, r32[15:0]/m16" , "op": "[RM ] EVEX.128.66.MAP5.WIG 6E /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vmulph W:xyz {kz}, ~xyz, ~xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 59 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vmulsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 59 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrcpph W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 4C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrcpsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 4D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vreduceph W:xyz {kz}, xyz/mxyz/b16, imm8 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 56 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vreducesh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16,imm8 {sae}", "op": "[RVM] EVEX.LIG.NP.0F3A.W0 57 /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrndscaleph W:xyz {kz}, xyz/mxyz/b16, imm8 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 08 /r ib" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrndscalesh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,imm8 {sae}", "op": "[RVM] EVEX.LIG.NP.0F3A.W0 0A /r ib" , "tt": "t1s" , "vl": "no"},
+ {"any": "vrsqrtph W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 4E /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vrsqrtsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 4F /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vscalefph W:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 2C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vscalefsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 2D /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vsqrtph W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 51 /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsqrtsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 51 /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vsubph W:xyz {kz}, ~xyz, ~xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5C /r" , "tt": "fv" , "vl": "xy"},
+ {"any": "vsubsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5C /r" , "tt": "t1s" , "vl": "no"},
+ {"any": "vucomish R:xmm[15:0], xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.NP.MAP5.W0 2E /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vaddnepbf16 W:xyz{kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 58 /r" , "tt": "fv"},
+ {"any": "vcmppbf16 W:k {k}, xyz, xyz/mxyz/b16, imm8" , "op": "[RVM] EVEX.xyz.F2.0F3A.W0 C2 /r ib" , "tt": "fv" , "k": "zeroing"},
+ {"any": "vcomsbf16 R:xmm, xmm/m16" , "op": "[RM ] EVEX.LIG.66.MAP5.W0 2F /r" , "tt": "t1s" , "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"},
+ {"any": "vdivnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5E /r" , "tt": "fv"},
+ {"any": "vfmadd132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 98 /r" , "tt": "fv"},
+ {"any": "vfmadd213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 A8 /r" , "tt": "fv"},
+ {"any": "vfmadd231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 B8 /r" , "tt": "fv"},
+ {"any": "vfmsub132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 9A /r" , "tt": "fv"},
+ {"any": "vfmsub213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 AA /r" , "tt": "fv"},
+ {"any": "vfmsub231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 BA /r" , "tt": "fv"},
+ {"any": "vfnmadd132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 9C /r" , "tt": "fv"},
+ {"any": "vfnmadd213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 AC /r" , "tt": "fv"},
+ {"any": "vfnmadd231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 BC /r" , "tt": "fv"},
+ {"any": "vfnmsub132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 9E /r" , "tt": "fv"},
+ {"any": "vfnmsub213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 AE /r" , "tt": "fv"},
+ {"any": "vfnmsub231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 BE /r" , "tt": "fv"},
+ {"any": "vfpclasspbf16 W:k {k}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 66 /r ib" , "tt": "fv" , "k": "zeroing"},
+ {"any": "vgetexppbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 42 /r" , "tt": "fv"},
+ {"any": "vgetmantpbf16 W:xyz {kz}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 26 /r ib" , "tt": "fv"},
+ {"any": "vmaxpbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5F /r" , "tt": "fv"},
+ {"any": "vminpbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5D /r" , "tt": "fv"},
+ {"any": "vmulnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 59 /r" , "tt": "fv"},
+ {"any": "vrcppbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.NP.MAP6.W0 4C /r" , "tt": "fv"},
+ {"any": "vreducenepbf16 W:xyz {kz}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 56 /r ib" , "tt": "fv"},
+ {"any": "vrndscalenepbf16 W:xyz {kz}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 08 /r ib" , "tt": "fv"},
+ {"any": "vrsqrtpbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.NP.MAP6.W0 4E /r" , "tt": "fv"},
+ {"any": "vscalefpbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 2C /r" , "tt": "fv"},
+ {"any": "vsqrtnepbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 51 /r " , "tt": "fv"},
+ {"any": "vsubnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5C /r" , "tt": "fv"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vcomxsd R:xmm[63:0], R:xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F3.0F.W1 2F /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcomxsh R:xmm[15:0], R:xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F2.MAP5.W0 2F /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"},
+ {"any": "vcomxss R:xmm[31:0], R:xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F2.0F.W0 2F /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"},
+ {"any": "vucomxsd R:xmm[63:0], R:xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F3.0F.W1 2E /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"},
+ {"any": "vucomxsh R:xmm[15:0], R:xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F2.MAP5.W0 2E /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"},
+ {"any": "vucomxss R:xmm[31:0], R:xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F2.0F.W0 2E /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vcvt2ps2phx W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 67 /r" , "tt": "fv"},
+ {"any": "vcvtbiasph2bf8 W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 74 /r" , "tt": "fv"},
+ {"any": "vcvtbiasph2bf8s W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 74 /r" , "tt": "fv"},
+ {"any": "vcvtbiasph2hf8 W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 18 /r" , "tt": "fv"},
+ {"any": "vcvtbiasph2hf8s W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 1B /r" , "tt": "fv"},
+ {"any": "vcvthf82ph W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 1E /r" , "tt": "hv"},
+ {"any": "vcvtne2ph2bf8 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 74 /r" , "tt": "fv"},
+ {"any": "vcvtne2ph2bf8s W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.MAP5.W0 74 /r" , "tt": "fv"},
+ {"any": "vcvtne2ph2hf8 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.MAP5.W0 18 /r" , "tt": "fv"},
+ {"any": "vcvtne2ph2hf8s W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.MAP5.W0 1B /r" , "tt": "fv"},
+ {"any": "vcvtneph2bf8 W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 74 /r" , "tt": "fv"},
+ {"any": "vcvtneph2bf8s W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 74 /r" , "tt": "fv"},
+ {"any": "vcvtneph2hf8 W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 18 /r" , "tt": "fv"},
+ {"any": "vcvtneph2hf8s W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 1B /r" , "tt": "fv"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vdpphps X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 52 /r" , "tt": "fv"},
+ {"any": "vmpsadbw W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.F3.0F3A.W0 42 /r ib" , "tt": "fv"},
+ {"any": "vpdpbssd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 50 /r" , "tt": "fv"},
+ {"any": "vpdpbssds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 51 /r" , "tt": "fv"},
+ {"any": "vpdpbsud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 50 /r" , "tt": "fv"},
+ {"any": "vpdpbsuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 51 /r" , "tt": "fv"},
+ {"any": "vpdpbuud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 50 /r" , "tt": "fv"},
+ {"any": "vpdpbuuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 51 /r" , "tt": "fv"},
+ {"any": "vpdpwsud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 D2 /r" , "tt": "fv"},
+ {"any": "vpdpwsuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 D3 /r" , "tt": "fv"},
+ {"any": "vpdpwusd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 D2 /r" , "tt": "fv"},
+ {"any": "vpdpwusds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 D3 /r" , "tt": "fv"},
+ {"any": "vpdpwuud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 D2 /r" , "tt": "fv"},
+ {"any": "vpdpwuuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 D3 /r" , "tt": "fv"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vminmaxnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16, imm8" , "op": "[RVM] EVEX.xyz.F2.0F3A.W0 52 /r ib" , "tt": "fv"},
+ {"any": "vminmaxpd W:xyz {kz}, xyz, xyz/mxyz/b64 {sae}, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 52 /r ib" , "tt": "fv"},
+ {"any": "vminmaxph W:xyz {kz}, xyz, xyz/mxyz/b16 {sae}, imm8" , "op": "[RVM] EVEX.xyz.NP.0F3A.W0 52 /r ib" , "tt": "fv"},
+ {"any": "vminmaxps W:xyz {kz}, xyz, xyz/mxyz/b32 {sae}, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 52 /r ib" , "tt": "fv"},
+ {"any": "vminmaxsd W:xmm {kz}, xmm, xmm/m64 {sae}, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W1 53 /r ib" , "tt": "t1s"},
+ {"any": "vminmaxsh W:xmm {kz}, xmm, xmm/m16 {sae}, imm8" , "op": "[RVM] EVEX.LIG.NP.0F3A.W0 53 /r ib" , "tt": "t1s"},
+ {"any": "vminmaxss W:xmm {kz}, xmm, xmm/m32 {sae}, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W0 53 /r ib" , "tt": "t1s"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vcvtnebf162ibs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 69 /r" , "tt": "fv"},
+ {"any": "vcvtnebf162iubs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 6B /r" , "tt": "fv"},
+ {"any": "vcvttnebf162ibs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 68 /r" , "tt": "fv"},
+ {"any": "vcvttnebf162iubs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 6A /r" , "tt": "fv"},
+ {"any": "vcvttpd2dqs W:xxy{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W1 6D /r" , "tt": "fv"},
+ {"any": "vcvttpd2qqs W:xyz{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W1 6D /r" , "tt": "fv"},
+ {"any": "vcvttpd2udqs W:xxy{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W1 6C /r" , "tt": "fv"},
+ {"any": "vcvttpd2uqqs W:xyz{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W1 6C /r" , "tt": "fv"},
+ {"any": "vcvtph2ibs W:xyz{kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 69 /r" , "tt": "fv"},
+ {"any": "vcvtph2iubs W:xyz{kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6B /r" , "tt": "fv"},
+ {"any": "vcvttph2ibs W:xyz{kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 68 /r" , "tt": "fv"},
+ {"any": "vcvttph2iubs W:xyz{kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6A /r" , "tt": "fv"},
+ {"any": "vcvttps2dqs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6D /r" , "tt": "fv"},
+ {"any": "vcvtps2ibs W:xyz{kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 69 /r" , "tt": "fv"},
+ {"any": "vcvtps2iubs W:xyz{kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 6B /r" , "tt": "fv"},
+ {"any": "vcvttps2ibs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 68 /r" , "tt": "fv"},
+ {"any": "vcvttps2iubs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 6A /r" , "tt": "fv"},
+ {"any": "vcvttps2qqs W:xyz{kz}, xxy/mxxy/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 6D /r" , "tt": "fv"},
+ {"any": "vcvttps2udqs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6C /r" , "tt": "fv"},
+ {"any": "vcvttps2uqqs W:xyz{kz}, xxy/mxxy/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 6C /r" , "tt": "fv"},
+ {"any": "vcvttsd2sis W:ry, xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F2.MAP5.Wy 6D /r" , "tt": "t1f"},
+ {"any": "vcvttsd2usis W:ry, xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F2.MAP5.Wy 6C /r" , "tt": "t1f"},
+ {"any": "vcvttss2sis W:ry, xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 6D /r" , "tt": "t1f"},
+ {"any": "vcvttss2usis W:ry, xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 6C /r" , "tt": "t1f"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [
+ {"any": "vmovd W:xmm[31:0], R:xmm[31:0]/m32" , "op": "[RM ] EVEX.128.F3.0F.W0 7E /r" , "tt": "t1"},
+ {"any": "vmovd W:xmm[31:0]/m32, R:xmm[31:0]" , "op": "[MR ] EVEX.128.66.0F.W0 D6 /r" , "tt": "t1"},
+ {"any": "vmovw W:xmm[15:0], R:xmm[15:0]/m16" , "op": "[RM ] EVEX.128.F3.MAP5.W0 6E /r" , "tt": "t1"},
+ {"any": "vmovw W:xmm[15:0]/m16, R:xmm[15:0]" , "op": "[MR ] EVEX.128.F3.MAP5.W0 7E /r" , "tt": "t1"}
+ ]},
+
+ {"category": "AVX10_2 SIMD", "ext": "AVX10_2 MOVRS", "instructions": [
+ {"x64": "vmovrsb X:xyz {kz}, R:mxyz" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 6F !(11):rrr:bbb", "tt": "fm"},
+ {"x64": "vmovrsd X:xyz {kz}, R:mxyz" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 6F !(11):rrr:bbb", "tt": "fm"},
+ {"x64": "vmovrsq X:xyz {kz}, R:mxyz" , "op": "[RM ] EVEX.xyz.F3.MAP5.W1 6F !(11):rrr:bbb", "tt": "fm"},
+ {"x64": "vmovrsw X:xyz {kz}, R:mxyz" , "op": "[RM ] EVEX.xyz.F2.MAP5.W1 6F !(11):rrr:bbb", "tt": "fm"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_TILE", "instructions": [
+ {"x64": "ldtilecfg R:m512" , "op": "[M ] VEX.128.NP.0F38.W0 49 !(11):000:bbb"},
+ {"apx": "ldtilecfg R:m512" , "op": "[M ] EVEX.128.NP.0F38.W0 49 !(11):000:bbb"},
+ {"x64": "sttilecfg W:m512" , "op": "[M ] VEX.128.66.0F38.W0 49 !(11):000:bbb"},
+ {"apx": "sttilecfg W:m512" , "op": "[M ] EVEX.128.66.0F38.W0 49 !(11):000:bbb"},
+ {"x64": "tileloadd W:tmm, tmem" , "op": "[RM ] VEX.128.F2.0F38.W0 4B !(11):rrr:100"},
+ {"apx": "tileloadd W:tmm, R:tmem" , "op": "[RM ] EVEX.128.F2.0F38.W0 4B !(11):rrr:100"},
+ {"x64": "tileloaddt1 W:tmm, tmem" , "op": "[RM ] VEX.128.66.0F38.W0 4B !(11):rrr:100"},
+ {"apx": "tileloaddt1 W:tmm, R:tmem" , "op": "[RM ] EVEX.128.66.0F38.W0 4B !(11):rrr:100"},
+ {"x64": "tilerelease" , "op": "[OP ] VEX.128.NP.0F38.W0 49 /0"},
+ {"x64": "tilestored W:tmem, R:tmm" , "op": "[MR ] VEX.128.F3.0F38.W0 4B !(11):rrr:100"},
+ {"apx": "tilestored W:tmem, R:tmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 4B !(11):rrr:100"},
+ {"x64": "tilezero W:tmm" , "op": "[R ] VEX.128.F2.0F38.W0 49 11:rrr:000"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_BF16", "instructions": [
+ {"x64": "tdpbf16ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.F3.0F38.W0 5C 11:rrr:bbb"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_COMPLEX", "instructions": [
+ {"x64": "tcmmimfp16ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.66.0F38.W0 6C 11:rrr:bbb"},
+ {"x64": "tcmmrlfp16ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.NP.0F38.W0 6C 11:rrr:bbb"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_FP16", "instructions": [
+ {"x64": "tdpfp16ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.F2.0F38.W0 5C 11:rrr:bbb"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_INT8", "instructions": [
+ {"x64": "tdpbssd X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.F2.0F38.W0 5E 11:rrr:bbb"},
+ {"x64": "tdpbsud X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.F3.0F38.W0 5E 11:rrr:bbb"},
+ {"x64": "tdpbusd X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.66.0F38.W0 5E 11:rrr:bbb"},
+ {"x64": "tdpbuud X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.NP.0F38.W0 5E 11:rrr:bbb"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_AVX512 AVX10_2", "instructions": [
+ {"x64": "tcvtrowd2ps W:zmm, tmm, r32" , "op": "[RMV] EVEX.512.F3.0F38.W0 4A 11:rrr:bbb"},
+ {"x64": "tcvtrowd2ps W:zmm, tmm, imm8" , "op": "[RM ] EVEX.512.F3.0F3A.W0 07 11:rrr:bbb ib"},
+ {"x64": "tcvtrowps2pbf16h W:zmm, tmm, r32" , "op": "[RMV] EVEX.512.F2.0F38.W0 6D 11:rrr:bbb"},
+ {"x64": "tcvtrowps2pbf16h W:zmm, tmm, imm8" , "op": "[RM ] EVEX.512.F2.0F3A.W0 07 11:rrr:bbb ib"},
+ {"x64": "tcvtrowps2pbf16l W:zmm, tmm, r32" , "op": "[RMV] EVEX.512.F3.0F38.W0 6D 11:rrr:bbb"},
+ {"x64": "tcvtrowps2pbf16l W:zmm, tmm, imm8" , "op": "[RM ] EVEX.512.F3.0F3A.W0 77 11:rrr:bbb ib"},
+ {"x64": "tcvtrowps2phh W:zmm, tmm, r32" , "op": "[RMV] EVEX.512.NP.0F38.W0 6D 11:rrr:bbb"},
+ {"x64": "tcvtrowps2phh W:zmm, tmm, imm8" , "op": "[RM ] EVEX.512.NP.0F3A.W0 07 11:rrr:bbb ib"},
+ {"x64": "tcvtrowps2phl W:zmm, tmm, r32" , "op": "[RMV] EVEX.512.66.0F38.W0 6D 11:rrr:bbb"},
+ {"x64": "tcvtrowps2phl W:zmm, tmm, imm8" , "op": "[RM ] EVEX.512.F2.0F3A.W0 77 11:rrr:bbb ib"},
+ {"x64": "tilemovrow W:zmm, tmm, r32" , "op": "[RMV] EVEX.512.66.0F38.W0 4A 11:rrr:bbb"},
+ {"x64": "tilemovrow W:zmm, tmm, imm8" , "op": "[RMV] EVEX.512.66.0F3A.W0 07 11:rrr:bbb ib"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_FP8", "instructions": [
+ {"x64": "tdpbf8ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.NP.MAP5.W0 FD 11:rrr:bbb"},
+ {"x64": "tdpbhf8ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.F2.MAP5.W0 FD 11:rrr:bbb"},
+ {"x64": "tdphbf8ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.F3.MAP5.W0 FD 11:rrr:bbb"},
+ {"x64": "tdphf8ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.66.MAP5.W0 FD 11:rrr:bbb"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_MOVRS", "instructions": [
+ {"x64": "tileloaddrs W:tmm, tmem" , "op": "[RM ] VEX.128.F2.0F38.W0 4A !(11):rrr:100"},
+ {"apx": "tileloaddrs W:tmm, tmem" , "op": "[RM ] EVEX.128.F2.0F38.W0 4A !(11):rrr:100"},
+ {"x64": "tileloaddrst1 W:tmm, tmem" , "op": "[RM ] VEX.128.66.0F38.W0 4A !(11):rrr:100"},
+ {"apx": "tileloaddrst1 W:tmm, tmem" , "op": "[RM ] EVEX.128.66.0F38.W0 4A !(11):rrr:100"}
+ ]},
+
+ {"category": "AMX", "ext": "AMX_TF32", "instructions": [
+ {"x64": "tmmultf32ps X:tmm, tmm, tmm" , "op": "[RMV] VEX.128.66.0F38.W0 48 11:rrr:bbb"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "APX_F", "instructions": [
+ {"apx": "adc x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 10 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 12 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /2 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 10 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 12 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "adc W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /2 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "add{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 00 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 02 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /0 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 00 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 02 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "add{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /0 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "and{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 20 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 22 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /4 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 20 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 22 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "and{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /4 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "cmovb X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"},
+ {"apx": "cmovbe X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"},
+ {"apx": "cmovl X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"},
+ {"apx": "cmovle X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"apx": "cmovnb X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"},
+ {"apx": "cmovnbe X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"},
+ {"apx": "cmovnl X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"},
+ {"apx": "cmovnle X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"apx": "cmovno X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"},
+ {"apx": "cmovnp X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"},
+ {"apx": "cmovns X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"},
+ {"apx": "cmovnz X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"},
+ {"apx": "cmovo X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"},
+ {"apx": "cmovp X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"},
+ {"apx": "cmovs X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"},
+ {"apx": "cmovz X:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"},
+ {"any": "crc32 X:r32, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W0 F0 /r"},
+ {"any": "crc32 X:r64, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W1 F0 /r"},
+ {"any": "crc32 X:r32, R:r16/m16" , "op": "[RM ] EVEX.ND=0.LLZ.66.MAP4.W0 F1 /r"},
+ {"any": "crc32 X:r32, R:r32/m32" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W0 F1 /r"},
+ {"any": "crc32 X:r64, R:r64/m64" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W1 F1 /r"},
+ {"apx": "dec{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "dec{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "dec{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "dec{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "inc{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "inc{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "inc{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"apx": "inc{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"},
+ {"any": "div{nf} x:<ax>, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"any": "div{nf} x:<dxv>, x:<axv>, R:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"apx": "idiv{nf} x:<ax>, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"apx": "idiv{nf} x:<dxv>, x:<axv>, R:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"},
+ {"apx": "imul{nf} x:<ax>, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imul{nf} w:<dxv>, x:<axv>, R:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imul{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imul{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imul{nf} w:rv, R:rv/mv, imms8" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imul{nf} w:rv, R:rv/mv, immv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 69 /r iv" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imulzu{nf} W:r16, R:r16/m16, imms8" , "op": "[RM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "imulzu{nf} W:r16, R:r16/m16, imm16" , "op": "[RM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 69 /r iv" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "mul{nf} x:<ax>, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /4" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "mul{nf} w:<dxv>, x:<axv>, rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /4" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"},
+ {"apx": "neg{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "neg{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "neg{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "neg{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "not{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /2"},
+ {"apx": "not{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /2"},
+ {"apx": "not{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG F6 /2"},
+ {"apx": "not{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv F7 /2"},
+ {"apx": "or{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /1 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "or{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /1 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "rcl x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /2 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcl x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /2 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcl W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /2" , "io": "CF=X OF=X"},
+ {"apx": "rcl W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /2 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcl W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /2 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcr x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /3 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcr x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /3 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcr W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /3" , "io": "CF=X OF=X"},
+ {"apx": "rcr W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /3 ib" , "io": "CF=X OF=X"},
+ {"apx": "rcr W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /3 ib" , "io": "CF=X OF=X"},
+ {"apx": "rol{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /0 ib" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /0 ib" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /0" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /0 ib" , "io": "CF=W OF=W"},
+ {"apx": "rol{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /0 ib" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /1 ib" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /1 ib" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /1" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /1 ib" , "io": "CF=W OF=W"},
+ {"apx": "ror{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /1 ib" , "io": "CF=W OF=W"},
+ {"apx": "sar{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sar{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sbb x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /3 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "sbb W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /3 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"},
+ {"apx": "shl{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shl{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shld{nf} x:rv/mv, R:rv, R:cl" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shld{nf} x:rv/mv, R:rv, imm8" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 24 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shld{nf} W:rv, R:rv/mv, R:rv, R:cl" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shld{nf} W:rv, R:rv/mv, R:rv, imm8" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 24 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shr{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shr{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "shrd{nf} x:rv/mv, R:rv, R:cl" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shrd{nf} x:rv/mv, R:rv, imm8" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 2C /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shrd{nf} W:rv, R:rv/mv, R:rv, R:cl" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "shrd{nf} W:rv, R:rv/mv, R:rv, imm8" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 2C /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"},
+ {"apx": "sub{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /5 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "sub{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /5 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"},
+ {"apx": "xor{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 38 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 39 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 3A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 3B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /6 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 38 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 39 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 3A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 3B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"},
+ {"apx": "xor{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /6 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "USER_MSR", "instructions": [
+ {"x64": "urdmsr W:r64, R:r64" , "op": "[MR ] F2 0F 38 F8 11:rrr:bbb"},
+ {"apx": "urdmsr W:r64, R:r64" , "op": "[MR ] EVEX.ND=0.LLZ.F2.MAP4.W0 F8 11:rrr:bbb"},
+ {"x64": "urdmsr W:r64, imm32" , "op": "[M ] VEX.128.F2.MAP7.W0 F8 11:000:bbb id"},
+ {"apx": "urdmsr W:r64, imm32" , "op": "[M ] EVEX.128.F2.MAP7.W0 F8 11:000:bbb id"},
+ {"x64": "uwrmsr R:r64, R:r64" , "op": "[RM ] F3 0F 38 F8 11:rrr:bbb"},
+ {"apx": "uwrmsr R:r64, R:r64" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.W0 F8 11:rrr:bbb"},
+ {"x64": "uwrmsr imm32, R:r64" , "op": "[M ] VEX.128.F3.MAP7.W0 F8 11:000:bbb id"},
+ {"apx": "uwrmsr imm32, R:r64" , "op": "[M ] EVEX.128.F3.MAP7.W0 F8 11:000:bbb id"}
+ ]},
+
+ {"category": "GP GP_EXT", "ext": "APX_F", "instructions": [
+ {"x64": "ccmpb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpb dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpb dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpb dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpbe dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpbe dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpbe dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpf dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpf dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpf dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpf dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpf dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpf dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpf dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpl dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpl dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpl dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmple dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmple dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmple dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmple dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmple dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmple dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmple dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpnb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpnb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpnb dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpnb dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpnb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpnb dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpnb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpnbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpnbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpnbe dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpnbe dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpnbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpnbe dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpnbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpnl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpnl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpnl dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpnl dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpnl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpnl dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpnl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpnle dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpnle dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpnle dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpnle dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpnle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpnle dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpnle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpno dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpno dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpno dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpno dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpno dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpno dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpno dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpns dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpns dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpns dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpns dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpns dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpns dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpns dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpnz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpnz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpnz dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpnz dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpnz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpnz dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpnz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpo dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpo dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpo dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpo dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpo dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpo dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpo dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmps dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmps dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmps dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmps dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmps dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmps dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmps dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpt dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpt dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpt dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpt dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpt dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpt dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpt dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "ccmpz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 38 /r" },
+ {"x64": "ccmpz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 39 /r" },
+ {"x64": "ccmpz dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 3A /r" },
+ {"x64": "ccmpz dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 3B /r" },
+ {"x64": "ccmpz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 80 /7 ib" },
+ {"x64": "ccmpz dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 83 /7 ib" },
+ {"x64": "ccmpz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 81 /7 iv" },
+ {"x64": "cfcmovb X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"},
+ {"x64": "cfcmovb X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"},
+ {"x64": "cfcmovb X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"},
+ {"x64": "cfcmovb W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"},
+ {"x64": "cfcmovbe X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovbe X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovbe X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovbe W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovl X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovl X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovl X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovl W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovle X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovle X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovle X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovle W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovnb X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"},
+ {"x64": "cfcmovnb X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"},
+ {"x64": "cfcmovnb X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"},
+ {"x64": "cfcmovnb W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"},
+ {"x64": "cfcmovnbe X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovnbe X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovnbe X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovnbe W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"},
+ {"x64": "cfcmovnl X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovnl X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovnl X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovnl W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"},
+ {"x64": "cfcmovnle X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovnle X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovnle X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovnle W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "cfcmovno X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"},
+ {"x64": "cfcmovno X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"},
+ {"x64": "cfcmovno X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"},
+ {"x64": "cfcmovno W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"},
+ {"x64": "cfcmovnp X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"},
+ {"x64": "cfcmovnp X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"},
+ {"x64": "cfcmovnp X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"},
+ {"x64": "cfcmovnp W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"},
+ {"x64": "cfcmovns X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"},
+ {"x64": "cfcmovns X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"},
+ {"x64": "cfcmovns X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"},
+ {"x64": "cfcmovns W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"},
+ {"x64": "cfcmovnz X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovnz X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovnz X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovnz W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovo X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"},
+ {"x64": "cfcmovo X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"},
+ {"x64": "cfcmovo X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"},
+ {"x64": "cfcmovo W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"},
+ {"x64": "cfcmovp X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"},
+ {"x64": "cfcmovp X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"},
+ {"x64": "cfcmovp X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"},
+ {"x64": "cfcmovp W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"},
+ {"x64": "cfcmovs X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"},
+ {"x64": "cfcmovs X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"},
+ {"x64": "cfcmovs X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"},
+ {"x64": "cfcmovs W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"},
+ {"x64": "cfcmovz X:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovz X:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovz X?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"},
+ {"x64": "cfcmovz W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"},
+ {"x64": "ctestb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestf dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestf dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestf dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestf dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestf dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestf dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestle dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestle dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestnb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestnb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestnb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestnb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestnb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestnb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestnbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestnbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestnbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestnbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestnbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestnbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestnl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestnl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestnl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestnl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestnl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestnl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestnle dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestnle dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestnle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestnle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestnle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestnle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestno dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestno dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestno dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestno dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestno dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestno dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestns dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestns dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestns dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestns dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestns dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestns dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestnz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestnz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestnz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestnz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestnz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestnz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctesto dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctesto dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctesto dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctesto dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctesto dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctesto dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctests dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctests dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctests dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctests dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctests dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctests dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestt dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestt dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestt dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestt dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestt dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestt dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "ctestz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 84 /r" },
+ {"x64": "ctestz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 85 /r" },
+ {"x64": "ctestz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG F6 /0 ib" },
+ {"x64": "ctestz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG F6 /1 ib" },
+ {"x64": "ctestz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv F7 /0 iv" },
+ {"x64": "ctestz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv F7 /1 iv" },
+ {"x64": "jmpabs imm64" , "op": "[OP] NO67 NP REX2.MAP0.W0 A1 iq"},
+ {"x64": "pop2 W:r64, W:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W0 8F 11:000:bbb"},
+ {"x64": "pop2p W:r64, W:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W1 8F 11:000:bbb"},
+ {"x64": "popp W:r64" , "op": "[OP] REX2.MAP0.W1 58+r"},
+ {"x64": "push2 R:r64, R:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W0 FF 11:110:bbb"},
+ {"x64": "push2p R:r64, R:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W1 FF 11:110:bbb"},
+ {"x64": "pushp R:r64" , "op": "[OP] REX2.MAP0.W1 50+r"},
+ {"x64": "setb w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 42 /r" , "io": "CF=R"},
+ {"x64": "setbe w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 46 /r" , "io": "CF=R ZF=R"},
+ {"x64": "setl w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4C /r" , "io": "SF=R OF=R"},
+ {"x64": "setle w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "setnb w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 43 /r" , "io": "CF=R"},
+ {"x64": "setnbe w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 47 /r" , "io": "CF=R ZF=R"},
+ {"x64": "setnl w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4D /r" , "io": "SF=R OF=R"},
+ {"x64": "setnle w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "setno w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 41 /r" , "io": "OF=R"},
+ {"x64": "setnp w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4B /r" , "io": "PF=R"},
+ {"x64": "setns w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 49 /r" , "io": "SF=R"},
+ {"x64": "setnz w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 45 /r" , "io": "ZF=R"},
+ {"x64": "seto w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 40 /r" , "io": "OF=R"},
+ {"x64": "setp w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4A /r" , "io": "PF=R"},
+ {"x64": "sets w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 48 /r" , "io": "SF=R"},
+ {"x64": "setz w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 44 /r" , "io": "ZF=R"},
+ {"x64": "setzub W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 42 /r" , "io": "CF=R"},
+ {"x64": "setzube W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 46 /r" , "io": "CF=R ZF=R"},
+ {"x64": "setzul W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4C /r" , "io": "SF=R OF=R"},
+ {"x64": "setzule W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4E /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "setzunb W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 43 /r" , "io": "CF=R"},
+ {"x64": "setzunbe W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 47 /r" , "io": "CF=R ZF=R"},
+ {"x64": "setzunl W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4D /r" , "io": "SF=R OF=R"},
+ {"x64": "setzunle W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4F /r" , "io": "ZF=R SF=R OF=R"},
+ {"x64": "setzuno W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 41 /r" , "io": "OF=R"},
+ {"x64": "setzunp W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4B /r" , "io": "PF=R"},
+ {"x64": "setzuns W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 49 /r" , "io": "SF=R"},
+ {"x64": "setzunz W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 45 /r" , "io": "ZF=R"},
+ {"x64": "setzuo W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 40 /r" , "io": "OF=R"},
+ {"x64": "setzup W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4A /r" , "io": "PF=R"},
+ {"x64": "setzus W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 48 /r" , "io": "SF=R"},
+ {"x64": "setzuz W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 44 /r" , "io": "ZF=R"}
+ ]}
+ ],
+
+ "aliases": {
+ "ccmpb" : {"aliases": ["ccmpnae", "ccmpc" ], "format": "ccmp.b|nae|c" , "sign": "u"},
+ "ccmpbe" : {"aliases": ["ccmpna" ], "format": "ccmp.be|na" , "sign": "u"},
+ "ccmpl" : {"aliases": ["ccmpnge" ], "format": "ccmp.l|nge" , "sign": "s"},
+ "ccmple" : {"aliases": ["ccmpng" ], "format": "ccmp.le|ng" , "sign": "s"},
+ "ccmpnb" : {"aliases": ["ccmpae", "ccmpnc" ], "format": "ccmp.nb|ae|nc" , "sign": "u"},
+ "ccmpnbe" : {"aliases": ["ccmpa" ], "format": "ccmp.nbe|a" , "sign": "u"},
+ "ccmpnl" : {"aliases": ["ccmpge" ], "format": "ccmp.nl|ge" , "sign": "s"},
+ "ccmpnle" : {"aliases": ["ccmpg" ], "format": "ccmp.nle|g" , "sign": "s"},
+ "ccmpnz" : {"aliases": ["ccmpne" ], "format": "ccmp.nz|ne" , "sign": "_"},
+ "ccmpz" : {"aliases": ["ccmpe" ], "format": "ccmp.z|e" , "sign": "_"},
+
+ "cfcmovb" : {"aliases": ["cfcmovnae", "cfcmovc"], "format": "cfmov.b|nae|c" , "sign": "u"},
+ "cfcmovbe" : {"aliases": ["cfcmovna" ], "format": "cfmov.be|na" , "sign": "u"},
+ "cfcmovl" : {"aliases": ["cfcmovnge" ], "format": "cfmov.l|nge" , "sign": "s"},
+ "cfcmovle" : {"aliases": ["cfcmovng" ], "format": "cfmov.le|ng" , "sign": "s"},
+ "cfcmovnb" : {"aliases": ["cfcmovae", "cfcmovnc"], "format": "cfmov.nb|ae|nc" , "sign": "u"},
+ "cfcmovnbe": {"aliases": ["cfcmova" ], "format": "cfmov.nbe|a" , "sign": "u"},
+ "cfcmovnl" : {"aliases": ["cfcmovge" ], "format": "cfmov.nl|ge" , "sign": "s"},
+ "cfcmovnle": {"aliases": ["cfcmovg" ], "format": "cfmov.nle|g" , "sign": "s"},
+ "cfcmovnp" : {"aliases": ["cfcmovpo" ], "format": "cfmov.np|po" , "sign": "_"},
+ "cfcmovnz" : {"aliases": ["cfcmovne" ], "format": "cfmov.nz|ne" , "sign": "_"},
+ "cfcmovp" : {"aliases": ["cfcmovpe" ], "format": "cfmov.p|pe" , "sign": "_"},
+ "cfcmovz" : {"aliases": ["cfcmove" ], "format": "cfmov.z|e" , "sign": "_"},
+
+ "cmovb" : {"aliases": ["cmovnae", "cmovc" ], "format": "cmov.b|nae|c" , "sign": "u"},
+ "cmovbe" : {"aliases": ["cmovna" ], "format": "cmov.be|na" , "sign": "u"},
+ "cmovl" : {"aliases": ["cmovnge" ], "format": "cmov.l|nge" , "sign": "s"},
+ "cmovle" : {"aliases": ["cmovng" ], "format": "cmov.le|ng" , "sign": "s"},
+ "cmovnb" : {"aliases": ["cmovae", "cmovnc" ], "format": "cmov.nb|ae|nc" , "sign": "u"},
+ "cmovnbe" : {"aliases": ["cmova" ], "format": "cmov.nbe|a" , "sign": "u"},
+ "cmovnl" : {"aliases": ["cmovge" ], "format": "cmov.nl|ge" , "sign": "s"},
+ "cmovnle" : {"aliases": ["cmovg" ], "format": "cmov.nle|g" , "sign": "s"},
+ "cmovnp" : {"aliases": ["cmovpo" ], "format": "cmov.np|po" , "sign": "_"},
+ "cmovnz" : {"aliases": ["cmovne" ], "format": "cmov.nz|ne" , "sign": "_"},
+ "cmovp" : {"aliases": ["cmovpe" ], "format": "cmov.p|pe" , "sign": "_"},
+ "cmovz" : {"aliases": ["cmove" ], "format": "cmov.z|e" , "sign": "_"},
+
+ "ctestb" : {"aliases": ["ctestnae", "ctestc" ], "format": "ctest.b|nae|c" , "sign": "u"},
+ "ctestbe" : {"aliases": ["ctestna" ], "format": "ctest.be|na" , "sign": "u"},
+ "ctestl" : {"aliases": ["ctestnge" ], "format": "ctest.l|nge" , "sign": "s"},
+ "ctestle" : {"aliases": ["ctestng" ], "format": "ctest.le|ng" , "sign": "s"},
+ "ctestnb" : {"aliases": ["ctestae", "ctestnc" ], "format": "ctest.nb|ae|nc" , "sign": "u"},
+ "ctestnbe" : {"aliases": ["ctesta" ], "format": "ctest.nbe|a" , "sign": "u"},
+ "ctestnl" : {"aliases": ["ctestge" ], "format": "ctest.nl|ge" , "sign": "s"},
+ "ctestnle" : {"aliases": ["ctestg" ], "format": "ctest.nle|g" , "sign": "s"},
+ "ctestnz" : {"aliases": ["ctestne" ], "format": "ctest.nz|ne" , "sign": "_"},
+ "ctestz" : {"aliases": ["cteste" ], "format": "ctest.z|e" , "sign": "_"},
+
+ "jb" : {"aliases": ["jnae", "jc" ], "format": "jb|jnae|jc" , "sign": "u"},
+ "jbe" : {"aliases": ["jna" ], "format": "jbe|jna" , "sign": "u"},
+ "jl" : {"aliases": ["jnge" ], "format": "jl|jnge" , "sign": "s"},
+ "jle" : {"aliases": ["jng" ], "format": "jle|jng" , "sign": "s"},
+ "jnb" : {"aliases": ["jae", "jnc" ], "format": "jnb|jae|jnc" , "sign": "u"},
+ "jnbe" : {"aliases": ["ja" ], "format": "jnbe|ja" , "sign": "u"},
+ "jnl" : {"aliases": ["jge" ], "format": "jnl|jge" , "sign": "s"},
+ "jnle" : {"aliases": ["jg" ], "format": "jnle|jg" , "sign": "s"},
+ "jnp" : {"aliases": ["jpo" ], "format": "jnp|jpo" , "sign": "_"},
+ "jnz" : {"aliases": ["jne" ], "format": "jnz|jne" , "sign": "_"},
+ "jp" : {"aliases": ["jpe" ], "format": "jp|jpe" , "sign": "_"},
+ "jz" : {"aliases": ["je" ], "format": "jz|je" , "sign": "_"},
+
+ "setb" : {"aliases": ["setnae", "setc" ], "format": "set.b|nae|c" , "sign": "u"},
+ "setbe" : {"aliases": ["setna" ], "format": "set.be|na" , "sign": "u"},
+ "setl" : {"aliases": ["setnge" ], "format": "set.l|nge" , "sign": "s"},
+ "setle" : {"aliases": ["setng" ], "format": "set.le|ng" , "sign": "s"},
+ "setnb" : {"aliases": ["setae", "setnc" ], "format": "set.nb|ae|nc" , "sign": "u"},
+ "setnbe" : {"aliases": ["seta" ], "format": "set.nbe|a" , "sign": "u"},
+ "setnl" : {"aliases": ["setge" ], "format": "set.nl|ge" , "sign": "s"},
+ "setnle" : {"aliases": ["setg" ], "format": "set.nle|g" , "sign": "s"},
+ "setnp" : {"aliases": ["setpo" ], "format": "set.np|po" , "sign": "_"},
+ "setnz" : {"aliases": ["setne" ], "format": "set.nz|ne" , "sign": "_"},
+ "setp" : {"aliases": ["setpe" ], "format": "set.p|pe" , "sign": "_"},
+ "setz" : {"aliases": ["sete" ], "format": "set.z|e" , "sign": "_"},
+
+ "setzub" : {"aliases": ["setzunae", "setzuc" ], "format": "setzu.b|nae|c" , "sign": "u"},
+ "setzube" : {"aliases": ["setzuna" ], "format": "setzu.be|na" , "sign": "u"},
+ "setzul" : {"aliases": ["setzunge" ], "format": "setzu.l|nge" , "sign": "s"},
+ "setzule" : {"aliases": ["setzung" ], "format": "setzu.le|ng" , "sign": "s"},
+ "setzunb" : {"aliases": ["setzuae", "setzunc" ], "format": "setzu.nb|ae|nc" , "sign": "u"},
+ "setzunbe" : {"aliases": ["setzua" ], "format": "setzu.nbe|a" , "sign": "u"},
+ "setzunl" : {"aliases": ["setzuge" ], "format": "setzu.nl|ge" , "sign": "s"},
+ "setzunle" : {"aliases": ["setzug" ], "format": "setzu.nle|g" , "sign": "s"},
+ "setzunp" : {"aliases": ["setzupo" ], "format": "setzu.np|po" , "sign": "_"},
+ "setzunz" : {"aliases": ["setzune" ], "format": "setzu.nz|ne" , "sign": "_"},
+ "setzup" : {"aliases": ["setzupe" ], "format": "setzu.p|pe" , "sign": "_"},
+ "setzuz" : {"aliases": ["setzue" ], "format": "setzu.z|e" , "sign": "_"},
+
+ "fwait" : {"aliases": ["wait" ], "format": "fwait"},
+ "shl" : {"aliases": ["sal" ], "format": "shl"}
+ },
+
+ "postproc": [
+ {"group": "Control Flow", "instructions": [
+ {"name": "call lcall", "control": "call"},
+ {"name": "iret iretd iretq", "control": "return"},
+ {"name": "jb jbe jl jle jnb jnbe jnl jnle jno jnp jns jnz jo jp js jz jecxz", "control": "branch"},
+ {"name": "jmp jmpabs ljmp", "control": "jump"},
+ {"name": "loop loope loopne", "control": "branch"},
+ {"name": "ret retf", "control": "return"}
+ ]},
+
+ {"group": "Encoding Preference", "instructions": [
+ {"name": "vcvtneps2bf16", "encodingPreference": "EVEX"},
+ {"name": "vpmadd52huq vpmadd52luq", "encodingPreference": "EVEX"},
+ {"name": "vpdpbusd vpdpbusds vpdpwssd vpdpwssds", "encodingPreference": "EVEX"}
+ ]}
+ ]
+}
diff --git a/3rdparty/asmjit/db/isa_x86.md b/3rdparty/asmjit/db/isa_x86.md
new file mode 100644
index 00000000000..7a761d7730d
--- /dev/null
+++ b/3rdparty/asmjit/db/isa_x86.md
@@ -0,0 +1,145 @@
+X86 ISA - JSON Database Documentation
+-------------------------------------
+
+This file provides a documentation of isa_x86.json file, which contains a compact X86 and X86_64 instruction database. The database has been created from several manuals from Intel and AMD, which describes the encoding of instructions and other properties. The database tries to keep the instruction and opcode formats compatible with the database, however, in cases where applicable it tries to simplify it (for example merging instructions that all use either XMM, YMM, or ZMM registers, etc...).
+
+## Instruction Category
+
+Each set of instructions start with category group, which looks like the following:
+
+```json
+{"category": "<LIST_OF_CATEGORIES>", "ext": "<LIST_OF_EXTENSIONS>", /* flags, */ "instructions": [
+ /* (instruction records) */
+]}
+```
+
+Fields:
+
+ - `category` - describes a single or multiple categories this instruction belongs to. In general the database is written in a way to provide "baseline" and "extended" categories, so have the following categories used to distinguish between different set of instructions:
+ - `GP` - General purpose instructions.
+ - `GP_EXT` - Extensions to general purpose instructions (such as BMI, POPCNT, etc...).
+ - `MMX` - MMX and 3DNOW instructions (in general instructions using MM registers).
+ - `SSE` - SSE to SSE4.2 instructions, including other extensions that don't use VEX/EVEX prefixes.
+ - `AVX` - AVX, AVX2, and other instructions that use SIMD registers (XMM, YMM) and VEX prefix.
+ - `AVX512` - AVX512 instructions.
+
+ - `ext` (optional) - describes extensions required to execute the instruction. When multiple extensions are in the list it means ALL of them must be available. For example `AESNI` means that `AESNI` extension is required, `AVX AESNI` means that both `AVX` and `AESNI` extensions are required.
+
+ - `deprecated` (optional) - deprecation flag (either `true` or `false`), by default instructions are not deprecated.
+
+ - `volatile` (optional) - volatility flag (either `true` or `false`), by default instructions are not volatile (note that volatile flag is used for code generators and in general it says that the instruction should not be reordered and nothing above it should move below and vice versa).
+
+ - `instructions` - array of instruction records, one line per instruction.
+
+## Instruction Record
+
+A single instruction record looks like the following:
+
+```json
+{"<ARCH>": "<INSTRUCTION_SIGNATURE>", "op": "[<ENCODING_OPS>] <ENCODING_DATA>" /*, <ADDITIONAL_DATA>*/ }
+```
+
+### Architecture Field
+
+`<ARCH>` field describes the architecture and optionally `APX_F` promoted instruction:
+
+ - `any` - The instruction can run in both 32-bit and 64-bit mode and shares the encoding.
+ - `x86` - The instruction can only run in 32-bit mode. This in general may be an indication that the instruction was deprecated in 64-bit mode or that the instruction has a different signature in 64-bit mode (some instructions require 32-bit registers in 32-bit mode and 64-bit registers in 64-bit mode, for example)
+ - `x64` - The instruction can only run in 64-bit mode.
+ - `apx` - The instruction can only run in 64-bit mode with `APX_F` extension present. This notation is only used for `APX_F` instructions that provide alternative `EVEX` encoding to existing instructions, but not new `APX_F` only instructions. For example `jmpabs` instruction is a new `APX_F` instruction, thus the arch notation it uses is `x64`.
+
+Explanation: The database uses this "variable" field name to save space and to avoid defining the architecture elsewhere.
+
+### Instruction Signature
+
+Instruction signature is composed of the following components:
+
+```
+[<PREFIX>|<OPTIONS>] <INSTRUCTION_NAME>|<ALIASES> <OPERANDS>
+```
+
+ - `[<PREFIX>|<OPTIONS>]` (optional) - prefixes and other options:
+ - `[bnd]` - instruction supports `bnd` prefix (deprecated).
+ - `[lock]` - instruction supports `lock` prefix.
+ - `[xacquire]` - instruction supports `xacquire` prefix.
+ - `[xacqrel]` - instruction supports both `xacquire` and `xrelease` prefixes.
+ - `[xrelease]` - instruction supports `xrelease` prefix.
+ - `[rep]` - instruction supports `rep` prefix (or `repe`).
+ - `[repne]` - instruction supports `repne` prefix.
+ - `[repIgnore]` - instruction supports `rep` prefix, which is ignored during execution (to support for example `rep ret`).
+
+ - `<INSTRUCTION_NAME>|<ALIASES>` (required) - the name of the instruction possibly followed by aliases if the instruction has them
+ - if the instruction has aliases, they will be recognized in AsmJit API (the API will provide aliases), but will not have a separate instruction identifier
+ - for example `cmovz|cmove` is a `cmovz` instruction that has a `cmove` alias.
+
+ - `<OPERANDS>` (optional):
+ - When an instruction has multiple operands, they are separated by comma.
+ - Registers:
+ - `r8` - 8-bit general purpose register.
+ - `r16` - 16-bit general purpose register.
+ - `r32` - 32-bit general purpose register.
+ - `r64` - 64-bit general purpose register (x64 only).
+ - `mm` - 64-bit MM register.
+ - `xmm` - 128-bit XMM register (SSE).
+ - `ymm` - 256-bit YMM register (AVX)
+ - `zmm` - 512-bit ZMM register (AVX512/AVX10).
+ - `k` - 64-bit K register (AVX512/AVX10).
+ - `tmm` - TMM register (AMX).
+ - `creg` - Control register.
+ - `dreg` - Debug register.
+ - `st(x)` - FPU register.
+ - `rip` - Instruction pointer register (used during addressing).
+ - `bnd` - Bounds register (deprecated).
+ - Memory:
+ - `mem` - Memory operand without size specified.
+ - `m8-m512` - Memory operand of a specified size.
+ - Immediate values
+ - `imm4` - Signed or unsigned 4-bit immediate value (only used by instructions where the other 4 bits are used to encode additional register operand).
+ - `imm8` - Signed or unsigned 8-bit immediate value.
+ - `imm16` - Signed or unsigned 16-bit immediate value.
+ - `imm32` - Signed or unsigned 32-bit immediate value.
+ - `imm64` - Signed or unsigned 64-bit immediate value.
+ - `imms8` - Signed 8-bit immediate value (instructions that sign-extend the immediate value to 32 or 64 bits).
+ - `immu8` - Unsigned 8-bit immediate value (instructions that zero-extend the immediate value to 32 or 64 bits).
+ - `immu16` - Unsigned 16-bit immediate value (instructions that zero-extend the immediate value to 32 or 64 bits).
+ - `imms32` - Signed 32-bit immediate value (instructions that sign-extend the immediate value to 64 bits).
+ - `immu32` - Unsigned 32-bit immediate value (instructions that zero-extend the immediate value to 64 bits).
+ - Relative operands (addressing labels and relative locations in code):
+ - `rel8` - 8-bit signed relative displacement.
+ - `rel16` - 16-bit signed relative displacement.
+ - `rel32` - 32-bit signed relative displacement.
+ - Combining:
+ - Register and memory operands can be combined, for example `r8/m8` means either 8-bit register or 8-bit memory operand
+ - Read/Write access:
+ - The first operand must be decorated by access in a form `[r|w|x]: <OPERAND>`:
+ - `R:` - read access.
+ - `W:` - write access (overwrites the whole register).
+ - `w:` - write access (only overwrites an addressed part of the register - 8-bit and 16-bit GP registers use this access).
+ - `X:` - read/write access (the final write operation overwrites the whole register).
+ - `x:` - read/write access (the final write operation only overwrites the addressed part of the register - 16-bit GP access).
+ - The access of the second operand and following operands is implied to be read-only, when not specified explicitly.
+ - Grouping:
+ - If the encoding used for multiple register combinations is the same, multiple instructions can be grouped into a single record.
+ - `GP` Instructions:
+ - `ry` - either `r32` or `r64`.
+ - `my` - either `m32` or `m64`.
+ - `rv` - either `r16`, `r32`, or `r64`.
+ - `mv` - either `m16`, `m32`, or `m64`.
+ - `immv` - either `imm16`, `imm32`, or `simm32`.
+ - All registers must match, example: `add x:rv, rv/mv` - either all `r16/m16`, `r32/m32`, or `r64/m64`.
+ - When `rv/mv/immv` is used, the instruction must use `66h` prefix (or 66h part of `VEX/EVEX`) when a 16-bit `r16/m16` is used, and `REX.W` (or `W` part of `VEX/EVEX`) when a 64-bit `r64/m64` is used. The immediate expands to `imm16` for instructions working with 16-bit registers, to `imm32` for instructions working with 32-bit registers, and to `simm32` for instructions working with 64-bit registers (32-bit immediate sign extended to 64 bits).
+ - When `rv/mv` is used with `w` and `x` access option, it only applies to a 16-bit operation, wider operations would use `W` or `X` (this is an architectural constraint that the tool processing the database must be aware of)
+ - Why `y` and `v`? `ry/my` and `rv/mv` appeared in initial manuals describing `APX_F` extension, so this database is using exactly this notation to group multiple instructions into a single entry.
+ - `AVX` Instructions:
+ - `xy/mxy` - either `xmm/m128` or `ymm/m256` register operand.
+ - All registers must match, example: `vfmadd132pd X:xy, xy, xy/mxy` - either all `xmm/m128` or all `ymm/m256`.
+ - Why `xy/mxy`? This notation is not used by instruction manuals, but we have found it easy to use and understand.
+ - `AVX512` and `AVX10` Instructions:
+ - `xxx/mxxx` - either `xmm[31:0]/m32`, `xmm[63:0]/m64`, or `xmm/m128` register operand.
+ - `xxy/mxxy` - either `xmm[63:0]/m64`, `xmm/m128`, or `ymm/m256` register operand.
+ - `xyz/mxyz` - either `xmm/m128`, `ymm/m256`, or `zmm/m512` register operand.
+ - All registers must match, example: `vvfmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}` - either all `xmm/m128`, `ymm/m256`, or `zmm/m512`.
+ - Embedded rounding `{er}` and `{sae}` are grouped - in AVX512 case only 512-bit operations can use `{er}/{sae}`; in AVX10.2 case both 256-bit and 512-bit operations can use `{er}/{sae}`, but not 128-bit operations - the assembler or the tool processing this data must be aware of this architectural constraint.
+ - Why `xyz/mxyz`? This notation is not used by instruction manuals, but we have found it easy to use and understand.
+
+
diff --git a/3rdparty/asmjit/db/package.json b/3rdparty/asmjit/db/package.json
new file mode 100644
index 00000000000..8b4f5fc3c6f
--- /dev/null
+++ b/3rdparty/asmjit/db/package.json
@@ -0,0 +1,29 @@
+{
+ "name": "asmdb",
+ "version": "0.1.0",
+ "license": "Zlib",
+ "engines": { "node": ">=8" },
+
+ "description": "Instructions database and utilities for X86/X64 and ARM (THUMB/A32/A64) architectures.",
+ "keywords": [
+ "asm", "assembler", "database", "instructions",
+ "arm", "thumb", "thumb2", "a32", "a64", "aarch32", "aarch64",
+ "x86", "x86_64", "x64", "amd64"
+ ],
+
+ "homepage": "https://github.com/asmjit/asmjit/db",
+ "bugs": {
+ "url": "https://github.com/asmjit/asmjit/issues"
+ },
+
+ "contributors": [
+ "Petr Kobalicek <kobalicek.petr@gmail.com> (kobalicek.com)"
+ ],
+
+ "main": "index.js",
+
+ "repository" : {
+ "type": "git",
+ "url": "https://github.com/asmjit/asmjit.git"
+ }
+}
diff --git a/3rdparty/asmjit/db/x86.js b/3rdparty/asmjit/db/x86.js
new file mode 100644
index 00000000000..1861b3c1c9b
--- /dev/null
+++ b/3rdparty/asmjit/db/x86.js
@@ -0,0 +1,1273 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See <asmjit/core.h> or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+(function($scope, $as) {
+"use strict";
+
+// Import.
+const base = $scope.base ? $scope.base : require("./base.js");
+
+const dict = base.dict;
+const NONE = base.NONE;
+const Parsing = base.Parsing;
+const MapUtils = base.MapUtils;
+
+// Export.
+const x86 = $scope[$as] = {};
+
+function FAIL(msg) { throw new Error("[X86] " + msg); }
+
+// Database
+// ========
+
+x86.dbName = "isa_x86.json";
+
+// Metadata Tables
+// ===============
+
+const ArchGroupInfo = dict({
+ "ry": ["ANY", "X64"],
+ "rv": ["ANY", "ANY", "X64"]
+});
+
+// Groups are used by instruction tables to group multiple operand combinations into a single record. In general
+// X86 and X86_64 instructions can be divided into GP and SIMD groups, where GP groups use `ry/my` syntax to
+// specify operation for 16/32/64 bit registers and "xy/mxy"/"xyz/mxyz" groups to specify a SIMD instruction that
+// uses either XMM/YMM (AVX) or XMM/YMM/ZMM registers (AVX-512).
+const OperandGroupInfo = dict({
+ "ry" : { "group": "ry" , "subst": ["r32", "r64"] },
+ "my" : { "group": "ry" , "subst": ["m32", "m64"] },
+ "axy" : { "group": "ry" , "subst": ["eax", "rax"] },
+ "bxy" : { "group": "ry" , "subst": ["ebx", "rbx"] },
+ "cxy" : { "group": "ry" , "subst": ["ecx", "rcx"] },
+ "dxy" : { "group": "ry" , "subst": ["edx", "rdx"] },
+
+ "rv" : { "group": "rv" , "subst": ["r16", "r32", "r64"] },
+ "mv" : { "group": "rv" , "subst": ["m16", "m32", "m64"] },
+ "axv" : { "group": "rv" , "subst": ["ax", "eax", "rax"] },
+ "bxv" : { "group": "rv" , "subst": ["bx", "ebx", "rbx"] },
+ "cxv" : { "group": "rv" , "subst": ["cx", "ecx", "rcx"] },
+ "dxv" : { "group": "rv" , "subst": ["dx", "edx", "rdx"] },
+ "immv" : { "group": "rv" , "subst": ["imm16", "imm32", "imms32"] },
+
+ "xy" : { "group": "xy" , "subst": ["xmm", "ymm"] },
+ "mxy" : { "group": "xy" , "subst": ["m128", "m256"] },
+
+ "xxx" : { "group": "xyz", "subst": ["xmm[31:0]", "xmm[63:0]", "xmm"] },
+ "xxy" : { "group": "xyz", "subst": ["xmm[63:0]", "xmm", "ymm"] },
+ "xyz" : { "group": "xyz", "subst": ["xmm", "ymm", "zmm"] },
+ "mxxx" : { "group": "xyz", "subst": ["m32", "m64", "m128"] },
+ "mxxy" : { "group": "xyz", "subst": ["m64", "m128", "m256"] },
+ "mxyz" : { "group": "xyz", "subst": ["m128", "m256", "m512"] }
+});
+
+const OpcodeGroupInfo = dict({
+ "Wy" : { "group": "ry" , "subst": ["W0", "W1"] },
+ "iv" : { "group": "rv" , "subst": ["iw", "id", "id"] },
+ "Pv" : { "group": "rv" , "subst": ["66", "NP", "NP"] },
+ "Wv" : { "group": "rv" , "subst": ["W0", "W0", "W1"] }
+});
+
+// Instruction tables use various notations to specify L/LL field, which is used by VEX/EVEX/XOP encodings. This
+// field has 1 bit (VEX/XOP) and 2 bits (EVEX) and in general the notation used is 128/256/512, which determines
+// the size of SIMD operation, and this is also the notation we want to convert everything else into.
+const OpcodeLLMapping = dict({
+ "128": "128",
+ "256": "256",
+ "512": "512",
+ "LZ" : "128",
+ "LLZ": "128",
+ "L0" : "128",
+ "L1" : "256",
+ "LIG": "LIG",
+ "Lxy": "xy",
+ "xyz": "xyz"
+});
+
+const RegSize = Object.freeze({
+ "r8" : 8,
+ "r8hi": 8,
+ "r16" : 16,
+ "r32" : 32,
+ "r64" : 64,
+ "mm" : 64,
+ "xmm" : 128,
+ "ymm" : 256,
+ "zmm" : 512,
+ "tmm" : 512, // Maximum size (64 bytes).
+ "bnd" : 128,
+ "k" : 64,
+ "st" : 80
+});
+
+// CpuRegs
+// =======
+
+// Build an object containing CPU registers as keys mapping them to type, kind, and index.
+function buildCpuRegs(defs) {
+ const map = dict();
+
+ for (let type in defs) {
+ const def = defs[type];
+ const kind = def.kind;
+ const names = def.names;
+ const group = def.group;
+
+ if (def.any)
+ map[def.any] = { type: type, kind: kind, index: -1, group: group };
+
+ if (names) {
+ for (let i = 0; i < names.length; i++) {
+ let name = names[i];
+ let m = /^([A-Za-z\(\)]+)(\d+)-(\d+)([A-Za-z\(\)]*)$/.exec(name);
+
+ if (m) {
+ let a = parseInt(m[2], 10);
+ let b = parseInt(m[3], 10);
+
+ for (let n = a; n <= b; n++) {
+ const index = m[1] + n + m[4];
+ map[index] = { type: type, kind: kind, index: index };
+ }
+ }
+ else {
+ map[name] = { type: type, kind: kind, index: i };
+ }
+ }
+ }
+ }
+
+ // HACK: In instruction manuals `r8` denotes low 8-bit register, however,
+ // that collides with `r8`, which is a 64-bit register. Since the result
+ // of this function is only used internally we patch it to be compatible
+ // with what Intel specifies.
+ map.r8.type = "r8";
+
+ return map;
+}
+
+const CpuRegisters = buildCpuRegs({
+ "r8" : { "kind": "gp" , "any": "r8" , "names": ["al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", "r8-15b"] },
+ "r8hi": { "kind": "gp" , "names": ["ah", "ch", "dh", "bh"] },
+ "r16" : { "kind": "gp" , "any": "r16" , "names": ["ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8-15w"] },
+ "r32" : { "kind": "gp" , "any": "r32" , "names": ["eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "r8-15d"] },
+ "r64" : { "kind": "gp" , "any": "r64" , "names": ["rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8-15"] },
+ "rxx" : { "kind": "gp" , "names": ["zax", "zcx", "zdx", "zbx", "zsp", "zbp", "zsi", "zdi"] },
+ "sreg": { "kind": "sreg", "any": "sreg" , "names": ["es", "cs", "ss", "ds", "fs", "gs" ] },
+ "creg": { "kind": "creg", "any": "creg" , "names": ["cr0-15"] },
+ "dreg": { "kind": "dreg", "any": "dreg" , "names": ["dr0-15"] },
+ "bnd" : { "kind": "bnd" , "any": "bnd" , "names": ["bnd0-3"] },
+ "st" : { "kind": "st" , "any": "st(i)", "names": ["st(0-7)"] },
+ "mm" : { "kind": "mm" , "any": "mm" , "names": ["mm0-7"] },
+ "k" : { "kind": "k" , "any": "k" , "names": ["k0-7"] },
+ "xmm" : { "kind": "vec" , "any": "xmm" , "names": ["xmm0-31"] },
+ "ymm" : { "kind": "vec" , "any": "ymm" , "names": ["ymm0-31"] },
+ "zmm" : { "kind": "vec" , "any": "zmm" , "names": ["zmm0-31"] },
+ "tmm" : { "kind": "tile", "any": "tmm" , "names": ["tmm0-7"] }
+});
+
+// asmdb.x86.Utils
+// ===============
+
+// X86/X64 utilities.
+class Utils {
+ static groupOf(op) {
+ return Object.hasOwn(OperandGroupInfo, op) ? OperandGroupInfo[op].group : null;
+ }
+
+ static splitInstructionSignature(s) {
+ let prefixes = [];
+ if (s.startsWith("[")) {
+ const prefixEnd = Parsing.matchClosingChar(s, 0);
+ prefixes = s.substring(1, prefixEnd).replace("xacqrel", "xacquire|xrelease").split("|");
+
+ s = s.substring(prefixEnd + 1).trim();
+ }
+
+ let nameEnd = s.indexOf(" ");
+ let names = s.substring(0, nameEnd === -1 ? s.length : nameEnd);
+ let operands = nameEnd === -1 ? "" : s.substring(nameEnd + 1).trim();
+
+ if (names.endsWith("{nf}")) {
+ names = names.substring(0, names.length - 4);
+ prefixes.nf = true;
+ }
+
+ return {
+ names: names.split("|"),
+ prefixes: prefixes,
+ operands: operands
+ }
+ }
+
+ // Split the operand(s) string into individual operands as defined by the
+ // instruction database.
+ //
+ // NOTE: X86/X64 doesn't require anything else than separating the commas,
+ // this function is here for compatibility with other instruction sets.
+ static splitOperands(s) {
+ const array = s.split(",");
+ for (let i = 0; i < array.length; i++)
+ array[i] = array[i].trim();
+ return array;
+ }
+
+ // Get whether the string `s` describes a register operand.
+ static isRegOp(s) { return s && Object.hasOwn(CpuRegisters, s); }
+ // Get whether the string `s` describes a memory operand.
+ static isMemOp(s) { return s && /^(?:mem|mib|tmem|moff||(?:m(?:off)?\d+(?:dec|bcd|fp|int)?)|(?:m16_\d+)|(?:vm\d+(?:x|y|z)))$/.test(s); }
+ // Get whether the string `s` describes an immediate operand.
+ static isImmOp(s) { return s && /^(?:1|imm4|imm8|imm16|imm32|imm64|imms8|imms32|immu16|immu32|immv|if|p16_16|p16_32|dfv)$/.test(s); }
+ // Get whether the string `s` describes a relative displacement (label).
+ static isRelOp(s) { return s && /^rel\d+$/.test(s); }
+
+ // Get a register type of a `s`, returns `null` if the register is unknown.
+ static regTypeOf(s) { return Object.hasOwn(CpuRegisters, s) ? CpuRegisters[s].type : null; }
+ // Get a register kind of a `s`, returns `null` if the register is unknown.
+ static regKindOf(s) { return Object.hasOwn(CpuRegisters, s) ? CpuRegisters[s].kind : null; }
+ // Get a register type of a `s`, returns `null` if the register is unknown and `-1`
+ // if the given string does only represent a register type, but not a specific reg.
+ static regIndexOf(s) { return Object.hasOwn(CpuRegisters, s) ? CpuRegisters[s].index : null; }
+
+ static regSize(s) {
+ if (s in RegSize)
+ return RegSize[s];
+
+ const reg = CpuRegisters[s];
+ if (reg && reg.type in RegSize)
+ return RegSize[reg.type];
+
+ return -1;
+ }
+
+ // Get size of an immediate `s` [in bits].
+ //
+ // Handles "ib", "iw", "id", "if", "iq", and also "/is4".
+ static immSize(s) {
+ switch (s) {
+ case "/is4" : return 4;
+ case "imm4" : return 4;
+ case "1" : return 8;
+ case "imm8" : return 8;
+ case "imm16" : return 16;
+ case "imm32" : return 32;
+ case "imm64" : return 64;
+ case "imms8" : return 8;
+ case "imms32": return 32;
+ case "immu16": return 16;
+ case "immu32": return 32;
+ case "ib" :
+ case "ub" : return 8;
+ case "iw" :
+ case "uw" : return 16;
+ case "id" :
+ case "ud" : return 32;
+ case "iq" :
+ case "uq" : return 64;
+ case "p16_16": return 32;
+ case "if" :
+ case "p16_32": return 48;
+
+ // Influences EVEX encoding, not an immediate byte.
+ case "dfv" : return 0;
+
+ // Invalid immediate.
+ default : FAIL(`Invalid immediate ${s}`);
+ }
+ }
+
+ // Get size of a relative displacement [in bits].
+ static relSize(s) {
+ switch (s) {
+ case "rel8" : return 8;
+ case "rel16" : return 16;
+ case "rel32" : return 32;
+ default : return -1;
+ }
+ }
+}
+x86.Utils = Utils;
+
+// asmdb.x86.Operand
+// =================
+
+// X86/X64 operand.
+class Operand extends base.Operand {
+ constructor() {
+ super();
+
+ this.groupPattern = ""; // Group pattern in case this operand was created from a group.
+ this.memSegment = ""; // Segment specified with register that is used to perform a memory IO.
+ this.memOff = false; // Memory operand is an absolute offset (only a specific version of MOV).
+ this.memFar = false; // Memory is a far pointer (includes segment in first two bytes).
+ this.vsibReg = ""; // AVX VSIB register type (xmm/ymm/zmm).
+ this.vsibSize = -1; // AVX VSIB register size (32/64).
+ this.bcstSize = -1; // AVX-512 broadcast size.
+ }
+
+ _substituteGroupOp(op, groupIndex) {
+ const opPart = op.match(/^([A-Za-z]+)/);
+ if (opPart) {
+ const groupPattern = Utils.groupOf(opPart[1]);
+ if (groupPattern) {
+ this.groupPattern = groupPattern;
+ return OperandGroupInfo[opPart[1]].subst[groupIndex] + op.substring(opPart[1].length);
+ }
+ }
+ return op;
+ }
+
+ assignData(data, defaultAccess, groupIndex) {
+ let s = data;
+ this.data = data;
+
+ const type = [];
+
+ // Handle RWX decorators prefix "[RWwXx]:".
+ let access = defaultAccess;
+ const access_match = /^(R|W|w|X|x)(\?)?\:/.exec(s);
+ if (access_match) {
+ // TODO: Conditional access is ignored at the moment.
+ access = access_match[1];
+ s = s.substring(access_match[0].length);
+ }
+
+ // Handle commutativity attribute.
+ if (Parsing.isCommutative(s)) {
+ this.commutative = true;
+ s = Parsing.clearCommutative(s);
+ }
+
+ // Handle AVX-512 broadcast possibility specified as "/bN" suffix.
+ const mBcst = /\/b(\d+)/.exec(s);
+ if (mBcst) {
+ this.bcstSize = parseInt(mBcst[1], 10);
+
+ // Remove the broadcast attribute from the definition; it's not needed anymore.
+ s = s.substring(0, mBcst.index) + s.substring(mBcst.index + mBcst[0].length);
+ }
+
+ // Handle <implicit> attribute.
+ if (Parsing.isImplicit(s)) {
+ this.implicit = true;
+ s = Parsing.clearImplicit(s);
+ }
+
+ // Support multiple operands separated by "/" (only used by r/m).
+ let ops = s.split("/");
+ let oArr = [];
+
+ for (let i = 0; i < ops.length; i++) {
+ let origOp = ops[i].trim();
+ let op = this._substituteGroupOp(origOp, groupIndex);
+
+ // Handle range suffix [A] or [A:B]:
+ const mRange = /\[(\d+)\s*(?:\:\s*(\d+)\s*)?\]$/.exec(op);
+ if (mRange) {
+ const a = parseInt(mRange[1], 10);
+ const b = parseInt(mRange[2] || String(a), 10);
+
+ if (a < b)
+ FAIL(`Operand '${origOp}' contains invalid range '[${a}:${b}]'`)
+
+ this.rwxIndex = b;
+ this.rwxWidth = a - b + 1;
+
+ op = op.substring(0, op.length - mRange[0].length);
+ }
+
+ // Handle a segment specification if this is an implicit register performing memory access.
+ const memSegRegM = op.match(/\((ds|es)\:\s*([\w]+)\)$/);
+ if (memSegRegM) {
+ this.memSegment = memSegRegM[1];
+ this.memRegOnly = memSegRegM[2];
+ op = op.substring(0, memSegRegM.index).trim();
+ }
+
+ oArr.push(op);
+
+ let regIndexRel = 0;
+ if (op.endsWith("+1") || op.endsWith("+2") || op.endsWith("+3")) {
+ regIndexRel = parseInt(op.substr(op.length - 1, 1));
+ op = op.substring(0, op.length - 2);
+ }
+
+ // Group substitution - when a rv/mv instruction uses 'w' or 'x' access it's only used by
+ // the 16-bit form, 32-bit and 64-bit always use 'W' and 'X' when used in a 'rv/mv' group.
+ if (this.groupPattern === "rv" && groupIndex > 0 && access !== "R") {
+ access = access.toUpperCase();
+ }
+
+ if (Utils.isRegOp(op)) {
+ this.reg = op;
+ this.regType = Utils.regTypeOf(op);
+ this.regIndexRel = regIndexRel;
+ this.setAccess(access);
+
+ type.push("reg");
+ continue;
+ }
+
+ if (Utils.isMemOp(op)) {
+ this.mem = op;
+ this.setAccess(access);
+
+ // Handle memory size.
+ const mOff = /^m(?:off)?(\d+)/.exec(op);
+ this.memSize = mOff ? parseInt(mOff[1], 10) : 0;
+ this.memOff = op.indexOf("moff") === 0;
+
+ const mSeg = /^m16_(\d+)/.exec(op);
+ if (mSeg) {
+ this.memFar = true;
+ this.memSize = parseInt(mSeg[1], 10) + 16;
+ }
+
+ // Handle vector addressing mode and size "vmXXr".
+ const mVM = /^vm(\d+)(x|y|z)$/.exec(op);
+ if (mVM) {
+ this.vsibReg = mVM[2] + "mm";
+ this.vsibSize = parseInt(mVM[1], 10);
+ }
+
+ type.push("mem");
+ continue;
+ }
+
+ if (Utils.isImmOp(op)) {
+ const size = Utils.immSize(op);
+ if (!this.imm)
+ this.imm = size;
+ else if (this.imm !== size)
+ FAIL(`Immediate size mismatch: ${this.imm} != ${size}`);
+
+ // Sign-extend / zero-extend.
+ const sign = op.startsWith("imms") ? "signed" :
+ op.startsWith("immu") ? "unsigned" : "any";
+ this.immSign = sign;
+
+ if (op === "1") {
+ this.immValue = 1;
+ this.implicit = true;
+ }
+
+ if (type.indexOf("imm") !== -1)
+ type.push("imm");
+ continue;
+ }
+
+ if (Utils.isRelOp(op)) {
+ this.rel = Utils.relSize(op);
+
+ type.push("rel");
+ continue;
+ }
+
+ FAIL(`Operand '${origOp}' unhandled`);
+ }
+
+ // In case the data has been modified it's always better to use the stripped off
+ // version as we have already processed and stored all the possible decorators.
+ this.data = oArr.join("/");
+ this.type = type.join("/");
+
+ if (this.rwxIndex === -1) {
+ const opSize = this.isReg() ? this.regSize :
+ this.isMem() ? this.memSize : -1;
+ if (opSize !== -1) {
+ this.rwxIndex = 0;
+ this.rwxWidth = opSize;
+ }
+ }
+ }
+
+ get regSize() {
+ return Utils.regSize(this.reg);
+ }
+
+ setAccess(x) {
+ const u = x.toUpperCase();
+ this.zext = x === "W" || x === "X";
+ this.read = u === "R" || u === "X";
+ this.write = u === "W" || u === "X";
+ return this;
+ }
+
+
+ isFixedReg() { return this.reg && this.reg !== this.regType && this.reg !== "st(i)"; }
+ isFixedMem() { return this.memSegment && this.isFixedReg(); }
+
+ isPartialOp() {
+ const maybePartial = this.regType === "r8" ||
+ this.regType === "r8hi" ||
+ this.regType === "r16" ||
+ this.regType === "xmm";
+ return maybePartial && !this.zext;
+ }
+
+ toRegMem() {
+ if (this.reg && this.mem)
+ return this.reg + "/m";
+ else if (this.mem && (this.vsibReg || /fp$|int$/.test(this.mem)))
+ return this.mem;
+ else if (this.mem)
+ return "m";
+ else
+ return this.toString();
+ }
+
+ toString() { return this.data; }
+}
+x86.Operand = Operand;
+
+// asmdb.x86.Instruction
+// =====================
+
+// X86/X64 instruction.
+class Instruction extends base.Instruction {
+ constructor(db) {
+ super(db);
+
+ this.opcode = dict({
+ byte : "", // Opcode byte (a single value specified as HEX string "00-FF").
+ ri : false, // Instruction opcode is combined with register, "XX+r" or "XX+i".
+ _67h : false, // Opcode 67h prefix use.
+ mm : "", // Opcode MM[MMM] part (map).
+ pp : "", // Opcode PP part.
+ w : "", // Opcode W field.
+ l : "", // EVEX.LL (nothing, 128, 256, 512, LIG).
+ nd : 0, // EVEX.ND (new dest) field (default is false, specified as ND=0 or ND=1).
+ nf : 0, // EVEX.NF (no flags) field (default is false, specified as NF=0 or NF=1).
+ scc : "", // EVEX.SCC field (4 bits - condition flags).
+ mod : "", // MODRM.MOD part (2 bits) - either "xx", "11" or "!(11)".
+ modr : "", // MODRM.R part (3 bits) - either "rrr"
+ modrm: "" // MODRM.R/M part - either "bbb"
+ });
+
+ this.prefix = ""; // Prefix - "", "3DNOW", "EVEX", "VEX", "XOP".
+ this.privilege = "L3"; // Privilege level required to execute the instruction.
+ this.groupPattern = ""; // Group pattern in case the instruction was created from a group such as "ry", "rv", "xy", "xyz".
+ this.groupIndex = -1; // Group index.
+
+ this.rel = 0; // Displacement ("cb", "cw", and "cd" parts).
+
+ this.fpuTop = 0; // FPU top index manipulation [-1, 0, 1, 2].
+ this.fpuStack = ""; // FPU stack manipulation
+
+ this.vsibReg = ""; // AVX VSIB register type (xmm/ymm/zmm).
+ this.vsibSize = -1; // AVX VSIB register size (32/64).
+
+ this.broadcast = false; // AVX-512 broadcast support.
+ this.bcstSize = -1; // AVX-512 broadcast size.
+
+ this.k = ""; // AVX-512 K function ("", "blend", "zeroing").
+ this.kmask = false; // AVX-512 merging {k}.
+ this.zmask = false; // AVX-512 zeroing {kz}, implies {k}.
+ this.er = false; // AVX-512 embedded rounding {er}, implies {sae}.
+ this.sae = false; // AVX-512 suppress all exceptions {sae} support.
+
+ this.tupleType = ""; // AVX-512 tuple-type.
+ this.elementSize = -1; // Instruction's element size.
+ this.encodingPreference = ""; // Encoding preference (either nothing or "EVEX").
+
+ this.consecutiveLead = 0; // Consecutive register leading N other registers.
+ this.prefixes = dict(); // Allowed prefixes.
+ }
+
+ _substituteOpcodePart(op, groupIndex) {
+ if (Object.hasOwn(OpcodeGroupInfo, op)) {
+ return OpcodeGroupInfo[op].subst[groupIndex];
+ }
+ else {
+ return op;
+ }
+ }
+
+ assignData(data, groupIndex) {
+ this.name = data.name;
+ this.groupIndex = groupIndex;
+
+ if (data.tt)
+ this.tupleType = data.tt;
+
+ const em = data.op.match(/^\[\s*(\w+)\s*\](.*)$/);
+ const encodingField = em ? em[1] : "NONE";
+ const opcodeField = em ? em[2] : data.op;
+
+ this._assignOperands(data.operands, groupIndex);
+ this._assignEncoding(encodingField);
+ this._assignOpcode(opcodeField.trim(), groupIndex);
+
+ for (let k in data) {
+ if (k === "name" || k === "op" || k === "operands")
+ continue;
+ this._assignAttribute(k, data[k]);
+ }
+
+ this._updateOperandsInfo();
+ this._postProcess();
+ }
+
+ _assignAttribute(key, value) {
+ switch (key) {
+ case "vl":
+ if (value) {
+ this.ext["AVX512_VL"] = true;
+ }
+ return;
+
+ case "prefixes":
+ this._combineAttribute("prefixes", value);
+ return;
+
+ case "fpuStack":
+ this.fpuStack = value;
+ switch (value) {
+ case "dec" : this.fpuTop = -1; break;
+ case "inc" : this.fpuTop = 1; break;
+ case "pop" : this.fpuTop = 1; break;
+ case "pop2x": this.fpuTop = 2; break;
+ case "push" : this.fpuTop = -1; break;
+ default:
+ FAIL(`Invalid fpuStack value '${value}'`);
+ }
+ return;
+
+ case "kz":
+ this.zmask = true;
+ this.kmask = true;
+ return;
+
+ case "k":
+ this.kmask = true;
+ if (typeof value === "string")
+ super._assignAttribute(key, value);
+ return;
+
+ case "er":
+ this.er = true;
+ this.sae = true; // {er} implies {sae}.
+ return;
+
+ case "sae":
+ this.sae = true;
+ return;
+
+ case "broadcast":
+ this.broadcast = true;
+ this.elementSize = value;
+ return;
+
+ default:
+ super._assignAttribute(key, value);
+ }
+ }
+
+ _assignOperands(s, groupIndex) {
+ if (!s) return;
+
+ // First remove all flags specified as {...}. We put them into `flags`
+ // map and mix with others. This seems to be the best we can do here.
+ for (;;) {
+ let a = s.indexOf("{");
+ let b = s.indexOf("}");
+
+ if (a === -1 || b === -1)
+ break;
+
+ // Get the `flag` and remove it from `s`.
+ this._assignAttribute(s.substring(a + 1, b), true);
+ s = s.substring(0, a) + s.substring(b + 1);
+ }
+
+ // Split into individual operands and push them to `operands`.
+ const arr = Utils.splitOperands(s);
+ for (let i = 0; i < arr.length; i++) {
+ const operand = new Operand();
+ operand.assignData(arr[i].trim(), i === 0 ? "X" : "R", groupIndex);
+
+ if (operand.mem == "tmem") {
+ this.tsib = true;
+ }
+
+ if (operand.groupPattern && this.groupPattern !== operand.groupPattern) {
+ if (this.groupPattern) {
+ FAIL(`Instruction ${this.name}: Operand's group pattern mismatch '${this.groupPattern}' != '${operand.groupPattern}'`);
+ }
+ this.groupPattern = operand.groupPattern;
+ }
+
+ this.operands.push(operand);
+ }
+ }
+
+ _assignEncoding(s) {
+ this.encoding = s;
+ }
+
+ _assignOpcode(s, groupIndex) {
+ this.opcodeString = s;
+
+ let parts = s.split(" ");
+
+ if (/^(VEX|EVEX|XOP)\./.test(s)) {
+ // Parse VEX/XOP and EVEX encoded instruction, which looks like "<PREFIX>.[APX-DATA].<LL>.<PP>.<MAP>.<W>"
+ let prefix = parts[0].split(".");
+ this.prefix = prefix[0];
+
+ for (let i = 1; i < prefix.length; i++) {
+ let comp = prefix[i];
+
+ if (/^(Pv|Wv|Wy)$/.test(comp)) {
+ comp = OpcodeGroupInfo[comp].subst[groupIndex];
+ }
+
+ // Process APX EVEX.ND field - ND=0 or ND=1.
+ if (/^ND=[01]$/.test(comp)) {
+ this.opcode.nd = comp === "ND=1";
+ continue;
+ }
+
+ // Process APX EVEX.NF field - NF=0 or NF=1.
+ if (/^NF=[01]$/.test(comp)) {
+ this.opcode.nf = comp === "NF=1";
+ continue;
+ }
+
+ // Process APX EVEX.SCC field - SCC=0-F
+ if (/^SCC=[0-9A-F]$/.test(comp)) {
+ this.opcode.scc = comp.charAt(5);
+ continue;
+ }
+
+ // Process `L/LL` field.
+ if (Object.hasOwn(OpcodeLLMapping, comp)) {
+ this.opcode.l = OpcodeLLMapping[comp];
+ continue;
+ }
+
+ // Process `PP` field - 66/F2/F3/NP (NP means no PP field used)
+ if (comp === "P0") { /* ignored, `P` is zero... */ continue; }
+ if (/^(?:66|F2|F3|NP)$/.test(comp)) { this.opcode.pp = comp; continue; }
+
+ // Process `MM` field - 0F/0F3A/0F38/MAP4/MAP5/MAP6/M8/M9.
+ if (/^(?:0F|0F3A|0F38|MAP[4-9A])$/.test(comp)) { this.opcode.mm = comp; continue; }
+
+ // Process `W` field.
+ if (/^(WIG|W0|W1|)$/.test(comp)) { this.opcode.w = comp; continue; }
+
+ // TODO: Some new APX instructions don't have W specified (ENQCMD/ENQCMDS).
+ if (comp === "W?") { this.opcode.w = "W0"; continue; }
+
+ // ERROR.
+ this.report(`'${this.opcodeString}' Unhandled component: ${comp}`);
+ }
+
+ for (let i = 1; i < parts.length; i++) {
+ let comp = parts[i];
+
+ // Parse opcode.
+ if (/^[0-9A-Fa-f]{2}$/.test(comp)) {
+ this.opcode.byte = comp.toUpperCase();
+ continue;
+ }
+
+ // Parse ModR/M field using "/r" or "/0-7" notation.
+ if (/^\/[r0-7]$/.test(comp)) {
+ this.opcode.mod = "xx";
+ this.opcode.modr = comp.charAt(1);
+ this.opcode.modm = "b";
+ continue;
+ }
+
+ // Parse ModR/M field using "11:xxx:xxx" and "!(11):xxx:xxx" notation.
+ const m = comp.match(/^(11|!\(11\)):(rrr|[01]{3}):(bbb|[01]{3})$/);
+ if (m) {
+ this.opcode.mod = m[1];
+ this.opcode.modr = m[2] === "rrr" ? "r" : String(parseInt(m[2], 2));
+ this.opcode.modrm = m[3] === "bbb" ? "b" : String(parseInt(m[3], 2));
+ continue;
+ }
+
+ // Parse immediate byte, word, dword, or qword.
+ comp = this._substituteOpcodePart(comp, groupIndex);
+ if (/^(?:ib|iw|id|iq|\/is4)$/.test(comp)) {
+ this.imm += Utils.immSize(comp);
+ continue;
+ }
+
+ this.report(`'${this.opcodeString}' Unhandled opcode component: ${comp}`);
+ }
+ }
+ else {
+ // Parse X86/X64 instruction (including legacy MMX/SSE/3DNOW instructions).
+ let rex_parsed = false;
+
+ for (let i = 0; i < parts.length; i++) {
+ let comp = parts[i];
+
+ if (comp === "NFx" || comp === "NOREP" || comp === "NO67") {
+ // Ignored for now.
+ continue;
+ }
+
+ // Parse REX or REX2 prefix.
+ if (comp.startsWith("REX2.") || comp === "REX.W") {
+ if (rex_parsed) {
+ FAIL(`'${this.opcodeString}' Multiple REX prefixes are invalid`);
+ }
+
+ rex_parsed = true;
+
+ // Instructions that force REX.W prefix or use REX2 prefix are always 64-bit instructions.
+ this.arch = "X64";
+
+ if (comp === "REX.W") {
+ this.opcode.w = "W1";
+ }
+ else {
+ this.prefix = "REX2";
+
+ // REX2 has always 3 components - "REX2.<MAP>.<W>".
+ const rex2 = comp.split(".");
+ if (rex2.length !== 3) {
+ FAIL(`'${this.opcodeString}' Invalid REX2 prefix - expected exactly 3 REX2 components`);
+ }
+
+ if (rex2[1] === "MAP0") {
+ // nothing.
+ }
+ else if (rex2[1] === "MAP1") {
+ this.opcode.mm = "0F";
+ }
+ else {
+ FAIL(`'${this.opcodeString}' Invalid REX2 prefix - REX2.MAP component could be either MAP0 or MAP1`);
+ }
+
+ this.opcode.w = rex2[2];
+ }
+
+ continue;
+ }
+
+ // Parse `PP` prefixes.
+ if (this.opcode.mm === "") {
+ if (this.opcode.pp === "" && /^(?:66|F2|F3|NP)$/.test(comp) ||
+ this.opcode.pp === "66" && /^(?:F2|F3)$/.test(comp)) {
+ this.opcode.pp += comp;
+ continue;
+ }
+ }
+
+ // Parse `MM` prefixes.
+ if ((this.opcode.mm === "" && comp === "0F") ||
+ (this.opcode.mm === "0F" && /^(?:01|3A|38)$/.test(comp))) {
+ this.opcode.mm += comp;
+ continue;
+ }
+
+ // Recognize "0F 0F /r XX" encoding.
+ if (this.opcode.mm === "0F" && comp === "0F") {
+ this.prefix = "3DNOW";
+ continue;
+ }
+
+ // Parse opcode byte.
+ if (/^[0-9A-F]{2}(?:\+[ri])?$/.test(comp)) {
+ // Parse "+r" or "+i" suffix.
+ if (comp.length > 2) {
+ this.opcode.ri = true;
+ comp = comp.substring(0, 2);
+ }
+
+ // FPU instructions are encoded as "PREFIX XX", where prefix is not the same
+ // as MM prefixes used everywhere else. AsmJit internally extends MM field in
+ // instruction tables to allow storing this prefix together with other "MM"
+ // prefixes, currently the unused indexes are used, but if X86 moves forward
+ // and starts using these we can simply use more bits in the opcode DWORD.
+ if (!this.opcode.pp && this.opcode.byte === "9B") {
+ this.opcode.pp = this.opcode.byte;
+ this.opcode.byte = comp;
+ continue;
+ }
+
+ if (!this.opcode.mm && (/^(?:D8|D9|DA|DB|DC|DD|DE|DF)$/.test(this.opcode.byte))) {
+ this.opcode.mm = this.opcode.byte;
+ this.opcode.byte = comp;
+ continue;
+ }
+
+ if (this.opcode.byte) {
+ if (this.opcode.byte === "67") {
+ this.opcode._67h = true;
+ }
+ else {
+ if (!this.opcode.modr && !this.opcode.modrm) {
+ const value = parseInt(comp, 16);
+ if ((value & 0xC0) == 0xC0) {
+ this.opcode.mod = "11";
+ this.opcode.modr = String((value >> 3) & 0x7);
+ this.opcode.modrm = String((value >> 0) & 0x7);
+ }
+ else {
+ this.report(`'${this.opcodeString}' Unsupported secondary opcode (MOD/RM) '${comp}' value`);
+ }
+ }
+ else {
+ this.report(`'${this.opcodeString}' Multiple opcodes, have ${this.opcode.byte}, found ${comp}`);
+ }
+ }
+ }
+
+ this.opcode.byte = comp;
+ continue;
+ }
+
+ // Parse ModR/M field using "/r" or "/0-7" notation.
+ if (/^\/[r0-7]$/.test(comp) && !this.opcode.modr) {
+ this.opcode.mod = "xx";
+ this.opcode.modr = comp.charAt(1);
+ this.opcode.modm = "b";
+ continue;
+ }
+
+ // Parse ModR/M field using "11:xxx:xxx" and "!(11):xxx:xxx" notation.
+ const m = comp.match(/^(11|!\(11\)):(rrr|[01]{3}):(bbb|[01]{3})$/);
+ if (m) {
+ this.opcode.mod = m[1];
+ this.opcode.modr = m[2] === "rrr" ? "r" : String(parseInt(m[2], 2));
+ this.opcode.modrm = m[3] === "bbb" ? "b" : String(parseInt(m[3], 2));
+ continue;
+ }
+
+ // Parse immediate byte, word, dword, fword, or qword.
+ if (/^(?:ib|iw|id|iq|iv|if)$/.test(comp)) {
+ if (comp === "iv")
+ comp = OpcodeGroupInfo[comp].subst[groupIndex];
+ this.imm += Utils.immSize(comp);
+ continue;
+ }
+
+ if (comp === "moff") {
+ this.moff = true;
+ continue;
+ }
+
+ // Parse displacement.
+ if (/^(?:cb|cw|cd)$/.test(comp) && !this.rel) {
+ this.rel = comp === "cb" ? 1 :
+ comp === "cw" ? 2 :
+ comp === "cd" ? 4 : -1;
+ continue;
+ }
+
+ // ERROR.
+ this.report(`'${this.opcodeString}' Unhandled opcode component: ${comp}`);
+ }
+ }
+
+ // HACK: Fix instructions having opcode "01".
+ if (this.opcode.byte === "" && this.opcode.mm.indexOf("0F01") === this.opcode.mm.length - 4) {
+ this.opcode.byte = "01";
+ this.opcode.mm = this.opcode.mm.substring(0, this.opcode.mm.length - 2);
+ }
+
+ if (this.opcode.byte)
+ this.opcodeValue = parseInt(this.opcode.byte, 16);
+
+ if (!this.opcode.byte)
+ this.report(`Couldn't parse instruction's opcode '${this.opcodeString}'`);
+ }
+
+ _updateOperandsInfo() {
+ super._updateOperandsInfo();
+
+ let consecutiveLead = null;
+ let consecutiveLastIndex = 0;
+
+ for (let i = 0; i < this.operands.length; i++) {
+ const op = this.operands[i];
+
+ // Instructions that use 64-bit GP registers are always 64-bit instructions.
+ if (op.reg === "r64" || op.reg === "rax" || op.reg === "rbx" || op.reg === "rcx" || op.reg === "rdx" || op.reg === "rsi" || op.reg === "rdi")
+ this.arch = "X64";
+
+ // Propagate broadcast.
+ if (op.bcstSize > 0)
+ this._assignAttribute("broadcast", op.bcstSize);
+
+ // Propagate VSIB.
+ if (op.vsibReg) {
+ if (this.vsibReg) {
+ this.report("Only one operand can be a vector memory address (vmNNx)");
+ }
+
+ this.vsibReg = op.vsibReg;
+ this.vsibSize = op.vsibSize;
+ }
+
+ if (op.regIndexRel) {
+ if (i - op.regIndexRel < 0) {
+ this.report(`The consecutive register information is invalid, index of the lead (${i - op.regIndexRel}) is out of range`);
+ }
+ else {
+ const lead = this.operands[i - op.regIndexRel];
+ if (consecutiveLead && consecutiveLead != lead) {
+ this.report(`The consecutive register chain is invalid`);
+ }
+ else {
+ consecutiveLead = lead;
+ consecutiveLastIndex = Math.max(consecutiveLastIndex, op.regIndexRel);
+ }
+ }
+ }
+ }
+
+ if (consecutiveLead) {
+ consecutiveLead.consecutive_lead_count = consecutiveLastIndex + 1;
+ }
+ }
+
+ // Validate the instruction's definition. Common mistakes can be checked and
+ // reported easily, however, if the mistake is just an invalid opcode or
+ // something else it's impossible to detect.
+ _postProcess() {
+ if (this.groupPattern) {
+ const archInfo = ArchGroupInfo[this.groupPattern];
+ if (this.arch === "ANY" && archInfo && this.arch !== archInfo[this.groupIndex]) {
+ // TODO: Never triggered, which means it should be removed.
+ this.arch = archInfo[this.groupIndex];
+ }
+ }
+ else {
+ this.groupIndex = -1;
+ }
+
+ if (this.privilege === "L0")
+ this.category.SYSTEM = true;
+
+ let immCount = this.immCount;
+
+ // Verify that the immediate operand/operands are specified in instruction
+ // encoding and opcode field. Basically if there is an "ix" in operands,
+ // the encoding should contain "I".
+ if (immCount > 0) {
+ if (immCount === 1 && this.operands[this.operands.length - 1].data === "1") {
+ // This must be one of rcl|rcr|rol|ror|sar|sal|shr. We won't validate
+ // these as these have "1" as implicit (encoded within opcode, not after).
+ }
+ else {
+ // Every immediate should have its imm byte ("ib", "iw", "id", or "iq") in the opcode data.
+ let m = this.opcodeString.match(/(?:^|\s+)(ib|iw|id|iq|iv|if|\/is4)/g);
+ if (!m || m.length !== immCount) {
+ this.report(`Immediate(s) [${immCount}] not found in opcode: ${this.opcodeString}`);
+ }
+ }
+ }
+ }
+
+ isAVX() { return this.isVEX() || this.isEVEX(); }
+ isVEX() { return this.prefix === "VEX" || this.prefix === "XOP"; }
+ isEVEX() { return this.prefix === "EVEX" }
+
+ getWValue() {
+ switch (this.opcode.w) {
+ case "W0": return 0;
+ case "W1": return 1;
+ }
+ return -1;
+ }
+
+ // Get signature of the instruction as "ARCH PREFIX ENCODING[:operands]" form.
+ get signature() {
+ let operands = this.operands;
+ let sign = this.arch;
+
+ if (this.prefix) {
+ sign += " " + this.prefix;
+ if (this.prefix !== "3DNOW") {
+ if (this.opcode.l === "L1")
+ sign += ".256";
+ else if (this.opcode.l === "256" || this.opcode.l === "512")
+ sign += `.${this.opcode.l}`;
+ else
+ sign += ".128";
+
+ if (this.opcode.w === "W1")
+ sign += ".W";
+ }
+ }
+ else if (this.opcode.w === "W1") {
+ sign += " REX.W";
+ }
+
+ sign += " " + this.encoding;
+
+ for (let i = 0; i < operands.length; i++) {
+ sign += (i === 0) ? ":" : ",";
+
+ let operand = operands[i];
+ if (operand.implicit)
+ sign += `[${operand.reg}]`;
+ else
+ sign += operand.toRegMem();
+ }
+
+ return sign;
+ }
+
+ get immCount() {
+ let ops = this.operands;
+ let n = 0;
+ for (let i = 0; i < ops.length; i++)
+ if (ops[i].isImm())
+ n++;
+ return n;
+ }
+
+ get modRValue() {
+ if (/^[0-7]$/.test(this.opcode.modr))
+ return parseInt(this.opcode.modr, 10);
+ else
+ return 0;
+ }
+
+ get modRMValue() {
+ if (/^[0-7]$/.test(this.opcode.modrm))
+ return parseInt(this.opcode.modrm, 10);
+ else
+ return 0;
+ }
+}
+x86.Instruction = Instruction;
+
+// asmdb.x86.ISA
+// =============
+
+const ArchKeys = MapUtils.mapFromArray(["any", "x86", "x64", "apx", "___"]);
+
+function findArch(inst) {
+ for (let a in ArchKeys) {
+ if (typeof inst[a] === "string") {
+ return a;
+ }
+ }
+
+ FAIL(`Instruction signature not found in record: ${JSON.stringify(inst)}`);
+}
+
+function mergeGroupData(data, group) {
+ for (let k in group) {
+ switch (k) {
+ case "group":
+ case "instructions":
+ break;
+
+ case "ext":
+ data[k] = (data[k] ? data[k] + " " : "") + group[k];
+ break;
+
+ default:
+ if (data[k] === undefined)
+ data[k] = group[k]
+ break;
+ }
+ }
+}
+
+// X86/X64 instruction database - stores Instruction instances in a map and
+// aggregates all instructions with the same name.
+class ISA extends base.ISA {
+ constructor(data) {
+ super(data);
+ this.addData(data || NONE);
+ }
+
+ _addInstructions(groups) {
+ for (let group of groups) {
+ for (let record of group.instructions) {
+ let arch = findArch(record);
+
+ // TODO: Ignore records having this (only used for testing purposes).
+ if (arch === "___")
+ continue;
+
+ const apx = arch === "apx";
+
+ const sgn = Utils.splitInstructionSignature(record[arch]);
+ const data = MapUtils.cloneExcept(record, arch);
+
+ mergeGroupData(data, group)
+
+ for (let j = 0; j < sgn.names.length; j++) {
+ data.name = sgn.names[j];
+ data.prefixes = sgn.prefixes;
+ data.operands = sgn.operands;
+
+ if (j > 0) {
+ data.aliasOf = sgn.names[0];
+ }
+
+ let groupIndex = 0;
+ let instruction = null;
+ do {
+ instruction = new Instruction(this);
+ instruction.arch = apx ? "X64" : arch.toUpperCase();
+ instruction.assignData(data, groupIndex);
+
+ if (apx) {
+ instruction.ext["APX_F"] = true;
+ if (instruction.category.GP) {
+ instruction.category.GP_EXT = true
+ }
+ }
+
+ this._addInstruction(instruction);
+ } while (instruction.groupPattern && ++groupIndex < OperandGroupInfo[instruction.groupPattern].subst.length);
+ }
+ }
+ }
+
+ return this;
+ }
+}
+x86.ISA = ISA;
+
+// asmdb.x86.X86DataCheck
+// ======================
+
+class X86DataCheck {
+ static checkVexEvex(db) {
+ const map = db.instructionMap;
+ for (let name in map) {
+ const instructions = map[name];
+ for (let i = 0; i < instructions.length; i++) {
+ const instA = instructions[i];
+ for (let j = i + 1; j < instructions.length; j++) {
+ const instB = instructions[j];
+ if (instA.operands.join("_") === instB.operands.join("_")) {
+ const vex = instA.prefix === "VEX" ? instA : instB.prefix === "VEX" ? instB : null;
+ const evex = instA.prefix === "EVEX" ? instA : instB.prefix === "EVEX" ? instB : null;
+
+ if (vex && evex && vex.opcode.byte === evex.opcode.byte) {
+ // NOTE: There are some false positives, they will be printed as well.
+ let ok = vex.opcode.w === evex.opcode.w && vex.opcode.l === evex.opcode.l;
+
+ if (!ok) {
+ console.log(`Instruction ${name} differs:`);
+ console.log(` ${vex.operands.join(" ")}: ${vex.opcodeString}`);
+ console.log(` ${evex.operands.join(" ")}: ${evex.opcodeString}`);
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+}
+x86.X86DataCheck = X86DataCheck;
+
+}).apply(this, typeof module === "object" && module && module.exports
+ ? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "x86"]);
diff --git a/3rdparty/asmjit/tools/enumgen.js b/3rdparty/asmjit/tools/enumgen.js
index d02c34d5e32..3823b803d88 100644
--- a/3rdparty/asmjit/tools/enumgen.js
+++ b/3rdparty/asmjit/tools/enumgen.js
@@ -405,7 +405,7 @@ class Generator {
}
const generator = new Generator({
- baseDir : path.resolve(__dirname, "../src"),
+ baseDir : path.resolve(__dirname, ".."),
verify : process.argv.indexOf("--verify") !== -1,
noBackup: process.argv.indexOf("--no-backup") !== -1
});
diff --git a/3rdparty/asmjit/tools/tablegen-a64.js b/3rdparty/asmjit/tools/tablegen-a64.js
index c0c416abdbf..363a47da364 100644
--- a/3rdparty/asmjit/tools/tablegen-a64.js
+++ b/3rdparty/asmjit/tools/tablegen-a64.js
@@ -83,7 +83,7 @@ class ArmTableGen extends core.TableGen {
// --------------------------------------------------------------------------
parse() {
- const rawData = this.dataOfFile("src/asmjit/arm/a64instdb.cpp");
+ const rawData = this.dataOfFile("asmjit/arm/a64instdb.cpp");
const stringData = StringUtils.extract(rawData, "// ${InstInfo:Begin}", "// ${InstInfo:End");
const re = new RegExp(
@@ -186,11 +186,11 @@ class ArmTableGen extends core.TableGen {
onBeforeRun() {
this.load([
- "src/asmjit/arm/a64emitter.h",
- "src/asmjit/arm/a64globals.h",
- "src/asmjit/arm/a64instdb.cpp",
- "src/asmjit/arm/a64instdb.h",
- "src/asmjit/arm/a64instdb_p.h"
+ "asmjit/arm/a64emitter.h",
+ "asmjit/arm/a64globals.h",
+ "asmjit/arm/a64instdb.cpp",
+ "asmjit/arm/a64instdb.h",
+ "asmjit/arm/a64instdb_p.h"
]);
this.parse();
}
diff --git a/3rdparty/asmjit/tools/tablegen-x86.js b/3rdparty/asmjit/tools/tablegen-x86.js
index 91d9754278c..e58328e52b4 100644
--- a/3rdparty/asmjit/tools/tablegen-x86.js
+++ b/3rdparty/asmjit/tools/tablegen-x86.js
@@ -469,7 +469,7 @@ class X86TableGen extends core.TableGen {
// --------------------------------------------------------------------------
parse() {
- const data = this.dataOfFile("src/asmjit/x86/x86instdb.cpp");
+ const data = this.dataOfFile("asmjit/x86/x86instdb.cpp");
const re = new RegExp(
"INST\\(" +
"([A-Za-z0-9_]+)\\s*" + "," + // [01] Instruction.
@@ -777,10 +777,10 @@ class X86TableGen extends core.TableGen {
onBeforeRun() {
this.load([
- "src/asmjit/x86/x86globals.h",
- "src/asmjit/x86/x86instdb.cpp",
- "src/asmjit/x86/x86instdb.h",
- "src/asmjit/x86/x86instdb_p.h"
+ "asmjit/x86/x86globals.h",
+ "asmjit/x86/x86instdb.cpp",
+ "asmjit/x86/x86instdb.h",
+ "asmjit/x86/x86instdb_p.h"
]);
this.parse();
}