1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
|
// license:BSD-3-Clause
// copyright-holders:Curt Coder
/**********************************************************************
MOS Technology 6530 Memory, I/O, Timer Array emulation
MOS Technology 6532 RAM, I/O, Timer Array emulation
**********************************************************************
_____ _____
Vss 1 |* \_/ | 40 PA1
PA0 2 | | 39 PA2
phi2 3 | | 38 PA3
RS0 4 | | 37 PA4
A9 5 | | 36 PA5
A8 6 | | 35 PA6
A7 7 | | 34 PA7
A6 8 | | 33 DB0
R/W 9 | | 32 DB1
A5 10 | MCS6530 | 31 DB2
A4 11 | | 30 DB3
A3 12 | | 29 DB4
A2 13 | | 28 DB5
A1 14 | | 27 DB6
A0 15 | | 26 DB7
_RES 16 | | 25 PB0
IRQ/PB7 17 | | 24 PB1
CS1/PB6 18 | | 23 PB2
CS2/PB5 19 | | 22 PB3
Vcc 20 |_____________| 21 PB4
_____ _____
Vss 1 |* \_/ | 40 A6
A5 2 | | 39 phi2
A4 3 | | 38 CS1
A3 4 | | 37 _CS2
A2 5 | | 36 _RS
A1 6 | | 35 R/W
A0 7 | | 34 _RES
PA0 8 | | 33 D0
PA1 9 | | 32 D1
PA2 10 | MCS6532 | 31 D2
PA3 11 | | 30 D3
PA4 12 | | 29 D4
PA5 13 | | 28 D5
PA6 14 | | 27 D6
PA7 15 | | 26 D7
PB7 16 | | 25 _IRQ
PB6 17 | | 24 PB0
PB5 18 | | 23 PB1
PB4 19 | | 22 PB2
Vcc 20 |_____________| 21 PB3
**********************************************************************/
#ifndef MAME_MACHINE_MOS6530N_H
#define MAME_MACHINE_MOS6530N_H
#pragma once
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
// ======================> mos6530_device_base
class mos6530_device_base : public device_t
{
public:
auto irq_wr_callback() { return m_irq_cb.bind(); }
auto pa_rd_callback() { return m_in8_pa_cb.bind(); }
auto pa_wr_callback() { return m_out8_pa_cb.bind(); }
auto pb_rd_callback() { return m_in8_pb_cb.bind(); }
auto pb_wr_callback() { return m_out8_pb_cb.bind(); }
template <unsigned N> auto pa_rd_callback() { return m_in_pa_cb[N].bind(); }
template <unsigned N> auto pa_wr_callback() { return m_out_pa_cb[N].bind(); }
template <unsigned N> auto pb_rd_callback() { return m_in_pb_cb[N].bind(); }
template <unsigned N> auto pb_wr_callback() { return m_out_pb_cb[N].bind(); }
DECLARE_WRITE_LINE_MEMBER( pa0_w ) { pa_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( pa1_w ) { pa_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( pa2_w ) { pa_w(2, state); }
DECLARE_WRITE_LINE_MEMBER( pa3_w ) { pa_w(3, state); }
DECLARE_WRITE_LINE_MEMBER( pa4_w ) { pa_w(4, state); }
DECLARE_WRITE_LINE_MEMBER( pa5_w ) { pa_w(5, state); }
DECLARE_WRITE_LINE_MEMBER( pa6_w ) { pa_w(6, state); }
DECLARE_WRITE_LINE_MEMBER( pa7_w ) { pa_w(7, state); }
DECLARE_WRITE_LINE_MEMBER( pb0_w ) { pb_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( pb1_w ) { pb_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( pb2_w ) { pb_w(2, state); }
DECLARE_WRITE_LINE_MEMBER( pb3_w ) { pb_w(3, state); }
DECLARE_WRITE_LINE_MEMBER( pb4_w ) { pb_w(4, state); }
DECLARE_WRITE_LINE_MEMBER( pb5_w ) { pb_w(5, state); }
DECLARE_WRITE_LINE_MEMBER( pb6_w ) { pb_w(6, state); }
DECLARE_WRITE_LINE_MEMBER( pb7_w ) { pb_w(7, state); }
protected:
// construction/destruction
mos6530_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, u32 rsize);
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
TIMER_CALLBACK_MEMBER(update);
enum
{
IRQ_EDGE = 0x40,
IRQ_TIMER = 0x80
};
void update_pa();
virtual void update_pb();
virtual void update_irq();
virtual uint8_t get_irq_flags();
void edge_detect();
void pa_w(int bit, int state);
void pb_w(int bit, int state);
void timer_w(offs_t offset, uint8_t data, bool ie);
uint8_t timer_r(bool ie);
uint8_t rom_r(offs_t offset) { return m_rom[offset]; }
uint8_t ram_r(offs_t offset) { return m_ram[offset]; }
void ram_w(offs_t offset, uint8_t data) { m_ram[offset] = data; }
uint8_t pa_data_r();
void pa_data_w(uint8_t data);
uint8_t pb_data_r();
void pb_data_w(uint8_t data);
uint8_t pa_ddr_r() { return m_pa_ddr; }
void pa_ddr_w(uint8_t data);
uint8_t pb_ddr_r() { return m_pb_ddr; }
void pb_ddr_w(uint8_t data);
uint8_t timer_off_r();
uint8_t timer_on_r();
uint8_t irq_r();
void timer_off_w(offs_t offset, uint8_t data);
void timer_on_w(offs_t offset, uint8_t data);
void edge_w(uint8_t data);
memory_share_creator<uint8_t> m_ram;
optional_region_ptr<uint8_t> m_rom;
devcb_write_line m_irq_cb;
devcb_read8 m_in8_pa_cb;
devcb_write8 m_out8_pa_cb;
devcb_read8 m_in8_pb_cb;
devcb_write8 m_out8_pb_cb;
devcb_read_line::array<8> m_in_pa_cb;
devcb_write_line::array<8> m_out_pa_cb;
devcb_read_line::array<8> m_in_pb_cb;
devcb_write_line::array<8> m_out_pb_cb;
uint8_t m_pa_in;
uint8_t m_pa_out;
uint8_t m_pa_ddr;
int m_pa7;
int m_pa7_dir;
uint8_t m_pb_in;
uint8_t m_pb_out;
uint8_t m_pb_ddr;
bool m_ie_timer;
bool m_irq_timer;
bool m_ie_edge;
bool m_irq_edge;
int m_prescale;
uint8_t m_timer;
enum {
IDLE,
RUNNING,
RUNNING_SYNCPOINT,
RUNNING_AFTER_INTERRUPT
};
struct live_info {
attotime tm, tm_irq;
attotime period;
int state, next_state;
uint8_t value;
};
live_info cur_live, checkpoint_live;
emu_timer *t_gen;
void live_start();
void checkpoint();
void rollback();
void live_delay(int state);
void live_sync();
void live_abort();
void live_run(const attotime &limit = attotime::never);
};
class mos6530_new_device : public mos6530_device_base
{
public:
// construction/destruction
mos6530_new_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void rom_map(address_map &map);
virtual void ram_map(address_map &map);
virtual void io_map(address_map &map);
protected:
// device-level overrides
void update_pb() override;
void update_irq() override;
uint8_t get_irq_flags() override;
};
class mos6532_new_device : public mos6530_device_base
{
public:
// construction/destruction
mos6532_new_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void ram_map(address_map &map);
virtual void io_map(address_map &map);
};
// device type definition
DECLARE_DEVICE_TYPE(MOS6530_NEW, mos6530_new_device)
DECLARE_DEVICE_TYPE(MOS6532_NEW, mos6532_new_device)
#endif // MAME_MACHINE_MOS6530N_H
|