summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/mn1880/mn1880d.cpp
blob: 01ab3fac038b4bece4be2ca0c4e5cf0c76e81612 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
// license:BSD-3-Clause
// copyright-holders:AJR
/***************************************************************************

    Panasonic MN1880 family disassembler

    Due to the dearth of available documentation for the MN1880 series,
    its instruction list has been reconstructed from MN1870 and MN1890
    manuals, a (decidedly incomplete) list of MN1880 instructions not
    provided in the MN1870 series, and a few educated guesses based on
    reverse engineering (which include CALL XP actually being provided by
    the MN1880 despite the MN1870 manual claiming it as exclusive).

    The direct flag (bit 5 of the flag status register) is the key to
    data memory addressing. When DF is cleared, the upper bytes of direct
    addresses are zeroed; when DF is set, the upper address bytes are
    taken from YPh for source operands and XPh for destination operands.

    Note that the REP opcode causes a temporary mode switch, decoding
    up to 15 extra sets of operands for the following instruction.
    REPEAT_COMBINED attempts to process this correctly by treating the
    full sequence as a single instruction, but this option has been
    disabled by default because it results in some repeated instructions
    being dozens of bytes long and the formatted output being difficult
    to read anyway since MAME requires it all be on a single line.

***************************************************************************/

#include "emu.h"
#include "mn1880d.h"

#define REPEAT_COMBINED 0

mn1880_disassembler::mn1880_disassembler(const char *const *inst_names)
	: util::disasm_interface()
	, m_inst_names(inst_names)
{
}

mn1880_disassembler::mn1880_disassembler()
	: mn1880_disassembler(s_inst_names)
{
}

// MOV, RDTBL, MOV1 and MOV1N may also be known as MV, MVROM, MV1 and MV1CPL
const char *const mn1880_disassembler::s_inst_names[256] =
{
	"nop", "rep", "rep", "rep", "rep", "rep", "rep", "rep",
	"rep", "rep", "rep", "rep", "rep", "rep", "rep", "rep",
	"clr", "clr", "clr", "clr", "clr", "clr", "clr", "clr",
	"set", "set", "set", "set", "set", "set", "set", "set",
	"t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz",
	"t1bz", "t1bz", "t1bz", "t1bz", "t1bz", "t1bz", "t1bz", "t1bz",
	nullptr, "movl", nullptr, "movl", "movl", "movl", "mov", "mov",
	"movl", "movl", "movl", "movl", "asl", "asl", "asr", "asr",
	"dec", "dec", "not", "not", "cmpm", "cmpm", "xch4", "xch4",
	"inc", "inc", "clr", "clr", "rol", "rol", "ror", "ror",
	"cmpm", "div", "cmpm", "movda", "mov", "mov", "mov", "mov",
	"xch", "mul", "xch", nullptr, "movl", "movl", "movl", "movl",
	"cmp", "cmp", "cmp", "cmp", "and", "and", "and", "and",
	"xor", "xor", "xor", "xor", "or", "or", "or", "or",
	"subc", "subc", "subc", "subc", "subd", "subd", "subd", "subd",
	"addc", "addc", "addc", "addc", "addd", "addd", "addd", "addd",
	"skip", "bc", "bz", "ble", "cmpl", "clr", "cmpl", "clr",
	"br", "bnc", "bnz", "bgt", nullptr, "set", nullptr, "set",
	"call", "call", "call", "call", "call", "call", "call", "call",
	"call", "call", "call", "call", "call", "call", "call", "call",
	"br", "br", "br", "br", "br", "br", "br", "br",
	"br", "br", "br", "br", "br", "br", "br", "br",
	nullptr, "pop", nullptr, "pop", "pop", "pop", "pop", "pop",
	nullptr, "push", nullptr, "push", "push", "push", "push", "push",
	"subcl", "div", "subcl", nullptr, "xch", "xch", "xch", "xch",
	"addcl", "mul", "addcl", nullptr, "mov", "mov", "mov", "mov",
	"cmp", "cmp", "cmp", "cmp", "xch", "xch", nullptr, "xch",
	"mov", "mov", "mov", "mov", "mov", "mov", "mov", "mov",
	"loop", "rloop", "loop", "rloop", "dec", "inc", "dec", "inc",
	"addr", "addr", "addr", "addr", "addr", "addr", "addr", "addr",
	"cmpbne", "cmpbne", "mov1", "wait", "ret", "reti", "br", "call",
	"cmpbe", "cmpbe", "mov1n", "push", "br", "call", "rdtbl", "pi"
};

mn1870_disassembler::mn1870_disassembler()
	: mn1880_disassembler(s_inst_names)
{
}

// STOP and HALT appear to be macros each implemented as a SET followed by a T1BNZ
// (their machine language codes are given as 19 16 21 16 FD and 18 16 20 16 FD)
const char *const mn1870_disassembler::s_inst_names[256] =
{
	"nop", nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
	nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
	"clr", "clr", "clr", "clr", "clr", "clr", "clr", "clr",
	"set", "set", "set", "set", "set", "set", "set", "set",
	"t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz", "t1bnz",
	"t1bz", "t1bz", "t1bz", "t1bz", "t1bz", "t1bz", "t1bz", "t1bz",
	nullptr, "movl", nullptr, "movl", nullptr, nullptr, "mov", "mov",
	"movl", "movl", "movl", "movl", nullptr, nullptr, nullptr, nullptr,
	"dec", "dec", "not", "not", "cmpm", "cmpm", "xch4", "xch4",
	"inc", "inc", "clr", "clr", "rol", "rol", "ror", "ror",
	"cmpm", "div", "cmpm", nullptr, "mov", "mov", "mov", "mov",
	"xch", "mul", "xch", nullptr, "movl", "movl", "movl", "movl",
	"cmp", "cmp", "cmp", "cmp", "and", "and", "and", "and",
	"xor", "xor", "xor", "xor", "or", "or", "or", "or",
	"subc", "subc", "subc", "subc", "subd", "subd", "subd", "subd",
	"addc", "addc", "addc", "addc", "addd", "addd", "addd", "addd",
	"skip", "bc", "bz", "ble", "cmpl", "clr", nullptr, "clr",
	"br", "bnc", "bnz", "bgt", nullptr, "set", nullptr, "set",
	"call", "call", "call", "call", "call", "call", "call", "call",
	"call", "call", "call", "call", "call", "call", "call", "call",
	"br", "br", "br", "br", "br", "br", "br", "br",
	"br", "br", "br", "br", "br", "br", "br", "br",
	"clr", "pop", "t1bnz", "pop", "pop", "pop", "pop", "pop",
	"set", "push", "t1bz", "push", "push", "push", "push", "push",
	nullptr, "div", nullptr, "decl", nullptr, nullptr, nullptr, nullptr,
	nullptr, "mul", nullptr, "incl", "mov", "mov", "mov", "mov",
	nullptr, "cmp", nullptr, "cmp", nullptr, "xch", nullptr, "xch",
	"mov", "mov", "mov", "mov", nullptr, nullptr, nullptr, nullptr,
	"loop", "rloop", "loop", "rloop", "dec", "inc", "dec", "inc",
	nullptr, "addr", nullptr, "addr", nullptr, "addr", nullptr, "addr",
	"cmpbne", "cmpbne", "mov1", nullptr, "ret", "reti", "br", "call",
	"cmpbe", "cmpbe", "mov1n", "push", "br", "call", "rdtbl", nullptr
};

u32 mn1880_disassembler::opcode_alignment() const
{
	return 1;
}

void mn1880_disassembler::format_direct(std::ostream &stream, u8 da) const
{
	util::stream_format(stream, "(x'%02X')", da);
}

void mn1880_disassembler::format_direct16(std::ostream &stream, u16 da) const
{
	util::stream_format(stream, "(x'%04X')", da);
}

void mn1880_disassembler::format_direct_bp(std::ostream &stream, u8 da, u8 bp) const
{
	util::stream_format(stream, "(x'%02X')%d", da, bp);
}

void mn1880_disassembler::format_indirect_bp(std::ostream &stream, const char *ptr, u8 bp) const
{
	util::stream_format(stream, "(%s)%d", ptr, bp);
}

void mn1880_disassembler::format_direct_masked(std::ostream &stream, u8 da, u8 mask) const
{
	util::stream_format(stream, "(x'%02X')x'%02X'", da, mask);
}

void mn1880_disassembler::format_indirect_masked(std::ostream &stream, const char *ptr, u8 mask) const
{
	util::stream_format(stream, "(%s)x'%02X'", ptr, mask);
}

void mn1880_disassembler::format_imm(std::ostream &stream, u8 imm) const
{
	util::stream_format(stream, "x'%02X'", imm);
}

void mn1880_disassembler::format_imm4(std::ostream &stream, u8 imm) const
{
	util::stream_format(stream, "%d", imm & 0x0f);
}

void mn1880_disassembler::format_imm16(std::ostream &stream, u16 imm) const
{
	util::stream_format(stream, "x'%04X'", imm);
}

void mn1880_disassembler::format_rel(std::ostream &stream, u16 base, s8 disp) const
{
	util::stream_format(stream, "$x'%04X'", (base + disp) & 0xffff);
}

void mn1880_disassembler::format_abs4k(std::ostream &stream, u16 label) const
{
	util::stream_format(stream, "x'%04X'", label);
}

void mn1880_disassembler::format_abs64k(std::ostream &stream, u16 label) const
{
	util::stream_format(stream, "/x'%04X'", label);
}

void mn1880_disassembler::dasm_operands(std::ostream &stream, u8 opcode, offs_t &pc, offs_t &flags, const mn1880_disassembler::data_buffer &opcodes)
{
	if (opcode < 0x10)
	{
		// REP
		format_imm4(stream, opcode);
	}
	else if (opcode < 0x30)
	{
		// CLR, SET, T1BNZ, T1BZ direct
		format_direct_bp(stream, opcodes.r8(pc++), opcode & 0x07);
		if (opcode >= 0x20)
		{
			stream << ", ";
			format_rel(stream, pc + 1, opcodes.r8(pc));
			++pc;
		}
	}
	else if (opcode < 0x34)
	{
		// MOVL immediate to pointer register
		if (BIT(opcode, 0))
		{
			util::stream_format(stream, "%s, ", BIT(opcode, 1) ? "yp" : "xp");
			format_imm16(stream, swapendian_int16(opcodes.r16(pc)));
			pc += 2;
		}
		else
			stream << "(unknown)";
	}
	else if (opcode < 0x3c)
	{
		// MOV/MOVL direct
		if (BIT(opcode, 0))
		{
			format_direct(stream, opcodes.r8(pc++));
			stream << ", ";
		}
		if (opcode < 0x38)
			util::stream_format(stream, "(%s)", BIT(opcode, 0) ? "yp" : "xp");
		else if (BIT(opcode, 1))
			stream << "yp";
		else
			stream << "xp";
		if (!BIT(opcode, 0))
		{
			stream << ", ";
			format_direct(stream, opcodes.r8(pc++));
		}
	}
	else if ((opcode & 0xfe) == 0x44)
	{
		// CMPM immediate
		if (BIT(opcode, 0))
		{
			format_direct_masked(stream, opcodes.r8(pc), opcodes.r8(pc + 1));
			pc += 2;
		}
		else
			format_indirect_masked(stream, "xp", opcodes.r8(pc++));
		stream << ", ";
		format_imm(stream, opcodes.r8(pc++));
	}
	else if (opcode < 0x50 || (opcode & 0xf7) == 0xb5 || (opcode & 0xf7) == 0xc3)
	{
		// Unary operations
		if (BIT(opcode, 0))
			format_direct(stream, opcodes.r8(pc++));
		else
			stream << "(xp)";
	}
	else if ((opcode & 0xfd) == 0x50)
	{
		// CMPM with two memory operands
		if (BIT(opcode, 1))
		{
			u8 da2 = opcodes.r8(pc++);
			u8 mask = opcodes.r8(pc++);
			format_direct_masked(stream, opcodes.r8(pc++), mask);
			stream << ", ";
			format_direct_masked(stream, da2, mask);
		}
		else
		{
			u8 mask = opcodes.r8(pc++);
			format_indirect_masked(stream, "xp", mask);
			stream << ", ";
			format_indirect_masked(stream, "yp", mask);
		}
	}
	else if ((opcode & 0xf7) == 0x51 || (opcode & 0xf7) == 0xb7)
	{
		// MUL, DIV, POP, PUSH indirect
		stream << "(xp)";
	}
	else if (opcode == 0x53)
	{
		// MOVDA (MN1880 only)
		format_direct16(stream, opcodes.r16(pc + 2));
		stream << ", ";
		format_direct16(stream, opcodes.r16(pc));
		pc += 4;
	}
	else if (opcode < 0x80 || (opcode & 0xfd) == 0x84 || (opcode & 0xf4) == 0xc0)
	{
		// Binary operations
		if (BIT(opcode, 1))
		{
			// Direct modes
			u8 op2 = opcodes.r8(pc++);
			format_direct(stream, opcodes.r8(pc++));
			stream << ", ";
			if (BIT(opcode, 0))
			{
				if (opcode == 0x5f)
					format_imm16(stream, op2 | u16(opcodes.r8(pc++)) << 8);
				else if ((opcode & 0xf4) == 0x74)
					format_imm4(stream, op2);
				else
					format_imm(stream, op2);
			}
			else
				format_direct(stream, op2);
		}
		else
		{
			// Indirect modes
			stream << "(xp), ";
			if (opcode == 0x5d)
			{
				format_imm16(stream, swapendian_int16(opcodes.r16(pc)));
				pc += 2;
			}
			else if (BIT(opcode, 0))
			{
				if ((opcode & 0xf4) == 0x74)
					format_imm4(stream, opcodes.r8(pc++));
				else
					format_imm(stream, opcodes.r8(pc++));
			}
			else
				stream << "(yp)";
		}
	}
	else if (opcode < 0x90 || (opcode & 0xfc) == 0xe0)
	{
		if (BIT(opcode, 2))
		{
			if (BIT(opcode, 0))
			{
				// CLR, SET special flag
				if (BIT(opcode, 1))
					stream << "cf";
				else
					stream << "df";
			}
			else
				stream << "(unknown)";
		}
		else
		{
			// Relative branches and loops
			if ((opcode & 0xfd) == 0xe1)
				util::stream_format(stream, "%s, ", BIT(opcode, 1) ? "yp" : "xp");
			format_rel(stream, pc + 1, opcodes.r8(pc));
			++pc;
		}
	}
	else if (opcode < 0xb0)
	{
		// CALL, BR within 4K page
		format_abs4k(stream, ((pc + 1) & 0xf000) | u16(opcode & 0x0f) << 8 | opcodes.r8(pc));
		++pc;
		if (opcode < 0xa0)
			flags |= STEP_OVER;
	}
	else if ((opcode & 0xf4) == 0xb0)
	{
		if (BIT(opcode, 0))
			stream << "fs";
		else
		{
			// CLR, SET, T1BNZ, T1BZ indirect (MN1870 only)
			format_indirect_bp(stream, "xp", opcodes.r8(pc++) & 0x07);
			if (BIT(opcode, 1))
			{
				stream << ", ";
				format_rel(stream, pc + 1, opcodes.r8(pc));
				++pc;
			}
		}
	}
	else if (opcode < 0xc0 || (opcode & 0xfc) == 0xe4 || (opcode & 0xfe) == 0xfc)
	{
		// PUSH, POP, DEC, INC, BR, CALL pointer
		if (BIT(opcode, 1))
			stream << "yp";
		else
			stream << "xp";
		if (opcode == 0xfd)
			flags |= STEP_OVER;
	}
	else if (opcode < 0xd0)
	{
		// XCH, MOV lower half of register
		if ((opcode & 0xf5) == 0xc5)
		{
			util::stream_format(stream, "%sl, ", BIT(opcode, 1) ? "yp" : "xp");
			format_direct(stream, opcodes.r8(pc++));
		}
		else if (BIT(opcode, 3))
		{
			format_direct(stream, opcodes.r8(pc++));
			util::stream_format(stream, ", %sl", BIT(opcode, 1) ? "yp" : "xp");
		}
		else
			util::stream_format(stream, "%sl, %sh", BIT(opcode, 1) ? "yp" : "xp", BIT(opcode, 1) ? "yp" : "xp");
	}
	else if (opcode < 0xe0)
	{
		if (BIT(opcode, 2))
		{
			// XCH, MOV between pointer registers
			if (opcode == 0xd4)
				stream << "xp, lp";
			else
			{
				if (BIT(opcode, 0))
					stream << "xp, ";
				if (BIT(opcode, 1))
					stream << "yp";
				else
					stream << "sp";
				if (!BIT(opcode, 0))
					stream << ", xp";
			}
		}
		else
		{
			// CMP, MOV 8-bit
			util::stream_format(stream, "%s%c, ", BIT(opcode, 1) ? "yp" : "xp", (opcode & 0xfd) == 0xd9 ? 'h' : 'l');
			if ((opcode & 0xfd) == 0xd0)
				format_direct(stream, opcodes.r8(pc++));
			else
				format_imm(stream, opcodes.r8(pc++));
		}
	}
	else if (opcode < 0xf0)
	{
		// ADDR
		util::stream_format(stream, "%sl, ", BIT(opcode, 1) ? "yp" : "xp");
		if (BIT(opcode, 2))
		{
			util::stream_format(stream, "%sl, ", BIT(opcode, 1) ? "yp" : "xp");
			if (BIT(opcode, 0))
				format_imm(stream, opcodes.r8(pc++));
			else
				util::stream_format(stream, "%sh", BIT(opcode, 1) ? "yp" : "xp");
		}
		else
		{
			u8 op2 = opcodes.r8(pc++);
			format_direct(stream, opcodes.r8(pc++));
			stream << ", ";
			if (BIT(opcode, 0))
				format_imm(stream, op2);
			else
				format_direct(stream, op2);
		}
	}
	else if ((opcode & 0xf6) == 0xf0)
	{
		// CMPBNE, CMPBE
		u8 imm = opcodes.r8(pc++);
		if (BIT(opcode, 0))
			format_direct(stream, opcodes.r8(pc++));
		else
			stream << "(xp)";
		stream << ", ";
		format_imm(stream, imm);
		stream << ", ";
		format_rel(stream, pc + 1, opcodes.r8(pc));
		++pc;
	}
	else if ((opcode & 0xf7) == 0xf2)
	{
		// MOV1, MOV1N
		u8 da2 = opcodes.r8(pc++);
		u8 bp = opcodes.r8(pc++);
		format_direct_bp(stream, opcodes.r8(pc++), (bp & 0x70) >> 4);
		stream << ", ";
		format_direct_bp(stream, da2, bp & 0x07);
	}
	else if (opcode == 0xf3)
	{
		// WAIT (MN1880 only)
		format_imm16(stream, opcodes.r16(pc));
		pc += 2;
	}
	else if ((opcode & 0xfe) == 0xf6)
	{
		// BR, CALL absolute
		format_abs64k(stream, opcodes.r16(pc));
		pc += 2;
		if (BIT(opcode, 0))
			flags |= STEP_OVER;
	}
	else if (opcode == 0xfb)
	{
		// PUSH immediate
		format_imm(stream, opcodes.r8(pc++));
	}
	else if (opcode == 0xfe)
	{
		// RDTBL
		stream << "(xp), (yp)";
	}
	else
		stream << "(unknown)";
}

offs_t mn1880_disassembler::disassemble(std::ostream &stream, offs_t pc, const mn1880_disassembler::data_buffer &opcodes, const mn1880_disassembler::data_buffer &params)
{
	const offs_t pc0 = pc;
	offs_t flags = SUPPORTED;

	u8 opcode = opcodes.r8(pc++);
	const char *mnemonic = m_inst_names[opcode];

	u8 rc = 0;
	if (REPEAT_COMBINED && mnemonic != nullptr && opcode > 0x00 && opcode < 0x10)
	{
		rc = opcode;
		opcode = opcodes.r8(pc++);
		mnemonic = m_inst_names[opcode];
	}

	if (mnemonic == nullptr)
	{
		util::stream_format(stream, "%-8s", "db");
		format_imm(stream, opcode);
	}
	else if (opcode == 0x00 || opcode == 0x80)
	{
		// NOP, SKIP (latter actually executes in immediate mode)
		stream << mnemonic;
	}
	else if (opcode == 0xff)
	{
		// PI (software interrupt)
		stream << mnemonic;
		flags |= STEP_OVER;
	}
	else if ((opcode & 0xfe) == 0xf4)
	{
		// RET, RETI
		stream << mnemonic;
		flags |= STEP_OUT;
	}
	else
	{
		util::stream_format(stream, "%-8s", mnemonic);
		offs_t pc1 = pc;
		dasm_operands(stream, opcode, pc, flags, opcodes);
		if (REPEAT_COMBINED && rc != 0 && pc1 != pc)
		{
			do {
				stream << ", ";
				dasm_operands(stream, opcode, pc, flags, opcodes);
			}
			while (--rc != 0);
		}
	}

	if (REPEAT_COMBINED && rc != 0)
		util::stream_format(stream, ", rep %d", rc);

	return (pc - pc0) | flags;
}