1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
|
// license:BSD-3-Clause
// copyright-holders:Ville Linde, Barry Rodewald, Carl, Philip Bennett, Samuele Zannoli
uint64_t pentium_device::opcode_rdmsr(bool &valid_msr)
{
uint32_t offset = REG32(ECX);
switch (offset)
{
// Machine Check Exception (TODO)
case 0x00:
valid_msr = true;
popmessage("RDMSR: Reading P5_MC_ADDR");
return 0;
case 0x01:
valid_msr = true;
popmessage("RDMSR: Reading P5_MC_TYPE");
return 0;
// Time Stamp Counter
case 0x10:
valid_msr = true;
popmessage("RDMSR: Reading TSC");
return m_tsc;
// Event Counters (TODO)
case 0x11: // CESR
valid_msr = true;
popmessage("RDMSR: Reading CESR");
return 0;
case 0x12: // CTR0
valid_msr = true;
return m_perfctr[0];
case 0x13: // CTR1
valid_msr = true;
return m_perfctr[1];
default:
if (!(offset & ~0xf)) // 2-f are test registers
{
valid_msr = true;
logerror("RDMSR: Reading test MSR %x", offset);
return 0;
}
logerror("RDMSR: invalid P5 MSR read %08x at %08x\n", offset, m_pc - 2);
valid_msr = false;
return 0;
}
return -1;
}
void pentium_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
{
uint32_t offset = REG32(ECX);
switch (offset)
{
// Machine Check Exception (TODO)
case 0x00:
popmessage("WRMSR: Writing P5_MC_ADDR");
valid_msr = true;
break;
case 0x01:
popmessage("WRMSR: Writing P5_MC_TYPE");
valid_msr = true;
break;
// Time Stamp Counter
case 0x10:
m_tsc = data;
popmessage("WRMSR: Writing to TSC");
valid_msr = true;
break;
// Event Counters (TODO)
case 0x11: // CESR
popmessage("WRMSR: Writing to CESR");
valid_msr = true;
break;
case 0x12: // CTR0
m_perfctr[0] = data;
valid_msr = true;
break;
case 0x13: // CTR1
m_perfctr[1] = data;
valid_msr = true;
break;
default:
if (!(offset & ~0xf)) // 2-f are test registers
{
valid_msr = true;
logerror("WRMSR: Writing test MSR %x", offset);
break;
}
logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n", offset, (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
valid_msr = false;
break;
}
}
uint64_t pentium_pro_device::opcode_rdmsr(bool &valid_msr)
{
uint32_t offset = REG32(ECX);
switch (offset)
{
// Machine Check Exception (TODO)
case 0x00:
valid_msr = true;
popmessage("RDMSR: Reading P5_MC_ADDR");
return 0;
case 0x01:
valid_msr = true;
popmessage("RDMSR: Reading P5_MC_TYPE");
return 0;
// Time Stamp Counter
case 0x10:
valid_msr = true;
popmessage("RDMSR: Reading TSC");
return m_tsc;
// Performance Counters (TODO)
case 0xc1: // PerfCtr0
valid_msr = true;
return m_perfctr[0];
case 0xc2: // PerfCtr1
valid_msr = true;
return m_perfctr[1];
default:
logerror("RDMSR: unimplemented register called %08x at %08x\n", offset, m_pc - 2);
valid_msr = true;
return 0;
}
return -1;
}
void pentium_pro_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
{
uint32_t offset = REG32(ECX);
switch (offset)
{
// Time Stamp Counter
case 0x10:
m_tsc = data;
popmessage("WRMSR: Writing to TSC");
valid_msr = true;
break;
// Performance Counters (TODO)
case 0xc1: // PerfCtr0
m_perfctr[0] = data;
valid_msr = true;
break;
case 0xc2: // PerfCtr1
m_perfctr[1] = data;
valid_msr = true;
break;
default:
logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n", offset, (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
valid_msr = true;
break;
}
}
uint64_t pentium4_device::opcode_rdmsr(bool &valid_msr)
{
logerror("RDMSR: unimplemented register called %08x at %08x\n", REG32(ECX), m_pc - 2);
valid_msr = true;
return 0;
}
void pentium4_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
{
logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n", REG32(ECX), (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
valid_msr = true;
}
|