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* sm5*: added sm530 disasm (nw) hap2018-05-121-0/+1
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* start looking at the extra opcodes in the SSD 2000 type XaviX chip (s… (#3514) David Haywood2018-05-041-0/+2
| | | | | | | | * start looking at the extra opcodes in the SSD 2000 type XaviX chip (seems some undocumented 6502 opcodes are replaced with more custom ones) * (nw) * the xavix memory mapping gets stranger with each piece of new evidence (nw)
* move some not-directly-emulation-related helpers to lib/util, further ↵ Vas Crabb2018-04-011-2/+16
| | | | extricate emu.h from tools (nw)
* Reshuffle some stuff: Vas Crabb2018-03-281-4/+5
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* unidasm, too (nw) Vas Crabb2018-03-251-2/+2
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* use more constexpr and literal classes in UML to give compiler more ↵ Vas Crabb2018-03-171-1/+1
| | | | optimisation opportunities (nw)
* unidasm: sharc fix (nw) Olivier Galibert2018-03-041-1/+1
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* unidasm typo fix (nw) Olivier Galibert2018-02-281-1/+1
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* z8: Make address spaces big-endian AJR2018-02-211-1/+1
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* unidasm: Correct endianness of m6800, m6805 and other Motorola-type CPUs AJR2018-02-201-13/+13
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* NUON disassembler [O. Galibert] Olivier Galibert2018-02-181-0/+2
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* unidasm: fix f8 endianness (nw) hap2018-02-171-1/+1
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* create derived 6502 type for XaviX because it has at least one custom… (#3154) David Haywood2018-02-021-0/+2
| | | | | | | | | | | | | | | | | | | | | * create derived 6502 type for XaviX because it has at least one custom 4-byte opcode that doesn't fit any other type. treating that opcode as NOP for now. have a feeling it might be something to do with the other integrated hardware, might be 'execute co-processor code chain at this address' or something similar It isn't a standard JSL (Jump Subroutine Long) like the SNES cpu opcode in the same place as this, it seems to point at some code-like structures tho) could also be a secondary operation mode with different encoding like ARM's Thumb mode tho I guess. We currently only have a single XaviX based dump (taitons1) but there are more on the way. I'm going to see if the code flow makes any sense at all with these missing, or if any of it gives a clue as to what they should actually do. * xavix - let's call these callf and retf then after further investigation these are some kind of extra 'long jump' subroutine / task handlers, the 0x80 also being a custom opcode was throwing me off trying to identify them before. looks like they might have been hacking 65816 features into the regular 6502 core? * prepare for extra address bits (nw) * better program flow (nw)
* mcs48: More specific emulation of Intel 8021 AJR2018-01-231-2/+3
| | | | | | - Separate disassembler for i802x (including unemulated 8022 instructions) - Provide separate (though mostly just more limited) 8021 opcode table - Writes to 8021 P0 no longer go through memory space
* mc68hc11: Fix dissassembly of instructions with 16-bit operands (immediate ↵ AJR2018-01-011-1/+1
| | | | or direct)
* srcclean and manual cleanups (nw) Vas Crabb2017-12-241-10/+10
| | | | | please people, remember to keep source UTF-8 and if you're committing on behalf of others, clean up indents to meet MAME conventions anyone can run srcclean over a submission and see what will get hit
* Revert "Revert "Merge branch 'master' of https://github.com/mamedev/mame"" Firehawke2017-12-131-1/+12
| | | | This reverts commit 54155441e9ba9941e85d80c4834a66376a11e791.
* Revert "Merge branch 'master' of https://github.com/mamedev/mame" Firehawke2017-12-131-12/+1
| | | | | This reverts commit f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4, reversing changes made to 0d70d798107d4e4e8fb9f230410aeb1e888d65c5.
* Hyperstone dasm fp/h support (nw) Olivier Galibert2017-12-021-1/+12
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* fix building with Visual Studio 2017 & clang 5.0.0 (also tested with gcc ↵ smf-2017-11-281-12/+11
| | | | 7.2.0) (nw)
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-568/+1100
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* never hurts to srcclean (nw) Vas Crabb2017-07-091-1/+1
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* Begin of HP80 emulation (#2448) fulivi2017-07-081-0/+2
| | | | | | | | | | | | | | | | | What works: * HP85A machine with 16K of RAM * Capricorn CPU works * Keyboard works (with minor issues) * CRT text / graphics modes work (correct speed is not emulated yet so service ROM complaints) * BASIC is usable What is missing (and I'll have hopefully working soon): * HW timers * Beeper * Integral printer * DC100 cassette drive * Extension ROMs * I/O modules (especially the HPIB interface so that we can hook up floppy drives) * Other models in the family (e.g. HP86)
* Merge tag 'mame0187' Vas Crabb2017-06-281-1/+1
|\ | | | | | | | | | | | | MAME 0.187 Conflicts: src/mame/drivers/socrates.cpp
| * unidasm: Fix MC68HC11 disassembly AJR2017-06-251-1/+1
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* | Rewrote 4004 core and disassembler: Vas Crabb2017-06-271-0/+2
|/ | | | | | | | | | * Renamed to MCS-40. * Emulated 8-clock instruction cycle, interruptible at any point. * Converted TEST input to an input line. * Added SYNC and CM output lines. * Added support for 4040 CY output, logical operations, extended registers, ROM banking and disassembly. * Made I/O space mapping more flexible to support the variety of peripherals available. * Notable missing features are 4040 interrupt and halt, and "program memory" space.
* sm510: made KB1013VK12 device a clone of SM5A (nw) hap2017-06-231-2/+2
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* hcd62121: Improve rotate and shift instructions. Identified COM and PORT ↵ Wilbert Pol2017-05-031-1/+1
| | | | registers. Fixed unidasm config. [Wilbert Pol]
* m6805: added skeleton CMOS devices Vas Crabb2017-01-301-0/+4
| | | | | | | * Added m146805 and m68hc05 to unidasm * Made opcode tables configurable in m6805_base_device, provided tables for HMOS, CMOS and HC families * Implemented MUL instruction, made unimplemented STOP and WAIT raise fatal error * Added skeleton MC68HC05C4 with RAM and ROM in correct locations in memory map
* initial pull request Patrick Mackinlay2017-01-241-0/+2
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* cop400: Properly separated COP444L from COP444C. [Curt Coder] Curt Coder2017-01-161-0/+2
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* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-201-17/+25
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* Fixed the unidasm registration for upd7725 Nathan Woods2016-11-181-1/+1
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* Added PDP8 to unidasm Nathan Woods2016-11-161-0/+2
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* Merge pull request #1657 from npwoods/dasmstream_arcompact Vas Crabb2016-11-171-0/+2
|\ | | | | Changed the arcompact disassembler to use 'std::ostream &' internally
| * Changed the arcompact disassembler to use 'std::ostream &' internally Nathan Woods2016-11-111-0/+2
| | | | | | | | Also added arcompact to unidasm
* | No need for osd_malloc, osd_malloc_array and osd_free (nw) Miodrag Milanovic2016-11-111-1/+1
|/ | | | MALLOC_DEBUG not applicable anymore since we use new to allocate in 99.9% of cases
* nanoprocessor: initial support. Disassembler only is known to work at this ↵ fulivi2016-11-031-0/+2
| | | | point.
* TRUE/FALSE in tools section (nw) Miodrag Milanovic2016-10-221-19/+19
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* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-221-31/+31
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* hp_hybrid: added hp_hybrid & hp_5061_3001 to unidasm fulivi2016-09-101-0/+4
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* made constexprs lower case and used constexpr for returning input value as ↵ Miodrag Milanovic2016-07-311-8/+8
| | | | well for rest of defines in osdcomm.h (nw)
* Add support for showing will branch/will fall through comment on SPARC ↵ Vas Crabb2016-06-271-8/+8
| | | | | | branches under the cursor Disabled until we can get a hook to refress the instructions under PC when stepping
* SPARC VIS 2+, VIS 3 and VIS 3B disassembler support [Vas Crabb] Vas Crabb2016-06-241-185/+183
| | | | | * Note that this omits non-VIS OSA 2007/2011 features * VIS 2+ ldtxa/ldtwa/sttwa still uses ldda/stda, using new mnemonics requires special-casing this instruction and checking ASI
* VIS I (UltraSPARC) and II (UltraSPARC III) for SPARC disassembler [Vas Crabb] Vas Crabb2016-06-231-8/+27
| | | | | * Supports %gsr, all ops with exception of SIAM, and all ASI constants * Use -arch sparcv9vis1 or -arch sparcv9vis2 with unidasm
* Add SPARC to unidasm [Vas Crabb] Vas Crabb2016-06-221-0/+6
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* remove all usages of tagmap Miodrag Milanovic2016-06-181-2/+2
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* sm510: added KB1013VK1-2 disasm hap2016-04-111-0/+2
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* sm500: added disasm hap2016-04-071-0/+4
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* tms1k: make disasm tables human-readable and added initial TP0320 hap2016-03-151-0/+2
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