| Commit message (Collapse) | Author | Age | Files | Lines |
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The device can be found in nlm_other.cpp.
Removed nld_ne566.*
Added SYS_SW, SYS_SW2 and SYS_COMP. These are single switch,
alternating switch and a analog comparator with digital outputs.
Renamed RES_SWITCH to SYS_SW.
Added example ne566.cpp in netlist/examples.
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- Fixed some clang lint warnings
- Removed dead code
- Experimental parser code to allow calculations in parameter value.
This already works for compiled netlists. These changes are
currently disabled. Updated pong netlist (and CRC/SHA) to work
with this new code.
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- Devices ttlhigh and ttlhow are no longer automatically created.
- All logic input devices (e.g. TTL_INPUT, LOGIC_INPUT) now need to have
their power terminals (VCC, GND) connected. This opens the route
for more appropriate proxy devices but comes at a cost. If the
connections are omitted your circuit will not work as expected.
Example:
LOGIC_INPUT(I_SD0, 1, "AY8910PORT")
NET_C(VCC, I_SD0.VCC)
NET_C(GND, I_SD0.GND)
- Updated all netlists.
- Removed proxy information from terminal objects. This was replaced by
a lookup hash whose life-span does not exceed netlest setup.
These changes enable the removal of a number of hacks from the
source going forward.
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This commit is a first step towards using formulas in parameters, i.e.
MAINCLOCK(clock, 20 * 30)
The intention is to improve readability and scalability.
Since device registration already provides all necessary information
about parameters, the code to create an include file for all
devices has been improved. Long term, this will remove the need for
device specific header files.
In addition going forward devices will accept either no connections or
all specified connections, i.e.
TTL_7400_NAND(name, chip1.2, chip2.3)
or
TTL_7400_NAND(name)
NET_C(...)
NET_C(...)
This will allow to remove all duplicate definitions which are currently
necessary, i.e. TTL_7400_NAND/TTL_7400_GATE
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All pstonum calls now need to specify if they want local locale
or the "classic" "C" locale.
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Also hook up all potentiometers so they can be adjusted from within the
MAME UI.
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modelling. [Couriersud]
Added global NETLIST.DEFAULT_MOS_CAPMODEL parameter. Setting this to
zero disables using capitance modelling in mos models.
On a per mos device basis this can be achieved by adding CAPMODEL=0 to
the model definition, e.g. MOSFET(X, "NMOS(CAPMODEL=0)")
Improve MOSFET convergence by using log-stepping.
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This is a significant improvement to the MOS transistor model. It adds
modelling of the Meyer capacitance model.
This is a somewhat academic addition since the effects occur on a
nanosecond time scale and have a huge impact on performance. I plan to
make the capacitance model selectable. Both on a model level as well as
by introducing a global solver parameter.
The model delivers comparable results to LTSpice.
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This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and
c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at
598cd5227223c3b04ca31f0dbc1981256d9ea3ff.
Before pushing, please check that what you're about to push is sane.
Check your local commit log and ensure there isn't anything out-of-place
before pushing to mainline. When things like this happen, it wastes
everyone's time. I really don't need this in a week when real work⢠is
busting my balls and I'm behind where I want to be with preparing for
MAME release.
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This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing
changes made to 009cba4fb8102102168ef32870892438327f3705.
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- added MOSFET model. Currently capacitances are not modelled.
This is a 3-pin model (Bulk connected to Source) with provisions to
extend it to 4-pin at a later stage.
- Add a capacitor generic model which is charge conserving.
Switch netlist to use this model instead of constant capacity model.
- Start putting constants into a central place.
Please expect minor timing differences due to a different numerical
path.
The cmos inverter example illustrates the analog implementation of a
cmos inverter gate. These were used a lot back in the 70s/80s to
generate sinus waves. The model should also be able to better emulate
4066 analog switches.
The addition of a relatively simple capacitor model is planned at a
later stage.
Expect everything from the MOSFET model at the current stage. Wrong
results as well as convergence issues and crashes.
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Despite the overhead - two devices more per transistor - this addition
significantly reduces computing time on switching conditions by reducing
the needed Newton-Raphson loops dramatically.
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-----------
Rebound [DICE team, Couriersud]
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nl_types.h is part of libc++. Any project with a file with the same name
on the include path just fails to compile. Renamed to nltypes.h
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sound board, completing the tromba circuit
(nw) I'm not sure whether the model works properly or not, but in the
circuit where it's used, I don't think it can work properly with the
current TTL output model. A capacitor is charged by the Q output of a
74LS74 flipflop (U3A) until the voltage passes the Schmitt trigger's
threshold, causing it to reset the flipflop. However, the positive
trigger voltage of the Schmitt trigger is 1.6V, but our TTL output model
has a high output voltage of 1.0V (see nl_base.cpp:89). I realise the
simplified model of TTL logic with high impedance inputs and outputs
behaving as though thery're loaded is convenient and fast to simulate,
but it's not detailed enough for applications like this where
7400-series chips are used in analog circuitry. This is what held me up
last time I tried adding a netlist for this sound board.
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Instead, they have to be prefixed by "netlist/". Removed unneeded link
librariers for nltool and nlwav along the way. (nw)
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