| Commit message (Collapse) | Author | Age | Files | Lines |
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This change uses sys.exc_info()[1] instead of the "as" syntax
to retain Python 2.5 compatibility.
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Explicit regions in address maps (AM_REGION) are now looked up relative to the
device rather than as siblings when in an internal address map (similar to
devices and shared pointers) Besides being more orthogonal than before, this
allows internal ROMs of MCUs and similar devices to be hooked up in a nicer
and more foolproof way. Updated the m37710 and m5074x (m6502 derivative)
to take advantage of this.
Divided the M37702/M37710 into specific models, with each model having its own
internal address map containing the correct amounts of internal RAM and ROM.
M37702 MCUs found on various Namco PCBs are now all unique devices and have
their respective internal ROMs loaded as device ROMs.
(nw)
Also did some spring (fall) cleaning in addrmap.c/memory.c/dimemory.c
m_devbase (the base device used for tagmap lookup when late-binding handlers and
finding memory regions and shares) is now a reference rather than a pointer,
since we know what it is when the address_map_entry is constructed and it
doesn't change (it depends solely on whether it's an entry in an MCFG-provided
address map or an internal one) And for the same reason, there's now only one
m_devbase per address_map_entry rather than individual copies for
read/write/setoffset/sharedptr.
Removed mysterious unused address_map_entry member "m_region_string", along
with a silly assert probably left over from when Aaron was replacing AM_BASE
with AM_SHARE years ago.
Added a comment noting that "make sure all devices exist" in
device_memory_interface::interface_validity_check() actually does nothing,
like the proverbial goggles. The reason there's just a comment and not a fix
is I haven't figured out how to fix it yet
(is it possible to extract the original device tag that was given to a
proto-delegate? Sorry, the template hell in devdelegate.h and
lib/util/delegate.h makes me want to run screaming like a little girl)
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compile-time disable the slow precalculation/caching (nw)
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timeslice [Alex Jackson]
(nw)
This precalculation seems to be part of OG's "CPU core template", as all CPU
cores written by him do it. It's used to optimize things like onboard serial
ports and high-frequency timers; however, the m6502 and its derivatives have
neither onboard serial ports nor high-frequency timers, and the precalculation
is simply a boat anchor on drivers with 6502-family CPUs and tight interleaving.
mess c64 benchmarks (3.4 GHz Sandy Bridge i5; 64-bit Linux GCC 4.8 build)
before:
[awj@localhost trunk]$ ./mess64 -window -bench 60 c64
Average speed: 238.17% (59 seconds)
[awj@localhost trunk]$ ./mess64 -window -bench 60 c64
Average speed: 236.36% (59 seconds)
after:
[awj@localhost trunk]$ ./mess64 -window -bench 60 c64
Average speed: 279.93% (59 seconds)
[awj@localhost trunk]$ ./mess64 -window -bench 60 c64
Average speed: 279.30% (59 seconds)
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nw: the 6510 version of lxa may be wrong in the same way (on 6502 it loads A
and X with the immediate value, no AND occurs), someone C= savvy please check.
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adding a missing dependency for YM3526 and a text change to the "RETURN" menu line. [MAMESICK]
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mamedev.org source zip) [R. Belmont]
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6809 and z80 [smf]
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Galibert]
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so, ff,00 instead of ff,100
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location [Miodrag Milanovic]
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- Support for all T=1 instructions
- Added COM and the accumulator-only versions of INC and DEC
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Belmont]
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- Added JMP (zp) instruction
- Working interrupts
- Moved 6502 family V line to make room for up to 16 IRQs
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