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* z8: Add register pairs to debug state AJR2019-04-062-30/+15
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* (nw) Clean up the mess on master Vas Crabb2019-03-263-103/+500
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-253-500/+103
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* z8: Write RRn instead of Rn when disassembling INCW/DECW AJR2019-02-031-1/+2
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* z8: Fix disassembly of LD IR, R opcode AJR2019-02-021-1/+1
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* z8: Split sio_tick into two functions (nw) AJR2019-01-212-23/+30
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* z8: Mask RP properly for debug register view (nw) AJR2019-01-201-2/+2
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* z8: Add standard_irq_callback for the sake of debugging (nw) AJR2019-01-191-0/+1
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* z8682: Provide Z8 test ROM from Zilog application note AJR2019-01-181-3/+2
| | | | (nw) First 18 bytes of this (the interrupt/reset bootstrap) are identical to the previous hand-crafted binary.
* amerihok: Slow down ADPCM chip to a much more reasonable speed AJR2019-01-181-1/+1
| | | | z8: Fix TOUT output (nw)
* z8: Preliminary UART emulation AJR2019-01-182-27/+174
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* z8: Handle more timer corner cases (nw) AJR2019-01-181-1/+17
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* z8: Rewrite timer emulation, including support for most TIN and TOUT modes AJR2019-01-182-85/+278
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* z8: Add Z8682 type with (fake) internal ROM; prevent timer from endlessly ↵ AJR2019-01-172-3/+36
| | | | thrashing with a count of 1
* z8: Fix typo in pre1_write (restores noise in amerihok); misc. minor ↵ AJR2018-12-092-4/+4
| | | | cleanups (nw)
* z8: Register overhaul AJR2018-12-083-341/+507
| | | | | | - Create address space for internal register file - Add port output registers to debug state - Lock out interrupts on reset until EI
* z8: Use devcb3 instead of MCFG_ macros (nw) AJR2018-11-181-36/+8
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* (nw) sm8500: fix line accidently deleted; z8 : when pc adjusted, move yellow bar Robbbert2018-10-131-3/+12
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* (nw) z8: allow step-over with djnz Robbbert2018-09-281-17/+17
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* srcclean (nw) Vas Crabb2018-09-231-1/+1
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* (nw) z8: fixed more bugs; jtc: fixed cassette, wave sound, added quickload Robbbert2018-09-202-17/+35
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* (nw) z8: fixed numerous bugs Robbbert2018-09-172-16/+21
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* (nw) z8 : added the DA instruction Robbbert2018-09-152-1/+19
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* (nw) z8: fixed JP @ and CALL @ instructions Robbbert2018-09-131-2/+2
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* (nw) z8: fixed detection of stack type; jtc: fixed display of jtces88 Robbbert2018-09-131-4/+4
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* Add dump of preprogrammed Z8671 MCU with BASIC/DEBUG interpreter AJR2018-07-112-13/+46
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* devcb3 Vas Crabb2018-07-071-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple issues with the current device callbacks: * They always dispatch through a pointer-to-member * Chained callbacks are a linked list so the branch unit can't predict the early * There's a runtime decision made on the left/right shift direction * There are runtime NULL checks on various objects * Binding a lambda isn't practical * Arbitrary transformations are not supported * When chaining callbacks it isn't clear what the MCFG_DEVCB_ modifiers apply to * It isn't possible to just append to a callback in derived configuration * The macros need a magic, hidden local called devcb * Moving code that uses the magic locals around is error-prone * Writing the MCFG_ macros to make a device usable is a pain * You can't discover applicable MCFG_ macros with intellisense * Macros are not scoped * Using an inappropriate macro isn't detected at compile time * Lots of other things This changeset overcomes the biggest obstacle to remving MCFG_ macros altogether. Essentially, to allow a devcb to be configured, call .bind() and expose the result (a bind target for the callback). Bind target methods starting with "set" repace the current callbacks; methods starting with "append" append to them. You can't reconfigure a callback after resolving it. There's no need to use a macro matching the handler signatures - use FUNC for everything. Current device is implied if no tag/finder is supplied (no need for explicit this). Lambdas are supported, and the memory space and offset are optional. These kinds of things work: * .read_cb().set([this] () { return something; }); * .read_cb().set([this] (offs_t offset) { return ~offset; }); * .write_cb().set([this] (offs_t offset, u8 data) { m_array[offset] = data; }); * .write_cb().set([this] (int state) { some_var = state; }); Arbitrary transforms are allowed, and they can modify offset/mask for example: * .read_cb().set(FUNC(my_state::handler)).transform([] (u8 data) { return bitswap<4>(data, 1, 3, 0, 2); }); * .read_cb().set(m_dev, FUNC(some_device::member)).transform([] (offs_t &offset, u8 data) { offset ^= 3; return data; }); It's possible to stack arbitrary transforms, at the cost of compile time (the whole transform stack gets inlined at compile time). Shifts count as an arbitrary transform, but mask/exor does not. Order of mask/shift/exor now matters. Modifications are applied in the specified order. These are NOT EQUIVALENT: * .read_cb().set(FUNC(my_state::handler)).mask(0x06).lshift(2); * .read_cb().set(FUNC(my_state::handler)).lshift(2).mask(0x06); The bit helper no longer reverses its behaviour for read callbacks, and I/O ports are no longer aware of the field mask. Binding a read callback to no-op is not supported - specify a constant. The GND and VCC aliases have been removed intentionally - they're TTL-centric, and were already being abused. Other quirks have been preserved, including write logger only logging when the data is non-zero (quite unhelpful in many of the cases where it's used). Legacy syntax is still supported for simple cases, but will be phased out. New devices should not have MCFG_ macros. I don't think I've missed any fundamental issues, but if I've broken something, let me know.
* diexec: Interrupt API changes (nw) AJR2018-05-181-0/+1
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-113-8/+8
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* maps: Finish devices/cpu (nw) Olivier Galibert2018-04-201-6/+8
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* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-3/+3
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-3/+3
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* destaticify initializations (nw) (#3289) wilbertpol2018-03-041-15/+13
| | | | | | * destaticify initializations (nw) * fix this->set_screen (nw)
* z8: Make address spaces big-endian AJR2018-02-211-4/+4
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* API change: Memory maps are now methods of the owner class [O. Galibert] Olivier Galibert2018-02-122-10/+10
| | | | | Also, a lot more freedom happened, that's going to be more visible soon.
* emumem: API change [O. Galibert] Olivier Galibert2017-11-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-264-21/+48
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* z8: Fix disassembly of LDE Irr, r AJR2017-10-041-2/+2
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* z8: Interrupts work better if vectors are read properly (nw) AJR2017-09-031-1/+1
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* z8: Interrupts are working now AJR2017-09-032-28/+193
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* z8: Fix C flag polarity for CP, SBC, SUB and actually subtract with carry in SBC AJR2017-09-031-4/+4
| | | | This lets amerihok pass its initial checksum calculation.
* z8: Mask external stack accesses too (nw) AJR2017-09-031-4/+4
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* z8: Mask addresses for external memory accesses based on P0 control bits AJR2017-09-033-38/+90
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* z8: Make data space optional; fix stack pop semantics AJR2017-09-031-33/+51
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* Tidy up (nw) AJR2017-07-201-1/+0
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* amerihok: Make some educated guesses regarding manufacturer, decade, MCU and ↵ AJR2017-07-202-8/+35
| | | | | | sound chip types (nw) z8: A few technical modifications to memory interface; add Z8681 type (nw)
* make device_memory_interface slightly less of a special case, use a typedef ↵ Vas Crabb2017-07-102-3/+3
| | | | to avoid nested templates everywhere (nw)
* dimemory: Lift the cap on the number of address spaces per device [O. Galibert] Olivier Galibert2017-07-032-10/+8
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* z8: Convert ports to DEVCB (nw) AJR2017-06-262-14/+61
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