| Commit message (Collapse) | Author | Age | Files | Lines |
| | |
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and
c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at
598cd5227223c3b04ca31f0dbc1981256d9ea3ff.
Before pushing, please check that what you're about to push is sane.
Check your local commit log and ensure there isn't anything out-of-place
before pushing to mainline. When things like this happen, it wastes
everyone's time. I really don't need this in a week when real work™ is
busting my balls and I'm behind where I want to be with preparing for
MAME release.
|
| |
|
|
|
| |
This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing
changes made to 009cba4fb8102102168ef32870892438327f3705.
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
(nw) First 18 bytes of this (the interrupt/reset bootstrap) are identical to the previous hand-crafted binary.
|
| |
|
|
| |
z8: Fix TOUT output (nw)
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
thrashing with a count of 1
|
| |
|
|
| |
cleanups (nw)
|
| |
|
|
|
|
| |
- Create address space for internal register file
- Add port output registers to debug state
- Lock out interrupts on reset until EI
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
There are multiple issues with the current device callbacks:
* They always dispatch through a pointer-to-member
* Chained callbacks are a linked list so the branch unit can't predict the early
* There's a runtime decision made on the left/right shift direction
* There are runtime NULL checks on various objects
* Binding a lambda isn't practical
* Arbitrary transformations are not supported
* When chaining callbacks it isn't clear what the MCFG_DEVCB_ modifiers apply to
* It isn't possible to just append to a callback in derived configuration
* The macros need a magic, hidden local called devcb
* Moving code that uses the magic locals around is error-prone
* Writing the MCFG_ macros to make a device usable is a pain
* You can't discover applicable MCFG_ macros with intellisense
* Macros are not scoped
* Using an inappropriate macro isn't detected at compile time
* Lots of other things
This changeset overcomes the biggest obstacle to remving MCFG_ macros
altogether. Essentially, to allow a devcb to be configured, call
.bind() and expose the result (a bind target for the callback). Bind
target methods starting with "set" repace the current callbacks; methods
starting with "append" append to them. You can't reconfigure a callback
after resolving it. There's no need to use a macro matching the
handler signatures - use FUNC for everything. Current device is implied
if no tag/finder is supplied (no need for explicit this).
Lambdas are supported, and the memory space and offset are optional.
These kinds of things work:
* .read_cb().set([this] () { return something; });
* .read_cb().set([this] (offs_t offset) { return ~offset; });
* .write_cb().set([this] (offs_t offset, u8 data) { m_array[offset] = data; });
* .write_cb().set([this] (int state) { some_var = state; });
Arbitrary transforms are allowed, and they can modify offset/mask for example:
* .read_cb().set(FUNC(my_state::handler)).transform([] (u8 data) { return bitswap<4>(data, 1, 3, 0, 2); });
* .read_cb().set(m_dev, FUNC(some_device::member)).transform([] (offs_t &offset, u8 data) { offset ^= 3; return data; });
It's possible to stack arbitrary transforms, at the cost of compile
time (the whole transform stack gets inlined at compile time). Shifts
count as an arbitrary transform, but mask/exor does not.
Order of mask/shift/exor now matters. Modifications are applied in the
specified order. These are NOT EQUIVALENT:
* .read_cb().set(FUNC(my_state::handler)).mask(0x06).lshift(2);
* .read_cb().set(FUNC(my_state::handler)).lshift(2).mask(0x06);
The bit helper no longer reverses its behaviour for read callbacks, and
I/O ports are no longer aware of the field mask. Binding a read
callback to no-op is not supported - specify a constant. The GND and
VCC aliases have been removed intentionally - they're TTL-centric, and
were already being abused.
Other quirks have been preserved, including write logger only logging
when the data is non-zero (quite unhelpful in many of the cases where
it's used). Legacy syntax is still supported for simple cases, but will
be phased out. New devices should not have MCFG_ macros.
I don't think I've missed any fundamental issues, but if I've broken
something, let me know.
|
| |
|
|
|
|
| |
- PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument.
- Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however.
- execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
|
| |
|
|
| |
template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
|
| | |
|
| |
|
|
|
|
| |
* Move around the debugger hooks to get a small but measurable performance increase
* Remove emucore from external tools
* Improve performance of DSP16 interpreter a little by generating six variants of execution loop
|
| | |
|
| |
|
|
| |
mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
|
| |
|
|
|
|
| |
* destaticify initializations (nw)
* fix this->set_screen (nw)
|
| | |
|
| |
|
|
|
| |
Also, a lot more freedom happened, that's going to be more visible
soon.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* direct_read_data is now a template which takes the address bus shift
as a parameter.
* address_space::direct<shift>() is now a template method that takes
the shift as a parameter and returns a pointer instead of a
reference
* the address to give to {read|write}_* on address_space or
direct_read_data is now the address one wants to access
Longer explanation:
Up until now, the {read|write}_* methods required the caller to give
the byte offset instead of the actual address. That's the same on
byte-addressing CPUs, e.g. the ones everyone knows, but it's different
on the word/long/quad addressing ones (tms, sharc, etc...) or the
bit-addressing one (tms340x0). Changing that required templatizing
the direct access interface on the bus addressing granularity,
historically called address bus shift. Also, since everybody was
taking the address of the reference returned by direct(), and
structurally didn't have much choice in the matter, it got changed to
return a pointer directly.
Longest historical explanation:
In a cpu core, the hottest memory access, by far, is the opcode
fetching. It's also an access with very good locality (doesn't move
much, tends to stay in the same rom/ram zone even when jumping around,
tends not to hit handlers), which makes efficient caching worthwhile
(as in, 30-50% faster core iirc on something like the 6502, but that
was 20 years ago and a number of things changed since then). In fact,
opcode fetching was, in the distant past, just an array lookup indexed
by pc on an offset pointer, which was updated on branches. It didn't
stay that way because more elaborate access is often needed (handlers,
banking with instructions crossing a bank...) but it still ends up with
a frontend of "if the address is still in the current range read from
pointer+address otherwise do the slowpath", e.g. two usually correctly
predicted branches plus the read most of the time.
Then the >8 bits cpus arrived. That was ok, it just required to do
the add to a u8 *, then convert to a u16/u32 * and do the read. At
the asm level, it was all identical except for the final read, and
read_byte/word/long being separate there was no test (and associated
overhead) added in the path.
Then the word-addressing CPUs arrived with, iirc, the tms cpus used in
atari games. They require, to read from the pointer, to shift the
address, either explicitely, or implicitely through indexing a u16 *.
There were three possibilities:
1- create a new read_* method for each size and granularity. That
amounts to a lot of copy/paste in the end, and functions with
identical prototypes so the compiler can't detect you're using the
wrong one.
2- put a variable shift in the read path. That was too expensive
especially since the most critical cpus are byte-addressing (68000 at
the time was the key). Having bit-adressing cpus which means the
shift can either be right or left depending on the variable makes
things even worse.
3- require the caller to do the shift himself when needed.
The last solution was chosen, and starting that day the address was a
byte offset and not the real address. Which is, actually, quite
surprising when writing a new cpu core or, worse, when using the
read/write methods from the driver code.
But since then, C++ happened. And, in particular, templates with
non-type parameters. Suddendly, solution 1 can be done without the
copy/paste and with different types allowing to detect (at runtime,
but systematically and at startup) if you got it wrong, while still
generating optimal code. So it was time to switch to that solution
and makes the address parameter sane again. Especially since it makes
mucking in the rest of the memory subsystem code a lot more
understandable.
|
| |
|
|
|
|
|
|
| |
Disassemblers are now independant classes. Not only the code is
cleaner, but unidasm has access to all the cpu cores again. The
interface to the disassembly method has changed from byte buffers to
objects that give a result to read methods. This also adds support
for lfsr and/or paged PCs.
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
This lets amerihok pass its initial checksum calculation.
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
|
| |
sound chip types (nw)
z8: A few technical modifications to memory interface; add Z8681 type (nw)
|
| |
|
|
| |
to avoid nested templates everywhere (nw)
|
| | |
|
| | |
|