| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | New clones marked as NOT_WORKING | 2021-09-25 | 1 | -5/+81 | |
| | | | | | | | | | -------------------------------- TX-0 upgraded system (8 kWords of RAM, old order code) * tx0_64kw: Swap LR and MBR when MLR and LMB are specified together * tx0_8kw: Recognize a few more composite OPRs in disassembly | ||||
| * | tx0dasm.cpp: Add notes on OPRs for reference | 2021-08-26 | 1 | -0/+74 | |
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| * | tx0_64kw, tx0_8kw: Fixes and improvements | 2021-08-12 | 1 | -85/+654 | |
| | | | | | | | | | | - Complete rewrite of disassemblers, using standard names for OPRs - Clear MBR in cycle 1 when AMB is not specified - Perform AMB before COM (tx0_64kw) - Fix characters printed on Flexowriter (bit order was incorrectly reversed) - Modernize logging in CPU device - Only call the debugger hook once per instruction cycle | ||||
| * | Separate TX-0 from PDP-1; separate some SoC types in build | 2020-11-19 | 1 | -0/+133 | |
