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path: root/src/devices/cpu/tx0/tx0.cpp
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* Various devices: Correct placement of U integer suffix in definitions of ↵ AJR2023-03-211-1/+1
| | | | shifted LOG_xxx constant macros
* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
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* srcclean in preparation for MAME 0.235, and two small adjustments. Vas Crabb2021-09-261-2/+2
| | | | | | | * Reduce repeated directory walking in cleansrc target (substantially improves speed of building the target on Windows). * Disable a validity check using an MSVC language extension when using clang in MSVC ABI mode.
* tx0: Turn RIM logging back off AJR2021-09-251-1/+1
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* New clones marked as NOT_WORKING AJR2021-09-251-11/+247
| | | | | | | | -------------------------------- TX-0 upgraded system (8 kWords of RAM, old order code) * tx0_64kw: Swap LR and MBR when MLR and LMB are specified together * tx0_8kw: Recognize a few more composite OPRs in disassembly
* tx0.cpp: Further fixes AJR2021-09-041-2/+2
| | | | | | - Load typewriter input into correct bit positions of LR - Invert MSB of display coordinates (fixes tic-tac-toe grid) - tx0_8kw: Resolve confusion between SHR and CYR semantics (these were incorrectly swapped)
* tx0_64kw, tx0_8kw: Fixes and improvements AJR2021-08-121-20/+28
| | | | | | | | | - Complete rewrite of disassemblers, using standard names for OPRs - Clear MBR in cycle 1 when AMB is not specified - Perform AMB before COM (tx0_64kw) - Fix characters printed on Flexowriter (bit order was incorrectly reversed) - Modernize logging in CPU device - Only call the debugger hook once per instruction cycle
* tx0_8kw: IOS fix AJR2021-07-251-0/+1
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* tx0_64kw: Various fixes AJR2021-07-251-26/+3
| | | | | | - Make IOS actually wait for I/O when used more than once - Remove break statement that disabled half the OPRs - Don't normalize minus zero sums (also applies to tx0_8kw)
* Separate TX-0 from PDP-1; separate some SoC types in build AJR2020-11-191-0/+1093