| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
| |
disassembly of branch displacements
|
| | |
|
| |
|
|
|
| |
- Compare architecture versions against correct enum values
- FLUSH exists (at least nominally) on v7 under the name IFLUSH
|
| |
|
|
|
|
|
|
| |
- Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected.
- Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions.
- Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse.
- Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx)
- Don't pass over delay slots for debugging in ASAP core
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
|
|
| |
* Updated sol2 to 3.2.2
* Updated pugixml to 1.10
* Increased minimum clang version to 6
* Cleaned up some stuff that can use new features
|
| |
|
|
|
|
|
|
| |
Disassemblers are now independant classes. Not only the code is
cleaner, but unidasm has access to all the cpu cores again. The
interface to the disassembly method has changed from byte buffers to
objects that give a result to read methods. This also adds support
for lfsr and/or paged PCs.
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
| |
Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8
also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
|
| | |
|
| | |
|
| |
|
|
|
|
| |
branches under the cursor
Disabled until we can get a hook to refress the instructions under PC when stepping
|
| |
|
|
|
| |
* Note that this omits non-VIS OSA 2007/2011 features
* VIS 2+ ldtxa/ldtwa/sttwa still uses ldda/stda, using new mnemonics requires special-casing this instruction and checking ASI
|
| | |
|
| | |
|
| |
|
|
|
| |
* Supports %gsr, all ops with exception of SIAM, and all ASI constants
* Use -arch sparcv9vis1 or -arch sparcv9vis2 with unidasm
|
| | |
|
| |
|
|
|
|
|
| |
* Fix addcc/andcc in SPARCv7 mode and simplify integer op tables
* Allow ASI descriptions to be supplied with MCFG macro
sun4: add SPARC ASI descriptions [Vas Crabb]
|
| |
|
|
|
|
|
|
| |
* Support SPARCv9
* Allow plug-in ASI comments
* Fix format of some opcodes
* Produce clr synthetic
* Allow running in v7, v8 and v9 modes
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|