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path: root/src/devices/cpu/sharc/sharcdrc.cpp
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* misc cpu: no need to check debug enabled flag manually hap2025-04-111-1/+1
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* cpu/cr16b, cpu/es5510, cpu/ks0164, cpu/mb86235, cpu/sharc, upd7220: Use ↵ AJR2022-11-011-8/+8
| | | | | | util::sext and other bit utility functions * cpu/sharc: Be a bit more paranoid about extreme values of bit6 and len6 (non-DRC)
* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
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* Eliminate ARRAY_LENGTH template in favor of C++17's std::size AJR2021-02-141-2/+2
| | | | | | | | | | * osdcomm.h: Move definition of EQUIVALENT_ARRAY to coretmpl.h * sharc.cpp, gt64xxx.cpp, ym2413.cpp, gb_lcd.cpp, snes_ppu.cpp: Use STRUCT_MEMBER for save state registration * gio/newport.cpp, megadrive/svp.cpp, nes_ctrl/bcbattle.cpp, arm7.cpp, tms9995.cpp, pckeybrd.cpp, sa1110.cpp, sa1111.cpp, jangou_blitter.cpp, vic4567.cpp: Use std::fill(_n) instead of memset * emucore.h: Remove obsolete typedef
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-251-368/+364
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* emumem: API change [O. Galibert] Olivier Galibert2017-11-291-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* sharcdrc: Fix horribly subtle bug (nw) Olivier Galibert2016-12-101-2/+2
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* sharc: Use standard memory maps [O. Galibert] Olivier Galibert2016-12-091-324/+14
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* Introduce u8/u16/u32/u64/s8/s16/s32/s64 Vas Crabb2016-11-191-14/+14
| | | | | | | | | | | | * New abbreviated types are in osd and util namespaces, and also in global namespace for things that #include "emu.h" * Get rid of import of cstdint types to global namespace (C99 does this anyway) * Remove the cstdint types from everything in emu * Get rid of U64/S64 macros * Fix a bug in dps16 caused by incorrect use of macro * Fix debugcon not checking for "do " prefix case-insensitively * Fix a lot of messed up tabulation * More constexpr * Fix up many __names
* converted lot of TRUE/FALSE to real boolean and updated types (nw) Miodrag Milanovic2016-10-221-56/+56
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* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-221-32/+32
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* sharcdrc: fix Linux crash (nw) Ville Linde2016-06-291-3/+3
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* Cleanup and version bumpmame0175 Miodrag Milanovic2016-06-291-1049/+1049
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* couple of things for zerogun (nw) Ville Linde2016-06-081-0/+6
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* sharcdrc: Model 2 compatibility (nw) Ville Linde2016-06-071-14/+333
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* sharcdrc: more fixes, more ops (nw) Ville Linde2016-06-041-17/+129
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* sharcdrc: some fixes + more ops (nw) Ville Linde2016-06-031-17/+281
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* sharcdrc: fix conditional loops (nw) Ville Linde2016-05-301-28/+53
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* cleanup (nw) Ville Linde2016-05-291-5/+0
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* Compile fix (uninitialized variable) (nw) Scott Stone2016-05-281-5/+5
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* Added highly experimental SHARC recompiler (disabled by default) [Ville Linde] Ville Linde2016-05-281-0/+4909