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* srcclean (nw) Vas Crabb2019-06-233-48/+48
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* mega32x.cpp: refactor and convert read/write handlers to 16-bit space ↵ Angelo Salese2019-06-222-7/+7
| | | | [Angelo Salese]
* sh2.cpp: first pass over SH7604 SoC refactoring [Angelo Salese] Angelo Salese2019-06-214-419/+1012
| | | | * Fixed division unit overflow flag clearance;
* (nw) Clean up the mess on master Vas Crabb2019-03-261-1/+1
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-1/+1
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* sh2: Fix interpreter for cps3 [O. Galibert] Olivier Galibert2019-01-191-1/+1
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* -sh2, sh4, sat_ctrl: Removed MCFG, nw mooglyguy2018-12-094-101/+44
| | | | | | | | | | | | -ticket: Added separate hopper_device, nw -aristmk6, atvtrack, cps3, cv1k, hikaru, saturn, sh4robot, stv: Removed MACHINE_CONFIG, nw -sat_ctrl/multitap, segatap: Refactored to use required_devicee_array, removed MACHINE_CONFIG, simplified code, nw -mega32x: Removed code duplication, eliminated MACHINE_CONFIG, nw -vegaeo: Removed machine().device, nw
* -mb86235, sh7604, sharc: Removed MCFG macros, nw mooglyguy2018-12-093-21/+0
| | | | -gticlub, model2, n64, nwk-tr: Removed MACHINE_CONFIG macros, nw
* as if millions of this pointers suddenly cried out in terror, and were ↵ Vas Crabb2018-06-084-28/+28
| | | | | | | suddenly silenced * streamline templates in addrmap.h * get rid of overloads on read/write member names - this will become even more important in the near future
* srcclean (nw) Vas Crabb2018-05-271-1/+1
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* diexec: Interrupt API changes (nw) AJR2018-05-182-1/+3
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* D'oh. (nw) arbee2018-05-161-0/+7
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* sh4drc: optimize FPU CMP instructions (nw) arbee2018-05-161-20/+8
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* sh4drc: fix SR damage in new CMP implementations (nw) arbee2018-05-151-4/+12
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* Start killing off non-diexec PULSE_LINE hacks (nw) AJR2018-05-155-18/+7
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* sh4drc: remove remaining CALLC from FRCHG (nw) arbee2018-05-151-5/+13
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* sh4drc: optimized some of the previously implemented UML (nw) arbee2018-05-141-23/+11
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* sh4drc: UML implementations of FSTS, FLOAT, FTRC, FNEG, FABS, FSCHG, and ↵ arbee2018-05-141-46/+76
| | | | FRCHG [R. Belmont]
* sh4drc: UML implementations of FLDI0, FLDI1, FCMP_EQ, and FCMP_GT [R. Belmont] arbee2018-05-131-28/+54
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* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-116-28/+65
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* Make MCFG_DEVICE_ADD and callable device types more flexible: Vas Crabb2018-05-042-6/+11
| | | | | | | | | | | | | | | | | | | | | * Allows defaulted clocks (see subtle example with vboy) * Allows additional constructors (see RS232 port in tranz330) * Allows use of device finder in place of tag in MCFG_DEVICE_ADD * Requires out-of-line destructor for devices using incomplete types * Requires XTAL or explicit u32 for clocks for devices with private types Devices must still define the standard constructor. When writing additional constructors, be aware that the constructor runs before device_add_mconfig in the context of the existing device, not the new device. See osborne1, zorba, tranz330, and vboy for examples of this in use. Compilation is a bit slower, but this is temporary while refactoring is in progress. Eliminated the need for MCFG_SOUND_ROUTE_EX. Removed macros from slot option configuration - they just obfuscated code and slowed it down with needless dynamic casts, but didn't actually simplify it.
* srcclean (nw) Vas Crabb2018-04-222-9/+9
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* maps: Finish devices/cpu (nw) Olivier Galibert2018-04-205-55/+64
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* sh4drc: 8 more UML conversions (nw) arbee2018-04-151-50/+9
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* sh4drc: UML version of FMAC, fixed possible error in previous FPU conversion ↵ arbee2018-04-153-69/+69
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* sh4drc: 3 more trivial UML conversions (nw) arbee2018-04-151-21/+6
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* sh4drc: UML implementations of FADD, FSUB, FMUL, and FDIV. [R. Belmont] arbee2018-04-145-327/+361
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* Reshuffle some stuff: Vas Crabb2018-03-283-5/+5
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-257-391/+364
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* reduce scope of stuff with different definitions across CPUs (nw) Vas Crabb2018-03-201-23/+31
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-152-7/+7
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* destaticify initializations (nw) (#3289) wilbertpol2018-03-042-32/+32
| | | | | | * destaticify initializations (nw) * fix this->set_screen (nw)
* API change: Memory maps are now methods of the owner class [O. Galibert] Olivier Galibert2018-02-1210-17/+22
| | | | | Also, a lot more freedom happened, that's going to be more visible soon.
* API change: Memory maps are now "last entry wins" [O. Galibert] Olivier Galibert2018-01-311-2/+2
| | | | | | | This allows for the much more natural "import another map and patch it" structure, or "cover a whole region then punch holes in it". Our previous first-entry-wins rule was always a surprise to newcomers, and oldcomers too.
* xtal.h is dead, long live to xtal.cpp [O. Galibert] Olivier Galibert2018-01-231-0/+1
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* API Change: Machine configs are now a method of the owner class, and the ↵ Olivier Galibert2018-01-171-3/+3
| | | | | | | | | | prototype is simplified [O. Galibert] Beware, the device context does not follow in MCFG_FRAGMENT_ADD anymore due to the prototype change. So creating a device then configuring through a fragment doesn't work as-is. The simplest solution is just to add a MCFG_DEVICE_MODIFY at the start of the fragment with the correct tag.
* Extended time! All space.device() removed from comments (nw) Olivier Galibert2018-01-051-1/+1
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* emumem: API change [O. Galibert] Olivier Galibert2017-11-293-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-268-127/+148
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* srcclean (nw) Vas Crabb2017-11-261-1/+1
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* SH3/4 drc: reset drc cache MetalliC2017-11-241-0/+1
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* some SH3/4 recompiler changes that got lost at some point (nw) (#2767) David Haywood2017-11-011-4/+13
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* add missing emu.h (nw) smf-2017-10-221-0/+1
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* srcclean (nw) Vas Crabb2017-10-229-97/+97
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* fix an error that was preventing dc from booting (my own mistake, was ↵ David Haywood2017-10-172-6/+8
| | | | testing something at the time) and document what were a few more differences between the cores (nw)
* a few dasm fixes that were in the sh4 core but not the sh2 core and got lost ↵ David Haywood2017-10-161-3/+6
| | | | when merging them (nw)
* these were meant to be part of that (nw) David Haywood2017-10-121-15/+3
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* fix CPS3/STV (we always use timers for SH2 DMA, and have done for years, ↵ David Haywood2017-10-121-4/+1
| | | | just forgot to remove the #ifdef on this code when cleaning up)
* sh4fe: Don't inline virtual functions (nw) AJR2017-10-111-2/+2
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* Preliminary SH3 / SH4 recompiler [David Haywood] (#2711) David Haywood2017-10-1118-10597/+9488
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