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* Fix for SH3/SH4 DRC regression in b26662f1bba6809df145d9e8b3f78f66e3a7c7db, ↵ smf-2025-05-071-1/+2
| | | | which prevented generate_checksum_block() being called for RAM areas. [smf]
* Implemented specific SH3/SH4 chips & pass the required endian into the ↵ smf-2025-04-171-8/+0
| | | | constructor, SH4 internal registers now work when using big endian. The debugger is now aware that the SH3/SH4 has an MMU. [smf]
* cpu/sh: Improved SH7021 SoC emulation. (#11610) [Ryan Holtz, Phil Bennett] Phil Bennett2023-10-161-5/+9
| | | | | * Added (rudimentary) SH7021 DMA, timers and GPIO, and logging for the rest. * Fixed SH2 NMIs occurring in a delay slot when using the interpreter. * Generally cleaned up code and renamed functions/macros/variables more conventionally.
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-111-4/+4
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* srcclean (nw) Vas Crabb2017-10-221-2/+2
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* sh4fe: Don't inline virtual functions (nw) AJR2017-10-111-2/+2
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* Preliminary SH3 / SH4 recompiler [David Haywood] (#2711) David Haywood2017-10-111-0/+317