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* -Switch to building MAME as C++17. Vas Crabb2020-11-151-0/+1
| | | | | | | * Updated sol2 to 3.2.2 * Updated pugixml to 1.10 * Increased minimum clang version to 6 * Cleaned up some stuff that can use new features
* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-251-12/+12
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* sh4.cpp: disable timers at reset (nw) yz70s2020-01-141-0/+14
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* sh2.cpp/sh4.cpp: Don't emit fast RAM accesses when the debugger is enabled ↵ Philip Bennett2019-09-241-45/+48
| | | | [Phil Bennett]
* -sh2, sh4, sat_ctrl: Removed MCFG, nw mooglyguy2018-12-091-10/+1
| | | | | | | | | | | | -ticket: Added separate hopper_device, nw -aristmk6, atvtrack, cps3, cv1k, hikaru, saturn, sh4robot, stv: Removed MACHINE_CONFIG, nw -sat_ctrl/multitap, segatap: Refactored to use required_devicee_array, removed MACHINE_CONFIG, simplified code, nw -mega32x: Removed code duplication, eliminated MACHINE_CONFIG, nw -vegaeo: Removed machine().device, nw
* as if millions of this pointers suddenly cried out in terror, and were ↵ Vas Crabb2018-06-081-6/+6
| | | | | | | suddenly silenced * streamline templates in addrmap.h * get rid of overloads on read/write member names - this will become even more important in the near future
* sh4drc: optimize FPU CMP instructions (nw) arbee2018-05-161-20/+8
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* sh4drc: fix SR damage in new CMP implementations (nw) arbee2018-05-151-4/+12
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* sh4drc: remove remaining CALLC from FRCHG (nw) arbee2018-05-151-5/+13
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* sh4drc: optimized some of the previously implemented UML (nw) arbee2018-05-141-23/+11
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* sh4drc: UML implementations of FSTS, FLOAT, FTRC, FNEG, FABS, FSCHG, and ↵ arbee2018-05-141-46/+76
| | | | FRCHG [R. Belmont]
* sh4drc: UML implementations of FLDI0, FLDI1, FCMP_EQ, and FCMP_GT [R. Belmont] arbee2018-05-131-28/+54
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* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-111-8/+38
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* srcclean (nw) Vas Crabb2018-04-221-8/+8
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* maps: Finish devices/cpu (nw) Olivier Galibert2018-04-201-21/+24
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* sh4drc: 8 more UML conversions (nw) arbee2018-04-151-50/+9
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* sh4drc: UML version of FMAC, fixed possible error in previous FPU conversion ↵ arbee2018-04-151-67/+67
| | | | (nw)
* sh4drc: 3 more trivial UML conversions (nw) arbee2018-04-151-21/+6
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* sh4drc: UML implementations of FADD, FSUB, FMUL, and FDIV. [R. Belmont] arbee2018-04-141-277/+301
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* Reshuffle some stuff: Vas Crabb2018-03-281-3/+3
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-251-103/+96
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-4/+4
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* API change: Memory maps are now methods of the owner class [O. Galibert] Olivier Galibert2018-02-121-5/+5
| | | | | Also, a lot more freedom happened, that's going to be more visible soon.
* emumem: API change [O. Galibert] Olivier Galibert2017-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-25/+3
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* srcclean (nw) Vas Crabb2017-11-261-1/+1
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* SH3/4 drc: reset drc cache MetalliC2017-11-241-0/+1
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* some SH3/4 recompiler changes that got lost at some point (nw) (#2767) David Haywood2017-11-011-4/+13
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* srcclean (nw) Vas Crabb2017-10-221-75/+75
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* fix an error that was preventing dc from booting (my own mistake, was ↵ David Haywood2017-10-171-4/+5
| | | | testing something at the time) and document what were a few more differences between the cores (nw)
* Preliminary SH3 / SH4 recompiler [David Haywood] (#2711) David Haywood2017-10-111-2944/+2110
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* use 'sh' instead of 'superh' David Haywood2017-10-021-0/+4743