summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/rii
Commit message (Collapse)AuthorAgeFilesLines
* Misc. code pruning and maintenance (nw) AJR2020-02-291-1/+1
|
* clean up various stuff (nw) Vas Crabb2020-02-261-1/+1
|
* rii: Fix TBRD address calculation; fix carry logic for several instructions (nw) AJR2020-02-212-17/+19
|
* epg3231: Add speech timer interrupt (nw) AJR2020-02-202-1/+28
|
* (nw) whole lot less of { *this } Vas Crabb2020-02-052-8/+6
|
* riscii: Add interrupt processing (nw) AJR2019-11-012-0/+47
|
* rii: Many updates AJR2019-09-254-72/+1038
| | | | | | | | | | | - Identify CPU type used by vreadere as ePG3231 - Add preliminary port I/O handlers and callbacks - Add stub handlers and state variables for interrupt controller, timers, synthesizer, UART and SPI - Fix TBRD addressing of external data memory - Fix calculation of carry flag for normal additive operations - Implement multi-byte carry/borrow for applicable registers - Implement signed multiplication option - Add internal stack buffer for saving PCH during calls/interrupts
* (nw) please try to ensure #include guards will trip special-casing in dumb ↵ Vas Crabb2019-09-161-1/+1
| | | | preprocessors to reduce filesystem operations
* riscii: Improve offset calculation for TBRD (nw) AJR2019-09-132-3/+10
|
* rii: Misc. adjustments (nw) AJR2019-09-101-5/+6
|
* rii: Stack endianness is swapped; TBRD is allowed to be RPTed (nw) AJR2019-09-101-5/+14
|
* rii: Add standard status flag display (nw) AJR2019-09-102-2/+24
|
* Add preliminary RISC II execution core AJR2019-09-103-26/+1128
|
* rii: Misc. notes; minor disassembler update (nw) AJR2019-09-103-24/+44
|
* Enable precompiled header usage in the Visual Studio compiler (#5473) S.Z2019-08-131-0/+2
| | | | | | | | | | * Enable precompiled header usage in the Visual Studio compiler But only for libraries emu frontend precompile dasm optional Also add emu.h include to hpcdasm.cpp * Include emu.h in some disassembler sources to use precompiled headers * Remove debug message
* riscii: Add the register space (nw) AJR2019-06-202-7/+37
|
* riscii: Minor update (nw) AJR2019-06-201-3/+4
|
* riidasm: Correct order of parameters for MOVRP and MOVPR (nw) AJR2019-06-201-4/+4
|
* Preliminary disassembler and skeleton CPU device for Elan RISC II/RII series ↵ AJR2019-06-204-0/+759
architecture