| Commit message (Collapse) | Author | Age | Files | Lines |
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-newport: Fixed VRAM tests and several fast-clear bugs. [Ryan Holtz]
-hpc3: Fixed several SGI IDE tests. [Ryan Holtz]
-ioc2: Added stubs for modern PS/2 keyboard controller, nw
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Corrects some TLB diagnostic errors (remaining ones require implementing a data cache), and the FPU "underflow" test (really an unimplemented instruction exception, not an underflow) by checking for denormalized or quiet NaN operands for all floating point arithmetic instructions..
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keyboard input. [Ryan Holtz]
-r4000: Changed LL/SC behaviour to not use a write tap. Possibly incorrect behaviour, but IRIX 6.5 installer doesn't hang anymore on miniroot creation, nw
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* relaxed address validity checks in 32-bit mode allowing simplified base + offset computation
* removed inaccurate/partial cycle counting
* slight adjustment to ll/sc logic
* corrected address alignment exception type
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non-DRC code sequences match
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While this behaviour is undefined according to the MIPS R4000 Microprocessor User's Manual, various factors point toward it most likely being correct, including:
1. The fact MIPS-I exposes 16x64-bit floating-point registers, but internally implements them as pairs of 32-bit registers (with only the even-numbered pairs being valid for arithmetic operations), making it somewhat likely MOV.S, like LWC1 and SWC1, can access either half.
2. Explicit mention in IDT documentation and "See MIPS Run", i.e. "The odd-numbered registers can be accessed by move and load/store instructions", and other commentary.
3. The presence of paired-single operations in later MIPS32/64 specifications, which operate on independent single-precision values stored in each of the lower and upper halves of a single floating-point register.
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fill in the table. (nw)
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This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and
c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at
598cd5227223c3b04ca31f0dbc1981256d9ea3ff.
Before pushing, please check that what you're about to push is sane.
Check your local commit log and ensure there isn't anything out-of-place
before pushing to mainline. When things like this happen, it wastes
everyone's time. I really don't need this in a week when real work™ is
busting my balls and I'm behind where I want to be with preparing for
MAME release.
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This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing
changes made to 009cba4fb8102102168ef32870892438327f3705.
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BCzF/BCzT can be used (by reading input lines) when coprocessor 2 or 3 are enabled, even when there's no real coprocessor hardware.
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Code refactoring makes the changes hard to isolate, but the main improvements are:
* implemented fpu instructions and exceptions
* corrected swl/swr implementation
* tlb mru lookup optimization
* interrupt and privilege debugger breakpoints
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* use the new 64x64 multiply helpers
* make sure unordered exceptions are generated by abs.fmt
* correct an unimportant drc flag
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* paranoid approach for 64-bit mode check
* sign extension bugs
* signed multiply bug
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Added a primitive mru scheme for tlb searches, resulting in an average of ~1.5 iterations per scan and 2-3% speedup in one test case. Also removed the confusing reverse-endian logic from lwl/lwr and friends because apparently no commercial software implementation has ever used it (and wasn't supported in any of the other instructions anyway).
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often, nw
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WIP checkpoint: while I believe it's largely accurate (and very slow), neither jazz nor sgi systems can fully boot yet using this device, so it remains experimental.
This implementation should go away when it has helped identify the improvements required for mips3.
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the Status Register
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[Ryan Holtz]
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* set the coprocessor error number in the cause register
* corrected side-effect handling in address translation
* added logging for RISC/os system calls
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* corrected cop0 context register encoding
* corrected invalid tlb entry exception vector
* improved logging
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Make sure the exception target address isn't incremented.
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I introduced this error when adding tlb support and modifying the exception code previously. This resolves the error, cleans up delayed branch handling and fixes a panic in the mips rx2030 and rx3230 driver.
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With these changes, RISC/os now loads and panics in kmemalloc().
* mips1: added fpa imp/revision numbers
* mips: hack around prom bootp broadcast bug
* rambo: timer/counter interrupt
* rambo: enough dma to make scsi work
* rambo: simulate RISC/os video dma test/init behaviour
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-30test, skeetsht, taitojc: Removed MACHINE_CONFIG macros. [Ryan Holtz]
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-aleck64, hng64, kinst, namcops2, namcos23, ps2sony, pyson, vp101: Removed MACHINE_CONFIG_*, nw
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template parameters, etc.)
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-mips3.cpp: Various changes: [Ryan Holtz]
* Added an #ifdef to display DPRINTF calls from the SGI O2 PROM.
* Switched R4000BE/LE, R4400BE, R4600BE, and R5000BE to 64-bit data bus.
* Fixed a bug that caused a crash with 64-bit data bus and the DRC.
-indy_indigo2.cpp: Moved a number of devices into HPC3. [Ryan Holtz]
-hpc3.cpp: Fixed an oversight with IRQs. [Ryan Holtz]
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