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* -r4000: Added bus error functionality. [Ryan Holtz] mooglyguy2019-05-252-6/+43
| | | | | | | | -newport: Fixed VRAM tests and several fast-clear bugs. [Ryan Holtz] -hpc3: Fixed several SGI IDE tests. [Ryan Holtz] -ioc2: Added stubs for modern PS/2 keyboard controller, nw
* r4000: fix brain damage (nw) Patrick Mackinlay2019-05-231-1/+1
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* r4000: sgi ide fixes (nw) Patrick Mackinlay2019-05-232-55/+277
| | | | Corrects some TLB diagnostic errors (remaining ones require implementing a data cache), and the FPU "underflow" test (really an unimplemented instruction exception, not an underflow) by checking for denormalized or quiet NaN operands for all floating point arithmetic instructions..
* r4000: housekeeping (nw) Patrick Mackinlay2019-05-132-23/+21
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* -ioc2: Fixed mappable interrupt checks. Fixes IRIX 6.5 installer hanging on ↵ mooglyguy2019-05-122-45/+9
| | | | | | keyboard input. [Ryan Holtz] -r4000: Changed LL/SC behaviour to not use a write tap. Possibly incorrect behaviour, but IRIX 6.5 installer doesn't hang anymore on miniroot creation, nw
* r4000: minor tweaks (nw) Patrick Mackinlay2019-05-072-40/+17
| | | | | | | * relaxed address validity checks in 32-bit mode allowing simplified base + offset computation * removed inaccurate/partial cycle counting * slight adjustment to ll/sc logic * corrected address alignment exception type
* MISP3 DRC: Fix tlbmiss in delay slot (#4979) tedgreen992019-05-051-5/+10
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* (nw) MIPS3: Use sequence generator for random tlb indices so that DRC and ↵ Ted Green2019-05-053-9/+26
| | | | non-DRC code sequences match
* mips: preserve upper 32 bits for single-precision fp operations (nw) Patrick Mackinlay2019-04-254-13/+47
| | | | | | | While this behaviour is undefined according to the MIPS R4000 Microprocessor User's Manual, various factors point toward it most likely being correct, including: 1. The fact MIPS-I exposes 16x64-bit floating-point registers, but internally implements them as pairs of 32-bit registers (with only the even-numbered pairs being valid for arithmetic operations), making it somewhat likely MOV.S, like LWC1 and SWC1, can access either half. 2. Explicit mention in IDT documentation and "See MIPS Run", i.e. "The odd-numbered registers can be accessed by move and load/store instructions", and other commentary. 3. The presence of paired-single operations in later MIPS32/64 specifications, which operate on independent single-precision values stored in each of the lower and upper halves of a single floating-point register.
* srcclean, fix up apple2_flop_clcracked.xml (nw) Vas Crabb2019-04-212-6/+6
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* (nw) MIPS3: Don't adjust EPC to pc-4 when not backing up Ted Green2019-04-111-7/+2
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* MIPS3 DRC: Always set BadVaddr on TLB miss. The TLB handler needs this to ↵ Ted Green2019-04-101-2/+1
| | | | fill in the table. (nw)
* MIPS3: Clean up LL/SC instructions and add debug break to DRC (nw) Ted Green2019-04-094-39/+81
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* MIPS3: Add divide by zero floating point exception (nw) Ted Green2019-04-064-6/+53
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* (nw) Clean up the mess on master Vas Crabb2019-03-269-766/+5237
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-259-5237/+766
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* mips1: bc2/bc3 always work (nw) Patrick Mackinlay2019-03-011-2/+64
| | | | BCzF/BCzT can be used (by reading input lines) when coprocessor 2 or 3 are enabled, even when there's no real coprocessor hardware.
* mips1: fpu emulation Patrick Mackinlay2019-02-262-726/+1354
| | | | | | | | Code refactoring makes the changes hard to isolate, but the main improvements are: * implemented fpu instructions and exceptions * corrected swl/swr implementation * tlb mru lookup optimization * interrupt and privilege debugger breakpoints
* mips3: trivial changes (nw) Patrick Mackinlay2019-02-183-80/+13
| | | | | | * use the new 64x64 multiply helpers * make sure unordered exceptions are generated by abs.fmt * correct an unimportant drc flag
* r4000: Fixed ABS.S and ABS.D. Fixes X server crashing in IRIX. [Ryan Holtz] MooglyGuy2019-02-161-0/+8
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* r4000: minor fixes (nw) Patrick Mackinlay2019-02-142-41/+32
| | | | | | * paranoid approach for 64-bit mode check * sign extension bugs * signed multiply bug
* r4000: small performance tweak (nw) Patrick Mackinlay2019-02-112-31/+48
| | | | Added a primitive mru scheme for tlb searches, resulting in an average of ~1.5 iterations per scan and 2-3% speedup in one test case. Also removed the confusing reverse-endian logic from lwl/lwr and friends because apparently no commercial software implementation has ever used it (and wasn't supported in any of the other instructions anyway).
* Fix compile, nw MooglyGuy2019-02-101-2/+2
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* -r4000: Added the ability to CTC and CFC from unknown fpr30, which IRIX does ↵ MooglyGuy2019-02-102-0/+8
| | | | often, nw
* r4000: tweak address calculation (nw) Patrick Mackinlay2019-02-081-103/+109
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* r4000: size does matter (nw) Patrick Mackinlay2019-02-041-4/+4
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* r4000: experimental mips3 implementation (nw) Patrick Mackinlay2019-02-012-0/+3533
| | | | | | WIP checkpoint: while I believe it's largely accurate (and very slow), neither jazz nor sgi systems can fully boot yet using this device, so it remains experimental. This implementation should go away when it has helped identify the improvements required for mips3.
* srcclean and cleanup (nw) Vas Crabb2019-01-273-10/+10
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* mips3: debugger exception hook (nw) Patrick Mackinlay2019-01-221-0/+1
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* MIPS3: Add minimal support for revealing the Secondary Cache Line size in ↵ tyfighter2019-01-143-0/+10
| | | | the Status Register
* mips3drc: Fixed block checksumming. Fixes IRIX installer hang on ip225015. ↵ MooglyGuy2019-01-121-24/+35
| | | | [Ryan Holtz]
* mips3: Fixed fastram accesses and COP0 exception handling. [Ryan Holtz] MooglyGuy2019-01-112-11/+24
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* mips1: magic number removal and more logging (nw) Patrick Mackinlay2019-01-092-60/+86
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* mips1: fix Clang compile (nw) arbee2019-01-041-1/+1
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* mips1: fix coprocessor exceptions (nw) Patrick Mackinlay2019-01-032-52/+276
| | | | | | * set the coprocessor error number in the cause register * corrected side-effect handling in address translation * added logging for RISC/os system calls
* mips1: fix stupid tlb error (nw) Patrick Mackinlay2019-01-011-3/+3
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* mips1: tlb fixes (nw) Patrick Mackinlay2018-12-202-19/+45
| | | | | | * corrected cop0 context register encoding * corrected invalid tlb entry exception vector * improved logging
* mips1: missed this (nw) Patrick Mackinlay2018-12-182-4/+9
| | | | Make sure the exception target address isn't incremented.
* mips1: handle exceptions in delay slot instructions (nw) Patrick Mackinlay2018-12-182-58/+70
| | | | I introduced this error when adding tlb support and modifying the exception code previously. This resolves the error, cleans up delayed branch handling and fixes a panic in the mips rx2030 and rx3230 driver.
* mips: enough to panic (nw) Patrick Mackinlay2018-12-181-0/+12
| | | | | | | | | With these changes, RISC/os now loads and panics in kmemalloc(). * mips1: added fpa imp/revision numbers * mips: hack around prom bootp broadcast bug * rambo: timer/counter interrupt * rambo: enough dma to make scsi work * rambo: simulate RISC/os video dma test/init behaviour
* -nanoprocessor, mn10200, ps2vu, m68hc11: Removed MCFG macros. [Ryan Holtz] mooglyguy2018-12-151-3/+4
| | | | -30test, skeetsht, taitojc: Removed MACHINE_CONFIG macros. [Ryan Holtz]
* -mips, rsp: Removed MCFG, nw mooglyguy2018-12-091-10/+0
| | | | -aleck64, hng64, kinst, namcops2, namcos23, ps2sony, pyson, vp101: Removed MACHINE_CONFIG_*, nw
* (nw) adjust some stuff (uniform spacing, standardised logging, capitalised ↵ Vas Crabb2018-11-282-2/+2
| | | | template parameters, etc.)
* srcclean and fixup (nw) Vas Crabb2018-11-252-250/+250
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* mips3dsm : Add secondary cache instruction decoding (nw) Happy2018-11-191-4/+8
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* mips3.cpp: Added logging of cache opcodes, nw mooglyguy2018-11-192-3/+94
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* mips1: handle no cache (nw) Patrick Mackinlay2018-11-191-2/+4
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* mips3.cpp: Started laying the groundwork for cache support, nw mooglyguy2018-11-194-63/+101
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* -o2.cpp: Added CRIME and MACE skeleton devices. [Ryan Holtz] mooglyguy2018-11-183-26/+451
| | | | | | | | | | | -mips3.cpp: Various changes: [Ryan Holtz] * Added an #ifdef to display DPRINTF calls from the SGI O2 PROM. * Switched R4000BE/LE, R4400BE, R4600BE, and R5000BE to 64-bit data bus. * Fixed a bug that caused a crash with 64-bit data bus and the DRC. -indy_indigo2.cpp: Moved a number of devices into HPC3. [Ryan Holtz] -hpc3.cpp: Fixed an oversight with IRQs. [Ryan Holtz]
* mips3: Added correct R5271 processor id (nw) Ted Green2018-11-131-1/+3
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