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* Merge branch 'master' into time-experiments2 Aaron Giles2021-09-101-1/+0
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| * Debugger-related feature removals and cleanup AJR2021-08-151-1/+0
| | | | | | | | | | | | | | | | - Remove the hotspot read tracker. This was never robustly implemented, but changes to the memory system made it much less useful, and the "speedup opportunities" which it aimed to determine are not very important from a current emulation standpoint. - Remove the CURSP/GENSP state symbol and the generic sp() getter. Stacking semantics vary too much between CPU architectures for this to be of much use. (A "SP" symbol has been added to a few CPU cores whose stack pointers were otherwise not being registered.) - Remove the cached pointer to device_state_interface and the state() fast accessor from device_t. Most users of device_state_interface either already had a pointer to the specific CPU device type or needed to check first for the presence of the interface. - Change the PC memory write tracker to use pcbase(), which works even when the instruction callback is masked out, instead of peeking at the PC history index. - Remove some obsolete watchpoint-related definitions from machine.h.
* | Use the device-provided timer_alloc instead of reaching around to the ↵ Aaron Giles2021-03-251-1/+1
|/ | | | scheduler. Also change machine().scheduler().time() calls to just machine().time().
* -osd: Clean up inline maths utilities. Vas Crabb2021-01-181-2/+2
| | | | | | | | | | * Removed inline assembly for operations compilers handle well. * Added ARM and AArch64 implementation for a few operations. * Added unsigned integer add with carry out operations. -cpu/drccache.cpp: Detect whether RWX pages are supported. -dynax.cpp: Improved a few hanafuda DIP switch descriptions.
* Enable GCC implicit fallthrough warning. Vas Crabb2020-11-151-0/+2
| | | | | | I've guessed whether break or [[fallthrough]] is appropriate. In cases where it looked particularly suspicious, I added a FIXME comment. All of these changes should be reviewed by someone familiar with the code.
* -Switch to building MAME as C++17. Vas Crabb2020-11-151-8/+8
| | | | | | | * Updated sol2 to 3.2.2 * Updated pugixml to 1.10 * Increased minimum clang version to 6 * Cleaned up some stuff that can use new features
* n64: modify burn_cycles method (nw) hap2020-06-221-5/+0
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* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-251-12/+12
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* mips3drc: log a message if a "fast" register is set via the debugger. If ↵ Vas Crabb2019-09-271-64/+74
| | | | there's a way to load a UML register from outside recompiled code, this will help someone fix GitHub issue #4904. Cached registers aren't reassigned dynamically, so it's pretty simple. (nw)
* (nw) MIPS3: Use sequence generator for random tlb indices so that DRC and ↵ Ted Green2019-05-051-4/+10
| | | | non-DRC code sequences match
* srcclean, fix up apple2_flop_clcracked.xml (nw) Vas Crabb2019-04-211-2/+2
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* (nw) MIPS3: Don't adjust EPC to pc-4 when not backing up Ted Green2019-04-111-7/+2
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* MIPS3: Clean up LL/SC instructions and add debug break to DRC (nw) Ted Green2019-04-091-22/+33
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* MIPS3: Add divide by zero floating point exception (nw) Ted Green2019-04-061-4/+24
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* (nw) Clean up the mess on master Vas Crabb2019-03-261-47/+27
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-27/+47
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* mips3: trivial changes (nw) Patrick Mackinlay2019-02-181-36/+2
| | | | | | * use the new 64x64 multiply helpers * make sure unordered exceptions are generated by abs.fmt * correct an unimportant drc flag
* srcclean and cleanup (nw) Vas Crabb2019-01-271-4/+4
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* mips3: debugger exception hook (nw) Patrick Mackinlay2019-01-221-0/+1
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* MIPS3: Add minimal support for revealing the Secondary Cache Line size in ↵ tyfighter2019-01-141-0/+1
| | | | the Status Register
* mips3: Fixed fastram accesses and COP0 exception handling. [Ryan Holtz] MooglyGuy2019-01-111-11/+23
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* srcclean and fixup (nw) Vas Crabb2018-11-251-1/+1
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* mips3.cpp: Added logging of cache opcodes, nw mooglyguy2018-11-191-3/+92
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* mips3.cpp: Started laying the groundwork for cache support, nw mooglyguy2018-11-191-44/+67
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* -o2.cpp: Added CRIME and MACE skeleton devices. [Ryan Holtz] mooglyguy2018-11-181-2/+15
| | | | | | | | | | | -mips3.cpp: Various changes: [Ryan Holtz] * Added an #ifdef to display DPRINTF calls from the SGI O2 PROM. * Switched R4000BE/LE, R4400BE, R4600BE, and R5000BE to 64-bit data bus. * Fixed a bug that caused a crash with 64-bit data bus and the DRC. -indy_indigo2.cpp: Moved a number of devices into HPC3. [Ryan Holtz] -hpc3.cpp: Fixed an oversight with IRQs. [Ryan Holtz]
* mips3: exception handling fixes (nw) Patrick Mackinlay2018-10-031-25/+19
| | | | | | * nested exceptions shouldn't overwrite the EPC * nested tlb exceptions go to the general exception vector * remove breakpoint for tlb exceptions and branch to proper vector
* mips3: add r4000 and r4400 variants (nw) Patrick Mackinlay2018-09-191-0/+4
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* Revert "MIPS3: Fixup LL/SC opcode operation. (nw)" Ted Green2018-09-011-21/+21
| | | | This reverts commit 326b1f7465540684ffe539099b20b2384f16feb7.
* MIPS3: Fixup LL/SC opcode operation. (nw) Ted Green2018-09-011-21/+21
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* mip3: Proper DMULT(U) implementation from git issue #3718 [bryanperris] (#3746) tedgreen992018-08-311-22/+32
| | | | | | * mip3: Proper DMULT(U) implementation from git issue #3718 [bryanperris] * mips3: Updated dmult(u) implementation.
* fix for undefined fmin & ceil on GNU Guix with GCC 5.5.0 (nw) smf-2018-08-111-0/+1
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* (nw) srcclean and some cleanup: Vas Crabb2018-07-221-141/+141
| | | | | | * Make more #include guards follow standard format - using MAME_ as the prefix makes it easy to see which ones come from our code in a preprocessor dump, and having both src/devices/machine/foo.h and src/mame/machine/foo.h causes issues anyway * Get #include "emu.h" out of headers - it should only be the first thing in a complilation unit or we get differences in behaviour with PCH on/off * Add out-of-line destructors to some devices - it forces the compiler to instantiate the vtable in a certain location and avoids some non-deterministic compiler behaviours
* ps2sony: Some basic VU1 support, major file reshuffling, nw mooglyguy2018-07-211-5/+4
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* ps2sony: Checkpoint, nw mooglyguy2018-07-171-76/+919
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* ps2sony: Checkpoint. Adds a bunch of vector and parallel ops to the EE core, ↵ mooglyguy2018-07-141-63/+348
| | | | and skeleton GIF VIF1, and GS devices.
* ps2sony: Checkpoint, nw mooglyguy2018-07-101-17/+43
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* ps2sony: checkpoint, nw mooglyguy2018-07-071-4/+16
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* -ps2sony: Various DMA and SIF bug fixes, initial OSDSYS ELF transfers to IOP ↵ mooglyguy2018-07-051-13/+62
| | | | now, but EE and IOP hang immediately thereafter. nw
* -ps2sony: Fleshing out the skeleton driver. [Ryan Holtz] mooglyguy2018-06-281-35/+1116
| | | | | | | | | | | | | * Added ps2timer device to encapsulate Playstation 2 timers. * Temporarily hacked R5900 core to always have scratchpad RAM mapped at 0x70000000. * Added reference counting to divtlb so that it does not unmap pages that are still shared with other entries. * Added a considerable amount of logging to ps2sony.cpp. -mips3: Added basic Emotion Engine support. [Ryan Holtz] * Added S bit to TLB mapping. * Added support for VSUB, VIADD, VSQI, VISWR, VOR, LQ, SQ, MFSA, MTSA, MFHI1, MFLO1, MULT1, DIV1, DIVU1, PEXTLW, PADDUW, PMFHI, PMFLO, PCPYLD, PCPYUD, SQC2, LQC2 opcodes. [Ryan Holtz]
* srcclean and other cleanup (nw) Vas Crabb2018-06-241-23/+23
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* mips3: Added VU0 macro-instructions to R5900 disassembler, pending split ↵ mooglyguy2018-06-231-28/+27
| | | | into separate device. nw
* mips3: Added disassembler for Emotion Engine core opcodes. VU macro ops are ↵ mooglyguy2018-06-231-27/+62
| | | | still to-do. [Ryan Holtz]
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-111-2/+13
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-251-2/+2
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-20/+20
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* emumem: API change [O. Galibert] Olivier Galibert2017-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-7/+3
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* mips3: Cleanup TX4925 implementation. (nw) Ted Green2017-11-061-71/+9
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* This is too contentious, please put it up for review Vas Crabb2017-08-011-13/+8
| | | | | | Revert "Changes to debugger memory address translation" This reverts commit bb0964f9a284b15851773f5428bd602ca01cc28b.