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* ax208 disassembly improvements (nw) (#5088) David Haywood2019-05-202-68/+600
| | | | | | | | | | * ax208 disassembly improvements (nw) * (nw) * (nw) * (nw)
* (nw) Clean up the mess on master Vas Crabb2019-03-262-0/+16
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-252-16/+0
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* mcs51: New version of old hack to break out of JB INT0/INT1 loops when ↵ AJR2019-03-222-0/+16
| | | | interrupt is triggered
* srcclean (nw) Vas Crabb2018-12-234-64/+64
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* add SFR register names for axc51 disassemler (#4405) David Haywood2018-12-213-2/+279
| | | | | | | | | | | | | | | | | | * add SFR register names for axc51 disassemler * better formatting (nw) * copy some code that looks a lot like boot code (nw) * current notes, lots of blocks that can definitely be copied to 0x5e00, nothing that appears to map at 0x9000 (yet there are lot of calls to 0x9000 ...) * (nw) * (nw) * (nw) * notes about the code in the ROMs (nw)
* add derived CPU type for AX51-CORE (used by AX208 and others) so that we can ↵ DavidHaywood2018-12-146-6/+147
| | | | start to customize disassembly and execution
* mcs51: Remove remaining MCFGs, nw mooglyguy2018-12-091-15/+3
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* mcs51.cpp: Removed MCFG. Various MACHINE_CONFIG removals. nw mooglyguy2018-12-091-27/+0
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* mcs48: Removed MCFG, nw mooglyguy2018-12-081-0/+3
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* New skeleton device: Western Digital WD1007A ESDI hard disk controller [Al ↵ AJR2018-07-142-0/+15
| | | | Kossow]
* devcb3 Vas Crabb2018-07-071-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple issues with the current device callbacks: * They always dispatch through a pointer-to-member * Chained callbacks are a linked list so the branch unit can't predict the early * There's a runtime decision made on the left/right shift direction * There are runtime NULL checks on various objects * Binding a lambda isn't practical * Arbitrary transformations are not supported * When chaining callbacks it isn't clear what the MCFG_DEVCB_ modifiers apply to * It isn't possible to just append to a callback in derived configuration * The macros need a magic, hidden local called devcb * Moving code that uses the magic locals around is error-prone * Writing the MCFG_ macros to make a device usable is a pain * You can't discover applicable MCFG_ macros with intellisense * Macros are not scoped * Using an inappropriate macro isn't detected at compile time * Lots of other things This changeset overcomes the biggest obstacle to remving MCFG_ macros altogether. Essentially, to allow a devcb to be configured, call .bind() and expose the result (a bind target for the callback). Bind target methods starting with "set" repace the current callbacks; methods starting with "append" append to them. You can't reconfigure a callback after resolving it. There's no need to use a macro matching the handler signatures - use FUNC for everything. Current device is implied if no tag/finder is supplied (no need for explicit this). Lambdas are supported, and the memory space and offset are optional. These kinds of things work: * .read_cb().set([this] () { return something; }); * .read_cb().set([this] (offs_t offset) { return ~offset; }); * .write_cb().set([this] (offs_t offset, u8 data) { m_array[offset] = data; }); * .write_cb().set([this] (int state) { some_var = state; }); Arbitrary transforms are allowed, and they can modify offset/mask for example: * .read_cb().set(FUNC(my_state::handler)).transform([] (u8 data) { return bitswap<4>(data, 1, 3, 0, 2); }); * .read_cb().set(m_dev, FUNC(some_device::member)).transform([] (offs_t &offset, u8 data) { offset ^= 3; return data; }); It's possible to stack arbitrary transforms, at the cost of compile time (the whole transform stack gets inlined at compile time). Shifts count as an arbitrary transform, but mask/exor does not. Order of mask/shift/exor now matters. Modifications are applied in the specified order. These are NOT EQUIVALENT: * .read_cb().set(FUNC(my_state::handler)).mask(0x06).lshift(2); * .read_cb().set(FUNC(my_state::handler)).lshift(2).mask(0x06); The bit helper no longer reverses its behaviour for read callbacks, and I/O ports are no longer aware of the field mask. Binding a read callback to no-op is not supported - specify a constant. The GND and VCC aliases have been removed intentionally - they're TTL-centric, and were already being abused. Other quirks have been preserved, including write logger only logging when the data is non-zero (quite unhelpful in many of the cases where it's used). Legacy syntax is still supported for simple cases, but will be phased out. New devices should not have MCFG_ macros. I don't think I've missed any fundamental issues, but if I've broken something, let me know.
* cidx628: Make this display something again AJR2018-06-222-0/+28
| | | | mcs51: Distinguish AT89C52/S52 device types (nw)
* mcs51.cpp: Consolidate internal address maps; remove P0 from ROMless ↵ AJR2018-06-132-24/+13
| | | | versions since it conflicts with external accesses on hardware (nw)
* diexec: Interrupt API changes (nw) AJR2018-05-181-1/+0
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-112-5/+5
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* mcs51.cpp: Eliminate atrocious hack for breaking out of INT0 polling loops (nw) AJR2018-05-091-4/+0
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* mcs51: Add more interrupt and timer registers to debug state AJR2018-05-012-2/+10
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* Sarayan made me do it. Vas Crabb2018-04-281-1/+1
| | | | | | | | | | Concrete device types now have a call operator that instantiates a device. This change means you *must* use DECLARE_DEVICE_TYPE to declare the public interface of your device, even if it's device_t. If you want to use private implementation classes, use DEFINE_DEVICE_TYPE_PRIVATE and instantiate the object finders.
* srcclean (nw) Vas Crabb2018-04-221-2/+2
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* maps: Finish devices/cpu (nw) Olivier Galibert2018-04-201-17/+21
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* mcs51: Safer way to propagate INT0 and INT1 inputs, which also need to be ↵ AJR2018-04-161-3/+3
| | | | active low (nw)
* vp415 updates, now actually starts proper testing loop, nw mooglyguy2018-04-151-1/+4
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* move some not-directly-emulation-related helpers to lib/util, further ↵ Vas Crabb2018-04-011-0/+3
| | | | extricate emu.h from tools (nw)
* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-18/+18
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-14/+14
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* destaticify initializations (nw) (#3289) wilbertpol2018-03-041-21/+21
| | | | | | * destaticify initializations (nw) * fix this->set_screen (nw)
* mcs51: Use callbacks for parallel ports (nw) AJR2018-02-272-86/+52
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* API change: Memory maps are now methods of the owner class [O. Galibert] Olivier Galibert2018-02-122-6/+10
| | | | | Also, a lot more freedom happened, that's going to be more visible soon.
* mcs51: Add DPTR, P0, P1, P2 and P3 to debug state registration AJR2018-01-232-3/+9
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* emumem: API change [O. Galibert] Olivier Galibert2017-11-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * direct_read_data is now a template which takes the address bus shift as a parameter. * address_space::direct<shift>() is now a template method that takes the shift as a parameter and returns a pointer instead of a reference * the address to give to {read|write}_* on address_space or direct_read_data is now the address one wants to access Longer explanation: Up until now, the {read|write}_* methods required the caller to give the byte offset instead of the actual address. That's the same on byte-addressing CPUs, e.g. the ones everyone knows, but it's different on the word/long/quad addressing ones (tms, sharc, etc...) or the bit-addressing one (tms340x0). Changing that required templatizing the direct access interface on the bus addressing granularity, historically called address bus shift. Also, since everybody was taking the address of the reference returned by direct(), and structurally didn't have much choice in the matter, it got changed to return a pointer directly. Longest historical explanation: In a cpu core, the hottest memory access, by far, is the opcode fetching. It's also an access with very good locality (doesn't move much, tends to stay in the same rom/ram zone even when jumping around, tends not to hit handlers), which makes efficient caching worthwhile (as in, 30-50% faster core iirc on something like the 6502, but that was 20 years ago and a number of things changed since then). In fact, opcode fetching was, in the distant past, just an array lookup indexed by pc on an offset pointer, which was updated on branches. It didn't stay that way because more elaborate access is often needed (handlers, banking with instructions crossing a bank...) but it still ends up with a frontend of "if the address is still in the current range read from pointer+address otherwise do the slowpath", e.g. two usually correctly predicted branches plus the read most of the time. Then the >8 bits cpus arrived. That was ok, it just required to do the add to a u8 *, then convert to a u16/u32 * and do the read. At the asm level, it was all identical except for the final read, and read_byte/word/long being separate there was no test (and associated overhead) added in the path. Then the word-addressing CPUs arrived with, iirc, the tms cpus used in atari games. They require, to read from the pointer, to shift the address, either explicitely, or implicitely through indexing a u16 *. There were three possibilities: 1- create a new read_* method for each size and granularity. That amounts to a lot of copy/paste in the end, and functions with identical prototypes so the compiler can't detect you're using the wrong one. 2- put a variable shift in the read path. That was too expensive especially since the most critical cpus are byte-addressing (68000 at the time was the key). Having bit-adressing cpus which means the shift can either be right or left depending on the variable makes things even worse. 3- require the caller to do the shift himself when needed. The last solution was chosen, and starting that day the address was a byte offset and not the real address. Which is, actually, quite surprising when writing a new cpu core or, worse, when using the read/write methods from the driver code. But since then, C++ happened. And, in particular, templates with non-type parameters. Suddendly, solution 1 can be done without the copy/paste and with different types allowing to detect (at runtime, but systematically and at startup) if you got it wrong, while still generating optimal code. So it was time to switch to that solution and makes the address parameter sane again. Especially since it makes mucking in the rest of the memory subsystem code a lot more understandable.
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-264-435/+444
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* x David Haywood2017-07-201-2/+2
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* gaelco / ds5002fp changes: David Haywood2017-07-192-31/+82
| | | | | | | | | | | | - made ds5002fp store internal ram and sfr registers to nvram as they're battery backed - this includes the 'configuration' details which are actually programmable, so don't belong in the 'MACHINE_CONFIG' section but rather as part of the default NVRAM - as the exact format of the NVRAM storage is not known, and as not to break compatibility with the 'wrally' set Gaelco offer these bytes are now configured in the ROM LOADING like default NVRAM. Slightly awkward, but probably the best way. - made the SRAM (external to DS5002FP, but still powered by the same battery) also save content, some games actually use it to store scores etc. as well as the game code. - cleaned up the Touch and Go Dallas dump, and added some preconfigured internal RAM so that it actually loads the score data from the SRAM properly - prepared all other drivers for the adding of the SRAM dumps, removing old 'never going to work' simulation code in the process. To do this a wrapper / interface device for the Gaelco Dallas + SRAM box was created. out of whatsnew Alligator Hunt was dumped and works, but not yet added, want to verify on a 2nd PCB first as the process does corrupt some bytes and a couple had to be handfixed, so the only way to know for sure is multiple dumps.
* A number of DS5002FP chips were dumped using the method published by Morten ↵ David Haywood2017-07-171-1/+1
| | | | | | | | | | | | | | | | Shearman Kirkegaard and Peter Wilhelmsen as documented at (#2484) http://www.afdelingp.dk/files/articles/ds5002fp/ds5002fp.pdf namely Touch and Go, World Rally 2, and TH Strikes Back a 2nd verification pass is still needed on them from additional boards, as bad bits existed in World Rally 2 even prior to extraction (steering logic was broken but bad byte was identified and fixed as the code for that command handler was identical to World Rally 1) and TH Strikes Back is crashing at the first boss (could also be a CPU core issue) Glass was also dumped, but at the time the data wasn't extracted, only the code, and the board has since died, so needs redoing. Machines promoted to WORKING ---------------------------- World Rally 2 [Morten Shearman Kirkegaard,Peter Wilhelmsen, David Haywood] Touch & Go (World) [Morten Shearman Kirkegaard,Peter Wilhelmsen, David Haywood] Touch & Go (Non North America) [Morten Shearman Kirkegaard,Peter Wilhelmsen, David Haywood] Touch & Go (earlier revision) [Morten Shearman Kirkegaard,Peter Wilhelmsen, David Haywood]
* make device_memory_interface slightly less of a special case, use a typedef ↵ Vas Crabb2017-07-102-3/+3
| | | | to avoid nested templates everywhere (nw)
* dimemory: Lift the cap on the number of address spaces per device [O. Galibert] Olivier Galibert2017-07-032-4/+10
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* Move static data out of devices into the device types. This is a ↵ Vas Crabb2017-05-142-65/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | significant change, so please pay attention. The core changes are: * Short name, full name and source file are no longer members of device_t, they are part of the device type * MACHINE_COFIG_START no longer needs a driver class * MACHINE_CONFIG_DERIVED_CLASS is no longer necessary * Specify the state class you want in the GAME/COMP/CONS line * The compiler will work out the base class where the driver init member is declared * There is one static device type object per driver rather than one per machine configuration Use DECLARE_DEVICE_TYPE or DECLARE_DEVICE_TYPE_NS to declare device type. * DECLARE_DEVICE_TYPE forward-declares teh device type and class, and declares extern object finders. * DECLARE_DEVICE_TYPE_NS is for devices classes in namespaces - it doesn't forward-declare the device type. Use DEFINE_DEVICE_TYPE or DEFINE_DEVICE_TYPE_NS to define device types. * These macros declare storage for the static data, and instantiate the device type and device finder templates. The rest of the changes are mostly just moving stuff out of headers that shouldn't be there, renaming stuff for consistency, and scoping stuff down where appropriate. Things I've actually messed with substantially: * More descriptive names for a lot of devices * Untangled the fantasy sound from the driver state, which necessitates breaking up sound/flip writes * Changed DECO BSMT2000 ready callback into a device delegate * Untangled Microprose 3D noise from driver state * Used object finders for CoCo multipak, KC85 D002, and Irem sound subdevices * Started to get TI-99 stuff out of the TI-990 directory and arrange bus devices properly * Started to break out common parts of Samsung ARM SoC devices * Turned some of FM, SID, SCSP DSP, EPIC12 and Voodoo cores into something resmbling C++ * Tried to make Z180 table allocation/setup a bit safer * Converted generic keyboard/terminal to not use WRITE8 - space/offset aren't relevant * Dynamically allocate generic terminal buffer so derived devices (e.g. teleprinter) can specify size * Imporved encapsulation of Z80DART channels * Refactored the SPC7110 bit table generator loop to make it more readable * Added wrappers for SNES PPU operations so members can be made protected * Factored out some boilerplate for YM chips with PSG * toaplan2 gfx * stic/intv resolution * Video System video * Out Run/Y-board sprite alignment * GIC video hookup * Amstrad CPC ROM box members * IQ151 ROM cart region * MSX cart IRQ callback resolution time * SMS passthrough control devices starting subslots I've smoke-tested several drivers, but I've probably missed something. Things I've missed will likely blow up spectacularly with failure to bind errors and the like. Let me know if there's more subtle breakage (could have happened in FM or Voodoo). And can everyone please, please try to keep stuff clean. In particular, please stop polluting the global namespace. Keep things out of headers that don't need to be there, and use things that can be scoped down rather than macros. It feels like an uphill battle trying to get this stuff under control while more of it's added.
* 8051 MCU family core fix : Fix the indirect memory access opcodes dec,inc ↵ Jean-François DEL NERO2017-03-301-3/+3
| | | | | | | and xch_a. Indirect access can't touch the SFR and must point to the extra memory above 0x80. This probably fix many machines using this MCU.
* fix some device validation errors, also fix uninitialised members in some ↵ Vas Crabb2017-03-031-1/+1
| | | | devices using constructor delegation (nw)
* Self-registering devices prep: Vas Crabb2017-02-271-14/+14
| | | | | | | | | | | | | | * Make device_creator a variable template and get rid of the ampersands * Remove screen.h and speaker.h from emu.h and add where necessary * Centralise instantiations of screen and speaker finder templates * Add/standardise #include guards in many hearers * Remove many redundant #includes * Order #includesr to help catch headers that can't be #included alone (nw) This changes #include order to be prefix, unit header if applicable then other stuff roughly in order from most dependent to least dependent library. This helps catch headers that don't #include things that they use.
* A round of spelling/typographical fixes to source comments (nw) Scott Stone2016-11-242-5/+5
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* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-203-32/+23
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* Changed the mcs51 disassembler to use 'std::ostream &' internally Nathan Woods2016-11-161-114/+123
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* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-224-446/+446
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* Make sure all cpu's export STATE_GENPCBASE and use safe_pcbase() for ↵ smf-2016-09-281-0/+1
| | | | everything in the debugger, which allows interruptible cpu's to work properly. [smf]
* Revert "Make sure all cpu's export STATE_GENPCBASE and use safe_pcbase() for ↵ Lord-Nightmare2016-09-271-1/+0
| | | | | | everything in the debugger, which allows interruptible cpu's to work properly. [smf]" This reverts commit 1a186c8a3a16a7ce99d7df2dd217a7552b696c92.
* Make sure all cpu's export STATE_GENPCBASE and use safe_pcbase() for ↵ smf-2016-09-271-0/+1
| | | | everything in the debugger, which allows interruptible cpu's to work properly. [smf]
* Cleanups and version bump Miodrag Milanovic2016-07-271-1/+1
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