| Commit message (Collapse) | Author | Age | Files | Lines |
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mcs51: remove old changelog from comments, remove copypasted comment block
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just not specifically at the last stage,
mcs51: add some todo notes
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PES bit is peripheral enable select on bytewide bus.
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micro3d: reverse throttle control
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* mode 0 is still incorrect
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instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one).
Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs.
* cpu/hd61700, cpu/tms32031: Add standard IRQ callback
* cpu/m68000gen.py: Change name of invoked executable to bin/python3
* cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
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emu/diimage.h: Removed fread overloads that allocate memory for output.
util/core_file.cpp: Changed output size of load to size_t.
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----------------------------------
Quasimidi Sirius [DBWBP]
Quasimidi Rave-O-Lution 309 [DBWBP]
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definitions for their disassemblers
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Read callbacks now need a default return value supplied at construction.
Replaced isnull() with isunset() which tells you if the callback wasn't
configured rather than whether it isn't safe to call.
Enabled validation of device callbacks (it seems it was disabled at some
point, probably accidentally).
Device callbacks and object finders now implement the same interface for
resolution.
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* fix [MT#05495](https://mametesters.org/view.php?id=5495)
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- Make CPUs pass interrupt return PC as a second argument to standard_irq_callback
- Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command
- Add messages to trace logs whenever interrupts are accepted
- Attempt to step over interrupt routines for applicable debugger commands
- Eliminate standard_irq_callback_member wrapper method
- Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes
- Remove IRQ callbacks for some input lines that never cause interrupts
- mb88xx, mcs48: Add IRQ callbacks for internal interrupts
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Haywood] (#10131)
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and save methods, and have these return false on I/O errors
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(City Game), Peter Ferrie, David Haywood] (#8916)
* Research into thoop and squash 'refrsh rate' protection [Victor Fernandez (City Game), Peter Ferrie, David Haywood]
- prevents freeze when dying in stage 4 of Thunder Hoop, and bad text on continue in Squash
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i186.cpp: Add clock note (nw)
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not pointers anymore [O. Galibert]
The last(?) two changes are:
- Add a template parameter to everything (theoretically the address
space width, in practice a level derived from it to keep as much
compatibility between widths as possible) so that the shift size
becomes a constant.
- Change the syntax of declaring and initializing the caches and
specifics so that they're embedded in the owner device. Solves
lifetime issues and also removes one indirection (looking up the base
dispatch pointer through the cache/specific pointer).
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https://github.com/mamedev/mame/tree/devcb-no-space branch build. (nw)
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* Finish midqslvr.cpp's documentation
U4 component on the Diego board was initially incorrect as "109B" instead of "1098" (A/D converter that obviously controls steering and throttle). Arctic Thunder's I/O cpu turned out to be a 87C552 MCU which uses the same architecture as the predicted 87C51/2; both Intel MCS-51 based. If anyone wants this decapped, I will (most likely) be happy to donate my substitute I/O board though I would hate to waste a fully working pcb.
* Because Arctic Thunder uses this MCU architecture
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emu\memarray.h cause I didn't want to cause a full recompile for this (nw)
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- Restore some 8052 SFR and bit names that were inadvertently omitted for more advanced models
- Add a few more T2-related names
- Add i8xc51fx and i8xc51gb disassemblers with additional SFR and bit names
- Remove i80c51 from unidasm (actual differences from i8051 are not significant)
Change device names from "Intel I8xxx" to "Intel 8xxx" (nw)
scm_500: Identify CPU type as 80C51GB (specific differences obviously not emulated) (nw)
unidasm: Realphabetize mips1 (nw)
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This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and
c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at
598cd5227223c3b04ca31f0dbc1981256d9ea3ff.
Before pushing, please check that what you're about to push is sane.
Check your local commit log and ensure there isn't anything out-of-place
before pushing to mainline. When things like this happen, it wastes
everyone's time. I really don't need this in a week when real work™ is
busting my balls and I'm behind where I want to be with preparing for
MAME release.
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This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing
changes made to 009cba4fb8102102168ef32870892438327f3705.
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interrupt is triggered
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Kossow]
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mcs51: Distinguish AT89C52/S52 device types (nw)
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versions since it conflicts with external accesses on hardware (nw)
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template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
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active low (nw)
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* Move around the debugger hooks to get a small but measurable performance increase
* Remove emucore from external tools
* Improve performance of DSP16 interpreter a little by generating six variants of execution loop
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mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
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