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path: root/src/devices/cpu/mcs51/mcs51.cpp
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* srcclean and manual cleanup Vas Crabb2025-01-261-6/+6
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* mcs51: clean up source code spacing hap2025-01-221-306/+303
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* misc: remove "all rights reserved" copyright comment, hap2025-01-221-115/+86
| | | | mcs51: remove old changelog from comments, remove copypasted comment block
* mcs51: remove unneeded powerdown check hap2025-01-221-4/+0
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* mcs51: improve execute_run icount timing hap2025-01-191-80/+50
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* micro3d: correct mcu type, re-add underclock hack, it was still crashing, ↵ hap2025-01-181-5/+6
| | | | | | just not specifically at the last stage, mcs51: add some todo notes
* cpu/mcs51/mcs51.cpp: Implemented PES bit for DS5002FP. (#13224) cam9002025-01-191-3/+11
| | | PES bit is peripheral enable select on bytewide bus.
* mcs51: don't mask P3.1 at reset Patrick Mackinlay2025-01-141-1/+1
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* mcs51: update savestates, hap2025-01-101-16/+22
| | | | micro3d: reverse throttle control
* mcs51: fix P3.1 output logic Patrick Mackinlay2025-01-101-7/+18
| | | | * mode 0 is still incorrect
* diexec: Add callback to allow debugger to break into the middle of wait-type ↵ AJR2024-11-171-0/+1
| | | | | | | | | | instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one). Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs. * cpu/hd61700, cpu/tms32031: Add standard IRQ callback * cpu/m68000gen.py: Change name of invoked executable to bin/python3 * cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
* util/ioprocs.cpp: Added wrappers for common patterns. (#11608) Vas Crabb2024-02-251-6/+14
| | | | | emu/diimage.h: Removed fread overloads that allocate memory for output. util/core_file.cpp: Changed output size of load to size_t.
* New machines marked as NOT_WORKING AJR2024-02-191-0/+11
| | | | | | ---------------------------------- Quasimidi Sirius [DBWBP] Quasimidi Rave-O-Lution 309 [DBWBP]
* mcs51: Add placeholder device types for P87C552 and P80C562, with custom SFR ↵ AJR2024-02-131-0/+27
| | | | definitions for their disassemblers
* emu/devcb.h: Eliminated the need to call resolve() on callbacks. (#11333) Vas Crabb2023-06-171-4/+1
| | | | | | | | | | | | Read callbacks now need a default return value supplied at construction. Replaced isnull() with isunset() which tells you if the callback wasn't configured rather than whether it isn't safe to call. Enabled validation of device callbacks (it seems it was disabled at some point, probably accidentally). Device callbacks and object finders now implement the same interface for resolution.
* mcs51: add rxb8 to uart reset hap2023-06-031-2/+3
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* mcs51: implement serial input/output as bit stream (#11190) Patrick Mackinlay2023-05-081-108/+222
| | | * fix [MT#05495](https://mametesters.org/view.php?id=5495)
* Interrupt callback rationalization AJR2023-03-111-10/+15
| | | | | | | | | | | - Make CPUs pass interrupt return PC as a second argument to standard_irq_callback - Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command - Add messages to trace logs whenever interrupts are accepted - Attempt to step over interrupt routines for applicable debugger commands - Eliminate standard_irq_callback_member wrapper method - Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes - Remove IRQ callbacks for some input lines that never cause interrupts - mb88xx, mcs48: Add IRQ callbacks for internal interrupts
* Monon / AX208 - load internal AX208 ROM in device [Peter Wilhelmson, David ↵ David Haywood2022-07-261-3/+9
| | | | Haywood] (#10131)
* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-2/+0
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* Use ioprocs classes instead of emu_file for device_nvram_interface's load ↵ AJR2022-02-271-7/+14
| | | | and save methods, and have these return false on I/O errors
* Remove fileio.h from emu.h AJR2022-02-111-1/+3
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* Research into thoop and squash 'refresh rate' protection [Victor Fernandez ↵ David Haywood2021-12-141-2/+31
| | | | | | (City Game), Peter Ferrie, David Haywood] (#8916) * Research into thoop and squash 'refrsh rate' protection [Victor Fernandez (City Game), Peter Ferrie, David Haywood] - prevents freeze when dying in stage 4 of Thunder Hoop, and bad text on continue in Squash
* wrinkles: added most of the sensors hap2021-09-171-10/+8
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* mcs51: add i8744 Patrick Mackinlay2021-07-231-0/+11
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* Add DS80C320, SAB80(C)515 and RUPI-44 disassemblers AJR2020-06-111-0/+33
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* consola_emt.cpp: Correct MCU type (nw) AJR2020-06-031-1/+17
| | | | i186.cpp: Add clock note (nw)
* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-251-22/+21
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* last batch of changes to make the ↵ Ivan Vangelista2020-05-211-2/+2
| | | | https://github.com/mamedev/mame/tree/devcb-no-space branch build. (nw)
* Finish midqslvr.cpp's documentation (nw) (#6340) Hydreigon2020-02-211-1/+4
| | | | | | | | * Finish midqslvr.cpp's documentation U4 component on the Diego board was initially incorrect as "109B" instead of "1098" (A/D converter that obviously controls steering and throttle). Arctic Thunder's I/O cpu turned out to be a 87C552 MCU which uses the same architecture as the predicted 87C51/2; both Intel MCS-51 based. If anyone wants this decapped, I will (most likely) be happy to donate my substitute I/O board though I would hate to waste a fully working pcb. * Because Arctic Thunder uses this MCU architecture
* sweeten most of the remaining arrays of delegates (nw) Vas Crabb2020-02-071-7/+4
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* (nw) removed every remaining AM_ macro I could find in comments, but one in ↵ Ivan Vangelista2019-10-101-1/+1
| | | | emu\memarray.h cause I didn't want to cause a full recompile for this (nw)
* mcs51: Disassembler update AJR2019-07-121-12/+23
| | | | | | | | | | | | | - Restore some 8052 SFR and bit names that were inadvertently omitted for more advanced models - Add a few more T2-related names - Add i8xc51fx and i8xc51gb disassemblers with additional SFR and bit names - Remove i80c51 from unidasm (actual differences from i8051 are not significant) Change device names from "Intel I8xxx" to "Intel 8xxx" (nw) scm_500: Identify CPU type as 80C51GB (specific differences obviously not emulated) (nw) unidasm: Realphabetize mips1 (nw)
* (nw) Clean up the mess on master Vas Crabb2019-03-261-0/+12
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-12/+0
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* mcs51: New version of old hack to break out of JB INT0/INT1 loops when ↵ AJR2019-03-221-0/+12
| | | | interrupt is triggered
* New skeleton device: Western Digital WD1007A ESDI hard disk controller [Al ↵ AJR2018-07-141-0/+6
| | | | Kossow]
* cidx628: Make this display something again AJR2018-06-221-0/+12
| | | | mcs51: Distinguish AT89C52/S52 device types (nw)
* mcs51.cpp: Consolidate internal address maps; remove P0 from ROMless ↵ AJR2018-06-131-20/+10
| | | | versions since it conflicts with external accesses on hardware (nw)
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-111-4/+4
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* mcs51.cpp: Eliminate atrocious hack for breaking out of INT0 polling loops (nw) AJR2018-05-091-4/+0
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* mcs51: Add more interrupt and timer registers to debug state AJR2018-05-011-0/+7
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* srcclean (nw) Vas Crabb2018-04-221-2/+2
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* maps: Finish devices/cpu (nw) Olivier Galibert2018-04-201-17/+21
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* mcs51: Safer way to propagate INT0 and INT1 inputs, which also need to be ↵ AJR2018-04-161-3/+3
| | | | active low (nw)
* vp415 updates, now actually starts proper testing loop, nw mooglyguy2018-04-151-1/+4
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* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-251-12/+12
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* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-14/+14
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* mcs51: Use callbacks for parallel ports (nw) AJR2018-02-271-71/+25
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