| Commit message (Collapse) | Author | Age | Files | Lines |
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(nw) This entails a major code reorganization just to keep the scale of it all halfway sane.
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Now athlon xp supports WrMem and RdMem bits in fixed range MTRRs
Accesses to the first megabyte can be directed to system memory (ram) or
memory-mapped-io (mmio) (the pci bus)
Above 1mb accesses below the top_mem MSR address ram the others mmio
At reset everyting is directed to mmio
Addresss spaces work in the following way
AS_PROGRAM is used for ram
AS_DATA is used for mmio
AS_OPCODES is used by the debugger disassembler and in memory views to
look at the memory contents from the point of view of the
microprocessor, including the cache
Also some class members have been added to the save state
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cacheflush() or cacheflush(0) writes back dirty cachelines to ram
cacheflush(1) also marks dirty cachelines as clean
cacheflush(2) or cacheflush(3) also invalidates the whole cache
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This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and
c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at
598cd5227223c3b04ca31f0dbc1981256d9ea3ff.
Before pushing, please check that what you're about to push is sane.
Check your local commit log and ensure there isn't anything out-of-place
before pushing to mainline. When things like this happen, it wastes
everyone's time. I really don't need this in a week when real work™ is
busting my balls and I'm behind where I want to be with preparing for
MAME release.
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This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing
changes made to 009cba4fb8102102168ef32870892438327f3705.
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.
A single 64K 2-way set associative cache
Used for both instructions and data
Enabled only for addresses in the first megabyte
Works always in writeback mode
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It is needed by the nforce motherboard bios that uses it to simulate a
block of ram at address d0000 before ddr ram is configured
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386sx cpus should work again
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-cpu/i386, lc8670: Removed MCFG macros. [Ryan Holtz]
-drivers/at, atpci, nforcepc, pcipc, svmu: Removed MACHINE_CONFIG macros. [Ryan Holtz]
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... and add placeholders for athlonxp msrs.
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enabled or disabled or the CS descriptor flags are changed
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-change order of include files at top of i386.cpp
-move some routines between i386.cpp and i386priv.h
-move part of x87ops.hxx into new file x87priv.h
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Now you only have to rename the hxx files to cpp and add the following
at the top of each one
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#include "emu.h"
#include "i386.h"
#include "i386priv.h"
#include "x87priv.h"
#include "cycles.h"
#include "debugger.h"
#include "debug/debugcpu.h"
#undef i386
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- add virtual methods opcode_cpuid opcode_rdmsr opcode_wrmsr
- default implementations in class i386_device log an error message
- derive Pentium MMX, Pentium II, Pentium III classes from
pentium_pro_device
- remove pentium_msr_* p6_msr_* piv_msr_* MSR_READ MSR_WRITE routines
and call virtual methods instead
- the routine pentium_rdmsr modifies the registers only if the msr is
valid
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Associated core changes (nw)
- Move definition of address_space_config from dimemory.cpp to emumem.cpp (declaration was already in emumem.h)
- Add getters for more members of address_space_config with future privatization in mind (nw)
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supported value in the eax register (nw)
Also set correct feature flags for athlon xp
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Also more stuff for athlon xp
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This is required by winxp setup.
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i386: Properly fix that detection check this time (nw)
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see a 386 as a 486
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cppcheck (#3753)
* Avoid some unintended undefined behavior. Spotted by cppcheck
* Some more undefined behavior caught by cppcheck (nw)
* fixup (nw)
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There are multiple issues with the current device callbacks:
* They always dispatch through a pointer-to-member
* Chained callbacks are a linked list so the branch unit can't predict the early
* There's a runtime decision made on the left/right shift direction
* There are runtime NULL checks on various objects
* Binding a lambda isn't practical
* Arbitrary transformations are not supported
* When chaining callbacks it isn't clear what the MCFG_DEVCB_ modifiers apply to
* It isn't possible to just append to a callback in derived configuration
* The macros need a magic, hidden local called devcb
* Moving code that uses the magic locals around is error-prone
* Writing the MCFG_ macros to make a device usable is a pain
* You can't discover applicable MCFG_ macros with intellisense
* Macros are not scoped
* Using an inappropriate macro isn't detected at compile time
* Lots of other things
This changeset overcomes the biggest obstacle to remving MCFG_ macros
altogether. Essentially, to allow a devcb to be configured, call
.bind() and expose the result (a bind target for the callback). Bind
target methods starting with "set" repace the current callbacks; methods
starting with "append" append to them. You can't reconfigure a callback
after resolving it. There's no need to use a macro matching the
handler signatures - use FUNC for everything. Current device is implied
if no tag/finder is supplied (no need for explicit this).
Lambdas are supported, and the memory space and offset are optional.
These kinds of things work:
* .read_cb().set([this] () { return something; });
* .read_cb().set([this] (offs_t offset) { return ~offset; });
* .write_cb().set([this] (offs_t offset, u8 data) { m_array[offset] = data; });
* .write_cb().set([this] (int state) { some_var = state; });
Arbitrary transforms are allowed, and they can modify offset/mask for example:
* .read_cb().set(FUNC(my_state::handler)).transform([] (u8 data) { return bitswap<4>(data, 1, 3, 0, 2); });
* .read_cb().set(m_dev, FUNC(some_device::member)).transform([] (offs_t &offset, u8 data) { offset ^= 3; return data; });
It's possible to stack arbitrary transforms, at the cost of compile
time (the whole transform stack gets inlined at compile time). Shifts
count as an arbitrary transform, but mask/exor does not.
Order of mask/shift/exor now matters. Modifications are applied in the
specified order. These are NOT EQUIVALENT:
* .read_cb().set(FUNC(my_state::handler)).mask(0x06).lshift(2);
* .read_cb().set(FUNC(my_state::handler)).lshift(2).mask(0x06);
The bit helper no longer reverses its behaviour for read callbacks, and
I/O ports are no longer aware of the field mask. Binding a read
callback to no-op is not supported - specify a constant. The GND and
VCC aliases have been removed intentionally - they're TTL-centric, and
were already being abused.
Other quirks have been preserved, including write logger only logging
when the data is non-zero (quite unhelpful in many of the cases where
it's used). Legacy syntax is still supported for simple cases, but will
be phased out. New devices should not have MCFG_ macros.
I don't think I've missed any fundamental issues, but if I've broken
something, let me know.
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- PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument.
- Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however.
- execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
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template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
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* Move around the debugger hooks to get a small but measurable performance increase
* Remove emucore from external tools
* Improve performance of DSP16 interpreter a little by generating six variants of execution loop
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mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
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* destaticify initializations (nw)
* fix this->set_screen (nw)
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d88_dsk: support bad crc (nw)
recreate columns copy protection (nw)
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