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path: root/src/devices/cpu/f2mc16/f2mc16.cpp
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* srcclean and cleanup Vas Crabb2024-10-271-1/+1
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* f2mc16: Created devices for the onboard analogue to digital converter, clock ↵ smf-2024-10-251-105/+191
| | | | | | | | | | | generator, interrupt controller/Extended intelligent I/O service, I/O port, Programmable Pulse Generator, reload timer and UART. CPU core exposes the RMW line for onboard devices. Log messages will contain the address of the start of the instruction, rather than the next byte the CPU is about to fetch. Added INT9/INT addr16 & INT addr24 software interrupt instructions. Fixed INCW @RWx & DECW @RWx instruction length Added missing fetch of immediate value in MOV @RWx + RW7, #imm8. Rewrote Tomy Prin-C keyboard handling and pen to use new onboard devices, substantially increasing the reload timer 0 frequency as it's now correctly waiting for 0x7530 underflows with reload = 0x37f at startup.
* Cleaned up various stuff. Vas Crabb2024-06-301-420/+420
| | | | | | | | | | * sony_news.xml: Added proper compatibility flags for different generations. * cpu/pic16x8x: This is very much a derivative work. * cpu/tms32025.cpp: Allow stack push/pop to be inlined. * tecmo/bombjack.cpp: Avoid needing to remove and replace devices in machine configuration. * Various other cleanup.
* f2mc16: Fix copy-paste mistakes AJR2024-06-251-2/+2
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* f2mc16: Flesh out CPU emulation AJR2024-06-251-4/+592
| | | | | | | | - Support INT #vct8, LSL A, R0 and FILSWI instructions - Support many more EA-type instruction modes - Prevent MOVS(W)I and FILS(W)I from clobbering RW0 if it lies within the destination range * mt80s: Add adequate amount of RAM to address map
* srcclean and manual cleanup. Vas Crabb2024-06-231-1/+1
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* cpu/f2mc16: Add additional instructions from Prin-C disassembly (#12443) qufb2024-06-041-0/+78
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* cpu/f2mc16: Removed ancient diagnostic printf. [R. Belmont] arbee2024-06-011-1/+1
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* cpu/f2mc16: Add and fix several instructions (#12427) qufb2024-06-011-148/+1583
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* Interrupt callback rationalization AJR2023-03-111-3/+4
| | | | | | | | | | | - Make CPUs pass interrupt return PC as a second argument to standard_irq_callback - Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command - Add messages to trace logs whenever interrupts are accepted - Attempt to step over interrupt routines for applicable debugger commands - Eliminate standard_irq_callback_member wrapper method - Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes - Remove IRQ callbacks for some input lines that never cause interrupts - mb88xx, mcs48: Add IRQ callbacks for internal interrupts
* -emu/rendersw.hxx: Fixed incorrect clipping of untextured rectangles. Vas Crabb2021-11-271-1/+1
| | | | | | -layouts: Started cleaning up fruit machine layouts to reduce bloat. -Fixed a few miscellaneous Coverity errors.
* srcclean for upcoming release Vas Crabb2021-08-221-1/+1
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* f2mc16: Updates AJR2021-07-281-14/+398
| | | | | | - Emulate many more opcodes - Add interrupt callback for debugger - Correct disassembly of MOVW io, A
* f2mc16: General cleanup AJR2021-07-281-340/+187
| | | | | | | | | - Add helper functions for increment and decrement operations and short direct banking - Rationalize use of temporary variables - Modify only lowest 8 bits of accumulator for XOR A, #imm8 - Perform a 16-bit rather than 8-bit write for MOVW @RLx + #disp8, A - Use SSB instead of USB for @RW3 or @RW7 addressing when S flag is set - Fix numerous flag calculations
* f2mc16: Updates and fixes AJR2021-07-261-29/+381
| | | | | | | | - Emulate various additional instructions and modes - Fix banking for direct addressing mode - Fix semantics of CLRB and number of bytes consumed by SETB - Fix mistake with calculating N and Z flags for SUB and CMP and writing incorrect result for SUB - Use INC(W)(L) A and DEC(W)(L) A pseudo-operations in disassembly
* f2mc16: Rewrite disassembler AJR2021-07-211-2/+2
| | | | - Fix bug in CPU core advancing PC by one too many bytes when executing ADDL A, RLn
* f2mc16: more opcodes, improved disassembly (nw) arbee2019-09-021-4/+225
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* f2mc16: fixed BBC branch offset, add savestates, cleanup variable usage in ↵ arbee2019-08-291-1/+23
| | | | utility functions [R. Belmont]
* f2mc16: More opcodes and more robust IRQ handling [R. Belmont] arbee2019-08-271-46/+276
| | | | mb9061x: Implemented timers 0 and 1, including external event counter mode [R. Belmont]
* f2mc16: checkpoint (nw) arbee2019-08-031-0/+68
| | | | princ now runs for a few seconds then enables Timer 0 (not yet implemented) and waits for it.
* f2mc16: First pass with working IRQs. [R. Belmont] arbee2019-07-241-9/+137
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* f2mc16: More opcodes and fixes. (nw) arbee2019-07-141-6/+224
| | | | princ now does what looks like a palette upload and waits for a timer interrupt.
* f2mc16: Many more opcodes supported, several bugfixes to both disassembly ↵ arbee2019-07-141-27/+438
| | | | and emulation (nw)
* f2mc16: Fix a few subtle mistakes (nw) AJR2019-07-101-2/+2
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* f2mc16: Checkpoint 2. princ runs far enough to jump into RAM where it ↵ arbee2019-07-101-6/+87
| | | | hasn't copied any code. (nw)
* f2mc16: Apply the same fix as last time (nw) AJR2019-07-091-2/+0
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* F2MC16: Checkpoint (nw) arbee2019-07-081-74/+730
| | | | Many more instructions are supported, including prefixes.
* f2mc16: Fix debug assert (nw) AJR2019-07-051-2/+0
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* F2MC-16: start executing instructions [R. Belmont] arbee2019-07-051-54/+648
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* f2mc16: more prep work (nw) arbee2019-07-041-2/+91
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* f2mc16: add MB90610A and MB90611A microcontrollers. [R. Belmont] arbee2019-07-031-3/+6
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* f2mc16: start populating the core (nw) arbee2019-07-031-8/+53
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* Preliminary Fujitsu F2MC-16 CPU core, currently disassembly only [R. Belmont] arbee2019-07-011-0/+78