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path: root/src/devices/cpu/drcbex86.cpp
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* Even more recompiler fixes: Vas Crabb2025-04-151-7/+12
| | | | | | | | | | | | | | | | | | | | * cpu/drcbearm64.cpp: Fixed ROLAND, ROLINS and CARRY clobbering the shift input when it's a a register. * cpu/drcbex86.cpp: Fixed DROLINS clobbering source in I0 and miscalculating flags when destination is I0. * cpu/uml.h: Removed assertion that's no longer valid. * cpu/drcbearm64.cpp: Added minimal operand swizzling to allow AND, OR and XOR to work without the simplifier. * cpu/drcbex64.cpp: Optimised shift operations slightly. * cpu/drcbec.cpp: Added stub implementations for TEST with no flag outputs to allow running with simplifier disabled. * cpu/drcbec.cpp: Implemented DREADM/DWRITEM with byte size access. * cpu/drcbec.cpp: Store pointer to address space directly in instruction stream. * cpu/drcbearm64.cpp: Removed some special cases for situations the simplifier deals with for ROLAND and ROLINS. * cpu/drcbec.cpp: Added some actual detail to error messages on encountering unexpected instructions.
* More recompiler fixes: Vas Crabb2025-04-121-15/+13
| | | | | | | | | | | * cpu/drcbec.cpp: Interpret index operand for load/store instructions as a signed value for consistency with other back-ends. * cpu/drcbec.cpp: Honour alignment rules when packing immediate values. * cpu/drcbex64.cpp: Don't special-case SEXT with an immediate source - the simplifier takes care of this. * cpu/drcbex86.cpp: Be explicit about preserving flags in load/store instructions. * docs: Added a couple more UML data movement instructions.
* Started moving UML instruction reference to main documentation, fixed more ↵ Vas Crabb2025-04-121-99/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | recompiler issues: * cpu/drcbearm64.cpp Interpret index operand for load and store instructions as a signed 32-bit value for consistency with x86-64. Moved code to interpret load and scale the index for integer load/store to a helper function to make it easier to update if it needs changes or fixes. * cpu/drcbearm64.cpp: Use and/orr to set carry flag directly rahter than using an intermediate register when both operands of a CARRY instruction are immediates. * cpu/drcbearm64.cpp: Fixed incorrect operand type assertion for FREAD. * cpu/drcbearm64.cpp: Use less verbose asmjit helper functions for shift operations and addressing modes. * cpu/drcbex64.cpp: Interpret index operand for floating point load/store as a signed 32-bit value for consistency with integer load/store. * cpu/drcbex64.cpp: Guard against any possibility of load and store instructions altering the flags. * cpu/drcbex64.cpp: Reduced copy/paste in floating point load/store instructions. * cpu/drcbex64.cpp: Cleaned up some casts between integer types with differing size and signedness. * docs: Added reference for UML flow control, data movement and emulated memory access instructions. * cpu/uml.cpp: Truncate immediates to size for a few more instructions. * cpu/uml.cpp: Added SPACE_OPCODES since it's a well-known address space now. * cpu/uml.cpp: Removed SCALE_DEFAULT. It's unimplemented by back-ends and unused by front-ends. * cpu/uml.h, cpu/drcumlsh.h: Less confusing names for parameters to read and write instruction generators. * cpu/drcbex86.cpp: Templated 64-bit multiplication helpers on the zero/sign flag source, cleaned up casting pointers to integers.
* cpu/drcbex86.cpp: Fixed flags for 64-bit multiply instructions. Vas Crabb2025-04-101-24/+22
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* Still more recompiler fixes: Vas Crabb2025-04-101-29/+10
| | | | | | | | | | | | | * cpu/uml.cpp: Fixed some cases where simplifying multiplication instructons incorrectly changed output flags. * cpu/drcbex64.cpp: Fixed some cases where a ROLC/RORC with zero shift count could incorrectly clear the carry flag. * cpu/drcbex86.cpp: Made 64-bit ROLC/RORC with zero bit count preserve the carry flag. * cpu/drcbec.cpp: Fixed FSMOV/FDMOV turning things that look like signalling NaNs into quiet NaNs on i686. * cpu/drcbex64.cpp: Greatly reduced copy/paste in the code generation for multiply instructions.
* -A few recompiler adjustments: Vas Crabb2025-04-091-2/+2
| | | | | | | | | | | * cpu/drcbec.cpp: Don't clear carry flag on a zero-bit rotate through carry. * cpu/drcbex86.cpp: Don't clear carry flag on a word-sized zero-bit rotate through carry (64-bit case is more involved). * cpu/drcbex64.cpp: Removed code for another special case of ROLAND that the simplifier deals with. -konami/ksys573.cpp, bus/pccard/linflash.cpp: Corrected "Gacha Gachamp".
* -cpu/e132xs: Got rid of "Mission Craft flags" compile time option. Vas Crabb2025-04-041-235/+222
| | | | | | | | | | | | | | | | | | | | | | | * Assume ROL sets the V and C flags the same way as SHL and MOVI clears the V flag. -cpu/drcbex64.cpp: Optimise SUB x,0,y to a NEG instruction (gets down to one instruction from two or three a lot of the time). This had been a TODO comment for ages. -cpu/drcbex86.cpp: Got rid of unnecessary std::function use. This substantially reduces the code size and reduces allocations during code generation. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of the intermediate tables in favour of bit switch statements. This improves startup time, reduces code size, and gives the compiler more optimisation opportunities. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of asmjit namespace qualifiers left over from when the class declarations were in headers and hence outside the scope of the using namespace statements.
* cpu/e132xs, cpu/drcbex64.cpp: Recompiler fixes and optimisations: Vas Crabb2025-03-211-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs.cpp: Refactored code generation to improve performance and fixed some issues: * Moved a considerable amound of logic from execution time to code generation time. * Fixed some cases where add/subtract carry was being interpreted incorrectly. * Fixed a case where a load double intruction was incorrectly writing the same register twice. * Use UML flags to generate condition codes for addition/subtraction. * Use UML carry flag for carry-/borrow-in. * Reduced UML register pressure (improves performance for hosts with fewer callee-saved CPU registers). * Moved more logic to helper functions to simplify maintenance. cpu/drcbex64.cpp: Fixed upper bits of UML registers being cleared when used as address offset for LOAD/STORE. cpu/drcbex64.cpp: Don't do expensive zero/sign flag update for shift operations if only carry flag will be used. cpu/drcbex64.cpp: Reduced copy/paste in READ[M]/WRITE[M] generators.
* -cpu/drcbe*.cpp: Print an error message and abort when running off the end ↵ Vas Crabb2025-03-181-4/+46
| | | | | | | | | of a generated code block. -cpu/drcbearm64.cpp: Don't emit code for UML NOP - the simplifier litters the code with these for elided operations. -frontend/mame/clifront.cpp: Added newline at end of -version output.
* cpu/drcbearm64.cpp: General cleanup, no functional changes. Vas Crabb2025-03-161-5/+5
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* cpu: Moved DRC backend declarations out of headers and into anonymous ↵ Vas Crabb2025-02-221-190/+486
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* cpu: Got rid of the rest of the static member function trampolines. Vas Crabb2025-02-041-17/+35
| | | | | | | | | | | cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed static trampoline fallbacks for get map variable value and debugger instrcution hook functions. cpu/drcbex86.cpp: Removed static trampolines for get map variable value and debugger instrcution hook functions. cpu/drcbex64.cpp: Corrected stack diagram in comment.
* cpu/drcbeut.cpp: Removed static address space accessors. Vas Crabb2025-02-031-0/+1
| | | | | | cpu/drcbex64.cpp: Removed fallback to static address space accessors. cpu/drcbex86.cpp: Fixed regression in FWRITE.
* Cleanup: Vas Crabb2025-02-031-99/+230
| | | | | | | | | | | | | | | | | cpu/drcbex86.cpp: Don't use static address space accessors. This gives a big performance improvement. cpu/drcbeut.cpp: Made failure to resolve address space accessors fatal. cpu/drcbearm64.cpp: Removed fallback to static address space accessors. cpu/mips3/mibs3.cpp: Removed static address space accessors. All they were doing was hurting performance. cpu/drcbex64.cpp: Don't use goofy X64_WINDOWS_ABI macro, just check _WIN32. The only other environment that uses the Windows calling convention is (U)EFI, and we can move feature detection to util/abi.h if we ever need to care about it.
* cpu/drcbe*.cpp: Added write byte with explicit mask. Vas Crabb2025-01-151-2/+9
| | | | | This wasn't added to the DRC implementations when it was added to the address space classes.
* -cpu/drcbex64.cpp: Be nicer to the return address predictor. Vas Crabb2025-01-151-22/+22
| | | | | | -cpu/drcbex86.cpp: Give hints to use short displacements for jumps to local unbound labels. -util/mfpresolve.h: Use references for some things that must not be null pointers.
* DRC: Calculate negative and zero flags for shifts/rotates with a zero shift ↵ 9871238791132025-01-141-93/+191
| | | | | | count. (#13232) * cpu/drcbec.cpp, cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Calculate NZ flags for shifts/rotates by 0 bits. * cpu/drcbex86.cpp: Fixed flag calculation for 64-bit multiplication when result is zero.
* -util/mfpresolve.cpp: Moved member function resolution code to a common ↵ Vas Crabb2025-01-141-42/+66
| | | | | | | | | | location. * util/delegate.cpp, cpu/drcbex64.cpp, cpu/drcbearm64.cpp: Use common member function resolution code. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Moved some stuff to anonymous namespaces. -cpu/drcbex64.cpp, cpu/drcbex86.cpp: Defer allocating labels if they aren't always needed.
* cpu/drcbex86.cpp: Sorry, I’m an idiot, didn't stage this line. Vas Crabb2025-01-131-0/+1
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* osd: Added helper for getting CPU cache line size. Vas Crabb2025-01-131-2/+14
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* Fixed more recompiler backend issues: (#13132) 9871238791132024-12-301-13/+19
| | | | | | * cpu/drcbex86.cpp: Clear top half of iregs on loads to I0-I3, fix LOADS sign extension, and fixed FLOAD/FSTORE data size. * cpu/drcbex64.cpp: Use appropriate register size for LOAD. * cpu/drcbec.cpp: Fix parameter sizes for READM/WRITEM, and clear upper half of registers after 32-bit operations. * cpu/uml.cpp: Fixed definition for FSREAD/FSWRITE and FDREAD/FDWRITE, and fixed READM/WRITEM simplification.
* Fixed various recompiler issues and added functionality: (#13108) 9871238791132024-12-291-360/+861
| | | | | | | | | | | | * cpu/uml.cpp: Added BREAK, SETFLGS, MULSLW and MULULW opcodes. * cpu/uml.cpp: Limit range of immediate shift count arguments for consistency. * cpu/uml.cpp: Fix simplification of multiplication and division operations. * cpu/drcbec.cpp: Added more methods of accessing OP_CARRY. * cpu/drcbec.cpp: Fixed flag calculation for BSWAP and MULS opcodes. * cpu/drcbec.cpp: Made calculation for shift and rotation opcodes consistent. * cpu/drcbec.cpp: Return mapvar register ID instead of value for mapvars. * cpu/drcbex64.cpp, cpu/drcbex86.cpp: Fixed bugs in various opcodes to make them behave like the C backend. * cpu/drcbex64.cpp: Fixed SAVE, RESTORE and SETFMOD. * cpu/powerpc: Implement MULLWx and MULLWOx using the new MULSLW opcode.
* drcbex64,drcbex86: avoid deprecated functions Patrick Mackinlay2024-04-121-1/+1
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* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+1
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* asmjit: mame integration Patrick Mackinlay2022-02-131-32/+32
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* Eliminate ARRAY_LENGTH template in favor of C++17's std::size AJR2021-02-141-8/+8
| | | | | | | | | | * osdcomm.h: Move definition of EQUIVALENT_ARRAY to coretmpl.h * sharc.cpp, gt64xxx.cpp, ym2413.cpp, gb_lcd.cpp, snes_ppu.cpp: Use STRUCT_MEMBER for save state registration * gio/newport.cpp, megadrive/svp.cpp, nes_ctrl/bcbattle.cpp, arm7.cpp, tms9995.cpp, pckeybrd.cpp, sa1110.cpp, sa1111.cpp, jangou_blitter.cpp, vic4567.cpp: Use std::fill(_n) instead of memset * emucore.h: Remove obsolete typedef
* cpu: Slightly reduce the number of page protection state changes Vas Crabb2021-01-061-0/+1
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* cpu/drcbex64.cpp, cpu/drcbex86.cpp: Don't leak using namespace from the header. Vas Crabb2020-11-291-2/+11
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* Remove x86emit.h AJR2020-07-101-1/+0
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* drcbex86: implemented asmjit emitter Patrick Mackinlay2020-07-101-2615/+2024
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* drcbe: fixed logging problem Patrick Mackinlay2020-07-101-4/+4
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* use C++ library includes (nw) firewave2020-01-221-1/+1
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* Reshuffle some stuff: Vas Crabb2018-03-281-4/+7
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* drcbex86: Fix remainder clobbering quotient, thanks smf, nw mooglyguy2017-12-311-2/+4
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* drcbex86: Fixed an 'optimization' which was actually a random bug inducer, nw mooglyguy2017-12-311-6/+2
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* Introduce u8/u16/u32/u64/s8/s16/s32/s64 Vas Crabb2016-11-191-2/+2
| | | | | | | | | | | | * New abbreviated types are in osd and util namespaces, and also in global namespace for things that #include "emu.h" * Get rid of import of cstdint types to global namespace (C99 does this anyway) * Remove the cstdint types from everything in emu * Get rid of U64/S64 macros * Fix a bug in dps16 caused by incorrect use of macro * Fix debugcon not checking for "do " prefix case-insensitively * Fix a lot of messed up tabulation * More constexpr * Fix up many __names
* Do not use FUNC in delegate where applicable (nw) Miodrag Milanovic2016-11-061-2/+2
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* converted lot of TRUE/FALSE to real boolean and updated types (nw) Miodrag Milanovic2016-10-221-4/+4
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* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-221-177/+177
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* use standard types uintptr_t, char16_t and char32_t instead of FPTR, ↵ Miodrag Milanovic2016-10-221-43/+43
| | | | utf16_char, unicode_char (nw)
* fix android x86 and x64 full build Jeffrey Clark2016-06-301-0/+12
| | | | * abuse namespace as done in 59f15d6819508188c184fc7525606e712ac4a73b
* Cleanups and version bumpmame0174 Miodrag Milanovic2016-05-251-16/+16
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* UML: Added TZCNT instruction (Trailing Zero Count) [Ville Linde] Ville Linde2016-05-201-0/+46
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* Cleanups and version bumpmame0173 Miodrag Milanovic2016-04-271-20/+20
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* Revert software-installed slot/image options when changing software AJR2016-04-041-0/+1
| | | | | - Remove emu.h's stealth include of emuopts.h through mconfig.h; reduce dependency on emuopts.h in other headers and source files. - MCFG_CPU_FORCE_NO_DRC is now a CPU configuration parameter rather than a global one; it still works to override the -drc option setting.
* UML: Added FCOPYI and ICOPYF instructions to pass raw data between integer ↵ Ville Linde2016-04-031-1/+102
| | | | and floating-point registers. [Ville Linde]
* Replace strformat, strprintf and strcatprintf with type-safe steam_format ↵ Vas Crabb2016-02-281-1/+1
| | | | | | | | | and string_format Update MAME to use new function Instantiate ODR-used static constant members Make some of the UI code more localisable Remove use of retired functions in tools
* Return std::string objects by value rather than pass by reference AJR2016-01-101-4/+2
| | | | | | - strprintf is unaltered, but strformat now takes one fewer argument - state_string_export still fills a buffer, but has been made const - get_default_card_software now takes no arguments but returns a string
* Modernize x86log.h and x86log.cpp: Vittorio Romeo2015-12-211-1/+1
| | | | | | | | | | | * Use variadic template functions instead of `va_list` * In `x86log_mark_as_data` and `x86log_printf` * Add `noexcept` where appropriate/safe * Use `constexpr std::size_t` instead of macros for constants * Nest `nullptr` check to prevent useless check, add assertion * In `x86log_printf` * Move definitions of `log_comment`, `data_range_t`, `x86log_context` to `x86_log.h` from `x86_log.cpp` * Adapt usages of `x86log_printf` in `drcbex64.cpp` and `drcbex86.cpp`
* clang-modernize part 6 Miodrag Milanovic2015-12-041-2/+2
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