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* fix various bitwise/logical warnings Patrick Mackinlay2025-04-251-1/+1
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* cpu/drcbex64.cpp: Always keep UML floating point registers in memory for ↵ Vas Crabb2025-04-171-88/+75
| | | | | | | | | | | | | SysV ABI. This was changed in 822c3b4232b0a66ce92bba7a24084678004af444 but it never worked for multiple reasons: * The comment mentions saving around CALLC, but there is no code to save and restore around CALLC, DEBUG and RECOVER, all of which can clobber callee-saved registers. * Numerous opcode handlers assume XMM0 and XMM1 can be used as scratch registers, but this change mapped them to UML F0 and F1. This resulted in F0 and F1 getting clobbered by many UML instructions.
* A couple of recompiler improvements involving the carry flag: Vas Crabb2025-04-161-15/+8
| | | | | | | | | * cpu/drcbearm64.cpp: Optimised setting up carry flag for ADDC and SUBB. There's no need to preserve the NZV flags so a two-instruction sequence can be used. * cpu/drcbex64.cpp: Simplified code generation for CARRY. I have no idea why it was preserving RAX at all - it always uses RAX as a scratch register.
* Even more recompiler fixes: Vas Crabb2025-04-151-22/+13
| | | | | | | | | | | | | | | | | | | | * cpu/drcbearm64.cpp: Fixed ROLAND, ROLINS and CARRY clobbering the shift input when it's a a register. * cpu/drcbex86.cpp: Fixed DROLINS clobbering source in I0 and miscalculating flags when destination is I0. * cpu/uml.h: Removed assertion that's no longer valid. * cpu/drcbearm64.cpp: Added minimal operand swizzling to allow AND, OR and XOR to work without the simplifier. * cpu/drcbex64.cpp: Optimised shift operations slightly. * cpu/drcbec.cpp: Added stub implementations for TEST with no flag outputs to allow running with simplifier disabled. * cpu/drcbec.cpp: Implemented DREADM/DWRITEM with byte size access. * cpu/drcbec.cpp: Store pointer to address space directly in instruction stream. * cpu/drcbearm64.cpp: Removed some special cases for situations the simplifier deals with for ROLAND and ROLINS. * cpu/drcbec.cpp: Added some actual detail to error messages on encountering unexpected instructions.
* cpu/drcbex64.cpp: Fixed another bug uncovered after fixing a bug in the DRC ↵ Vas Crabb2025-04-131-2/+1
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* More recompiler fixes: Vas Crabb2025-04-121-29/+13
| | | | | | | | | | | * cpu/drcbec.cpp: Interpret index operand for load/store instructions as a signed value for consistency with other back-ends. * cpu/drcbec.cpp: Honour alignment rules when packing immediate values. * cpu/drcbex64.cpp: Don't special-case SEXT with an immediate source - the simplifier takes care of this. * cpu/drcbex86.cpp: Be explicit about preserving flags in load/store instructions. * docs: Added a couple more UML data movement instructions.
* Started moving UML instruction reference to main documentation, fixed more ↵ Vas Crabb2025-04-121-70/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | recompiler issues: * cpu/drcbearm64.cpp Interpret index operand for load and store instructions as a signed 32-bit value for consistency with x86-64. Moved code to interpret load and scale the index for integer load/store to a helper function to make it easier to update if it needs changes or fixes. * cpu/drcbearm64.cpp: Use and/orr to set carry flag directly rahter than using an intermediate register when both operands of a CARRY instruction are immediates. * cpu/drcbearm64.cpp: Fixed incorrect operand type assertion for FREAD. * cpu/drcbearm64.cpp: Use less verbose asmjit helper functions for shift operations and addressing modes. * cpu/drcbex64.cpp: Interpret index operand for floating point load/store as a signed 32-bit value for consistency with integer load/store. * cpu/drcbex64.cpp: Guard against any possibility of load and store instructions altering the flags. * cpu/drcbex64.cpp: Reduced copy/paste in floating point load/store instructions. * cpu/drcbex64.cpp: Cleaned up some casts between integer types with differing size and signedness. * docs: Added reference for UML flow control, data movement and emulated memory access instructions. * cpu/uml.cpp: Truncate immediates to size for a few more instructions. * cpu/uml.cpp: Added SPACE_OPCODES since it's a well-known address space now. * cpu/uml.cpp: Removed SCALE_DEFAULT. It's unimplemented by back-ends and unused by front-ends. * cpu/uml.h, cpu/drcumlsh.h: Less confusing names for parameters to read and write instruction generators. * cpu/drcbex86.cpp: Templated 64-bit multiplication helpers on the zero/sign flag source, cleaned up casting pointers to integers.
* Still more recompiler fixes: Vas Crabb2025-04-101-247/+85
| | | | | | | | | | | | | * cpu/uml.cpp: Fixed some cases where simplifying multiplication instructons incorrectly changed output flags. * cpu/drcbex64.cpp: Fixed some cases where a ROLC/RORC with zero shift count could incorrectly clear the carry flag. * cpu/drcbex86.cpp: Made 64-bit ROLC/RORC with zero bit count preserve the carry flag. * cpu/drcbec.cpp: Fixed FSMOV/FDMOV turning things that look like signalling NaNs into quiet NaNs on i686. * cpu/drcbex64.cpp: Greatly reduced copy/paste in the code generation for multiply instructions.
* cpu/uml.cpp: Fixed assertion failures when simplification reduces operand count. Vas Crabb2025-04-091-88/+13
| | | | | | * Also added a few more simplifications. * cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed more speical cases for things the simplifier deals with.
* -A few recompiler adjustments: Vas Crabb2025-04-091-60/+26
| | | | | | | | | | | * cpu/drcbec.cpp: Don't clear carry flag on a zero-bit rotate through carry. * cpu/drcbex86.cpp: Don't clear carry flag on a word-sized zero-bit rotate through carry (64-bit case is more involved). * cpu/drcbex64.cpp: Removed code for another special case of ROLAND that the simplifier deals with. -konami/ksys573.cpp, bus/pccard/linflash.cpp: Corrected "Gacha Gachamp".
* -cpu/uml.cpp: Rewrote the UML simplification code. Vas Crabb2025-04-081-218/+153
| | | | | | | | | | | | | | | | | | | * Fixed many cases that could cause the upper bits of a register not to cleared following a 32-bit operation. * Added more simplifications. * Allow many simplifications when flag updates are requested. * Fixed various bits of unreachable code. * cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed code for special-casing some situations the simplifier can now take care of consistently. -cpu/drcbex64.cpp: Fixed a bug causing some shifts to be treated as a no-op when the destination and source are not the same. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Added a special case for comparing something to itself. -cpu/e132xs: Use the CARRY instruction rather than a right shift to set up carry in.
* -cpu/e132xs: Got rid of "Mission Craft flags" compile time option. Vas Crabb2025-04-041-226/+221
| | | | | | | | | | | | | | | | | | | | | | | * Assume ROL sets the V and C flags the same way as SHL and MOVI clears the V flag. -cpu/drcbex64.cpp: Optimise SUB x,0,y to a NEG instruction (gets down to one instruction from two or three a lot of the time). This had been a TODO comment for ages. -cpu/drcbex86.cpp: Got rid of unnecessary std::function use. This substantially reduces the code size and reduces allocations during code generation. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of the intermediate tables in favour of bit switch statements. This improves startup time, reduces code size, and gives the compiler more optimisation opportunities. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of asmjit namespace qualifiers left over from when the class declarations were in headers and hence outside the scope of the using namespace statements.
* -cpu/e132xs: Miscellaneous fixes/optimisation: Vas Crabb2025-04-031-15/+28
| | | | | | | | | | | | | | | | | | | | | * Fixed behaviour of delayed branches, trace exceptions, and saved PC calculation for error exceptions in delay slots for the interpreter. All instructions in delay slots, branching instructions that can raise exceptions and tracing shoud now (mis)behave properly for the interpreter, including things the manual says you shouldn't do. * Fixed and optimised flag updates for left shifts for the recompiler. * Optimised ROL instruction for the recompiler and made flag calculation equivalent to the interpreter both with and without the "Missioncraft flags" compile-time option. * Only block interrupts for one instruction following a delayed branch. * Optimised the SOFTWARE instruction a little for the recompiler. * Added more SDRAM configuration logging and cleaned up code a bit. -cpu/drcbearm64.cpp: Apply the change from 7efe37938f9dd6a366e to OR and XOR instructions as well, and fix some cases where a 32-bit logical operation would fail to clear the upper bits of a register. -cpu/drcbex64.cpp: Avoid more conditional branches on conditional MOV.
* -cpu/e132xs: General cleanup and usability improvements: Vas Crabb2025-03-291-13/+16
| | | | | | | | | | | | | | | | | | | | | | | * Aligned the operand field in disassembly. * Calculate results of immediate values against the PC to make position-independent code easier to read without constantly using a calculator (e.g. this shows destinations for call Rd, PC, imm). * Added more symbols to the UML helper to make logged generated code more readable. * Made single-instruction-per-sequence mode configurable rather than a compile-time option. * Got rid of a criminal amount of copy/paste in the disassembler, and got rid of all the deprecated strcpy calls. * Got rid of some duplicated constants, changed some constants from macros to enumerated values or constexpr globals. * Reduced the amound of stuff in headers that doesn't need to be there. -cpu/drcbex64.cpp: Don't construct std::function objects during code generation - they require allocation. -eolith/eolith.cpp: Turned single-instruction-per-sequence mode on for now until someone works out why turning it off causes Raccoon World to generate so much code it's unplayably slow.
* -cpu/e132xs: Fixes and optimisations: Vas Crabb2025-03-261-4/+17
| | | | | | | | | | | | | | | | | | | * Fixed XM (index move) instructions failing to update the destination register on range error for interpreter and recompiler. * Fixed double-word stores when the source indicates SR (both stored words are zero) for interpreter and recompiler. * Fixed recompiler failing to set ILC and P on range error and frame error exceptions. * Optimised recompiled code for word size shifts. * Pushed more recompiler logic from run-time to code generation time and simplified delay slot PC check and trace check logic. * Use MOV rather than LOAD where possible in recompiler to improve code generation performance and symbolic memory locatin names in disassembled UML. * Updated TODO list in header comment, reduced copy/paste some more. -cpu/drcbex64.cpp: Avoid some more unnecessary register copies for ROLAND.
* cpu/e132xs, cpu/drcbex64.cpp: More fixes and optimisation: Vas Crabb2025-03-251-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs: Implemented supervisor and trace modes as recompiler modes. This eliminates or simplifies a lot of run-time checks. In particular, the trace checks on every instruction are not generated when not tracing, and simplified to just checking the P bit when tracing. cpu/e132xs: Optimised code generation for RET, avoid a redundant load when checking for an overflow trap, use the exception parameter for exception codes rather than generating one function for each possible code. Also simplified interpreter code for RET. cpu/e132xs: Implemented SUMS for the recompiler. cpu/e132xs: Implemented privilege check for setting L (interrupt lockout) for recompiler. Not implemented for interpreter. cpu/e132xs: Partially fixed tracing. P flag should be set by all instructions except RET. Trace exceptions are not triggered for branches when using the recompiler. cpu/e132xs: Fixed ILC being set incorrectly for RET. cpu/drcbex64.cpp: Avoid unnecessary expensive operations when a shift operation request the zero and/or sign flags but not the carry flag.
* cpu/e132xs: More recompiler fixes: Vas Crabb2025-03-221-1/+1
| | | | | | | | | * Cleaned up and commented code for generating an exception, reducing about nine memory accesses to update SR to two. * Implemented NEGS, and fixed ADDS and SUBS not setting excption handler address. * Optimised code to update Z flag on logic operations to avoid branches. * Reduced copy/paste a bit more.
* cpu/e132xs, cpu/drcbex64.cpp: Recompiler fixes and optimisations: Vas Crabb2025-03-211-247/+161
| | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs.cpp: Refactored code generation to improve performance and fixed some issues: * Moved a considerable amound of logic from execution time to code generation time. * Fixed some cases where add/subtract carry was being interpreted incorrectly. * Fixed a case where a load double intruction was incorrectly writing the same register twice. * Use UML flags to generate condition codes for addition/subtraction. * Use UML carry flag for carry-/borrow-in. * Reduced UML register pressure (improves performance for hosts with fewer callee-saved CPU registers). * Moved more logic to helper functions to simplify maintenance. cpu/drcbex64.cpp: Fixed upper bits of UML registers being cleared when used as address offset for LOAD/STORE. cpu/drcbex64.cpp: Don't do expensive zero/sign flag update for shift operations if only carry flag will be used. cpu/drcbex64.cpp: Reduced copy/paste in READ[M]/WRITE[M] generators.
* Some relatively simple recompiler optimisations: Vas Crabb2025-03-201-22/+42
| | | | | | | | | | | | | | | | cpu/drcbex64.cpp: Avoid a lot of unnecessary flag manipulation on shift/rotate operations. Don't calculate flags when not requested. Don't preserve carry in for operations that don't use it as an input. cpu/drcbex64.cpp: Avoid loading CL when ECX can be used. Loading CL doesn't clear the upper bits, so it depends on the previous value of RCX, causing pipeline dependencies. Loading ECX can grab a fresh rename register. cpu/drcbearm64.cpp: Attempt more optimisation on one more load immediate operation. cpu/e132xs: Get rid of a redundant TEST - ROLAND can set the Z flag.
* -More DRC fixes/improvements: Vas Crabb2025-03-201-224/+591
| | | | | | | | | | | | | | | | | | | * cpu/uml.cpp: Handle some more cases where ROLAND can be turned into AND in the simplifier. * cpu/drcbearm.cpp, cpu/drcbex64.cpp: Fixed a number of cases where 4-byte operations wouldn't clear the upper half of the destination (there are plenty more of these caused by the simplifier that will be harder to fix). * cpu/drcbearm64.cpp: Fixed some cases where a conditional MOV could unexpectedly clear the upper bits of the destination. * cpu/drcbex64.cpp: Improved code generation for various arithmetic and logical operations. More AND/OR/XOR/ADD/ADDC operand combinations are optimised. Special cases of ROLAND/ROLINS are optimised. * cpu/drcbex64.cpp: Don't treat operands to FADD/FMUL as commutative. This isn't true when one is a NaN. -cpu/e132xs: Use osd_printf_error for diagnositc output, and make more local variables const.
* -cpu/drcbe*.cpp: Print an error message and abort when running off the end ↵ Vas Crabb2025-03-181-16/+63
| | | | | | | | | of a generated code block. -cpu/drcbearm64.cpp: Don't emit code for UML NOP - the simplifier litters the code with these for elided operations. -frontend/mame/clifront.cpp: Added newline at end of -version output.
* cpu/drcbearm64.cpp: General cleanup, no functional changes. Vas Crabb2025-03-161-5/+5
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* -cpu/drcbex64.cpp: Align HANDLE entry point to 16-byte boundary. Vas Crabb2025-03-121-4/+6
| | | | -cpu/mips/mips3drc.cpp: Don't start a new block for every callable helper.
* -seta/rmhaihai.cpp: Added Real Mahjong Haihai DIP switch locations from manual. Vas Crabb2025-03-071-1/+0
| | | | -cpu/drcbearm64.cpp: Added some glue for supporting memory access optimisations.
* cpu: Moved DRC backend declarations out of headers and into anonymous ↵ Vas Crabb2025-02-221-3/+293
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* -cpu/drcbeut.cpp: Don't allocate from the DRC cache unnecessarily. Vas Crabb2025-02-121-7/+7
| | | | | | | | | | | | | | * Allocate label helpers and map variable changes from the process heap. They're only used during code generation and have no business being in the DRC cache. * Keep map variable changes contiguous, don't deallocate label helpers and map variable changes on completing a block. * Got rid of simple_list, more const, tidied a little. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Shuffled RECOVER instructions a bit to be nicer to the CPU's scheduler. -bus/hp_dio/hp_dio.cpp: Removed vestigial simple_list support code.
* cpu/drcbex64.cpp: Slightly optimised some degenerate cases for memory accesses. Vas Crabb2025-02-081-69/+236
| | | | | This gives a very small improvement for systems with 32 address lines and no global address mask (e.g. pmac6100, sf2049 or coolmini).
* -cpu/drcbex64.cpp: Fixed handling of address map global mask. Vas Crabb2025-02-061-4/+4
| | | | | | | | * Fixed Final Furlong failing to boot. -util/mfpresolve.cpp, emu/emumem_aspace.cpp: Moved some member function pointer manipulation stuff into the library. Gives another slight reduction in the size of libemu.
* cpu/drcbearm64.cpp: Added scaffolding for directly dispatching memory accesses. Vas Crabb2025-02-051-13/+15
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* -cpu/drcbex64.cpp: Directly dispatch memory accesses no larger than native ↵ Vas Crabb2025-02-051-69/+439
| | | | | | width to specific handlers. (#13325) emu/emumem_aspace.cpp: Got rid of static accessors structure, added a helper for obtaining info for dispatching specific accessors.
* cpu: Got rid of the rest of the static member function trampolines. Vas Crabb2025-02-041-31/+44
| | | | | | | | | | | cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed static trampoline fallbacks for get map variable value and debugger instrcution hook functions. cpu/drcbex86.cpp: Removed static trampolines for get map variable value and debugger instrcution hook functions. cpu/drcbex64.cpp: Corrected stack diagram in comment.
* cpu/drcbeut.cpp: Removed static address space accessors. Vas Crabb2025-02-031-209/+76
| | | | | | cpu/drcbex64.cpp: Removed fallback to static address space accessors. cpu/drcbex86.cpp: Fixed regression in FWRITE.
* Cleanup: Vas Crabb2025-02-031-4/+4
| | | | | | | | | | | | | | | | | cpu/drcbex86.cpp: Don't use static address space accessors. This gives a big performance improvement. cpu/drcbeut.cpp: Made failure to resolve address space accessors fatal. cpu/drcbearm64.cpp: Removed fallback to static address space accessors. cpu/mips3/mibs3.cpp: Removed static address space accessors. All they were doing was hurting performance. cpu/drcbex64.cpp: Don't use goofy X64_WINDOWS_ABI macro, just check _WIN32. The only other environment that uses the Windows calling convention is (U)EFI, and we can move feature detection to util/abi.h if we ever need to care about it.
* Slight DRC code generation optimisation: Vas Crabb2025-01-171-1/+7
| | | | | | | | | | | | | | | cpu/drcbex64.cpp: Consider a RIP-relative LEA for generating 64-bit values (7-byte instruction versus a 10-byte MOV instruction). Seems to work pretty well for heap pointers. cpu/drcbearm64.cpp: Changed the near cache base pointer offset from 0x80 to 0x100. The value 0x80 was copied from the x86-64 back-end where it was choses to allow an 8-bit signed displacement to reach as much of the top of the near cache as possible. However, AArch64 use 9-bit signed displacements, so a quarter of the range was being wasted. cpu/drcbearm64.cpp: Consider an adrp/add sequence for generating immediate values as well as memory references.
* DRC cleanup and minor optimisation: [Windy Fairy, Vas Crabb] Vas Crabb2025-01-161-53/+41
| | | | | | | | | | | | | | | * Build all native back-ends if any native back-end is enabled so errors caused by changing interfaces can be found faster. * cpu/drcbeut.cpp: Moved resolved member function stuff to a place where it can be shared by back-ends. * cpu/drcbearm64.cpp: Use ubfx instruction to extract unordered flag. * cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Bypass trampolines when calling get map variable value and debugger instruction hook functions. * cpu/drcbearm64.cpp: Moved some internal helpers that don't need to be members to anonymous namespace. * cpu/drcbearm64.cpp: Added a comment with some info to help when debugging generated code. * cpu/drcbec.cpp: Put code in the drc namespace.
* cpu/drcbe*.cpp: Added write byte with explicit mask. Vas Crabb2025-01-151-6/+34
| | | | | This wasn't added to the DRC implementations when it was added to the address space classes.
* -cpu/drcbex64.cpp: Be nicer to the return address predictor. Vas Crabb2025-01-151-24/+24
| | | | | | -cpu/drcbex86.cpp: Give hints to use short displacements for jumps to local unbound labels. -util/mfpresolve.h: Use references for some things that must not be null pointers.
* DRC: Calculate negative and zero flags for shifts/rotates with a zero shift ↵ 9871238791132025-01-141-19/+21
| | | | | | count. (#13232) * cpu/drcbec.cpp, cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Calculate NZ flags for shifts/rotates by 0 bits. * cpu/drcbex86.cpp: Fixed flag calculation for 64-bit multiplication when result is zero.
* -util/mfpresolve.cpp: Moved member function resolution code to a common ↵ Vas Crabb2025-01-141-103/+72
| | | | | | | | | | location. * util/delegate.cpp, cpu/drcbex64.cpp, cpu/drcbearm64.cpp: Use common member function resolution code. -cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Moved some stuff to anonymous namespaces. -cpu/drcbex64.cpp, cpu/drcbex86.cpp: Defer allocating labels if they aren't always needed.
* cpu/drcbearm64.cpp: Added a 64-bit ARMv8 (AArch64) DRC back-end. (#13162) 9871238791132025-01-141-1/+3
| | | | | * cpu/uml.cpp: Removed unused vector type. * 3rdparty/asmjit: Update asmjit to latest upstream. * cpu/drcbex64.cpp: Fixed crash with LOG_HASHJMPS enabled (stack needs to be 16-byte aligned before calling debug_log_hashjmp_fail).
* osd: Added helper for getting CPU cache line size. Vas Crabb2025-01-131-2/+15
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* Fixed more recompiler backend issues: (#13132) 9871238791132024-12-301-13/+10
| | | | | | * cpu/drcbex86.cpp: Clear top half of iregs on loads to I0-I3, fix LOADS sign extension, and fixed FLOAD/FSTORE data size. * cpu/drcbex64.cpp: Use appropriate register size for LOAD. * cpu/drcbec.cpp: Fix parameter sizes for READM/WRITEM, and clear upper half of registers after 32-bit operations. * cpu/uml.cpp: Fixed definition for FSREAD/FSWRITE and FDREAD/FDWRITE, and fixed READM/WRITEM simplification.
* Fixed various recompiler issues and added functionality: (#13108) 9871238791132024-12-291-400/+615
| | | | | | | | | | | | * cpu/uml.cpp: Added BREAK, SETFLGS, MULSLW and MULULW opcodes. * cpu/uml.cpp: Limit range of immediate shift count arguments for consistency. * cpu/uml.cpp: Fix simplification of multiplication and division operations. * cpu/drcbec.cpp: Added more methods of accessing OP_CARRY. * cpu/drcbec.cpp: Fixed flag calculation for BSWAP and MULS opcodes. * cpu/drcbec.cpp: Made calculation for shift and rotation opcodes consistent. * cpu/drcbec.cpp: Return mapvar register ID instead of value for mapvars. * cpu/drcbex64.cpp, cpu/drcbex86.cpp: Fixed bugs in various opcodes to make them behave like the C backend. * cpu/drcbex64.cpp: Fixed SAVE, RESTORE and SETFMOD. * cpu/powerpc: Implement MULLWx and MULLWOx using the new MULSLW opcode.
* drcbex64,drcbex86: avoid deprecated functions Patrick Mackinlay2024-04-121-2/+2
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* drcbex64.cpp: Fix assert in debug build with some CPUs (PowerPC, SH) AJR2022-04-071-10/+9
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* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+1
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* asmjit: mame integration Patrick Mackinlay2022-02-131-75/+83
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* cpu/drcbex64.cpp: Proof-of-concept for optimisation of calling out. Vas Crabb2021-09-221-44/+265
| | | | | | | | | | | | | | | | Resolve address space virtual member function addresses on constrcution and call them directly. Provides a small but measurable improvement to performance in drivers that use the recompiler and access the memory system a lot. Also made MSVC delegates capable of walking past all the thunks MSVC puts in the way of actually calling a member function. I'm not accounting for the "this" pointer being passed in RDX when the return value is an oversize scalar. This is harmless because it won't see anything that looks like a virtual call thunk using RCX when RCX points to uninitialised space for the return value. It just means virtual member function calls won't be bypassed if the return value is an oversize scalar, but that doesn't happen frequently anyway.
* Eliminate ARRAY_LENGTH template in favor of C++17's std::size AJR2021-02-141-7/+7
| | | | | | | | | | * osdcomm.h: Move definition of EQUIVALENT_ARRAY to coretmpl.h * sharc.cpp, gt64xxx.cpp, ym2413.cpp, gb_lcd.cpp, snes_ppu.cpp: Use STRUCT_MEMBER for save state registration * gio/newport.cpp, megadrive/svp.cpp, nes_ctrl/bcbattle.cpp, arm7.cpp, tms9995.cpp, pckeybrd.cpp, sa1110.cpp, sa1111.cpp, jangou_blitter.cpp, vic4567.cpp: Use std::fill(_n) instead of memset * emucore.h: Remove obsolete typedef
* cpu: Slightly reduce the number of page protection state changes Vas Crabb2021-01-061-0/+1
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