| Commit message (Collapse) | Author | Age | Files | Lines |
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ROLAND could clobber source registers or produce incorrect results if
the desination was the same UML register as the shift or mask.
Fixed a bug in the logic for deciding whether to use a temporary
register for the mask for ROLINS.
Also optimised ROLAND and ROLINS some more (particularly translation
from UML's left rotate to ARM's right rotate) and removed a special case
that the simplifier now takes care of.
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* cpu/drcbearm64.cpp: Optimised setting up carry flag for ADDC and SUBB.
There's no need to preserve the NZV flags so a two-instruction
sequence can be used.
* cpu/drcbex64.cpp: Simplified code generation for CARRY. I have no
idea why it was preserving RAX at all - it always uses RAX as a
scratch register.
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* cpu/drcbearm64.cpp: Fixed ROLAND, ROLINS and CARRY clobbering the
shift input when it's a a register.
* cpu/drcbex86.cpp: Fixed DROLINS clobbering source in I0 and
miscalculating flags when destination is I0.
* cpu/uml.h: Removed assertion that's no longer valid.
* cpu/drcbearm64.cpp: Added minimal operand swizzling to allow AND, OR
and XOR to work without the simplifier.
* cpu/drcbex64.cpp: Optimised shift operations slightly.
* cpu/drcbec.cpp: Added stub implementations for TEST with no flag
outputs to allow running with simplifier disabled.
* cpu/drcbec.cpp: Implemented DREADM/DWRITEM with byte size access.
* cpu/drcbec.cpp: Store pointer to address space directly in instruction
stream.
* cpu/drcbearm64.cpp: Removed some special cases for situations the
simplifier deals with for ROLAND and ROLINS.
* cpu/drcbec.cpp: Added some actual detail to error messages on
encountering unexpected instructions.
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* cpu/drcbec.cpp: Interpret index operand for load/store instructions as
a signed value for consistency with other back-ends.
* cpu/drcbec.cpp: Honour alignment rules when packing immediate values.
* cpu/drcbex64.cpp: Don't special-case SEXT with an immediate source -
the simplifier takes care of this.
* cpu/drcbex86.cpp: Be explicit about preserving flags in load/store
instructions.
* docs: Added a couple more UML data movement instructions.
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recompiler issues:
* cpu/drcbearm64.cpp Interpret index operand for load and store
instructions as a signed 32-bit value for consistency with x86-64.
Moved code to interpret load and scale the index for integer
load/store to a helper function to make it easier to update if it
needs changes or fixes.
* cpu/drcbearm64.cpp: Use and/orr to set carry flag directly rahter than
using an intermediate register when both operands of a CARRY
instruction are immediates.
* cpu/drcbearm64.cpp: Fixed incorrect operand type assertion for FREAD.
* cpu/drcbearm64.cpp: Use less verbose asmjit helper functions for shift
operations and addressing modes.
* cpu/drcbex64.cpp: Interpret index operand for floating point
load/store as a signed 32-bit value for consistency with integer
load/store.
* cpu/drcbex64.cpp: Guard against any possibility of load and store
instructions altering the flags.
* cpu/drcbex64.cpp: Reduced copy/paste in floating point load/store
instructions.
* cpu/drcbex64.cpp: Cleaned up some casts between integer types with
differing size and signedness.
* docs: Added reference for UML flow control, data movement and emulated
memory access instructions.
* cpu/uml.cpp: Truncate immediates to size for a few more instructions.
* cpu/uml.cpp: Added SPACE_OPCODES since it's a well-known address space
now.
* cpu/uml.cpp: Removed SCALE_DEFAULT. It's unimplemented by back-ends
and unused by front-ends.
* cpu/uml.h, cpu/drcumlsh.h: Less confusing names for parameters to read
and write instruction generators.
* cpu/drcbex86.cpp: Templated 64-bit multiplication helpers on the
zero/sign flag source, cleaned up casting pointers to integers.
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* Also added a few more simplifications.
* cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed more speical cases for
things the simplifier deals with.
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* Fixed many cases that could cause the upper bits of a register not to
cleared following a 32-bit operation.
* Added more simplifications.
* Allow many simplifications when flag updates are requested.
* Fixed various bits of unreachable code.
* cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed code for special-casing
some situations the simplifier can now take care of consistently.
-cpu/drcbex64.cpp: Fixed a bug causing some shifts to be treated as a
no-op when the destination and source are not the same.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Added a special case for
comparing something to itself.
-cpu/e132xs: Use the CARRY instruction rather than a right shift to set
up carry in.
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* Got package option (T, N or B suffix) out of device type.
* Enabled 4x PLL clock multiplier for GMS30C2216/GMS30C2232.
* Implemented entering power down mode via MCR for E1 and E1-X cores.
* Marginally better code generation for a few instructions.
* Log available bus/memory configuration options for different cores.
* Added post load handler for E1-XS and E1-XSR cores to install SDRAM
mode/configuration handlers if necessary.
* Improved comment about different Hynix and Hyperstone CPU models.
-cpu/drcbearm64.cpp: Don't update flags that aren't requested in a few
places.
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* Assume ROL sets the V and C flags the same way as SHL and MOVI clears
the V flag.
-cpu/drcbex64.cpp: Optimise SUB x,0,y to a NEG instruction (gets down to
one instruction from two or three a lot of the time). This had been a
TODO comment for ages.
-cpu/drcbex86.cpp: Got rid of unnecessary std::function use. This
substantially reduces the code size and reduces allocations during code
generation.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of the
intermediate tables in favour of bit switch statements. This improves
startup time, reduces code size, and gives the compiler more
optimisation opportunities.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Got rid of
asmjit namespace qualifiers left over from when the class declarations
were in headers and hence outside the scope of the using namespace
statements.
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Sorry, I'm too tired and didn't git add this. My bad.
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* Fixed behaviour of delayed branches, trace exceptions, and saved PC
calculation for error exceptions in delay slots for the interpreter.
All instructions in delay slots, branching instructions that can raise
exceptions and tracing shoud now (mis)behave properly for the
interpreter, including things the manual says you shouldn't do.
* Fixed and optimised flag updates for left shifts for the recompiler.
* Optimised ROL instruction for the recompiler and made flag calculation
equivalent to the interpreter both with and without the "Missioncraft
flags" compile-time option.
* Only block interrupts for one instruction following a delayed branch.
* Optimised the SOFTWARE instruction a little for the recompiler.
* Added more SDRAM configuration logging and cleaned up code a bit.
-cpu/drcbearm64.cpp: Apply the change from 7efe37938f9dd6a366e to OR and
XOR instructions as well, and fix some cases where a 32-bit logical
operation would fail to clear the upper bits of a register.
-cpu/drcbex64.cpp: Avoid more conditional branches on conditional MOV.
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-cpu/drcbearm64.cpp: Simplified logic for choosing optimal AND strategy.
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cpu/drcbex64.cpp: Avoid a lot of unnecessary flag manipulation on
shift/rotate operations. Don't calculate flags when not requested.
Don't preserve carry in for operations that don't use it as an input.
cpu/drcbex64.cpp: Avoid loading CL when ECX can be used. Loading CL
doesn't clear the upper bits, so it depends on the previous value of
RCX, causing pipeline dependencies. Loading ECX can grab a fresh rename
register.
cpu/drcbearm64.cpp: Attempt more optimisation on one more load immediate
operation.
cpu/e132xs: Get rid of a redundant TEST - ROLAND can set the Z flag.
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* cpu/uml.cpp: Handle some more cases where ROLAND can be turned into
AND in the simplifier.
* cpu/drcbearm.cpp, cpu/drcbex64.cpp: Fixed a number of cases where
4-byte operations wouldn't clear the upper half of the destination
(there are plenty more of these caused by the simplifier that will be
harder to fix).
* cpu/drcbearm64.cpp: Fixed some cases where a conditional MOV could
unexpectedly clear the upper bits of the destination.
* cpu/drcbex64.cpp: Improved code generation for various arithmetic and
logical operations. More AND/OR/XOR/ADD/ADDC operand combinations are
optimised. Special cases of ROLAND/ROLINS are optimised.
* cpu/drcbex64.cpp: Don't treat operands to FADD/FMUL as commutative.
This isn't true when one is a NaN.
-cpu/e132xs: Use osd_printf_error for diagnositc output, and make more
local variables const.
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of a generated code block.
-cpu/drcbearm64.cpp: Don't emit code for UML NOP - the simplifier
litters the code with these for elided operations.
-frontend/mame/clifront.cpp: Added newline at end of -version output.
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* scripts/minimaws: Set option strict for JavaScript code.
* util/mfpresolve.h: Be explicit about turning nullptr into a pointer to
data.
* cpu/drcbearm64.cpp: Reduced number of temporary registers used for AND
with some operand combinations.
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Track the state of the native carry flag to avoid unnecessarily
manipulating the native NZCV register. If the native carry flag does
not correspond to the UML carry flag, test the bit in the flags register
for the C and NC conditions.
Use condition select instructions to implement conditional forms of MOV
and FMOV when advantageous.
Fixed EXIT with C/NC/A/BE condition not working properly if it doesn't
immediately follow a CMP or SUB. Extended reach of conditional EXIT to
+/-128MiB (was +/-1MiB for conditions other than U/NU).
Moved code to set up skipping conditional instructions to a common
function.
Use TBZ/TBNZ for short backward jumps with U/NU/C/NC conditions to save
one instruction and a temporary register.
Simplified/optimised ADD[C]/SUB[B] code generation - avoids an
unnecessary register copy when one operand is in memory and the other is
a small immediate value. Also fixed another unnecessary register copy
for SUB[B] when an operand is kept in a host register.
Slightly optimised generated code for AND immediate.
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Clear V/Z/S bits in flags register after SETFLGS or RESTORE. These
flags are kept in the native NZCV register, and SAVE assumes the
corresponding bits in the flags register are clear.
Don't use an extra temporary register for SETFMOD with operand loaded
from memory. It doesn't allow additional parallelism anyway.
Slightly optimised generated code for GETFLGS.
Avoid a redundant TST when flags are requested for the non-optimised
ROLAND case. Also avoid unnecessarily updating flags when not
requested.
Don't update flags for ADD/ADDC/SUB/SUBB/AND if not requested. Slightly
reduces pressure on the NZCV register.
Added TODO notes for opportunities to use CSEL/FCSEL rather than
conditional branches.
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generation. (#13476)
* Fixed potential crash on generating code for UML ADDC or SUBB with immediate operands (GitHub #13475).
* Optimised generated code for various degenerate cases and cases where register loads can be avoided.
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* Correctly identify valid immediate constants for add/sub/cmp (it was
too conservative).
* Don't unnecessarily copy UML register values kept in host registers
for CMP.
* Fixed detection of TST against immediate zero and optimised generated
code.
* Optimised TST against immediate with all bits set.
-cpu/alto2: Follow the same pattern as the other things that have been
altered to avoid problematic memsets in this device.
-cpu/powerpc: Realigned some comments that had drifted.
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language. (#13472)
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Emit optimised code for native-width reads and writes no larger than native width.
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-cpu/drcbearm64.cpp: Added some glue for supporting memory access optimisations.
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namespaces.
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* Allocate label helpers and map variable changes from the process heap.
They're only used during code generation and have no business being in
the DRC cache.
* Keep map variable changes contiguous, don't deallocate label helpers
and map variable changes on completing a block.
* Got rid of simple_list, more const, tidied a little.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Shuffled RECOVER instructions a
bit to be nicer to the CPU's scheduler.
-bus/hp_dio/hp_dio.cpp: Removed vestigial simple_list support code.
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* Recognise immediate values that can be generated using a movn with
shift 16 or an orr immediate into a W register.
* Recognise repeating patterns that can be represented as a bitmask
immediate value.
* Slightly optimised generated code for UML AND when at least one
argument is immediate zero.
* Added optimised UML AND code when the instruction size is 8 but the
second argument is a valid 32-bit bitmask immediate.
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* Detect immediates that can be generated with a single movz/movn/orr.
* Prefer adr over add to base register (no register dependency).
* Don't bother trying to load base register value from memory.
* Got rid of loop in check for contiguous mask values.
* Slightly optimised generation of ROLAND/ROLINS shift counts.
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cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Removed static trampoline
fallbacks for get map variable value and debugger instrcution hook
functions.
cpu/drcbex86.cpp: Removed static trampolines for get map variable value
and debugger instrcution hook functions.
cpu/drcbex64.cpp: Corrected stack diagram in comment.
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cpu/drcbex86.cpp: Don't use static address space accessors. This gives
a big performance improvement.
cpu/drcbeut.cpp: Made failure to resolve address space accessors fatal.
cpu/drcbearm64.cpp: Removed fallback to static address space accessors.
cpu/mips3/mibs3.cpp: Removed static address space accessors. All they
were doing was hurting performance.
cpu/drcbex64.cpp: Don't use goofy X64_WINDOWS_ABI macro, just check
_WIN32. The only other environment that uses the Windows calling
convention is (U)EFI, and we can move feature detection to util/abi.h if
we ever need to care about it.
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ADRP output must always be an X register.
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handling.
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cpu/drcbex64.cpp: Consider a RIP-relative LEA for generating 64-bit
values (7-byte instruction versus a 10-byte MOV instruction). Seems to
work pretty well for heap pointers.
cpu/drcbearm64.cpp: Changed the near cache base pointer offset from 0x80
to 0x100. The value 0x80 was copied from the x86-64 back-end where it
was choses to allow an 8-bit signed displacement to reach as much of the
top of the near cache as possible. However, AArch64 use 9-bit signed
displacements, so a quarter of the range was being wasted.
cpu/drcbearm64.cpp: Consider an adrp/add sequence for generating
immediate values as well as memory references.
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* Build all native back-ends if any native back-end is enabled so errors
caused by changing interfaces can be found faster.
* cpu/drcbeut.cpp: Moved resolved member function stuff to a place where
it can be shared by back-ends.
* cpu/drcbearm64.cpp: Use ubfx instruction to extract unordered flag.
* cpu/drcbearm64.cpp, cpu/drcbex64.cpp: Bypass trampolines when calling
get map variable value and debugger instruction hook functions.
* cpu/drcbearm64.cpp: Moved some internal helpers that don't need to be
members to anonymous namespace.
* cpu/drcbearm64.cpp: Added a comment with some info to help when
debugging generated code.
* cpu/drcbec.cpp: Put code in the drc namespace.
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This wasn't added to the DRC implementations when it was added to the
address space classes.
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Handle landing pads save the LR/FP pair, so the return address for the
first level of callh, exh or "no code" handler can be recovered from
below the base frame pointer.
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-cpu/drcbex86.cpp: Give hints to use short displacements for jumps to local unbound labels.
-util/mfpresolve.h: Use references for some things that must not be null pointers.
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count. (#13232)
* cpu/drcbec.cpp, cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Calculate NZ flags for shifts/rotates by 0 bits.
* cpu/drcbex86.cpp: Fixed flag calculation for 64-bit multiplication when result is zero.
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location.
* util/delegate.cpp, cpu/drcbex64.cpp, cpu/drcbearm64.cpp: Use common member function resolution code.
-cpu/drcbearm64.cpp, cpu/drcbex64.cpp, cpu/drcbex86.cpp: Moved some stuff to anonymous namespaces.
-cpu/drcbex64.cpp, cpu/drcbex86.cpp: Defer allocating labels if they aren't always needed.
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* cpu/uml.cpp: Removed unused vector type.
* 3rdparty/asmjit: Update asmjit to latest upstream.
* cpu/drcbex64.cpp: Fixed crash with LOG_HASHJMPS enabled (stack needs to be 16-byte aligned before calling debug_log_hashjmp_fail).
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