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path: root/src/devices/cpu/arm7/arm7thmb.cpp
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* arm7: Clean up various code using util::sext and multiply inlines AJR2023-02-201-17/+5
| | | | * mb86235: One more use of util::sext
* eminline.h: Additions AJR2022-09-251-2/+1
| | | | | | - Add mul_16x16 inline function to perform a signed 16x16-bit multiplication with 32-bit result. This was moved from cpu/e132xs to unite it with the analogous 32x32 operations. - Add rotl_32, rotr_32, rotl_64 and rotr_64 inline functions to perform 32-bit and 64-bit circular shifts in either direction by the specified number of places, modulo 32 or 64. It is anticipated that these will eventually be replaced by standard functions in C++20's <bit> header, and so they have been given similar signatures and semantics (which are also validity-checked). - Remove LSL, LSR, ROL and ROR macros from cpu/arm and cpu/arm7 to ameliorate unnecessary obfuscation.
* arm7thmb.cpp this should be more accurate ROR fix MetalliC2020-08-051-3/+3
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* -arm7thmb: Fixed THUMB ROR behavior for shift values of 0 or >= 32. All ↵ Ryan Holtz2020-08-051-12/+16
| | | | tests in FuzzARM now pass. [Ryan Holtz]
* resolve merge conflicts (nw) MetalliC2017-12-271-17/+14
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* Merge tag 'mame0193' Vas Crabb2017-12-271-14/+17
|\ | | | | | | | | | | | | MAME 0.193 Conflicts: src/devices/cpu/arm7/arm7thmb.cpp
| * Arm Thumb: same but handle 2 magical ROR cases (nw) MetalliC2017-12-241-19/+22
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* | arm7: revert previous changes, explicit masking and rotating was unneeded ↵ MetalliC2017-12-251-36/+16
| | | | | | | | | | | | | | | | | | | | | | (except for POP {Rlist} which is correct), handle v5 behavior (lsb address bit is ignored in 16bit loads) in arm946es_cpu_device::arm7_cpu_read16 instead, manually handle v4 and v5 difference for LDRSH signed halfword load. note: it looks like all? v5 cores ignore least significant address bit during 16bit loads, so we should add something like virtual uint32_t arm7_cpu_read16(uint32_t addr) override { return base_class::arm7_cpu_read16(addr & ~1)}; into theirs class declaration.
* | ARM thumb: v4 is really a bit different in edge cases (nw) MetalliC2017-12-241-5/+20
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* | Arm Thumb: same but handle 2 magical ROR cases (nw) MetalliC2017-12-241-19/+22
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* Revert "ARM Thumb: mask address lsb during 16/32 bit memory access, as per ↵ arbee2017-12-231-17/+17
| | | | | | ARMv5/ARM9 behavior." This reverts commit 1bc2a2ab12757e21a90ef191bf9fe69a541132e8.
* ARM Thumb: mask address lsb during 16/32 bit memory access, as per ↵ MetalliC2017-12-241-17/+17
| | | | | | ARMv5/ARM9 behavior. this needed to be changed or split when we will be emulate ARMv6/ARM11
* Revert "Revert "Merge branch 'master' of https://github.com/mamedev/mame"" Firehawke2017-12-131-3/+2
| | | | This reverts commit 54155441e9ba9941e85d80c4834a66376a11e791.
* Revert "Merge branch 'master' of https://github.com/mamedev/mame" Firehawke2017-12-131-2/+3
| | | | | This reverts commit f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4, reversing changes made to 0d70d798107d4e4e8fb9f230410aeb1e888d65c5.
* arm7: LDMIA/STMIA always align to a 32-bit boundry [endrift, R. Belmont] arbee2017-12-051-3/+2
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* dumped internal IGS036 rom for Oriental Legend 2 [Morten Shearman Kirkegaard ↵ David Haywood2017-11-061-2/+7
| | | | | | | | | | and Peter Wilhelmsen] started adding some devices to the driver to support it [David Haywood] derived IGS036 type in ARM7/9 core, because it seems like mmu could be different, and there are probably other internal devices [David Haywood] fixed(?) BLX (LO) thumb opcode in ARM7/9 core, was storing a return address that skipped the following opcode [David Haywood] I think there might still be ARM9 issues.
* Further fixes for ARM trap152017-02-111-0/+1
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* gba fix, add update_irq_state on places missing (nw) Miodrag Milanovic2016-10-231-0/+1
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* Fix copy/paste error per Mooglyguy (nw) Scott Stone2016-10-221-1/+1
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* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-221-321/+321
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* -arm7: Performed some minor optimization. [Ryan Holtz] therealmogminer@gmail.com2016-10-211-204/+204
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* Rename *.c -> *.cpp in our source (nw) Miodrag Milanovic2015-11-081-0/+1587