summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/arm7/arm7dasm.cpp
Commit message (Collapse)AuthorAgeFilesLines
* misc: remove "all rights reserved" copyright comment, hap2025-01-221-2/+2
| | | | mcs51: remove old changelog from comments, remove copypasted comment block
* arm7: another disassembly fix Olivier Galibert2023-11-091-1/+1
|
* arm7: correct dasm of register shift op2 Olivier Galibert2023-11-081-1/+1
|
* arm7: Clean up various code using util::sext and multiply inlines AJR2023-02-201-15/+3
| | | | * mb86235: One more use of util::sext
* eminline.h: Additions AJR2022-09-251-1/+1
| | | | | | - Add mul_16x16 inline function to perform a signed 16x16-bit multiplication with 32-bit result. This was moved from cpu/e132xs to unite it with the analogous 32x32 operations. - Add rotl_32, rotr_32, rotl_64 and rotr_64 inline functions to perform 32-bit and 64-bit circular shifts in either direction by the specified number of places, modulo 32 or 64. It is anticipated that these will eventually be replaced by standard functions in C++20's <bit> header, and so they have been given similar signatures and semantics (which are also validity-checked). - Remove LSL, LSR, ROL and ROR macros from cpu/arm and cpu/arm7 to ameliorate unnecessary obfuscation.
* Debugger feature improvements AJR2022-03-271-8/+28
| | | | | | | | - Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected. - Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions. - Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse. - Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx) - Don't pass over delay slots for debugging in ASAP core
* srcclean and manual tidying up in preparation for 0.242 release Vas Crabb2022-03-271-2/+2
|
* arm7: Disassembly improvements AJR2022-03-131-823/+873
| | | | | | | | | | | | | | | | | - Correct formatting of LDR and STR pre-indexed writeback modes - Correct opcode suffixes for LDM and STM in ARM mode - Correct LDRSH mnemonic in Thumb mode - Omit destination register for data processing instructions when Rd = Rs - Recognize RRX shift mode - Disassemble immediate ADD or SUB from R15 as ADR in both ARM and Thumb modes - Use ARM-preferred LSL, LSR, ASR, ROR and RRX mnemonics for shifted MOV operations - Fully disassemble flag field for MSR [CS]PSR - Use 0x as hexadecimal prefix except for small constants - Make output in Thumb mode prettier - Recognize a few more ARMv5/v5TE instructions - Add STEP_OUT debugging flag to a few more instructions commonly used for exits - Regularize a lot of sloppy formatting - Somewhat reduce code duplication in Thumb disassembler
* New machines marked as NOT_WORKING Ryan Holtz2020-12-241-1/+2
| | | | | | | | | | | | | ------------------ Hewlett-Packard Jornada 720 [Ryan Holtz] * arm7: Fixed interaction between instruction prefetching with the MMU enabled. [Ryan Holtz] * sa111: Added skeleton device for Intel SA-1111 Microprocessor Companion Chip. [Ryan Holtz] * sed1356: Added skeleton device for Epson/Seiko SED1356 video controller. [Ryan Holtz] * sa1110: Various cleanups. Added rudimentary SSP module support. [Ryan Holtz]
* -Switch to building MAME as C++17. Vas Crabb2020-11-151-0/+1
| | | | | | | * Updated sol2 to 3.2.2 * Updated pugixml to 1.10 * Increased minimum clang version to 6 * Cleaned up some stuff that can use new features
* arm7dasm.cpp: Remove unnecessary newline (nw) AJR2019-08-041-1/+1
|
* arm7 disasm fix (nw) Olivier Galibert2017-11-271-4/+4
|
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-33/+31
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* srcclean (nw) Vas Crabb2017-11-261-1/+1
|
* arm7: Implement BLX Rn instruction for ARM9. NDS ARM9 BIOS gets to the ↵ arbee2017-11-161-1/+9
| | | | first checkpoint. [R. Belmont]
* ARMv5 additions to ARM7 trap152017-02-101-7/+23
|
* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-201-22/+4
|
* Changed the arm7 disassembler to use 'std::ostream &' internally Nathan Woods2016-11-141-313/+321
|
* NOTICE (TYPE NAME CONSOLIDATION) Miodrag Milanovic2016-10-221-23/+23
| | | | | Use standard uint64_t, uint32_t, uint16_t or uint8_t instead of UINT64, UINT32, UINT16 or UINT8 also use standard int64_t, int32_t, int16_t or int8_t instead of INT64, INT32, INT16 or INT8
* cleanups (nw) Miodrag Milanovic2015-12-251-1/+1
|
* Rename *.c -> *.cpp in our source (nw) Miodrag Milanovic2015-11-081-0/+1331