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* f2mc16: add MB90610A and MB90611A microcontrollers. [R. Belmont] arbee2019-07-031-0/+2
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* Preliminary Fujitsu F2MC-16 CPU core, currently disassembly only [R. Belmont] arbee2019-07-011-0/+17
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* Add disassembler and skeleton device for DP8344 Biphase Communications Processor AJR2019-06-221-0/+17
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* Preliminary disassembler and skeleton CPU device for Elan RISC II/RII series ↵ AJR2019-06-201-0/+17
| | | | architecture
* i386: Improve splitting of unaligned accesses (excluding program fetches) AJR2019-05-191-0/+3
| | | | (nw) This entails a major code reorganization just to keep the scale of it all halfway sane.
* TV Game Work (progress towards smartfp and wrlshunt) (#4956) David Haywood2019-04-301-0/+10
| | | | | | | | | | | | | | | | | | | | * unsp refactoring / tv game work (nw) * unsp refactoring / tv game work (nw) * srcclean (nw) * more ops (nw) * (nw) * (nw) * guesses (nw) * more guesses (nw) * (nw)
* m680x0: gratuitously convert the generator to python [O. Galibert] Olivier Galibert2019-04-291-2/+0
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* swp20, dspv: Skeletons [O. Galibert] Olivier Galibert2019-04-091-0/+17
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* (nw) Clean up the mess on master Vas Crabb2019-03-261-1/+77
| | | | | | | | | | | | | This effectively reverts b380514764cf857469bae61c11143a19f79a74c5 and c24473ddff715ecec2e258a6eb38960cf8c8e98e, restoring the state at 598cd5227223c3b04ca31f0dbc1981256d9ea3ff. Before pushing, please check that what you're about to push is sane. Check your local commit log and ensure there isn't anything out-of-place before pushing to mainline. When things like this happen, it wastes everyone's time. I really don't need this in a week when real work™ is busting my balls and I'm behind where I want to be with preparing for MAME release.
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-77/+1
| | | | | This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing changes made to 009cba4fb8102102168ef32870892438327f3705.
* ns32000: Skeleton CPU device with disassembler for NS32000 family. Nigel Barnes2019-03-231-0/+17
| | | | bbc: Added preliminary Acorn 32016 2nd Processor, incomplete CPU emulation.
* ymmu100: Start adding the MEG [O. Galibert] Olivier Galibert2019-03-231-0/+17
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* i386: add a simple cache to the athlon xp processor (nw) yz70s2019-03-141-0/+1
| | | | | | | | | | | . A single 64K 2-way set associative cache Used for both instructions and data Enabled only for addresses in the first megabyte Works always in writeback mode . It is needed by the nforce motherboard bios that uses it to simulate a block of ram at address d0000 before ddr ram is configured
* Add skeleton CPU device and disassembler for HPC architecture AJR2019-03-031-0/+17
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* r4000: experimental mips3 implementation (nw) Patrick Mackinlay2019-02-011-0/+3
| | | | | | WIP checkpoint: while I believe it's largely accurate (and very slow), neither jazz nor sgi systems can fully boot yet using this device, so it remains experimental. This implementation should go away when it has helped identify the improvements required for mips3.
* alpha: new cpu, disassembler only Patrick Mackinlay2019-01-241-0/+17
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* unsp: Created a SunPlus u'nSP recompiler. [Ryan Holtz] MooglyGuy2019-01-121-1/+5
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* Last round of macro removals before the freeze. (nw) mooglyguy2018-12-221-0/+20
| | | | | | | | | | | | -sound/discrete, okim6295: Removed MCFG macros. [Ryan Holtz] -norautp, osi, audio/mario: Removed MACHINE_CONFIG macros. [Ryan Holtz] -vsmile: Split into its own driver from vii.cpp. [Ryan Holtz] -vii: Fixed broken controller inputs. [Ryan Holtz] -konamim2: Massive update. Most games work, but are still marked non-working due to rare MAME crashes in the PPC DRC. [Phil Bennett, Ryan Holtz]
* add derived CPU type for AX51-CORE (used by AX208 and others) so that we can ↵ DavidHaywood2018-12-141-0/+4
| | | | start to customize disassembly and execution
* i386.cpp: move cpuid and msr routines to new file cpuidmsrs.hxx ... (nw) yz70s2018-12-091-0/+1
| | | | ... and add placeholders for athlonxp msrs.
* -o2.cpp: Added CRIME and MACE skeleton devices. [Ryan Holtz] mooglyguy2018-11-181-0/+1
| | | | | | | | | | | -mips3.cpp: Various changes: [Ryan Holtz] * Added an #ifdef to display DPRINTF calls from the SGI O2 PROM. * Switched R4000BE/LE, R4400BE, R4600BE, and R5000BE to 64-bit data bus. * Fixed a bug that caused a crash with 64-bit data bus and the DRC. -indy_indigo2.cpp: Moved a number of devices into HPC3. [Ryan Holtz] -hpc3.cpp: Fixed an oversight with IRQs. [Ryan Holtz]
* r3000: call it like it is (nw) Patrick Mackinlay2018-11-061-11/+11
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* i386.cpp: prepare to change hxx files into regular cpp files (nw) yz70s2018-11-031-0/+1
| | | | | | | | | | | | | | | | | | -change order of include files at top of i386.cpp -move some routines between i386.cpp and i386priv.h -move part of x87ops.hxx into new file x87priv.h . Now you only have to rename the hxx files to cpp and add the following at the top of each one . #include "emu.h" #include "i386.h" #include "i386priv.h" #include "x87priv.h" #include "cycles.h" #include "debugger.h" #include "debug/debugcpu.h" #undef i386
* v53: final tidy (nw) Patrick Mackinlay2018-11-011-3/+3
| | | | | | * changed copyright holder due to near-complete replacement * name changed to v5x which better reflects actual use * minor comment cleanup
* -sun4: Added a sun4c MMU device. Currently wraps the functionality of ↵ mooglyguy2018-09-221-0/+1
| | | | | | S4-buffer, S4-cache, and S4-MMU, will eventually be split. [Ryan Holtz] -sun4: Significant optimization, from 150% -> 330% unthrottled on an i7-5930K. [Ryan Holtz]
* -st62xx: Added a skeleton driver for the STmicro ST6 series of ↵ mooglyguy2018-08-251-0/+17
| | | | | | | | microcontrollers. [Ryan Holtz] New machines marked as NOT_WORKING ---------------------------------- Catherine Wheel [f205v, Ryan Holtz]
* tms57002: Trick to reduce the compiler memory usage [O. Galibert] Olivier Galibert2018-08-231-0/+2
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* Amiga keyboard overhaul: Vas Crabb2018-08-231-0/+3
| | | | | | | | | | | | | * Implement Mitsumi Amiga 500, 600, and 2000/3000/4000/CDTV keyboards * Add unlabeled keys to UK layout * Restrict available keyboards depending on system type * Note that C-A-A reset is now broken on "big box" Amigas as MAME doesn't implement it properly, and the hack providing a fake dedicated reset line has been removed 6502 MCU: fix execute loop 6500/1: implement as device with onboard peripherals Fix some bogus comments
* h8: H8/3003 support [R. Belmont] arbee2018-08-021-0/+2
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* Flesh out TLCS870 core (#3763) David Haywood2018-07-231-0/+5
| | | | | | | | | | | | | | | | * rewrote most of the execution for my tlcs870 core * no longer the case (nw) * note updates (nw) * address concerns, const qualify more things where possible (nw) * more const (nw) * oops (nw) * consistency (nw)
* ps2sony: Some basic VU1 support, major file reshuffling, nw mooglyguy2018-07-211-2/+4
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* ps2sony: Checkpoint, nw mooglyguy2018-07-171-0/+4
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* proposal: move z80daisy* to devices/machine (#3572) Patrick Mackinlay2018-05-151-7/+0
| | | | | | | | | | * proposal: move z80daisy* to devices/machine Seems to me this is a machine, not a CPU? Main reason was to stop the Z80 CPU from being dragged into systems that don't have one just because they use a Z80 family peripheral. * missed this one (nw) * missed a spot (nw)
* sm5*: added sm530 disasm (nw) hap2018-05-121-0/+3
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* start looking at the extra opcodes in the SSD 2000 type XaviX chip (s… (#3514) David Haywood2018-05-041-0/+9
| | | | | | | | * start looking at the extra opcodes in the SSD 2000 type XaviX chip (seems some undocumented 6502 opcodes are replaced with more custom ones) * (nw) * the xavix memory mapping gets stranger with each piece of new evidence (nw)
* srcclean and regenerate localisations (nw) Vas Crabb2018-03-251-1/+1
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* dsp16: move most core state into DRC cache - keeps a lot of details out of ↵ Vas Crabb2018-03-211-0/+5
| | | | the main header (DRC is still stubbed out) (nw)
* prettier way of adding DRC framework on-demand (nw) Vas Crabb2018-03-201-2/+12
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* dsp16: start adding recompiler boilerplate (nw) Vas Crabb2018-03-171-2/+4
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* use more constexpr and literal classes in UML to give compiler more ↵ Vas Crabb2018-03-171-4/+4
| | | | optimisation opportunities (nw)
* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-0/+1
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* Cycle-accurate DSP16 core (disabled in QSound for performance reasons) Vas Crabb2018-03-151-1/+0
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* Merge pull request #3266 from JoakimLarsson/diablo_1 R. Belmont2018-02-281-0/+17
|\ | | | | WIP: Diablo printer CPU
| * WIP: Diablo printer CPU joakim2018-02-241-0/+17
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* | srcclean (nw) Vas Crabb2018-02-251-1/+1
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* | NUON disassembler [O. Galibert] Olivier Galibert2018-02-181-0/+10
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* create derived 6502 type for XaviX because it has at least one custom… (#3154) David Haywood2018-02-021-1/+10
| | | | | | | | | | | | | | | | | | | | | * create derived 6502 type for XaviX because it has at least one custom 4-byte opcode that doesn't fit any other type. treating that opcode as NOP for now. have a feeling it might be something to do with the other integrated hardware, might be 'execute co-processor code chain at this address' or something similar It isn't a standard JSL (Jump Subroutine Long) like the SNES cpu opcode in the same place as this, it seems to point at some code-like structures tho) could also be a secondary operation mode with different encoding like ARM's Thumb mode tho I guess. We currently only have a single XaviX based dump (taitons1) but there are more on the way. I'm going to see if the code flow makes any sense at all with these missing, or if any of it gives a clue as to what they should actually do. * xavix - let's call these callf and retf then after further investigation these are some kind of extra 'long jump' subroutine / task handlers, the 0x80 also being a custom opcode was throwing me off trying to identify them before. looks like they might have been hacking 65816 features into the regular 6502 core? * prepare for extra address bits (nw) * better program flow (nw)
* -e132xs: fix botched DRC merge, nw mooglyguy2017-12-291-0/+3
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* fixed build errors, nw mooglyguy2017-12-291-1/+1
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* tms1000c: added correct microinstructions pla (nw) hap2017-12-211-0/+3
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