diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/emu/cpu/drcumlsh.h | 44 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3drc.c | 1204 | ||||
-rw-r--r-- | src/emu/cpu/powerpc/ppcdrc.c | 1746 | ||||
-rw-r--r-- | src/emu/cpu/rsp/rspdrc.c | 366 | ||||
-rw-r--r-- | src/emu/cpu/sh2/sh2drc.c | 1062 | ||||
-rw-r--r-- | src/emu/cpu/uml.h | 3 |
6 files changed, 2192 insertions, 2233 deletions
diff --git a/src/emu/cpu/drcumlsh.h b/src/emu/cpu/drcumlsh.h index f64d0fec83d..55e75285f09 100644 --- a/src/emu/cpu/drcumlsh.h +++ b/src/emu/cpu/drcumlsh.h @@ -20,50 +20,6 @@ /*************************************************************************** - CONSTANTS -***************************************************************************/ - -/* shorthand for conditions */ -#define IF_Z uml::COND_Z -#define IF_NZ uml::COND_NZ -#define IF_S uml::COND_S -#define IF_NS uml::COND_NS -#define IF_C uml::COND_C -#define IF_NC uml::COND_NC -#define IF_V uml::COND_V -#define IF_NV uml::COND_NV -#define IF_U uml::COND_U -#define IF_NU uml::COND_NU -#define IF_E uml::COND_E -#define IF_NE uml::COND_NE -#define IF_A uml::COND_A -#define IF_AE uml::COND_AE -#define IF_B uml::COND_B -#define IF_BE uml::COND_BE -#define IF_G uml::COND_G -#define IF_GE uml::COND_GE -#define IF_L uml::COND_L -#define IF_LE uml::COND_LE -#define IF_ALWAYS uml::COND_ALWAYS - - - -/*************************************************************************** - MACROS -***************************************************************************/ - -/* macros for wrapping parameters */ -#define NONE uml::parameter() -#define IMM(x) (x) -#define IREG(x) uml::ireg(x) -#define FREG(x) uml::freg(x) -#define VREG(x) uml::vreg(x) -#define MVAR(x) uml::mapvar(x) -#define MEM(x) uml::parameter::make_memory((void *)(x)) - - - -/*************************************************************************** INLINE FUNCTIONS ***************************************************************************/ diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index 8cfebe39855..83f95669eff 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -90,8 +90,8 @@ using namespace uml; ***************************************************************************/ /* map variables */ -#define MAPVAR_PC MVAR(0) -#define MAPVAR_CYCLES MVAR(1) +#define MAPVAR_PC M0 +#define MAPVAR_CYCLES M1 /* modes */ #define MODE_KERNEL 0 @@ -124,22 +124,22 @@ using namespace uml; #define R32(reg) mips3->impstate->regmaplo[reg] #define LO32 R32(REG_LO) #define HI32 R32(REG_HI) -#define CPR032(reg) MEM(LOPTR(&mips3->cpr[0][reg])) -#define CCR032(reg) MEM(LOPTR(&mips3->ccr[0][reg])) -#define FPR32(reg) MEM(((mips3->impstate->mode & 1) == 0) ? &((float *)&mips3->cpr[1][0])[reg] : (float *)&mips3->cpr[1][reg]) -#define CCR132(reg) MEM(LOPTR(&mips3->ccr[1][reg])) -#define CPR232(reg) MEM(LOPTR(&mips3->cpr[2][reg])) -#define CCR232(reg) MEM(LOPTR(&mips3->ccr[2][reg])) +#define CPR032(reg) mem(LOPTR(&mips3->cpr[0][reg])) +#define CCR032(reg) mem(LOPTR(&mips3->ccr[0][reg])) +#define FPR32(reg) mem(((mips3->impstate->mode & 1) == 0) ? &((float *)&mips3->cpr[1][0])[reg] : (float *)&mips3->cpr[1][reg]) +#define CCR132(reg) mem(LOPTR(&mips3->ccr[1][reg])) +#define CPR232(reg) mem(LOPTR(&mips3->cpr[2][reg])) +#define CCR232(reg) mem(LOPTR(&mips3->ccr[2][reg])) #define R64(reg) mips3->impstate->regmap[reg] #define LO64 R64(REG_LO) #define HI64 R64(REG_HI) -#define CPR064(reg) MEM(&mips3->cpr[0][reg]) -#define CCR064(reg) MEM(&mips3->ccr[0][reg]) -#define FPR64(reg) MEM(((mips3->impstate->mode & 1) == 0) ? (double *)&mips3->cpr[1][(reg)/2] : (double *)&mips3->cpr[1][reg]) -#define CCR164(reg) MEM(&mips3->ccr[1][reg]) -#define CPR264(reg) MEM(&mips3->cpr[2][reg]) -#define CCR264(reg) MEM(&mips3->ccr[2][reg]) +#define CPR064(reg) mem(&mips3->cpr[0][reg]) +#define CCR064(reg) mem(&mips3->ccr[0][reg]) +#define FPR64(reg) mem(((mips3->impstate->mode & 1) == 0) ? (double *)&mips3->cpr[1][(reg)/2] : (double *)&mips3->cpr[1][reg]) +#define CCR164(reg) mem(&mips3->ccr[1][reg]) +#define CPR264(reg) mem(&mips3->cpr[2][reg]) +#define CCR264(reg) mem(&mips3->ccr[2][reg]) #define FCCSHIFT(which) fcc_shift[(mips3->flavor < MIPS3_TYPE_MIPS_IV) ? 0 : ((which) & 7)] #define FCCMASK(which) ((UINT32)(1 << FCCSHIFT(which))) @@ -359,7 +359,7 @@ INLINE void load_fast_iregs(mips3_state *mips3, drcuml_block *block) for (regnum = 0; regnum < ARRAY_LENGTH(mips3->impstate->regmap); regnum++) if (mips3->impstate->regmap[regnum].is_int_register()) - UML_DMOV(block, IREG(mips3->impstate->regmap[regnum].ireg() - REG_I0), MEM(&mips3->r[regnum])); + UML_DMOV(block, ireg(mips3->impstate->regmap[regnum].ireg() - REG_I0), mem(&mips3->r[regnum])); } @@ -374,7 +374,7 @@ INLINE void save_fast_iregs(mips3_state *mips3, drcuml_block *block) for (regnum = 0; regnum < ARRAY_LENGTH(mips3->impstate->regmap); regnum++) if (mips3->impstate->regmap[regnum].is_int_register()) - UML_DMOV(block, MEM(&mips3->r[regnum]), IREG(mips3->impstate->regmap[regnum].ireg() - REG_I0)); + UML_DMOV(block, mem(&mips3->r[regnum]), ireg(mips3->impstate->regmap[regnum].ireg() - REG_I0)); } @@ -483,18 +483,18 @@ static void mips3_init(mips3_flavor flavor, int bigendian, legacy_cpu_device *de mips3->impstate->drcuml->get_backend_info(beinfo); if (beinfo.direct_iregs > 4) { - mips3->impstate->regmap[2] = IREG(4); - mips3->impstate->regmaplo[2] = IREG(4); + mips3->impstate->regmap[2] = I4; + mips3->impstate->regmaplo[2] = I4; } if (beinfo.direct_iregs > 5) { - mips3->impstate->regmap[3] = IREG(5); - mips3->impstate->regmaplo[3] = IREG(5); + mips3->impstate->regmap[3] = I5; + mips3->impstate->regmaplo[3] = I5; } if (beinfo.direct_iregs > 6) { - mips3->impstate->regmap[4] = IREG(6); - mips3->impstate->regmaplo[4] = IREG(6); + mips3->impstate->regmap[4] = I6; + mips3->impstate->regmaplo[4] = I6; } } @@ -812,7 +812,7 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc | 0x80000000 - UML_HASHJMP(block, IMM(mips3->impstate->mode), IMM(seqhead->pc), *mips3->impstate->nocode); + UML_HASHJMP(block, mips3->impstate->mode, seqhead->pc, *mips3->impstate->nocode); // hashjmp <mode>,seqhead->pc,nocode continue; } @@ -838,14 +838,14 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4; /* count off cycles and go there */ - generate_update_cycles(mips3, block, &compiler, IMM(nextpc), TRUE); // <subtract cycles> + generate_update_cycles(mips3, block, &compiler, nextpc, TRUE); // <subtract cycles> /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */ if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES) - UML_HASHJMP(block, MEM(&mips3->impstate->mode), IMM(nextpc), *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&mips3->impstate->mode), nextpc, *mips3->impstate->nocode); // hashjmp <mode>,nextpc,nocode else if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) - UML_HASHJMP(block, IMM(mips3->impstate->mode), IMM(nextpc), *mips3->impstate->nocode); + UML_HASHJMP(block, mips3->impstate->mode, nextpc, *mips3->impstate->nocode); // hashjmp <mode>,nextpc,nocode } @@ -998,28 +998,28 @@ static void static_generate_entry_point(mips3_state *mips3) UML_HANDLE(block, *mips3->impstate->entry); // handle entry /* reset the FPU mode */ - UML_AND(block, IREG(0), CCR132(31), IMM(3)); // and i0,ccr1[31],3 - UML_LOAD(block, IREG(0), &mips3->impstate->fpmode[0], IREG(0), SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte - UML_SETFMOD(block, IREG(0)); // setfmod i0 + UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3 + UML_LOAD(block, I0, &mips3->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte + UML_SETFMOD(block, I0); // setfmod i0 /* load fast integer registers */ load_fast_iregs(mips3, block); /* check for interrupts */ - UML_AND(block, IREG(0), CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] - UML_AND(block, IREG(0), IREG(0), IMM(0xfc00)); // and i0,i0,0xfc00,Z - UML_JMPc(block, IF_Z, skip); // jmp skip,Z - UML_TEST(block, CPR032(COP0_Status), IMM(SR_IE)); // test [Status],SR_IE - UML_JMPc(block, IF_Z, skip); // jmp skip,Z - UML_TEST(block, CPR032(COP0_Status), IMM(SR_EXL | SR_ERL)); // test [Status],SR_EXL | SR_ERL - UML_JMPc(block, IF_NZ, skip); // jmp skip,NZ - UML_MOV(block, IREG(0), MEM(&mips3->pc)); // mov i0,pc - UML_MOV(block, IREG(1), IMM(0)); // mov i1,0 + UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] + UML_AND(block, I0, I0, 0xfc00); // and i0,i0,0xfc00,Z + UML_JMPc(block, COND_Z, skip); // jmp skip,Z + UML_TEST(block, CPR032(COP0_Status), SR_IE); // test [Status],SR_IE + UML_JMPc(block, COND_Z, skip); // jmp skip,Z + UML_TEST(block, CPR032(COP0_Status), SR_EXL | SR_ERL); // test [Status],SR_EXL | SR_ERL + UML_JMPc(block, COND_NZ, skip); // jmp skip,NZ + UML_MOV(block, I0, mem(&mips3->pc)); // mov i0,pc + UML_MOV(block, I1, 0); // mov i1,0 UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]); // callh exception_norecover UML_LABEL(block, skip); // skip: /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, MEM(&mips3->impstate->mode), MEM(&mips3->pc), *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&mips3->impstate->mode), mem(&mips3->pc), *mips3->impstate->nocode); // hashjmp <mode>,<pc>,nocode block->end(); } @@ -1041,10 +1041,10 @@ static void static_generate_nocode_handler(mips3_state *mips3) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &mips3->impstate->nocode, "nocode"); UML_HANDLE(block, *mips3->impstate->nocode); // handle nocode - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&mips3->pc), IREG(0)); // mov [pc],i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&mips3->pc), I0); // mov [pc],i0 save_fast_iregs(mips3, block); - UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); } @@ -1066,10 +1066,10 @@ static void static_generate_out_of_cycles(mips3_state *mips3) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &mips3->impstate->out_of_cycles, "out_of_cycles"); UML_HANDLE(block, *mips3->impstate->out_of_cycles); // handle out_of_cycles - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&mips3->pc), IREG(0)); // mov <pc>,i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&mips3->pc), I0); // mov <pc>,i0 save_fast_iregs(mips3, block); - UML_EXIT(block, IMM(EXECUTE_OUT_OF_CYCLES)); // exit EXECUTE_OUT_OF_CYCLES + UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); } @@ -1095,31 +1095,31 @@ static void static_generate_tlb_mismatch(mips3_state *mips3) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &mips3->impstate->tlb_mismatch, "tlb_mismatch"); UML_HANDLE(block, *mips3->impstate->tlb_mismatch); // handle tlb_mismatch - UML_RECOVER(block, IREG(0), MAPVAR_PC); // recover i0,PC - UML_MOV(block, MEM(&mips3->pc), IREG(0)); // mov <pc>,i0 - UML_SHR(block, IREG(1), IREG(0), IMM(12)); // shr i1,i0,12 - UML_LOAD(block, IREG(1), (void *)vtlb_table(mips3->vtlb), IREG(1), SIZE_DWORD, SCALE_x4);// load i1,[vtlb_table],i1,dword + UML_RECOVER(block, I0, MAPVAR_PC); // recover i0,PC + UML_MOV(block, mem(&mips3->pc), I0); // mov <pc>,i0 + UML_SHR(block, I1, I0, 12); // shr i1,i0,12 + UML_LOAD(block, I1, (void *)vtlb_table(mips3->vtlb), I1, SIZE_DWORD, SCALE_x4);// load i1,[vtlb_table],i1,dword if (PRINTF_MMU) { static const char text[] = "TLB mismatch @ %08X (ent=%08X)\n"; - UML_MOV(block, MEM(&mips3->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&mips3->impstate->arg0), IREG(0)); // mov [arg0],i0 - UML_MOV(block, MEM(&mips3->impstate->arg1), IREG(1)); // mov [arg1],i1 + UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&mips3->impstate->arg0), I0); // mov [arg0],i0 + UML_MOV(block, mem(&mips3->impstate->arg1), I1); // mov [arg1],i1 UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug } - UML_TEST(block, IREG(1), IMM(VTLB_FETCH_ALLOWED)); // test i1,VTLB_FETCH_ALLOWED - UML_JMPc(block, IF_NZ, 1); // jmp 1,nz - UML_TEST(block, IREG(1), IMM(VTLB_FLAG_FIXED)); // test i1,VTLB_FLAG_FIXED - UML_EXHc(block, IF_NZ, *mips3->impstate->exception[EXCEPTION_TLBLOAD], IREG(0)); // exh exception[TLBLOAD],i0,nz - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], IREG(0)); // exh exception[TLBLOAD_FILL],i0 + UML_TEST(block, I1, VTLB_FETCH_ALLOWED); // test i1,VTLB_FETCH_ALLOWED + UML_JMPc(block, COND_NZ, 1); // jmp 1,nz + UML_TEST(block, I1, VTLB_FLAG_FIXED); // test i1,VTLB_FLAG_FIXED + UML_EXHc(block, COND_NZ, *mips3->impstate->exception[EXCEPTION_TLBLOAD], I0); // exh exception[TLBLOAD],i0,nz + UML_EXH(block, *mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], I0); // exh exception[TLBLOAD_FILL],i0 UML_LABEL(block, 1); // 1: save_fast_iregs(mips3, block); // the saved PC may be set 1 instruction back with the low bit set to indicate // a delay slot; in this path we want the original instruction address, so recover it - UML_ADD(block, IREG(0), MEM(&mips3->pc), IMM(3)); // add i0,<pc>,3 - UML_AND(block, MEM(&mips3->pc), IREG(0), IMM(~3)); // and <pc>,i0,~3 - UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE + UML_ADD(block, I0, mem(&mips3->pc), 3); // add i0,<pc>,3 + UML_AND(block, mem(&mips3->pc), I0, ~3); // and <pc>,i0,~3 + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); } @@ -1157,47 +1157,47 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE || exception == EXCEPTION_TLBMOD || exception == EXCEPTION_ADDRLOAD || exception == EXCEPTION_ADDRSTORE) { /* set BadVAddr to the fault address */ - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_TEST(block, CPR032(COP0_Status), IMM(SR_EXL)); // test [Status],SR_EXL - UML_MOVc(block, IF_Z, CPR032(COP0_BadVAddr), IREG(0)); // mov [BadVAddr],i0,Z + UML_GETEXP(block, I0); // getexp i0 + UML_TEST(block, CPR032(COP0_Status), SR_EXL); // test [Status],SR_EXL + UML_MOVc(block, COND_Z, CPR032(COP0_BadVAddr), I0); // mov [BadVAddr],i0,Z } if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE) { /* set the upper bits of EntryHi and the lower bits of Context to the fault page */ - UML_ROLINS(block, CPR032(COP0_EntryHi), IREG(0), IMM(0), IMM(0xffffe000)); // rolins [EntryHi],i0,0,0xffffe000 - UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7ffff0)); // rolins [Context],i0,32-9,0x7ffff0 + UML_ROLINS(block, CPR032(COP0_EntryHi), I0, 0, 0xffffe000); // rolins [EntryHi],i0,0,0xffffe000 + UML_ROLINS(block, CPR032(COP0_Context), I0, 32-9, 0x7ffff0); // rolins [Context],i0,32-9,0x7ffff0 } /* set the EPC and Cause registers */ if (recover) { - UML_RECOVER(block, IREG(0), MAPVAR_PC); // recover i0,PC - UML_RECOVER(block, IREG(1), MAPVAR_CYCLES); // recover i1,CYCLES + UML_RECOVER(block, I0, MAPVAR_PC); // recover i0,PC + UML_RECOVER(block, I1, MAPVAR_CYCLES); // recover i1,CYCLES } - UML_AND(block, IREG(2), CPR032(COP0_Cause), IMM(~0x800000ff)); // and i2,[Cause],~0x800000ff - UML_TEST(block, IREG(0), IMM(1)); // test i0,1 - UML_JMPc(block, IF_Z, next); // jz <next> - UML_OR(block, IREG(2), IREG(2), IMM(0x80000000)); // or i2,i2,0x80000000 - UML_SUB(block, IREG(0), IREG(0), IMM(1)); // sub i0,i0,1 + UML_AND(block, I2, CPR032(COP0_Cause), ~0x800000ff); // and i2,[Cause],~0x800000ff + UML_TEST(block, I0, 1); // test i0,1 + UML_JMPc(block, COND_Z, next); // jz <next> + UML_OR(block, I2, I2, 0x80000000); // or i2,i2,0x80000000 + UML_SUB(block, I0, I0, 1); // sub i0,i0,1 UML_LABEL(block, next); // <next>: - UML_MOV(block, IREG(3), IMM(offset)); // mov i3,offset - UML_TEST(block, CPR032(COP0_Status), IMM(SR_EXL)); // test [Status],SR_EXL - UML_MOVc(block, IF_Z, CPR032(COP0_EPC), IREG(0)); // mov [EPC],i0,Z - UML_MOVc(block, IF_NZ, IREG(3), IMM(0x180)); // mov i3,0x180,NZ - UML_OR(block, CPR032(COP0_Cause), IREG(2), IMM(exception << 2)); // or [Cause],i2,exception << 2 + UML_MOV(block, I3, offset); // mov i3,offset + UML_TEST(block, CPR032(COP0_Status), SR_EXL); // test [Status],SR_EXL + UML_MOVc(block, COND_Z, CPR032(COP0_EPC), I0); // mov [EPC],i0,Z + UML_MOVc(block, COND_NZ, I3, 0x180); // mov i3,0x180,NZ + UML_OR(block, CPR032(COP0_Cause), I2, exception << 2); // or [Cause],i2,exception << 2 /* for BADCOP exceptions, we use the exception parameter to know which COP */ if (exception == EXCEPTION_BADCOP) { - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_ROLINS(block, CPR032(COP0_Cause), IREG(0), IMM(28), IMM(0x30000000)); // rolins [Cause],i0,28,0x30000000 + UML_GETEXP(block, I0); // getexp i0 + UML_ROLINS(block, CPR032(COP0_Cause), I0, 28, 0x30000000); // rolins [Cause],i0,28,0x30000000 } /* set EXL in the SR */ - UML_OR(block, IREG(0), CPR032(COP0_Status), IMM(SR_EXL)); // or i0,[Status],SR_EXL - UML_MOV(block, CPR032(COP0_Status), IREG(0)); // mov [Status],i0 + UML_OR(block, I0, CPR032(COP0_Status), SR_EXL); // or i0,[Status],SR_EXL + UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 generate_update_mode(mips3, block); /* optionally print exceptions */ @@ -1208,17 +1208,17 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r } /* choose our target PC */ - UML_ADD(block, IREG(0), IREG(3), IMM(0xbfc00200)); // add i0,i3,0xbfc00200 - UML_TEST(block, IREG(1), IMM(SR_BEV)); // test i1,SR_BEV - UML_JMPc(block, IF_NZ, skip); // jnz <skip> - UML_ADD(block, IREG(0), IREG(3), IMM(0x80000000)); // add i0,i3,0x80000000,z + UML_ADD(block, I0, I3, 0xbfc00200); // add i0,i3,0xbfc00200 + UML_TEST(block, I1, SR_BEV); // test i1,SR_BEV + UML_JMPc(block, COND_NZ, skip); // jnz <skip> + UML_ADD(block, I0, I3, 0x80000000); // add i0,i3,0x80000000,z UML_LABEL(block, skip); // <skip>: /* adjust cycles */ - UML_SUB(block, MEM(&mips3->icount), MEM(&mips3->icount), IREG(1)); // sub icount,icount,cycles,S - UML_EXHc(block, IF_S, *mips3->impstate->out_of_cycles, IREG(0)); // exh out_of_cycles,i0 + UML_SUB(block, mem(&mips3->icount), mem(&mips3->icount), I1); // sub icount,icount,cycles,S + UML_EXHc(block, COND_S, *mips3->impstate->out_of_cycles, I0); // exh out_of_cycles,i0 - UML_HASHJMP(block, MEM(&mips3->impstate->mode), IREG(0), *mips3->impstate->nocode);// hashjmp <mode>,i0,nocode + UML_HASHJMP(block, mem(&mips3->impstate->mode), I0, *mips3->impstate->nocode);// hashjmp <mode>,i0,nocode block->end(); } @@ -1252,28 +1252,28 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si /* user mode? generate address exception if top bit is set */ if (mode == MODE_USER) { - UML_TEST(block, IREG(0), IMM(0x80000000)); // test i0,0x80000000 - UML_EXHc(block, IF_NZ, exception_addrerr, IREG(0)); // exh addrerr,i0,nz + UML_TEST(block, I0, 0x80000000); // test i0,0x80000000 + UML_EXHc(block, COND_NZ, exception_addrerr, I0); // exh addrerr,i0,nz } /* supervisor mode? generate address exception if not in user space or in $C0000000-DFFFFFFF */ if (mode == MODE_SUPER) { int addrok; - UML_TEST(block, IREG(0), IMM(0x80000000)); // test i0,0x80000000 - UML_JMPc(block, IF_Z, addrok = label++); // jz addrok - UML_SHR(block, IREG(3), IREG(0), IMM(29)); // shr i3,i0,29 - UML_CMP(block, IREG(3), IMM(6)); // cmp i3,6 - UML_EXHc(block, IF_NE, exception_addrerr, IREG(0)); // exh addrerr,i0,ne + UML_TEST(block, I0, 0x80000000); // test i0,0x80000000 + UML_JMPc(block, COND_Z, addrok = label++); // jz addrok + UML_SHR(block, I3, I0, 29); // shr i3,i0,29 + UML_CMP(block, I3, 6); // cmp i3,6 + UML_EXHc(block, COND_NE, exception_addrerr, I0); // exh addrerr,i0,ne UML_LABEL(block, addrok); // addrok: } /* general case: assume paging and perform a translation */ - UML_SHR(block, IREG(3), IREG(0), IMM(12)); // shr i3,i0,12 - UML_LOAD(block, IREG(3), (void *)vtlb_table(mips3->vtlb), IREG(3), SIZE_DWORD, SCALE_x4);// load i3,[vtlb_table],i3,dword - UML_TEST(block, IREG(3), IMM(iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED));// test i3,iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED - UML_JMPc(block, IF_Z, tlbmiss = label++); // jmp tlbmiss,z - UML_ROLINS(block, IREG(0), IREG(3), IMM(0), IMM(0xfffff000)); // rolins i0,i3,0,0xfffff000 + UML_SHR(block, I3, I0, 12); // shr i3,i0,12 + UML_LOAD(block, I3, (void *)vtlb_table(mips3->vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb_table],i3,dword + UML_TEST(block, I3, iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED);// test i3,iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED + UML_JMPc(block, COND_Z, tlbmiss = label++); // jmp tlbmiss,z + UML_ROLINS(block, I0, I3, 0, 0xfffff000); // rolins i0,i3,0,0xfffff000 if ((mips3->device->machine->debug_flags & DEBUG_FLAG_ENABLED) == 0) for (ramnum = 0; ramnum < MIPS3_MAX_FASTRAM; ramnum++) @@ -1283,37 +1283,37 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si UINT32 skip = label++; if (mips3->impstate->fastram[ramnum].end != 0xffffffff) { - UML_CMP(block, IREG(0), IMM(mips3->impstate->fastram[ramnum].end)); // cmp i0,end - UML_JMPc(block, IF_A, skip); // ja skip + UML_CMP(block, I0, mips3->impstate->fastram[ramnum].end); // cmp i0,end + UML_JMPc(block, COND_A, skip); // ja skip } if (mips3->impstate->fastram[ramnum].start != 0x00000000) { - UML_CMP(block, IREG(0), IMM(mips3->impstate->fastram[ramnum].start));// cmp i0,fastram_start - UML_JMPc(block, IF_B, skip); // jb skip + UML_CMP(block, I0, mips3->impstate->fastram[ramnum].start);// cmp i0,fastram_start + UML_JMPc(block, COND_B, skip); // jb skip } if (!iswrite) { if (size == 1) { - UML_XOR(block, IREG(0), IREG(0), IMM(mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0))); + UML_XOR(block, I0, I0, mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); // xor i0,i0,bytexor - UML_LOAD(block, IREG(0), fastbase, IREG(0), SIZE_BYTE, SCALE_x1); // load i0,fastbase,i0,byte + UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1); // load i0,fastbase,i0,byte } else if (size == 2) { - UML_XOR(block, IREG(0), IREG(0), IMM(mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0))); + UML_XOR(block, I0, I0, mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); // xor i0,i0,wordxor - UML_LOAD(block, IREG(0), fastbase, IREG(0), SIZE_WORD, SCALE_x1); // load i0,fastbase,i0,word_x1 + UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1); // load i0,fastbase,i0,word_x1 } else if (size == 4) { - UML_LOAD(block, IREG(0), fastbase, IREG(0), SIZE_DWORD, SCALE_x1); // load i0,fastbase,i0,dword_x1 + UML_LOAD(block, I0, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i0,fastbase,i0,dword_x1 } else if (size == 8) { - UML_DLOAD(block, IREG(0), fastbase, IREG(0), SIZE_QWORD, SCALE_x1); // dload i0,fastbase,i0,qword_x1 - UML_DROR(block, IREG(0), IREG(0), IMM(32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)))); + UML_DLOAD(block, I0, fastbase, I0, SIZE_QWORD, SCALE_x1); // dload i0,fastbase,i0,qword_x1 + UML_DROR(block, I0, I0, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); // dror i0,i0,32*bytexor } UML_RET(block); // ret @@ -1322,41 +1322,41 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si { if (size == 1) { - UML_XOR(block, IREG(0), IREG(0), IMM(mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0))); + UML_XOR(block, I0, I0, mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); // xor i0,i0,bytexor - UML_STORE(block, fastbase, IREG(0), IREG(1), SIZE_BYTE, SCALE_x1);// store fastbase,i0,i1,byte + UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1);// store fastbase,i0,i1,byte } else if (size == 2) { - UML_XOR(block, IREG(0), IREG(0), IMM(mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0))); + UML_XOR(block, I0, I0, mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); // xor i0,i0,wordxor - UML_STORE(block, fastbase, IREG(0), IREG(1), SIZE_WORD, SCALE_x1);// store fastbase,i0,i1,word_x1 + UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1);// store fastbase,i0,i1,word_x1 } else if (size == 4) { if (ismasked) { - UML_LOAD(block, IREG(3), fastbase, IREG(0), SIZE_DWORD, SCALE_x1); // load i3,fastbase,i0,dword_x1 - UML_ROLINS(block, IREG(3), IREG(1), IMM(0), IREG(2)); // rolins i3,i1,0,i2 - UML_STORE(block, fastbase, IREG(0), IREG(3), SIZE_DWORD, SCALE_x1); // store fastbase,i0,i3,dword_x1 + UML_LOAD(block, I3, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i3,fastbase,i0,dword_x1 + UML_ROLINS(block, I3, I1, 0, I2); // rolins i3,i1,0,i2 + UML_STORE(block, fastbase, I0, I3, SIZE_DWORD, SCALE_x1); // store fastbase,i0,i3,dword_x1 } else - UML_STORE(block, fastbase, IREG(0), IREG(1), SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1 + UML_STORE(block, fastbase, I0, I1, SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1 } else if (size == 8) { - UML_DROR(block, IREG(1), IREG(1), IMM(32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)))); + UML_DROR(block, I1, I1, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); // dror i1,i1,32*bytexor if (ismasked) { - UML_DROR(block, IREG(2), IREG(2), IMM(32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)))); + UML_DROR(block, I2, I2, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); // dror i2,i2,32*bytexor - UML_DLOAD(block, IREG(3), fastbase, IREG(0), SIZE_QWORD, SCALE_x1); // dload i3,fastbase,i0,qword_x1 - UML_DROLINS(block, IREG(3), IREG(1), IMM(0), IREG(2)); // drolins i3,i1,0,i2 - UML_DSTORE(block, fastbase, IREG(0), IREG(3), SIZE_QWORD, SCALE_x1); // dstore fastbase,i0,i3,qword_x1 + UML_DLOAD(block, I3, fastbase, I0, SIZE_QWORD, SCALE_x1); // dload i3,fastbase,i0,qword_x1 + UML_DROLINS(block, I3, I1, 0, I2); // drolins i3,i1,0,i2 + UML_DSTORE(block, fastbase, I0, I3, SIZE_QWORD, SCALE_x1); // dstore fastbase,i0,i3,qword_x1 } else - UML_DSTORE(block, fastbase, IREG(0), IREG(1), SIZE_QWORD, SCALE_x1); // dstore fastbase,i0,i1,qword_x1 + UML_DSTORE(block, fastbase, I0, I1, SIZE_QWORD, SCALE_x1); // dstore fastbase,i0,i1,qword_x1 } UML_RET(block); // ret } @@ -1368,32 +1368,32 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si { case 1: if (iswrite) - UML_WRITE(block, IREG(0), IREG(1), SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte + UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte else - UML_READ(block, IREG(0), IREG(0), SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte + UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte break; case 2: if (iswrite) - UML_WRITE(block, IREG(0), IREG(1), SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word + UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word else - UML_READ(block, IREG(0), IREG(0), SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word + UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word break; case 4: if (iswrite) { if (!ismasked) - UML_WRITE(block, IREG(0), IREG(1), SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword + UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword else - UML_WRITEM(block, IREG(0), IREG(1), IREG(2), SIZE_DWORD, SPACE_PROGRAM); // writem i0,i1,i2,program_dword + UML_WRITEM(block, I0, I1, I2, SIZE_DWORD, SPACE_PROGRAM); // writem i0,i1,i2,program_dword } else { if (!ismasked) - UML_READ(block, IREG(0), IREG(0), SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword + UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword else - UML_READM(block, IREG(0), IREG(0), IREG(2), SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword + UML_READM(block, I0, I0, I2, SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword } break; @@ -1401,16 +1401,16 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si if (iswrite) { if (!ismasked) - UML_DWRITE(block, IREG(0), IREG(1), SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword + UML_DWRITE(block, I0, I1, SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword else - UML_DWRITEM(block, IREG(0), IREG(1), IREG(2), SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i1,i2,program_qword + UML_DWRITEM(block, I0, I1, I2, SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i1,i2,program_qword } else { if (!ismasked) - UML_DREAD(block, IREG(0), IREG(0), SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword + UML_DREAD(block, I0, I0, SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword else - UML_DREADM(block, IREG(0), IREG(0), IREG(2), SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword + UML_DREADM(block, I0, I0, I2, SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword } break; } @@ -1421,13 +1421,13 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si UML_LABEL(block, tlbmiss); // tlbmiss: if (iswrite) { - UML_TEST(block, IREG(3), IMM(VTLB_READ_ALLOWED)); // test i3,VTLB_READ_ALLOWED - UML_EXHc(block, IF_NZ, *mips3->impstate->exception[EXCEPTION_TLBMOD], IREG(0)); + UML_TEST(block, I3, VTLB_READ_ALLOWED); // test i3,VTLB_READ_ALLOWED + UML_EXHc(block, COND_NZ, *mips3->impstate->exception[EXCEPTION_TLBMOD], I0); // exh tlbmod,i0,nz } - UML_TEST(block, IREG(3), IMM(VTLB_FLAG_FIXED)); // test i3,VTLB_FLAG_FIXED - UML_EXHc(block, IF_NZ, exception_tlb, IREG(0)); // exh tlb,i0,nz - UML_EXH(block, exception_tlbfill, IREG(0)); // exh tlbfill,i0 + UML_TEST(block, I3, VTLB_FLAG_FIXED); // test i3,VTLB_FLAG_FIXED + UML_EXHc(block, COND_NZ, exception_tlb, I0); // exh tlb,i0,nz + UML_EXH(block, exception_tlbfill, I0); // exh tlbfill,i0 } block->end(); @@ -1446,11 +1446,11 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si static void generate_update_mode(mips3_state *mips3, drcuml_block *block) { - UML_ROLAND(block, IREG(2), IREG(0), IMM(32-2), IMM(0x06)); // roland i2,i0,32-2,0x06 - UML_TEST(block, IREG(0), IMM(SR_EXL | SR_ERL)); // test i0,SR_EXL | SR_ERL - UML_MOVc(block, IF_NZ, IREG(2), IMM(0)); // mov i2,0,nz - UML_ROLINS(block, IREG(2), IREG(0), IMM(32-26), IMM(0x01)); // rolins i2,i0,32-26,0x01 - UML_MOV(block, MEM(&mips3->impstate->mode), IREG(2)); // mov [mode],i2 + UML_ROLAND(block, I2, I0, 32-2, 0x06); // roland i2,i0,32-2,0x06 + UML_TEST(block, I0, SR_EXL | SR_ERL); // test i0,SR_EXL | SR_ERL + UML_MOVc(block, COND_NZ, I2, 0); // mov i2,0,nz + UML_ROLINS(block, I2, I0, 32-26, 0x01); // rolins i2,i0,32-26,0x01 + UML_MOV(block, mem(&mips3->impstate->mode), I2); // mov [mode],i2 } @@ -1468,11 +1468,11 @@ static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, comp code_label skip; compiler->checksoftints = FALSE; - UML_AND(block, IREG(0), CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] - UML_AND(block, IREG(0), IREG(0), IMM(0x0300)); // and i0,i0,0x0300 - UML_JMPc(block, IF_Z, skip = compiler->labelnum++); // jmp skip,Z - UML_MOV(block, IREG(0), param); // mov i0,nextpc - UML_MOV(block, IREG(1), IMM(compiler->cycles)); // mov i1,cycles + UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] + UML_AND(block, I0, I0, 0x0300); // and i0,i0,0x0300 + UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z + UML_MOV(block, I0, param); // mov i0,nextpc + UML_MOV(block, I1, compiler->cycles); // mov i1,cycles UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);// callh interrupt_norecover UML_LABEL(block, skip); // skip: } @@ -1483,15 +1483,15 @@ static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, comp code_label skip; compiler->checkints = FALSE; - UML_AND(block, IREG(0), CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] - UML_AND(block, IREG(0), IREG(0), IMM(0xfc00)); // and i0,i0,0xfc00 - UML_JMPc(block, IF_Z, skip = compiler->labelnum++); // jmp skip,Z - UML_TEST(block, CPR032(COP0_Status), IMM(SR_IE)); // test [Status],SR_IE - UML_JMPc(block, IF_Z, skip); // jmp skip,Z - UML_TEST(block, CPR032(COP0_Status), IMM(SR_EXL | SR_ERL)); // test [Status],SR_EXL | SR_ERL - UML_JMPc(block, IF_NZ, skip); // jmp skip,NZ - UML_MOV(block, IREG(0), param); // mov i0,nextpc - UML_MOV(block, IREG(1), IMM(compiler->cycles)); // mov i1,cycles + UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] + UML_AND(block, I0, I0, 0xfc00); // and i0,i0,0xfc00 + UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z + UML_TEST(block, CPR032(COP0_Status), SR_IE); // test [Status],SR_IE + UML_JMPc(block, COND_Z, skip); // jmp skip,Z + UML_TEST(block, CPR032(COP0_Status), SR_EXL | SR_ERL); // test [Status],SR_EXL | SR_ERL + UML_JMPc(block, COND_NZ, skip); // jmp skip,NZ + UML_MOV(block, I0, param); // mov i0,nextpc + UML_MOV(block, I1, compiler->cycles); // mov i1,cycles UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);// callh interrupt_norecover UML_LABEL(block, skip); // skip: } @@ -1499,10 +1499,10 @@ static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, comp /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, MEM(&mips3->icount), MEM(&mips3->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_SUB(block, mem(&mips3->icount), mem(&mips3->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 if (allow_exception) - UML_EXHc(block, IF_S, *mips3->impstate->out_of_cycles, param); + UML_EXHc(block, COND_S, *mips3->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; @@ -1526,9 +1526,9 @@ static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, com if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP)) { void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,0,dword - UML_CMP(block, IREG(0), IMM(seqhead->opptr.l[0])); // cmp i0,opptr[0] - UML_EXHc(block, IF_NE, *mips3->impstate->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_CMP(block, I0, seqhead->opptr.l[0]); // cmp i0,opptr[0] + UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -1540,33 +1540,33 @@ static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, com if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,0,dword - UML_CMP(block, IREG(0), IMM(curdesc->opptr.l[0])); // cmp i0,opptr[0] - UML_EXHc(block, IF_NE, *mips3->impstate->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_CMP(block, I0, curdesc->opptr.l[0]); // cmp i0,opptr[0] + UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc } #else UINT32 sum = 0; void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword sum += seqhead->opptr.l[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { base = mips3->direct->read_decrypted_ptr(curdesc->physpc); - UML_LOAD(block, IREG(1), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, IREG(0), IREG(0), IREG(1)); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.l[0]; if (curdesc->delay.first() != NULL && (curdesc == seqlast || (curdesc->next() != NULL && curdesc->next()->physpc != curdesc->delay.first()->physpc))) { base = mips3->direct->read_decrypted_ptr(curdesc->delay.first()->physpc); - UML_LOAD(block, IREG(1), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, IREG(0), IREG(0), IREG(1)); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->delay.first()->opptr.l[0]; } } - UML_CMP(block, IREG(0), IMM(sum)); // cmp i0,sum - UML_EXHc(block, IF_NE, *mips3->impstate->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_CMP(block, I0, sum); // cmp i0,sum + UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc #endif } } @@ -1607,24 +1607,24 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc /* if we want a probe, add it here */ if (desc->pc == PROBE_ADDRESS) { - UML_MOV(block, MEM(&mips3->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc UML_CALLC(block, cfunc_printf_probe, mips3); // callc cfunc_printf_probe,mips3 } /* if we are debugging, call the debugger */ if ((mips3->device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, MEM(&mips3->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(mips3, block); - UML_DEBUG(block, IMM(desc->pc)); // debug desc->pc + UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, MEM(&mips3->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(mips3, block); - UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE + UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } /* if we hit a compiler page fault, it's just like a TLB mismatch */ @@ -1633,11 +1633,11 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc if (PRINTF_MMU) { static const char text[] = "Compiler page fault @ %08X"; - UML_MOV(block, MEM(&mips3->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&mips3->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc + UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc); // mov [arg0],desc->pc UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug } - UML_EXH(block, *mips3->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0 + UML_EXH(block, *mips3->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 } /* validate our TLB entry at this PC; if we fail, we need to handle it */ @@ -1651,13 +1651,13 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc if (PRINTF_MMU) { static const char text[] = "Checking TLB at @ %08X\n"; - UML_MOV(block, MEM(&mips3->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&mips3->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc + UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc); // mov [arg0],desc->pc UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug } - UML_LOAD(block, IREG(0), &tlbtable[desc->pc >> 12], IMM(0), SIZE_DWORD, SCALE_x4); // load i0,tlbtable[desc->pc >> 12],0,dword - UML_CMP(block, IREG(0), IMM(tlbtable[desc->pc >> 12])); // cmp i0,*tlbentry - UML_EXHc(block, IF_NE, *mips3->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0,NE + UML_LOAD(block, I0, &tlbtable[desc->pc >> 12], 0, SIZE_DWORD, SCALE_x4); // load i0,tlbtable[desc->pc >> 12],0,dword + UML_CMP(block, I0, tlbtable[desc->pc >> 12]); // cmp i0,*tlbentry + UML_EXHc(block, COND_NE, *mips3->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0,NE } /* otherwise, we generate an unconditional exception */ @@ -1666,17 +1666,17 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc if (PRINTF_MMU) { static const char text[] = "No valid TLB @ %08X\n"; - UML_MOV(block, MEM(&mips3->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&mips3->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc + UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc); // mov [arg0],desc->pc UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug } - UML_EXH(block, *mips3->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0 + UML_EXH(block, *mips3->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 } } /* if this is an invalid opcode, generate the exception now */ if (desc->flags & OPFLAG_INVALID_OPCODE) - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], IMM(0)); // exh invalidop,0 + UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], 0); // exh invalidop,0 /* otherwise, unless this is a virtual no-op, it's a regular instruction */ else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP)) @@ -1684,8 +1684,8 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc /* compile the instruction */ if (!generate_opcode(mips3, block, compiler, desc)) { - UML_MOV(block, MEM(&mips3->pc), IMM(desc->pc)); // mov [pc],desc->pc - UML_MOV(block, MEM(&mips3->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&mips3->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_unimplemented, mips3); // callc cfunc_unimplemented } } @@ -1703,11 +1703,11 @@ static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *blo /* fetch the target register if dynamic, in case it is modified by the delay slot */ if (desc->targetpc == BRANCH_TARGET_DYNAMIC) - UML_MOV(block, MEM(&mips3->impstate->jmpdest), R32(RSREG)); // mov [jmpdest],<rsreg> + UML_MOV(block, mem(&mips3->impstate->jmpdest), R32(RSREG)); // mov [jmpdest],<rsreg> /* set the link if needed -- before the delay slot */ if (linkreg != 0) - UML_DMOV(block, R64(linkreg), IMM((INT32)(desc->pc + 8))); // dmov <linkreg>,desc->pc + 8 + UML_DMOV(block, R64(linkreg), (INT32)(desc->pc + 8)); // dmov <linkreg>,desc->pc + 8 /* compile the delay slot using temporary compiler state */ assert(desc->delay.first() != NULL); @@ -1716,18 +1716,18 @@ static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *blo /* update the cycles and jump through the hash table to the target */ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { - generate_update_cycles(mips3, block, &compiler_temp, IMM(desc->targetpc), TRUE); // <subtract cycles> + generate_update_cycles(mips3, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000 else - UML_HASHJMP(block, IMM(mips3->impstate->mode), IMM(desc->targetpc), *mips3->impstate->nocode); + UML_HASHJMP(block, mips3->impstate->mode, desc->targetpc, *mips3->impstate->nocode); // hashjmp <mode>,desc->targetpc,nocode } else { - generate_update_cycles(mips3, block, &compiler_temp, MEM(&mips3->impstate->jmpdest), TRUE); + generate_update_cycles(mips3, block, &compiler_temp, mem(&mips3->impstate->jmpdest), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(mips3->impstate->mode), MEM(&mips3->impstate->jmpdest), *mips3->impstate->nocode); + UML_HASHJMP(block, mips3->impstate->mode, mem(&mips3->impstate->jmpdest), *mips3->impstate->nocode); // hashjmp <mode>,<rsreg>,nocode } @@ -1779,7 +1779,7 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x04: /* BEQ - MIPS I */ case 0x14: /* BEQL - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_JMPc(block, IF_NE, skip = compiler->labelnum++); // jmp skip,NE + UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -1787,7 +1787,7 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x05: /* BNE - MIPS I */ case 0x15: /* BNEL - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_JMPc(block, IF_E, skip = compiler->labelnum++); // jmp skip,E + UML_JMPc(block, COND_E, skip = compiler->labelnum++); // jmp skip,E generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -1796,8 +1796,8 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x16: /* BLEZL - MIPS II */ if (RSREG != 0) { - UML_DCMP(block, R64(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_G, skip = compiler->labelnum++); // jmp skip,G + UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_G, skip = compiler->labelnum++); // jmp skip,G generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: } @@ -1807,8 +1807,8 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x07: /* BGTZ - MIPS I */ case 0x17: /* BGTZL - MIPS II */ - UML_DCMP(block, R64(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_LE, skip = compiler->labelnum++); // jmp skip,LE + UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_LE, skip = compiler->labelnum++); // jmp skip,LE generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -1818,68 +1818,68 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x0f: /* LUI - MIPS I */ if (RTREG != 0) - UML_DMOV(block, R64(RTREG), IMM(SIMMVAL << 16)); // dmov <rtreg>,SIMMVAL << 16 + UML_DMOV(block, R64(RTREG), SIMMVAL << 16); // dmov <rtreg>,SIMMVAL << 16 return TRUE; case 0x08: /* ADDI - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) - UML_EXHc(block, IF_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); + UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0 if (RTREG != 0) - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_DWORD); // dsext <rtreg>,i0,dword + UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword return TRUE; case 0x09: /* ADDIU - MIPS I */ if (RTREG != 0) { - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL,V - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_DWORD); // dsext <rtreg>,i0,dword + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL,V + UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword } return TRUE; case 0x18: /* DADDI - MIPS III */ - UML_DADD(block, IREG(0), R64(RSREG), IMM(SIMMVAL)); // dadd i0,<rsreg>,SIMMVAL + UML_DADD(block, I0, R64(RSREG), SIMMVAL); // dadd i0,<rsreg>,SIMMVAL if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) - UML_EXHc(block, IF_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); + UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0 if (RTREG != 0) - UML_DMOV(block, R64(RTREG), IREG(0)); // dmov <rtreg>,i0 + UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 return TRUE; case 0x19: /* DADDIU - MIPS III */ if (RTREG != 0) - UML_DADD(block, R64(RTREG), R64(RSREG), IMM(SIMMVAL)); // dadd <rtreg>,<rsreg>,SIMMVAL + UML_DADD(block, R64(RTREG), R64(RSREG), SIMMVAL); // dadd <rtreg>,<rsreg>,SIMMVAL return TRUE; case 0x0c: /* ANDI - MIPS I */ if (RTREG != 0) - UML_DAND(block, R64(RTREG), R64(RSREG), IMM(UIMMVAL)); // dand <rtreg>,<rsreg>,UIMMVAL + UML_DAND(block, R64(RTREG), R64(RSREG), UIMMVAL); // dand <rtreg>,<rsreg>,UIMMVAL return TRUE; case 0x0d: /* ORI - MIPS I */ if (RTREG != 0) - UML_DOR(block, R64(RTREG), R64(RSREG), IMM(UIMMVAL)); // dor <rtreg>,<rsreg>,UIMMVAL + UML_DOR(block, R64(RTREG), R64(RSREG), UIMMVAL); // dor <rtreg>,<rsreg>,UIMMVAL return TRUE; case 0x0e: /* XORI - MIPS I */ if (RTREG != 0) - UML_DXOR(block, R64(RTREG), R64(RSREG), IMM(UIMMVAL)); // dxor <rtreg>,<rsreg>,UIMMVAL + UML_DXOR(block, R64(RTREG), R64(RSREG), UIMMVAL); // dxor <rtreg>,<rsreg>,UIMMVAL return TRUE; case 0x0a: /* SLTI - MIPS I */ if (RTREG != 0) { - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_DSETc(block, IF_L, R64(RTREG)); // dset <rtreg>,l + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_DSETc(block, COND_L, R64(RTREG)); // dset <rtreg>,l } return TRUE; case 0x0b: /* SLTIU - MIPS I */ if (RTREG != 0) { - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_DSETc(block, IF_B, R64(RTREG)); // dset <rtreg>,b + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_DSETc(block, COND_B, R64(RTREG)); // dset <rtreg>,b } return TRUE; @@ -1887,347 +1887,347 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta /* ----- memory load operations ----- */ case 0x20: /* LB - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read8[mips3->impstate->mode >> 1]); // callh read8 if (RTREG != 0) - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_BYTE); // dsext <rtreg>,i0,byte + UML_DSEXT(block, R64(RTREG), I0, SIZE_BYTE); // dsext <rtreg>,i0,byte if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x21: /* LH - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read16[mips3->impstate->mode >> 1]); // callh read16 if (RTREG != 0) - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_WORD); // dsext <rtreg>,i0,word + UML_DSEXT(block, R64(RTREG), I0, SIZE_WORD); // dsext <rtreg>,i0,word if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x23: /* LW - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 if (RTREG != 0) - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_DWORD); // dsext <rtreg>,i0 + UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x30: /* LL - MIPS II */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 if (RTREG != 0) - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_DWORD); // dsext <rtreg>,i0 - UML_MOV(block, MEM(&mips3->llbit), IMM(1)); // mov [llbit],1 + UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0 + UML_MOV(block, mem(&mips3->llbit), 1); // mov [llbit],1 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x24: /* LBU - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read8[mips3->impstate->mode >> 1]); // callh read8 if (RTREG != 0) - UML_DAND(block, R64(RTREG), IREG(0), IMM(0xff)); // dand <rtreg>,i0,0xff + UML_DAND(block, R64(RTREG), I0, 0xff); // dand <rtreg>,i0,0xff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x25: /* LHU - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read16[mips3->impstate->mode >> 1]); // callh read16 if (RTREG != 0) - UML_DAND(block, R64(RTREG), IREG(0), IMM(0xffff)); // dand <rtreg>,i0,0xffff + UML_DAND(block, R64(RTREG), I0, 0xffff); // dand <rtreg>,i0,0xffff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x27: /* LWU - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 if (RTREG != 0) - UML_DAND(block, R64(RTREG), IREG(0), IMM(0xffffffff)); // dand <rtreg>,i0,0xffffffff + UML_DAND(block, R64(RTREG), I0, 0xffffffff); // dand <rtreg>,i0,0xffffffff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x37: /* LD - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 if (RTREG != 0) - UML_DMOV(block, R64(RTREG), IREG(0)); // dmov <rtreg>,i0 + UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x34: /* LLD - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 if (RTREG != 0) - UML_DMOV(block, R64(RTREG), IREG(0)); // dmov <rtreg>,i0 - UML_MOV(block, MEM(&mips3->llbit), IMM(1)); // mov [llbit],1 + UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 + UML_MOV(block, mem(&mips3->llbit), 1); // mov [llbit],1 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x22: /* LWL - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(1), IREG(0), IMM(3)); // shl i1,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~3)); // and i0,i0,~3 + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I1, I0, 3); // shl i1,i0,3 + UML_AND(block, I0, I0, ~3); // and i0,i0,~3 if (!mips3->bigendian) - UML_XOR(block, IREG(1), IREG(1), IMM(0x18)); // xor i1,i1,0x18 - UML_SHR(block, IREG(2), IMM(~0), IREG(1)); // shr i2,~0,i1 + UML_XOR(block, I1, I1, 0x18); // xor i1,i1,0x18 + UML_SHR(block, I2, ~0, I1); // shr i2,~0,i1 UML_CALLH(block, *mips3->impstate->read32mask[mips3->impstate->mode >> 1]); // callh read32mask if (RTREG != 0) { - UML_SHL(block, IREG(2), IMM(~0), IREG(1)); // shl i2,~0,i1 - UML_MOV(block, IREG(3), R32(RTREG)); // mov i3,<rtreg> - UML_ROLINS(block, IREG(3), IREG(0), IREG(1), IREG(2)); // rolins i3,i0,i1,i2 - UML_DSEXT(block, R64(RTREG), IREG(3), SIZE_DWORD); // dsext <rtreg>,i3,dword + UML_SHL(block, I2, ~0, I1); // shl i2,~0,i1 + UML_MOV(block, I3, R32(RTREG)); // mov i3,<rtreg> + UML_ROLINS(block, I3, I0, I1, I2); // rolins i3,i0,i1,i2 + UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD); // dsext <rtreg>,i3,dword } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x26: /* LWR - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(1), IREG(0), IMM(3)); // shl i1,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~3)); // and i0,i0,~3 + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I1, I0, 3); // shl i1,i0,3 + UML_AND(block, I0, I0, ~3); // and i0,i0,~3 if (mips3->bigendian) - UML_XOR(block, IREG(1), IREG(1), IMM(0x18)); // xor i1,i1,0x18 - UML_SHL(block, IREG(2), IMM(~0), IREG(1)); // shl i2,~0,i1 + UML_XOR(block, I1, I1, 0x18); // xor i1,i1,0x18 + UML_SHL(block, I2, ~0, I1); // shl i2,~0,i1 UML_CALLH(block, *mips3->impstate->read32mask[mips3->impstate->mode >> 1]); // callh read32mask if (RTREG != 0) { - UML_SHR(block, IREG(2), IMM(~0), IREG(1)); // shr i2,~0,i1 - UML_SUB(block, IREG(1), IMM(32), IREG(1)); // sub i1,32,i1 - UML_MOV(block, IREG(3), R32(RTREG)); // mov i3,<rtreg> - UML_ROLINS(block, IREG(3), IREG(0), IREG(1), IREG(2)); // rolins i3,i0,i1,i2 - UML_DSEXT(block, R64(RTREG), IREG(3), SIZE_DWORD); // dsext <rtreg>,i3,dword + UML_SHR(block, I2, ~0, I1); // shr i2,~0,i1 + UML_SUB(block, I1, 32, I1); // sub i1,32,i1 + UML_MOV(block, I3, R32(RTREG)); // mov i3,<rtreg> + UML_ROLINS(block, I3, I0, I1, I2); // rolins i3,i0,i1,i2 + UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD); // dsext <rtreg>,i3,dword } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x1a: /* LDL - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(1), IREG(0), IMM(3)); // shl i1,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~7)); // and i0,i0,~7 + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I1, I0, 3); // shl i1,i0,3 + UML_AND(block, I0, I0, ~7); // and i0,i0,~7 if (!mips3->bigendian) - UML_XOR(block, IREG(1), IREG(1), IMM(0x38)); // xor i1,i1,0x38 - UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshr i2,~0,i1 + UML_XOR(block, I1, I1, 0x38); // xor i1,i1,0x38 + UML_DSHR(block, I2, (UINT64)~0, I1); // dshr i2,~0,i1 UML_CALLH(block, *mips3->impstate->read64mask[mips3->impstate->mode >> 1]); // callh read64mask if (RTREG != 0) { - UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshl i2,~0,i1 - UML_DROLINS(block, R64(RTREG), IREG(0), IREG(1), IREG(2)); // drolins <rtreg>,i0,i1,i2 + UML_DSHL(block, I2, (UINT64)~0, I1); // dshl i2,~0,i1 + UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2 } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x1b: /* LDR - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(1), IREG(0), IMM(3)); // shl i1,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~7)); // and i0,i0,~7 + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I1, I0, 3); // shl i1,i0,3 + UML_AND(block, I0, I0, ~7); // and i0,i0,~7 if (mips3->bigendian) - UML_XOR(block, IREG(1), IREG(1), IMM(0x38)); // xor i1,i1,0x38 - UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshl i2,~0,i1 + UML_XOR(block, I1, I1, 0x38); // xor i1,i1,0x38 + UML_DSHL(block, I2, (UINT64)~0, I1); // dshl i2,~0,i1 UML_CALLH(block, *mips3->impstate->read64mask[mips3->impstate->mode >> 1]); // callh read64mask if (RTREG != 0) { - UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshr i2,~0,i1 - UML_SUB(block, IREG(1), IMM(64), IREG(1)); // sub i1,64,i1 - UML_DROLINS(block, R64(RTREG), IREG(0), IREG(1), IREG(2)); // drolins <rtreg>,i0,i1,i2 + UML_DSHR(block, I2, (UINT64)~0, I1); // dshr i2,~0,i1 + UML_SUB(block, I1, 64, I1); // sub i1,64,i1 + UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2 } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x31: /* LWC1 - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 - UML_MOV(block, FPR32(RTREG), IREG(0)); // mov <cpr1_rt>,i0 + UML_MOV(block, FPR32(RTREG), I0); // mov <cpr1_rt>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x35: /* LDC1 - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 - UML_DMOV(block, FPR64(RTREG), IREG(0)); // dmov <cpr1_rt>,i0 + UML_DMOV(block, FPR64(RTREG), I0); // dmov <cpr1_rt>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x32: /* LWC2 - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 - UML_DAND(block, CPR264(RTREG), IREG(0), IMM(0xffffffff)); // dand <cpr2_rt>,i0,0xffffffff + UML_DAND(block, CPR264(RTREG), I0, 0xffffffff); // dand <cpr2_rt>,i0,0xffffffff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x36: /* LDC2 - MIPS II */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 - UML_DMOV(block, CPR264(RTREG), IREG(0)); // dmov <cpr2_rt>,i0 + UML_DMOV(block, CPR264(RTREG), I0); // dmov <cpr2_rt>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; /* ----- memory store operations ----- */ case 0x28: /* SB - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *mips3->impstate->write8[mips3->impstate->mode >> 1]); // callh write8 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x29: /* SH - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *mips3->impstate->write16[mips3->impstate->mode >> 1]); // callh write16 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2b: /* SW - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x38: /* SC - MIPS II */ - UML_CMP(block, MEM(&mips3->llbit), IMM(0)); // cmp [llbit],0 - UML_JMPc(block, IF_E, skip = compiler->labelnum++); // je skip - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_CMP(block, mem(&mips3->llbit), 0); // cmp [llbit],0 + UML_JMPc(block, COND_E, skip = compiler->labelnum++); // je skip + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 UML_LABEL(block, skip); // skip: - UML_DSEXT(block, R64(RTREG), MEM(&mips3->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword + UML_DSEXT(block, R64(RTREG), mem(&mips3->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3f: /* SD - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3c: /* SCD - MIPS III */ - UML_CMP(block, MEM(&mips3->llbit), IMM(0)); // cmp [llbit],0 - UML_JMPc(block, IF_E, skip = compiler->labelnum++); // je skip - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg> + UML_CMP(block, mem(&mips3->llbit), 0); // cmp [llbit],0 + UML_JMPc(block, COND_E, skip = compiler->labelnum++); // je skip + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 UML_LABEL(block, skip); // skip: - UML_DSEXT(block, R64(RTREG), MEM(&mips3->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword + UML_DSEXT(block, R64(RTREG), mem(&mips3->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2a: /* SWL - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(3), IREG(0), IMM(3)); // shl i3,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~3)); // and i0,i0,~3 - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I3, I0, 3); // shl i3,i0,3 + UML_AND(block, I0, I0, ~3); // and i0,i0,~3 + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> if (!mips3->bigendian) - UML_XOR(block, IREG(3), IREG(3), IMM(0x18)); // xor i3,i3,0x18 - UML_SHR(block, IREG(2), IMM(~0), IREG(3)); // shr i2,~0,i3 - UML_SHR(block, IREG(1), IREG(1), IREG(3)); // shr i1,i1,i3 + UML_XOR(block, I3, I3, 0x18); // xor i3,i3,0x18 + UML_SHR(block, I2, ~0, I3); // shr i2,~0,i3 + UML_SHR(block, I1, I1, I3); // shr i1,i1,i3 UML_CALLH(block, *mips3->impstate->write32mask[mips3->impstate->mode >> 1]); // callh write32mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2e: /* SWR - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(3), IREG(0), IMM(3)); // shl i3,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~3)); // and i0,i0,~3 - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I3, I0, 3); // shl i3,i0,3 + UML_AND(block, I0, I0, ~3); // and i0,i0,~3 + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> if (mips3->bigendian) - UML_XOR(block, IREG(3), IREG(3), IMM(0x18)); // xor i3,i3,0x18 - UML_SHL(block, IREG(2), IMM(~0), IREG(3)); // shl i2,~0,i3 - UML_SHL(block, IREG(1), IREG(1), IREG(3)); // shl i1,i1,i3 + UML_XOR(block, I3, I3, 0x18); // xor i3,i3,0x18 + UML_SHL(block, I2, ~0, I3); // shl i2,~0,i3 + UML_SHL(block, I1, I1, I3); // shl i1,i1,i3 UML_CALLH(block, *mips3->impstate->write32mask[mips3->impstate->mode >> 1]); // callh write32mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2c: /* SDL - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(3), IREG(0), IMM(3)); // shl i3,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~7)); // and i0,i0,~7 - UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I3, I0, 3); // shl i3,i0,3 + UML_AND(block, I0, I0, ~7); // and i0,i0,~7 + UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> if (!mips3->bigendian) - UML_XOR(block, IREG(3), IREG(3), IMM(0x38)); // xor i3,i3,0x38 - UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(3)); // dshr i2,~0,i3 - UML_DSHR(block, IREG(1), IREG(1), IREG(3)); // dshr i1,i1,i3 + UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38 + UML_DSHR(block, I2, (UINT64)~0, I3); // dshr i2,~0,i3 + UML_DSHR(block, I1, I1, I3); // dshr i1,i1,i3 UML_CALLH(block, *mips3->impstate->write64mask[mips3->impstate->mode >> 1]); // callh write64mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2d: /* SDR - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_SHL(block, IREG(3), IREG(0), IMM(3)); // shl i3,i0,3 - UML_AND(block, IREG(0), IREG(0), IMM(~7)); // and i0,i0,~7 - UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_SHL(block, I3, I0, 3); // shl i3,i0,3 + UML_AND(block, I0, I0, ~7); // and i0,i0,~7 + UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> if (mips3->bigendian) - UML_XOR(block, IREG(3), IREG(3), IMM(0x38)); // xor i3,i3,0x38 - UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(3)); // dshl i2,~0,i3 - UML_DSHL(block, IREG(1), IREG(1), IREG(3)); // dshl i1,i1,i3 + UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38 + UML_DSHL(block, I2, (UINT64)~0, I3); // dshl i2,~0,i3 + UML_DSHL(block, I1, I1, I3); // dshl i1,i1,i3 UML_CALLH(block, *mips3->impstate->write64mask[mips3->impstate->mode >> 1]); // callh write64mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x39: /* SWC1 - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), FPR32(RTREG)); // mov i1,<cpr1_rt> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, FPR32(RTREG)); // mov i1,<cpr1_rt> UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3d: /* SDC1 - MIPS III */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_DMOV(block, IREG(1), FPR64(RTREG)); // dmov i1,<cpr1_rt> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_DMOV(block, I1, FPR64(RTREG)); // dmov i1,<cpr1_rt> UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3a: /* SWC2 - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), CPR232(RTREG)); // mov i1,<cpr2_rt> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, CPR232(RTREG)); // mov i1,<cpr2_rt> UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3e: /* SDC2 - MIPS II */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_DMOV(block, IREG(1), CPR264(RTREG)); // dmov i1,<cpr2_rt> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_DMOV(block, I1, CPR264(RTREG)); // dmov i1,<cpr2_rt> UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; @@ -2250,7 +2250,7 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta return generate_cop1x(mips3, block, compiler, desc); case 0x12: /* COP2 - MIPS I */ - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], IMM(0));// exh invalidop,0 + UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], 0);// exh invalidop,0 return TRUE; @@ -2280,79 +2280,79 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x00: /* SLL - MIPS I */ if (RDREG != 0) { - UML_SHL(block, IREG(0), R32(RTREG), IMM(SHIFT)); // shl i0,<rtreg>,<shift> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SHL(block, I0, R32(RTREG), SHIFT); // shl i0,<rtreg>,<shift> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x02: /* SRL - MIPS I */ if (RDREG != 0) { - UML_SHR(block, IREG(0), R32(RTREG), IMM(SHIFT)); // shr i0,<rtreg>,<shift> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SHR(block, I0, R32(RTREG), SHIFT); // shr i0,<rtreg>,<shift> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x03: /* SRA - MIPS I */ if (RDREG != 0) { - UML_SAR(block, IREG(0), R32(RTREG), IMM(SHIFT)); // sar i0,<rtreg>,<shift> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SAR(block, I0, R32(RTREG), SHIFT); // sar i0,<rtreg>,<shift> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x04: /* SLLV - MIPS I */ if (RDREG != 0) { - UML_SHL(block, IREG(0), R32(RTREG), R32(RSREG)); // shl i0,<rtreg>,<rsreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SHL(block, I0, R32(RTREG), R32(RSREG)); // shl i0,<rtreg>,<rsreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x06: /* SRLV - MIPS I */ if (RDREG != 0) { - UML_SHR(block, IREG(0), R32(RTREG), R32(RSREG)); // shr i0,<rtreg>,<rsreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SHR(block, I0, R32(RTREG), R32(RSREG)); // shr i0,<rtreg>,<rsreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x07: /* SRAV - MIPS I */ if (RDREG != 0) { - UML_SAR(block, IREG(0), R32(RTREG), R32(RSREG)); // sar i0,<rtreg>,<rsreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SAR(block, I0, R32(RTREG), R32(RSREG)); // sar i0,<rtreg>,<rsreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x38: /* DSLL - MIPS III */ if (RDREG != 0) - UML_DSHL(block, R64(RDREG), R64(RTREG), IMM(SHIFT)); // dshl <rdreg>,<rtreg>,<shift> + UML_DSHL(block, R64(RDREG), R64(RTREG), SHIFT); // dshl <rdreg>,<rtreg>,<shift> return TRUE; case 0x3a: /* DSRL - MIPS III */ if (RDREG != 0) - UML_DSHR(block, R64(RDREG), R64(RTREG), IMM(SHIFT)); // dshr <rdreg>,<rtreg>,<shift> + UML_DSHR(block, R64(RDREG), R64(RTREG), SHIFT); // dshr <rdreg>,<rtreg>,<shift> return TRUE; case 0x3b: /* DSRA - MIPS III */ if (RDREG != 0) - UML_DSAR(block, R64(RDREG), R64(RTREG), IMM(SHIFT)); // dsar <rdreg>,<rtreg>,<shift> + UML_DSAR(block, R64(RDREG), R64(RTREG), SHIFT); // dsar <rdreg>,<rtreg>,<shift> return TRUE; case 0x3c: /* DSLL32 - MIPS III */ if (RDREG != 0) - UML_DSHL(block, R64(RDREG), R64(RTREG), IMM(SHIFT + 32)); // dshl <rdreg>,<rtreg>,<shift>+32 + UML_DSHL(block, R64(RDREG), R64(RTREG), SHIFT + 32); // dshl <rdreg>,<rtreg>,<shift>+32 return TRUE; case 0x3e: /* DSRL32 - MIPS III */ if (RDREG != 0) - UML_DSHR(block, R64(RDREG), R64(RTREG), IMM(SHIFT + 32)); // dshr <rdreg>,<rtreg>,<shift>+32 + UML_DSHR(block, R64(RDREG), R64(RTREG), SHIFT + 32); // dshr <rdreg>,<rtreg>,<shift>+32 return TRUE; case 0x3f: /* DSRA32 - MIPS III */ if (RDREG != 0) - UML_DSAR(block, R64(RDREG), R64(RTREG), IMM(SHIFT + 32)); // dsar <rdreg>,<rtreg>,<shift>+32 + UML_DSAR(block, R64(RDREG), R64(RTREG), SHIFT + 32); // dsar <rdreg>,<rtreg>,<shift>+32 return TRUE; case 0x14: /* DSLLV - MIPS III */ @@ -2376,35 +2376,35 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x20: /* ADD - MIPS I */ if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_EXHc(block, IF_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } else if (RDREG != 0) { - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x21: /* ADDU - MIPS I */ if (RDREG != 0) { - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x2c: /* DADD - MIPS III */ if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { - UML_DADD(block, IREG(0), R64(RSREG), R64(RTREG)); // dadd i0,<rsreg>,<rtreg> - UML_EXHc(block, IF_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); + UML_DADD(block, I0, R64(RSREG), R64(RTREG)); // dadd i0,<rsreg>,<rtreg> + UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) - UML_DMOV(block, R64(RDREG), IREG(0)); // dmov <rdreg>,i0 + UML_DMOV(block, R64(RDREG), I0); // dmov <rdreg>,i0 } else if (RDREG != 0) UML_DADD(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dadd <rdreg>,<rsreg>,<rtreg> @@ -2418,35 +2418,35 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x22: /* SUB - MIPS I */ if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { - UML_SUB(block, IREG(0), R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> - UML_EXHc(block, IF_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); + UML_SUB(block, I0, R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> + UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } else if (RDREG != 0) { - UML_SUB(block, IREG(0), R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SUB(block, I0, R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x23: /* SUBU - MIPS I */ if (RDREG != 0) { - UML_SUB(block, IREG(0), R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext <rdreg>,i0,dword + UML_SUB(block, I0, R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword } return TRUE; case 0x2e: /* DSUB - MIPS III */ if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { - UML_DSUB(block, IREG(0), R64(RSREG), R64(RTREG)); // dsub i0,<rsreg>,<rtreg> - UML_EXHc(block, IF_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); + UML_DSUB(block, I0, R64(RSREG), R64(RTREG)); // dsub i0,<rsreg>,<rtreg> + UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) - UML_DMOV(block, R64(RDREG), IREG(0)); // dmov <rdreg>,i0 + UML_DMOV(block, R64(RDREG), I0); // dmov <rdreg>,i0 } else if (RDREG != 0) UML_DSUB(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dsub <rdreg>,<rsreg>,<rtreg> @@ -2458,15 +2458,15 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st return TRUE; case 0x18: /* MULT - MIPS I */ - UML_MULS(block, IREG(0), IREG(1), R32(RSREG), R32(RTREG)); // muls i0,i1,<rsreg>,<rtreg> - UML_DSEXT(block, LO64, IREG(0), SIZE_DWORD); // dsext lo,i0,dword - UML_DSEXT(block, HI64, IREG(1), SIZE_DWORD); // dsext hi,i1,dword + UML_MULS(block, I0, I1, R32(RSREG), R32(RTREG)); // muls i0,i1,<rsreg>,<rtreg> + UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword + UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword return TRUE; case 0x19: /* MULTU - MIPS I */ - UML_MULU(block, IREG(0), IREG(1), R32(RSREG), R32(RTREG)); // mulu i0,i1,<rsreg>,<rtreg> - UML_DSEXT(block, LO64, IREG(0), SIZE_DWORD); // dsext lo,i0,dword - UML_DSEXT(block, HI64, IREG(1), SIZE_DWORD); // dsext hi,i1,dword + UML_MULU(block, I0, I1, R32(RSREG), R32(RTREG)); // mulu i0,i1,<rsreg>,<rtreg> + UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword + UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword return TRUE; case 0x1c: /* DMULT - MIPS III */ @@ -2478,15 +2478,15 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st return TRUE; case 0x1a: /* DIV - MIPS I */ - UML_DIVS(block, IREG(0), IREG(1), R32(RSREG), R32(RTREG)); // divs i0,i1,<rsreg>,<rtreg> - UML_DSEXT(block, LO64, IREG(0), SIZE_DWORD); // dsext lo,i0,dword - UML_DSEXT(block, HI64, IREG(1), SIZE_DWORD); // dsext hi,i1,dword + UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG)); // divs i0,i1,<rsreg>,<rtreg> + UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword + UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword return TRUE; case 0x1b: /* DIVU - MIPS I */ - UML_DIVU(block, IREG(0), IREG(1), R32(RSREG), R32(RTREG)); // divu i0,i1,<rsreg>,<rtreg> - UML_DSEXT(block, LO64, IREG(0), SIZE_DWORD); // dsext lo,i0,dword - UML_DSEXT(block, HI64, IREG(1), SIZE_DWORD); // dsext hi,i1,dword + UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG)); // divu i0,i1,<rsreg>,<rtreg> + UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword + UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword return TRUE; case 0x1e: /* DDIV - MIPS III */ @@ -2518,8 +2518,8 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x27: /* NOR - MIPS I */ if (RDREG != 0) { - UML_DOR(block, IREG(0), R64(RSREG), R64(RTREG)); // dor i0,<rsreg>,<rtreg> - UML_DXOR(block, R64(RDREG), IREG(0), IMM((UINT64)~0)); // dxor <rdreg>,i0,~0 + UML_DOR(block, I0, R64(RSREG), R64(RTREG)); // dor i0,<rsreg>,<rtreg> + UML_DXOR(block, R64(RDREG), I0, (UINT64)~0); // dxor <rdreg>,i0,~0 } return TRUE; @@ -2530,7 +2530,7 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st if (RDREG != 0) { UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_DSETc(block, IF_L, R64(RDREG)); // dset <rdreg>,l + UML_DSETc(block, COND_L, R64(RDREG)); // dset <rdreg>,l } return TRUE; @@ -2538,7 +2538,7 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st if (RDREG != 0) { UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_DSETc(block, IF_B, R64(RDREG)); // dset <rdreg>,b + UML_DSETc(block, COND_B, R64(RDREG)); // dset <rdreg>,b } return TRUE; @@ -2547,32 +2547,32 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x30: /* TGE - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, IF_GE, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,GE + UML_EXHc(block, COND_GE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,GE return TRUE; case 0x31: /* TGEU - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, IF_AE, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,AE + UML_EXHc(block, COND_AE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,AE return TRUE; case 0x32: /* TLT - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, IF_L, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,LT + UML_EXHc(block, COND_L, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,LT return TRUE; case 0x33: /* TLTU - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, IF_B, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,B + UML_EXHc(block, COND_B, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,B return TRUE; case 0x34: /* TEQ - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, IF_E, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,E + UML_EXHc(block, COND_E, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,E return TRUE; case 0x36: /* TNE - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, IF_NE, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,NE + UML_EXHc(block, COND_NE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,NE return TRUE; @@ -2581,24 +2581,24 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x0a: /* MOVZ - MIPS IV */ if (RDREG != 0) { - UML_DCMP(block, R64(RTREG), IMM(0)); // dcmp <rtreg>,0 - UML_DMOVc(block, IF_Z, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,Z + UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0 + UML_DMOVc(block, COND_Z, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,Z } return TRUE; case 0x0b: /* MOVN - MIPS IV */ if (RDREG != 0) { - UML_DCMP(block, R64(RTREG), IMM(0)); // dcmp <rtreg>,0 - UML_DMOVc(block, IF_NZ, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,NZ + UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0 + UML_DMOVc(block, COND_NZ, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,NZ } return TRUE; case 0x01: /* MOVF/MOVT - MIPS IV */ if (RDREG != 0) { - UML_TEST(block, CCR132(31), IMM(FCCMASK(op >> 18))); // test ccr31,fcc_mask[x] - UML_DMOVc(block, ((op >> 16) & 1) ? IF_NZ : IF_Z, R64(RDREG), R64(RSREG)); + UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr31,fcc_mask[x] + UML_DMOVc(block, ((op >> 16) & 1) ? COND_NZ : COND_Z, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,NZ/Z } return TRUE; @@ -2618,11 +2618,11 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st /* ----- system calls ----- */ case 0x0c: /* SYSCALL - MIPS I */ - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_SYSCALL], IMM(0)); // exh syscall,0 + UML_EXH(block, *mips3->impstate->exception[EXCEPTION_SYSCALL], 0); // exh syscall,0 return TRUE; case 0x0d: /* BREAK - MIPS I */ - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_BREAK], IMM(0)); // exh break,0 + UML_EXH(block, *mips3->impstate->exception[EXCEPTION_BREAK], 0); // exh break,0 return TRUE; @@ -2675,8 +2675,8 @@ static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x12: /* BLTZALL */ if (RSREG != 0) { - UML_DCMP(block, R64(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_GE, skip = compiler->labelnum++); // jmp skip,GE + UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_GE, skip = compiler->labelnum++); // jmp skip,GE generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: @@ -2689,8 +2689,8 @@ static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x13: /* BGEZALL */ if (RSREG != 0) { - UML_DCMP(block, R64(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_L, skip = compiler->labelnum++); // jmp skip,L + UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_L, skip = compiler->labelnum++); // jmp skip,L generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: @@ -2701,33 +2701,33 @@ static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_sta return TRUE; case 0x08: /* TGEI */ - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, IF_GE, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,GE + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_EXHc(block, COND_GE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,GE return TRUE; case 0x09: /* TGEIU */ - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, IF_AE, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,AE + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_EXHc(block, COND_AE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,AE return TRUE; case 0x0a: /* TLTI */ - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, IF_L, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,L + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_EXHc(block, COND_L, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,L return TRUE; case 0x0b: /* TLTIU */ - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, IF_B, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,B + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_EXHc(block, COND_B, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,B return TRUE; case 0x0c: /* TEQI */ - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, IF_E, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,E + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_EXHc(block, COND_E, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,E return TRUE; case 0x0e: /* TNEI */ - UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, IF_NE, *mips3->impstate->exception[EXCEPTION_TRAP], IMM(0));// exh trap,0,NE + UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_EXHc(block, COND_NE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,NE return TRUE; } return FALSE; @@ -2753,30 +2753,30 @@ static int generate_idt(mips3_state *mips3, drcuml_block *block, compiler_state case 0: /* MAD */ if (RSREG != 0 && RTREG != 0) { - UML_MULS(block, IREG(0), IREG(1), R32(RSREG), R32(RTREG)); // muls i0,i1,rsreg,rtreg - UML_ADD(block, IREG(0), IREG(0), LO32); // add i0,i0,lo - UML_ADDC(block, IREG(1), IREG(1), HI32); // addc i1,i1,hi - UML_DSEXT(block, LO64, IREG(0), SIZE_DWORD); // dsext lo,i0,dword - UML_DSEXT(block, HI64, IREG(1), SIZE_DWORD); // dsext hi,i1,dword + UML_MULS(block, I0, I1, R32(RSREG), R32(RTREG)); // muls i0,i1,rsreg,rtreg + UML_ADD(block, I0, I0, LO32); // add i0,i0,lo + UML_ADDC(block, I1, I1, HI32); // addc i1,i1,hi + UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword + UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword } return TRUE; case 1: /* MADU */ if (RSREG != 0 && RTREG != 0) { - UML_MULU(block, IREG(0), IREG(1), R32(RSREG), R32(RTREG)); // mulu i0,i1,rsreg,rtreg - UML_ADD(block, IREG(0), IREG(0), LO32); // add i0,i0,lo - UML_ADDC(block, IREG(1), IREG(1), HI32); // addc i1,i1,hi - UML_DSEXT(block, LO64, IREG(0), SIZE_DWORD); // dsext lo,i0,dword - UML_DSEXT(block, HI64, IREG(1), SIZE_DWORD); // dsext hi,i1,dword + UML_MULU(block, I0, I1, R32(RSREG), R32(RTREG)); // mulu i0,i1,rsreg,rtreg + UML_ADD(block, I0, I0, LO32); // add i0,i0,lo + UML_ADDC(block, I1, I1, HI32); // addc i1,i1,hi + UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword + UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword } return TRUE; case 2: /* MUL */ if (RDREG != 0) { - UML_MULS(block, IREG(0), IREG(0), R32(RSREG), R32(RTREG)); // muls i0,i0,rsreg,rtreg - UML_DSEXT(block, R64(RDREG), IREG(0), SIZE_DWORD); // dsext rdreg,i0,dword + UML_MULS(block, I0, I0, R32(RSREG), R32(RTREG)); // muls i0,i0,rsreg,rtreg + UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext rdreg,i0,dword } return TRUE; } @@ -2797,41 +2797,41 @@ static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compil switch (reg) { case COP0_Cause: - UML_ROLINS(block, CPR032(COP0_Cause), IREG(0), IMM(0), IMM(~0xfc00)); // rolins [Cause],i0,0,~0xfc00 + UML_ROLINS(block, CPR032(COP0_Cause), I0, 0, ~0xfc00); // rolins [Cause],i0,0,~0xfc00 compiler->checksoftints = TRUE; if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case COP0_Status: - generate_update_cycles(mips3, block, compiler, IMM(desc->pc), !in_delay_slot); // <subtract cycles> - UML_MOV(block, IREG(1), CPR032(COP0_Status)); // mov i1,[Status] - UML_MOV(block, CPR032(COP0_Status), IREG(0)); // mov [Status],i0 + generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> + UML_MOV(block, I1, CPR032(COP0_Status)); // mov i1,[Status] + UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 generate_update_mode(mips3, block); // <update mode> - UML_XOR(block, IREG(0), IREG(0), IREG(1)); // xor i0,i0,i1 - UML_TEST(block, IREG(0), IMM(0x8000)); // test i0,0x8000 - UML_CALLCc(block, IF_NZ, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core,NZ + UML_XOR(block, I0, I0, I1); // xor i0,i0,i1 + UML_TEST(block, I0, 0x8000); // test i0,0x8000 + UML_CALLCc(block, COND_NZ, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core,NZ compiler->checkints = TRUE; if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case COP0_Count: - generate_update_cycles(mips3, block, compiler, IMM(desc->pc), !in_delay_slot); // <subtract cycles> - UML_MOV(block, CPR032(COP0_Count), IREG(0)); // mov [Count],i0 + generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> + UML_MOV(block, CPR032(COP0_Count), I0); // mov [Count],i0 UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 - UML_DAND(block, IREG(0), IREG(0), IMM(0xffffffff)); // and i0,i0,0xffffffff - UML_DADD(block, IREG(0), IREG(0), IREG(0)); // dadd i0,i0,i0 - UML_DSUB(block, MEM(&mips3->count_zero_time), MEM(&mips3->impstate->numcycles), IREG(0)); + UML_DAND(block, I0, I0, 0xffffffff); // and i0,i0,0xffffffff + UML_DADD(block, I0, I0, I0); // dadd i0,i0,i0 + UML_DSUB(block, mem(&mips3->count_zero_time), mem(&mips3->impstate->numcycles), I0); // dsub [count_zero_time],[mips3->impstate->numcycles],i0 UML_CALLC(block, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core return TRUE; case COP0_Compare: - UML_MOV(block, MEM(&mips3->compare_armed), IMM(1)); // mov [compare_armed],1 - generate_update_cycles(mips3, block, compiler, IMM(desc->pc), !in_delay_slot); // <subtract cycles> - UML_MOV(block, CPR032(COP0_Compare), IREG(0)); // mov [Compare],i0 - UML_AND(block, CPR032(COP0_Cause), CPR032(COP0_Cause), IMM(~0x8000)); // and [Cause],[Cause],~0x8000 + UML_MOV(block, mem(&mips3->compare_armed), 1); // mov [compare_armed],1 + generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> + UML_MOV(block, CPR032(COP0_Compare), I0); // mov [Compare],i0 + UML_AND(block, CPR032(COP0_Cause), CPR032(COP0_Cause), ~0x8000); // and [Cause],[Cause],~0x8000 UML_CALLC(block, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core return TRUE; @@ -2839,20 +2839,20 @@ static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compil return TRUE; case COP0_Config: - UML_ROLINS(block, CPR032(COP0_Config), IREG(0), IMM(0), IMM(0x0007)); // rolins [Config],i0,0,0x0007 + UML_ROLINS(block, CPR032(COP0_Config), I0, 0, 0x0007); // rolins [Config],i0,0,0x0007 return TRUE; case COP0_EntryHi: - UML_XOR(block, IREG(1), IREG(0), CPR032(reg)); // xor i1,i0,cpr0[reg] - UML_MOV(block, CPR032(reg), IREG(0)); // mov cpr0[reg],i0 - UML_TEST(block, IREG(1), IMM(0xff)); // test i1,0xff - UML_JMPc(block, IF_Z, link = compiler->labelnum++); // jmp link,z + UML_XOR(block, I1, I0, CPR032(reg)); // xor i1,i0,cpr0[reg] + UML_MOV(block, CPR032(reg), I0); // mov cpr0[reg],i0 + UML_TEST(block, I1, 0xff); // test i1,0xff + UML_JMPc(block, COND_Z, link = compiler->labelnum++); // jmp link,z UML_CALLC(block, (c_function)mips3com_asid_changed, mips3); // callc mips3com_asid_changed UML_LABEL(block, link); // link: return TRUE; default: - UML_MOV(block, CPR032(reg), IREG(0)); // mov cpr0[reg],i0 + UML_MOV(block, CPR032(reg), I0); // mov cpr0[reg],i0 return TRUE; } } @@ -2870,34 +2870,34 @@ static int generate_get_cop0_reg(mips3_state *mips3, drcuml_block *block, compil switch (reg) { case COP0_Count: - generate_update_cycles(mips3, block, compiler, IMM(desc->pc), FALSE); // <subtract cycles> + generate_update_cycles(mips3, block, compiler, desc->pc, FALSE); // <subtract cycles> UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 - UML_DSUB(block, IREG(0), MEM(&mips3->impstate->numcycles), MEM(&mips3->count_zero_time)); + UML_DSUB(block, I0, mem(&mips3->impstate->numcycles), mem(&mips3->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] - UML_DSHR(block, IREG(0), IREG(0), IMM(1)); // dshr i0,i0,1 - UML_DSEXT(block, IREG(0), IREG(0), SIZE_DWORD); // dsext i0,i0,dword + UML_DSHR(block, I0, I0, 1); // dshr i0,i0,1 + UML_DSEXT(block, I0, I0, SIZE_DWORD); // dsext i0,i0,dword return TRUE; case COP0_Random: - generate_update_cycles(mips3, block, compiler, IMM(desc->pc), FALSE); // <subtract cycles> + generate_update_cycles(mips3, block, compiler, desc->pc, FALSE); // <subtract cycles> UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 - UML_DSUB(block, IREG(0), MEM(&mips3->impstate->numcycles), MEM(&mips3->count_zero_time)); + UML_DSUB(block, I0, mem(&mips3->impstate->numcycles), mem(&mips3->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] - UML_AND(block, IREG(1), CPR032(COP0_Wired), IMM(0x3f)); // and i1,[Wired],0x3f - UML_SUB(block, IREG(2), IMM(48), IREG(1)); // sub i2,48,i1 - UML_JMPc(block, IF_BE, link1 = compiler->labelnum++); // jmp link1,BE - UML_DAND(block, IREG(2), IREG(2), IMM(0xffffffff)); // dand i2,i2,0xffffffff - UML_DDIVU(block, IREG(0), IREG(2), IREG(0), IREG(2)); // ddivu i0,i2,i0,i2 - UML_ADD(block, IREG(0), IREG(2), IREG(1)); // add i0,i2,i1 - UML_DAND(block, IREG(0), IREG(0), IMM(0x3f)); // dand i0,i0,0x3f + UML_AND(block, I1, CPR032(COP0_Wired), 0x3f); // and i1,[Wired],0x3f + UML_SUB(block, I2, 48, I1); // sub i2,48,i1 + UML_JMPc(block, COND_BE, link1 = compiler->labelnum++); // jmp link1,BE + UML_DAND(block, I2, I2, 0xffffffff); // dand i2,i2,0xffffffff + UML_DDIVU(block, I0, I2, I0, I2); // ddivu i0,i2,i0,i2 + UML_ADD(block, I0, I2, I1); // add i0,i2,i1 + UML_DAND(block, I0, I0, 0x3f); // dand i0,i0,0x3f UML_JMP(block, link2 = compiler->labelnum++); // jmp link2 UML_LABEL(block, link1); // link1: - UML_DMOV(block, IREG(0), IMM(47)); // dmov i0,47 + UML_DMOV(block, I0, 47); // dmov i0,47 UML_LABEL(block, link2); // link2: return TRUE; default: - UML_DSEXT(block, IREG(0), CPR032(reg), SIZE_DWORD); // dsext i0,cpr0[reg],dword + UML_DSEXT(block, I0, CPR032(reg), SIZE_DWORD); // dsext i0,cpr0[reg],dword return TRUE; } } @@ -2916,8 +2916,8 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state /* generate an exception if COP0 is disabled unless we are in kernel mode */ if ((mips3->impstate->mode >> 1) != MODE_KERNEL) { - UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP0)); // test [Status],SR_COP0 - UML_EXHc(block, IF_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], IMM(0));// exh cop,0,Z + UML_TEST(block, CPR032(COP0_Status), SR_COP0); // test [Status],SR_COP0 + UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 0);// exh cop,0,Z } switch (opswitch) @@ -2926,7 +2926,7 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state if (RTREG != 0) { generate_get_cop0_reg(mips3, block, compiler, desc, RDREG); // <get cop0 reg> - UML_DSEXT(block, R64(RTREG), IREG(0), SIZE_DWORD); // dsext <rtreg>,i0,dword + UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword } return TRUE; @@ -2934,7 +2934,7 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state if (RTREG != 0) { generate_get_cop0_reg(mips3, block, compiler, desc, RDREG); // <get cop0 reg> - UML_DMOV(block, R64(RTREG), IREG(0)); // dmov <rtreg>,i0 + UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 } return TRUE; @@ -2944,12 +2944,12 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state return TRUE; case 0x04: /* MTCz */ - UML_DSEXT(block, IREG(0), R32(RTREG), SIZE_DWORD); // dsext i0,<rtreg>,dword + UML_DSEXT(block, I0, R32(RTREG), SIZE_DWORD); // dsext i0,<rtreg>,dword generate_set_cop0_reg(mips3, block, compiler, desc, RDREG); // <set cop0 reg> return TRUE; case 0x05: /* DMTCz */ - UML_DMOV(block, IREG(0), R64(RTREG)); // dmov i0,<rtreg> + UML_DMOV(block, I0, R64(RTREG)); // dmov i0,<rtreg> generate_set_cop0_reg(mips3, block, compiler, desc, RDREG); // <set cop0 reg> return TRUE; @@ -2992,25 +2992,25 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state return TRUE; case 0x18: /* ERET */ - UML_MOV(block, MEM(&mips3->llbit), IMM(0)); // mov [llbit],0 - UML_MOV(block, IREG(0), CPR032(COP0_Status)); // mov i0,[Status] - UML_TEST(block, IREG(0), IMM(SR_ERL)); // test i0,SR_ERL - UML_JMPc(block, IF_NZ, skip = compiler->labelnum++); // jmp skip,nz - UML_AND(block, IREG(0), IREG(0), IMM(~SR_EXL)); // and i0,i0,~SR_EXL - UML_MOV(block, CPR032(COP0_Status), IREG(0)); // mov [Status],i0 + UML_MOV(block, mem(&mips3->llbit), 0); // mov [llbit],0 + UML_MOV(block, I0, CPR032(COP0_Status)); // mov i0,[Status] + UML_TEST(block, I0, SR_ERL); // test i0,SR_ERL + UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,nz + UML_AND(block, I0, I0, ~SR_EXL); // and i0,i0,~SR_EXL + UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 generate_update_mode(mips3, block); compiler->checkints = TRUE; generate_update_cycles(mips3, block, compiler, CPR032(COP0_EPC), TRUE);// <subtract cycles> - UML_HASHJMP(block, MEM(&mips3->impstate->mode), CPR032(COP0_EPC), *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&mips3->impstate->mode), CPR032(COP0_EPC), *mips3->impstate->nocode); // hashjmp <mode>,[EPC],nocode UML_LABEL(block, skip); // skip: - UML_AND(block, IREG(0), IREG(0), IMM(~SR_ERL)); // and i0,i0,~SR_ERL - UML_MOV(block, CPR032(COP0_Status), IREG(0)); // mov [Status],i0 + UML_AND(block, I0, I0, ~SR_ERL); // and i0,i0,~SR_ERL + UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 generate_update_mode(mips3, block); compiler->checkints = TRUE; generate_update_cycles(mips3, block, compiler, CPR032(COP0_ErrorPC), TRUE); // <subtract cycles> - UML_HASHJMP(block, MEM(&mips3->impstate->mode), CPR032(COP0_ErrorPC), *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&mips3->impstate->mode), CPR032(COP0_ErrorPC), *mips3->impstate->nocode); // hashjmp <mode>,[EPC],nocode return TRUE; @@ -3042,8 +3042,8 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state /* generate an exception if COP1 is disabled */ if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1) { - UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP1)); // test [Status],SR_COP1 - UML_EXHc(block, IF_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], IMM(1));// exh cop,1,Z + UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 + UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 1);// exh cop,1,Z } switch (RSREG) @@ -3076,13 +3076,13 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_DSEXT(block, CCR164(RDREG), R32(RTREG), SIZE_DWORD); // dsext ccr1[rdreg],<rtreg>,dword else { - UML_XOR(block, IREG(0), CCR132(31), R32(RTREG)); // xor i0,ccr1[31],<rtreg> + UML_XOR(block, I0, CCR132(31), R32(RTREG)); // xor i0,ccr1[31],<rtreg> UML_DSEXT(block, CCR164(31), R32(RTREG), SIZE_DWORD); // dsext ccr1[31],<rtreg>,dword - UML_TEST(block, IREG(0), IMM(3)); // test i0,3 - UML_JMPc(block, IF_Z, skip = compiler->labelnum++); // jmp skip,Z - UML_AND(block, IREG(0), CCR132(31), IMM(3)); // and i0,ccr1[31],3 - UML_LOAD(block, IREG(0), &mips3->impstate->fpmode[0], IREG(0), SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte - UML_SETFMOD(block, IREG(0)); // setfmod i0 + UML_TEST(block, I0, 3); // test i0,3 + UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z + UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3 + UML_LOAD(block, I0, &mips3->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte + UML_SETFMOD(block, I0); // setfmod i0 UML_LABEL(block, skip); // skip: } return TRUE; @@ -3092,16 +3092,16 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state { case 0x00: /* BCzF - MIPS I */ case 0x02: /* BCzFL - MIPS II */ - UML_TEST(block, CCR132(31), IMM(FCCMASK(op >> 18))); // test ccr1[31],fccmask[which] - UML_JMPc(block, IF_NZ, skip = compiler->labelnum++); // jmp skip,NZ + UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which] + UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);// <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; case 0x01: /* BCzT - MIPS I */ case 0x03: /* BCzTL - MIPS II */ - UML_TEST(block, CCR132(31), IMM(FCCMASK(op >> 18))); // test ccr1[31],fccmask[which] - UML_JMPc(block, IF_Z, skip = compiler->labelnum++); // jmp skip,Z + UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which] + UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);// <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -3224,8 +3224,8 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state return TRUE; case 0x11: - condition = ((op >> 16) & 1) ? IF_NZ : IF_Z; - UML_TEST(block, CCR132(31), IMM(FCCMASK(op >> 18))); // test ccr31,fccmask[op] + condition = ((op >> 16) & 1) ? COND_NZ : COND_Z; + UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr31,fccmask[op] if (IS_SINGLE(op)) /* MOVT/F.S - MIPS IV */ UML_FSMOVc(block, condition, FPR32(FDREG), FPR32(FSREG)); // fsmov <fdreg>,<fsreg>,condition else /* MOVT/F.D - MIPS IV */ @@ -3233,19 +3233,19 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state return TRUE; case 0x12: - UML_DCMP(block, R64(RTREG), IMM(0)); // dcmp <rtreg>,0 + UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0 if (IS_SINGLE(op)) /* MOVZ.S - MIPS IV */ - UML_FSMOVc(block, IF_Z, FPR32(FDREG), FPR32(FSREG)); // fsmov <fdreg>,<fsreg>,Z + UML_FSMOVc(block, COND_Z, FPR32(FDREG), FPR32(FSREG)); // fsmov <fdreg>,<fsreg>,Z else /* MOVZ.D - MIPS IV */ - UML_FDMOVc(block, IF_Z, FPR64(FDREG), FPR64(FSREG)); // fdmov <fdreg>,<fsreg>,Z + UML_FDMOVc(block, COND_Z, FPR64(FDREG), FPR64(FSREG)); // fdmov <fdreg>,<fsreg>,Z return TRUE; case 0x13: - UML_DCMP(block, R64(RTREG), IMM(0)); // dcmp <rtreg>,0 + UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0 if (IS_SINGLE(op)) /* MOVN.S - MIPS IV */ - UML_FSMOVc(block, IF_NZ, FPR32(FDREG), FPR32(FSREG)); // fsmov <fdreg>,<fsreg>,NZ + UML_FSMOVc(block, COND_NZ, FPR32(FDREG), FPR32(FSREG)); // fsmov <fdreg>,<fsreg>,NZ else /* MOVN.D - MIPS IV */ - UML_FDMOVc(block, IF_NZ, FPR64(FDREG), FPR64(FSREG)); // fdmov <fdreg>,<fsreg>,NZ + UML_FDMOVc(block, COND_NZ, FPR64(FDREG), FPR64(FSREG)); // fdmov <fdreg>,<fsreg>,NZ return TRUE; case 0x15: @@ -3302,7 +3302,7 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state case 0x30: case 0x38: /* C.F.S/D - MIPS I */ - UML_AND(block, CCR132(31), CCR132(31), IMM(~FCCMASK(op >> 8))); // and ccr31,ccr31,~fccmask[op] + UML_AND(block, CCR132(31), CCR132(31), ~FCCMASK(op >> 8)); // and ccr31,ccr31,~fccmask[op] return TRUE; case 0x31: @@ -3311,8 +3311,8 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.UN.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_U, IREG(0)); // set i0,u - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_U, I0); // set i0,u + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; @@ -3322,10 +3322,10 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.EQ.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_E, IREG(0)); // set i0,e - UML_SETc(block, IF_NU, IREG(1)); // set i1,nu - UML_AND(block, IREG(0), IREG(0), IREG(1)); // and i0,i0,i1 - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_E, I0); // set i0,e + UML_SETc(block, COND_NU, I1); // set i1,nu + UML_AND(block, I0, I0, I1); // and i0,i0,i1 + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; @@ -3335,10 +3335,10 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.UEQ.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_U, IREG(0)); // set i0,u - UML_SETc(block, IF_E, IREG(1)); // set i1,e - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_U, I0); // set i0,u + UML_SETc(block, COND_E, I1); // set i1,e + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; @@ -3348,10 +3348,10 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.OLT.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_B, IREG(0)); // set i0,b - UML_SETc(block, IF_NU, IREG(1)); // set i1,nu - UML_AND(block, IREG(0), IREG(0), IREG(1)); // and i0,i0,i1 - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_B, I0); // set i0,b + UML_SETc(block, COND_NU, I1); // set i1,nu + UML_AND(block, I0, I0, I1); // and i0,i0,i1 + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; @@ -3361,10 +3361,10 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.ULT.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_U, IREG(0)); // set i0,u - UML_SETc(block, IF_B, IREG(1)); // set i1,b - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_U, I0); // set i0,u + UML_SETc(block, COND_B, I1); // set i1,b + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; @@ -3374,10 +3374,10 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.OLE.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_BE, IREG(0)); // set i0,be - UML_SETc(block, IF_NU, IREG(1)); // set i1,nu - UML_AND(block, IREG(0), IREG(0), IREG(1)); // and i0,i0,i1 - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_BE, I0); // set i0,be + UML_SETc(block, COND_NU, I1); // set i1,nu + UML_AND(block, I0, I0, I1); // and i0,i0,i1 + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; @@ -3387,10 +3387,10 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_FSCMP(block, FPR32(FSREG), FPR32(FTREG)); // fscmp <fsreg>,<ftreg> else /* C.ULE.D - MIPS I */ UML_FDCMP(block, FPR64(FSREG), FPR64(FTREG)); // fdcmp <fsreg>,<ftreg> - UML_SETc(block, IF_U, IREG(0)); // set i0,u - UML_SETc(block, IF_BE, IREG(1)); // set i1,be - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLINS(block, CCR132(31), IREG(0), IMM(FCCSHIFT(op >> 8)), IMM(FCCMASK(op >> 8))); + UML_SETc(block, COND_U, I0); // set i0,u + UML_SETc(block, COND_BE, I1); // set i1,be + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc return TRUE; } @@ -3416,87 +3416,87 @@ static int generate_cop1x(mips3_state *mips3, drcuml_block *block, compiler_stat if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1) { - UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP1)); // test [Status],SR_COP1 - UML_EXHc(block, IF_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], IMM(1));// exh cop,1,Z + UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 + UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 1);// exh cop,1,Z } switch (op & 0x3f) { case 0x00: /* LWXC1 - MIPS IV */ - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 - UML_MOV(block, FPR32(FDREG), IREG(0)); // mov <cpr1_fd>,i0 + UML_MOV(block, FPR32(FDREG), I0); // mov <cpr1_fd>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x01: /* LDXC1 - MIPS IV */ - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 - UML_DMOV(block, FPR64(FDREG), IREG(0)); // dmov <cpr1_fd>,i0 + UML_DMOV(block, FPR64(FDREG), I0); // dmov <cpr1_fd>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x08: /* SWXC1 - MIPS IV */ - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_MOV(block, IREG(1), FPR32(FSREG)); // mov i1,<cpr1_fs> + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_MOV(block, I1, FPR32(FSREG)); // mov i1,<cpr1_fs> UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x09: /* SDXC1 - MIPS IV */ - UML_ADD(block, IREG(0), R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_DMOV(block, IREG(1), FPR64(FSREG)); // dmov i1,<cpr1_fs> + UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> + UML_DMOV(block, I1, FPR64(FSREG)); // dmov i1,<cpr1_fs> UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x0f: /* PREFX */ return TRUE; case 0x20: /* MADD.S - MIPS IV */ - UML_FSMUL(block, FREG(0), FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> - UML_FSADD(block, FPR32(FDREG), FREG(0), FPR32(FRREG)); // fsadd <fdreg>,f0,<frreg> + UML_FSMUL(block, F0, FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> + UML_FSADD(block, FPR32(FDREG), F0, FPR32(FRREG)); // fsadd <fdreg>,f0,<frreg> return TRUE; case 0x21: /* MADD.D - MIPS IV */ - UML_FDMUL(block, FREG(0), FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> - UML_FDADD(block, FPR64(FDREG), FREG(0), FPR64(FRREG)); // fdadd <fdreg>,f0,<frreg> + UML_FDMUL(block, F0, FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> + UML_FDADD(block, FPR64(FDREG), F0, FPR64(FRREG)); // fdadd <fdreg>,f0,<frreg> return TRUE; case 0x28: /* MSUB.S - MIPS IV */ - UML_FSMUL(block, FREG(0), FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> - UML_FSSUB(block, FPR32(FDREG), FREG(0), FPR32(FRREG)); // fssub <fdreg>,f0,<frreg> + UML_FSMUL(block, F0, FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> + UML_FSSUB(block, FPR32(FDREG), F0, FPR32(FRREG)); // fssub <fdreg>,f0,<frreg> return TRUE; case 0x29: /* MSUB.D - MIPS IV */ - UML_FDMUL(block, FREG(0), FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> - UML_FDSUB(block, FPR64(FDREG), FREG(0), FPR64(FRREG)); // fdsub <fdreg>,f0,<frreg> + UML_FDMUL(block, F0, FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> + UML_FDSUB(block, FPR64(FDREG), F0, FPR64(FRREG)); // fdsub <fdreg>,f0,<frreg> return TRUE; case 0x30: /* NMADD.S - MIPS IV */ - UML_FSMUL(block, FREG(0), FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> - UML_FSADD(block, FREG(0), FREG(0), FPR32(FRREG)); // fsadd f0,f0,<frreg> - UML_FSNEG(block, FPR32(FDREG), FREG(0)); // fsneg <fdreg>,f0 + UML_FSMUL(block, F0, FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> + UML_FSADD(block, F0, F0, FPR32(FRREG)); // fsadd f0,f0,<frreg> + UML_FSNEG(block, FPR32(FDREG), F0); // fsneg <fdreg>,f0 return TRUE; case 0x31: /* NMADD.D - MIPS IV */ - UML_FDMUL(block, FREG(0), FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> - UML_FDADD(block, FREG(0), FREG(0), FPR64(FRREG)); // fdadd f0,f0,<frreg> - UML_FDNEG(block, FPR64(FDREG), FREG(0)); // fdneg <fdreg>,f0 + UML_FDMUL(block, F0, FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> + UML_FDADD(block, F0, F0, FPR64(FRREG)); // fdadd f0,f0,<frreg> + UML_FDNEG(block, FPR64(FDREG), F0); // fdneg <fdreg>,f0 return TRUE; case 0x38: /* NMSUB.S - MIPS IV */ - UML_FSMUL(block, FREG(0), FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> - UML_FSSUB(block, FPR32(FDREG), FPR32(FRREG), FREG(0)); // fssub <fdreg>,<frreg>,f0 + UML_FSMUL(block, F0, FPR32(FSREG), FPR32(FTREG)); // fsmul f0,<fsreg>,<ftreg> + UML_FSSUB(block, FPR32(FDREG), FPR32(FRREG), F0); // fssub <fdreg>,<frreg>,f0 return TRUE; case 0x39: /* NMSUB.D - MIPS IV */ - UML_FDMUL(block, FREG(0), FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> - UML_FDSUB(block, FPR64(FDREG), FPR64(FRREG), FREG(0)); // fdsub <fdreg>,<frreg>,f0 + UML_FDMUL(block, F0, FPR64(FSREG), FPR64(FTREG)); // fdmul f0,<fsreg>,<ftreg> + UML_FDSUB(block, FPR64(FDREG), FPR64(FRREG), F0); // fdsub <fdreg>,<frreg>,f0 return TRUE; default: diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c index 63876956420..8aff8c0a62f 100644 --- a/src/emu/cpu/powerpc/ppcdrc.c +++ b/src/emu/cpu/powerpc/ppcdrc.c @@ -55,9 +55,9 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); ***************************************************************************/ /* map variables */ -#define MAPVAR_PC MVAR(0) -#define MAPVAR_CYCLES MVAR(1) -#define MAPVAR_DSISR MVAR(2) +#define MAPVAR_PC M0 +#define MAPVAR_CYCLES M1 +#define MAPVAR_DSISR M2 /* mode bits */ #define MODE_LITTLE_ENDIAN 0x01 @@ -89,12 +89,12 @@ extern offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op); #define R32(reg) ppc->impstate->regmap[reg] #define R32Z(reg) (((reg) == 0) ? parameter(0) : ppc->impstate->regmap[reg]) #define F64(reg) ppc->impstate->fdregmap[reg] -#define CR32(reg) MEM(&ppc->cr[reg]) -#define FPSCR32 MEM(&ppc->fpscr) -#define MSR32 MEM(&ppc->msr) -#define XERSO32 MEM(&ppc->xerso) -#define SR32(reg) MEM(&ppc->sr[reg]) -#define SPR32(reg) MEM(&ppc->spr[reg]) +#define CR32(reg) mem(&ppc->cr[reg]) +#define FPSCR32 mem(&ppc->fpscr) +#define MSR32 mem(&ppc->msr) +#define XERSO32 mem(&ppc->xerso) +#define SR32(reg) mem(&ppc->sr[reg]) +#define SPR32(reg) mem(&ppc->spr[reg]) #define CRMASK(reg) (0xf0000000 >> ((reg) * 4)) @@ -475,7 +475,7 @@ INLINE void load_fast_iregs(powerpc_state *ppc, drcuml_block *block) for (regnum = 0; regnum < ARRAY_LENGTH(ppc->impstate->regmap); regnum++) if (ppc->impstate->regmap[regnum].is_int_register()) - UML_MOV(block, IREG(ppc->impstate->regmap[regnum].ireg() - REG_I0), MEM(&ppc->r[regnum])); + UML_MOV(block, ireg(ppc->impstate->regmap[regnum].ireg() - REG_I0), mem(&ppc->r[regnum])); } @@ -490,7 +490,7 @@ INLINE void save_fast_iregs(powerpc_state *ppc, drcuml_block *block) for (regnum = 0; regnum < ARRAY_LENGTH(ppc->impstate->regmap); regnum++) if (ppc->impstate->regmap[regnum].is_int_register()) - UML_MOV(block, MEM(&ppc->r[regnum]), IREG(ppc->impstate->regmap[regnum].ireg() - REG_I0)); + UML_MOV(block, mem(&ppc->r[regnum]), ireg(ppc->impstate->regmap[regnum].ireg() - REG_I0)); } @@ -636,8 +636,8 @@ static void ppcdrc_init(powerpc_flavor flavor, UINT8 cap, int tb_divisor, legacy /* compute the register parameters */ for (regnum = 0; regnum < 32; regnum++) { - ppc->impstate->regmap[regnum] = MEM(&ppc->r[regnum]); - ppc->impstate->fdregmap[regnum] = MEM(&ppc->f[regnum]); + ppc->impstate->regmap[regnum] = mem(&ppc->r[regnum]); + ppc->impstate->fdregmap[regnum] = mem(&ppc->f[regnum]); } /* if we have registers to spare, assign r0, r1, r2 to leftovers */ @@ -645,11 +645,11 @@ static void ppcdrc_init(powerpc_flavor flavor, UINT8 cap, int tb_divisor, legacy { ppc->impstate->drcuml->get_backend_info(beinfo); if (beinfo.direct_iregs > 5) - ppc->impstate->regmap[0] = IREG(5); + ppc->impstate->regmap[0] = I5; if (beinfo.direct_iregs > 6) - ppc->impstate->regmap[1] = IREG(6); + ppc->impstate->regmap[1] = I6; if (beinfo.direct_iregs > 7) - ppc->impstate->regmap[2] = IREG(7); + ppc->impstate->regmap[2] = I7; } /* mark the cache dirty so it is updated on next execute */ @@ -978,7 +978,7 @@ logerror("Compile %08X\n", pc); else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc | 0x80000000 - UML_HASHJMP(block, IMM(ppc->impstate->mode), IMM(seqhead->pc), *ppc->impstate->nocode); + UML_HASHJMP(block, ppc->impstate->mode, seqhead->pc, *ppc->impstate->nocode); // hashjmp <mode>,seqhead->pc,nocode continue; } @@ -1004,13 +1004,13 @@ logerror("Compile %08X\n", pc); nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4; /* count off cycles and go there */ - generate_update_cycles(ppc, block, &compiler, IMM(nextpc), TRUE); // <subtract cycles> + generate_update_cycles(ppc, block, &compiler, nextpc, TRUE); // <subtract cycles> /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */ if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES) - UML_HASHJMP(block, MEM(&ppc->impstate->mode), IMM(nextpc), *ppc->impstate->nocode);// hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, mem(&ppc->impstate->mode), nextpc, *ppc->impstate->nocode);// hashjmp <mode>,nextpc,nocode else if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) - UML_HASHJMP(block, IMM(ppc->impstate->mode), IMM(nextpc), *ppc->impstate->nocode);// hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, ppc->impstate->mode, nextpc, *ppc->impstate->nocode);// hashjmp <mode>,nextpc,nocode } /* end the sequence */ @@ -1127,25 +1127,25 @@ static void static_generate_entry_point(powerpc_state *ppc) UML_HANDLE(block, *ppc->impstate->entry); // handle entry /* reset the FPU mode */ - UML_AND(block, IREG(0), FPSCR32, IMM(3)); // and i0,fpscr,3 - UML_LOAD(block, IREG(0), &ppc->impstate->fpmode[0], IREG(0), SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte - UML_SETFMOD(block, IREG(0)); // setfmod i0 + UML_AND(block, I0, FPSCR32, 3); // and i0,fpscr,3 + UML_LOAD(block, I0, &ppc->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte + UML_SETFMOD(block, I0); // setfmod i0 /* load fast integer registers */ load_fast_iregs(ppc, block); // <load fastregs> /* check for interrupts */ - UML_TEST(block, MEM(&ppc->irq_pending), IMM(~0)); // test [irq_pending],0 - UML_JMPc(block, IF_Z, skip); // jmp skip,Z - UML_TEST(block, MSR32, IMM(MSR_EE)); // test msr,MSR_EE - UML_JMPc(block, IF_Z, skip); // jmp skip,Z - UML_MOV(block, IREG(0), MEM(&ppc->pc)); // mov i0,pc - UML_MOV(block, IREG(1), IMM(0)); // mov i1,0 + UML_TEST(block, mem(&ppc->irq_pending), ~0); // test [irq_pending],0 + UML_JMPc(block, COND_Z, skip); // jmp skip,Z + UML_TEST(block, MSR32, MSR_EE); // test msr,MSR_EE + UML_JMPc(block, COND_Z, skip); // jmp skip,Z + UML_MOV(block, I0, mem(&ppc->pc)); // mov i0,pc + UML_MOV(block, I1, 0); // mov i1,0 UML_CALLH(block, *ppc->impstate->exception_norecover[EXCEPTION_EI]); // callh exception_norecover UML_LABEL(block, skip); // skip: /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, MEM(&ppc->impstate->mode), MEM(&ppc->pc), *ppc->impstate->nocode); // hashjmp <mode>,<pc>,nocode + UML_HASHJMP(block, mem(&ppc->impstate->mode), mem(&ppc->pc), *ppc->impstate->nocode); // hashjmp <mode>,<pc>,nocode block->end(); } @@ -1167,10 +1167,10 @@ static void static_generate_nocode_handler(powerpc_state *ppc) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &ppc->impstate->nocode, "nocode"); UML_HANDLE(block, *ppc->impstate->nocode); // handle nocode - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&ppc->pc), IREG(0)); // mov [pc],i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&ppc->pc), I0); // mov [pc],i0 save_fast_iregs(ppc, block); // <save fastregs> - UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); } @@ -1192,10 +1192,10 @@ static void static_generate_out_of_cycles(powerpc_state *ppc) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &ppc->impstate->out_of_cycles, "out_of_cycles"); UML_HANDLE(block, *ppc->impstate->out_of_cycles); // handle out_of_cycles - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&ppc->pc), IREG(0)); // mov <pc>,i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&ppc->pc), I0); // mov <pc>,i0 save_fast_iregs(ppc, block); // <save fastregs> - UML_EXIT(block, IMM(EXECUTE_OUT_OF_CYCLES)); // exit EXECUTE_OUT_OF_CYCLES + UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); } @@ -1223,35 +1223,35 @@ static void static_generate_tlb_mismatch(powerpc_state *ppc) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &ppc->impstate->tlb_mismatch, "tlb_mismatch"); UML_HANDLE(block, *ppc->impstate->tlb_mismatch); // handle tlb_mismatch - UML_RECOVER(block, IREG(0), MAPVAR_PC); // recover i0,PC - UML_SHR(block, IREG(1), IREG(0), IMM(12)); // shr i1,i0,12 - UML_LOAD(block, IREG(2), (void *)vtlb_table(ppc->vtlb), IREG(1), SIZE_DWORD, SCALE_x4); // load i2,[vtlb],i1,dword - UML_MOV(block, MEM(&ppc->param0), IREG(0)); // mov [param0],i0 - UML_MOV(block, MEM(&ppc->param1), IMM(TRANSLATE_FETCH)); // mov [param1],TRANSLATE_FETCH + UML_RECOVER(block, I0, MAPVAR_PC); // recover i0,PC + UML_SHR(block, I1, I0, 12); // shr i1,i0,12 + UML_LOAD(block, I2, (void *)vtlb_table(ppc->vtlb), I1, SIZE_DWORD, SCALE_x4); // load i2,[vtlb],i1,dword + UML_MOV(block, mem(&ppc->param0), I0); // mov [param0],i0 + UML_MOV(block, mem(&ppc->param1), TRANSLATE_FETCH); // mov [param1],TRANSLATE_FETCH UML_CALLC(block, (c_function)ppccom_tlb_fill, ppc); // callc tlbfill,ppc - UML_LOAD(block, IREG(1), (void *)vtlb_table(ppc->vtlb), IREG(1), SIZE_DWORD, SCALE_x4); // load i1,[vtlb],i1,dword - UML_TEST(block, IREG(1), IMM(VTLB_FETCH_ALLOWED)); // test i1,VTLB_FETCH_ALLOWED - UML_JMPc(block, IF_Z, isi = label++); // jmp isi,z - UML_CMP(block, IREG(2), IMM(0)); // cmp i2,0 - UML_JMPc(block, IF_NZ, exit = label++); // jmp exit,nz - UML_HASHJMP(block, MEM(&ppc->impstate->mode), IREG(0), *ppc->impstate->nocode); // hashjmp <mode>,i0,nocode + UML_LOAD(block, I1, (void *)vtlb_table(ppc->vtlb), I1, SIZE_DWORD, SCALE_x4); // load i1,[vtlb],i1,dword + UML_TEST(block, I1, VTLB_FETCH_ALLOWED); // test i1,VTLB_FETCH_ALLOWED + UML_JMPc(block, COND_Z, isi = label++); // jmp isi,z + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_NZ, exit = label++); // jmp exit,nz + UML_HASHJMP(block, mem(&ppc->impstate->mode), I0, *ppc->impstate->nocode); // hashjmp <mode>,i0,nocode UML_LABEL(block, exit); // exit: - UML_MOV(block, MEM(&ppc->pc), IREG(0)); // mov <pc>,i0 + UML_MOV(block, mem(&ppc->pc), I0); // mov <pc>,i0 save_fast_iregs(ppc, block); // <save fastregs> - UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE UML_LABEL(block, isi); // isi: if (!(ppc->cap & PPCCAP_603_MMU)) { - UML_MOV(block, SPR32(SPROEA_DSISR), MEM(&ppc->param0)); // mov [dsisr],[param0] - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ISI], IREG(0)); // exh isi,i0 + UML_MOV(block, SPR32(SPROEA_DSISR), mem(&ppc->param0)); // mov [dsisr],[param0] + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ISI], I0); // exh isi,i0 } else { - UML_MOV(block, SPR32(SPR603_IMISS), IREG(0)); // mov [imiss],i0 - UML_MOV(block, SPR32(SPR603_ICMP), MEM(&ppc->mmu603_cmp)); // mov [icmp],[mmu603_cmp] - UML_MOV(block, SPR32(SPR603_HASH1), MEM(&ppc->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] - UML_MOV(block, SPR32(SPR603_HASH2), MEM(&ppc->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ITLBMISS], IREG(0)); // exh itlbmiss,i0 + UML_MOV(block, SPR32(SPR603_IMISS), I0); // mov [imiss],i0 + UML_MOV(block, SPR32(SPR603_ICMP), mem(&ppc->mmu603_cmp)); // mov [icmp],[mmu603_cmp] + UML_MOV(block, SPR32(SPR603_HASH1), mem(&ppc->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] + UML_MOV(block, SPR32(SPR603_HASH2), mem(&ppc->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ITLBMISS], I0); // exh itlbmiss,i0 } block->end(); @@ -1281,15 +1281,15 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r /* exception parameter is expected to be the fault address in this case */ if (exception == EXCEPTION_ISI || exception == EXCEPTION_DSI) { - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, SPR32(SPROEA_DAR), IREG(0)); // mov [dar],i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, SPR32(SPROEA_DAR), I0); // mov [dar],i0 } /* fetch the PC and uncounted cycles */ if (recover) { - UML_RECOVER(block, IREG(0), MAPVAR_PC); // recover i0,PC - UML_RECOVER(block, IREG(1), MAPVAR_CYCLES); // recover i1,CYCLES + UML_RECOVER(block, I0, MAPVAR_PC); // recover i0,PC + UML_RECOVER(block, I1, MAPVAR_CYCLES); // recover i1,CYCLES } /* OEA handling of SRR exceptions */ @@ -1299,36 +1299,36 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r UINT32 msrormask = 0; /* check registers to see the real source of our exception (EI exceptions only) */ - UML_MOV(block, IREG(3), IMM(vector)); // mov i3,vector + UML_MOV(block, I3, vector); // mov i3,vector if (exception == EXCEPTION_EI) { code_label not_decrementer; - UML_TEST(block, MEM(&ppc->irq_pending), IMM(0x01)); // test [irq_pending],0x01 - UML_JMPc(block, IF_NZ, not_decrementer = label++); // jmp not_decrementer,nz - UML_MOV(block, IREG(3), IMM(EXCEPTION_DECREMENT << 8)); // mov i3,EXCEPTION_DECREMENT << 8 - UML_AND(block, MEM(&ppc->irq_pending), MEM(&ppc->irq_pending), IMM(~0x02)); // and [irq_pending],[irq_pending],~0x02 + UML_TEST(block, mem(&ppc->irq_pending), 0x01); // test [irq_pending],0x01 + UML_JMPc(block, COND_NZ, not_decrementer = label++); // jmp not_decrementer,nz + UML_MOV(block, I3, EXCEPTION_DECREMENT << 8); // mov i3,EXCEPTION_DECREMENT << 8 + UML_AND(block, mem(&ppc->irq_pending), mem(&ppc->irq_pending), ~0x02); // and [irq_pending],[irq_pending],~0x02 UML_LABEL(block, not_decrementer); // not_decrementer: } /* exception PC goes into SRR0 */ - UML_MOV(block, SPR32(SPROEA_SRR0), IREG(0)); // mov [srr0],i0 + UML_MOV(block, SPR32(SPROEA_SRR0), I0); // mov [srr0],i0 /* MSR bits go into SRR1, along with some exception-specific data */ - UML_AND(block, SPR32(SPROEA_SRR1), MSR32, IMM(0x87c0ffff)); // and [srr1],[msr],0x87c0ffff + UML_AND(block, SPR32(SPROEA_SRR1), MSR32, 0x87c0ffff); // and [srr1],[msr],0x87c0ffff if (exception == EXCEPTION_PROGRAM) { - UML_GETEXP(block, IREG(1)); // getexp i1 - UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), IREG(1)); // or [srr1],[srr1],i1 + UML_GETEXP(block, I1); // getexp i1 + UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), I1); // or [srr1],[srr1],i1 } if (ppc->cap & PPCCAP_603_MMU) { if (exception == EXCEPTION_ITLBMISS) - UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), IMM(0x00040000)); // or [srr1],0x00040000 + UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), 0x00040000); // or [srr1],0x00040000 else if (exception == EXCEPTION_DTLBMISSL) - UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), IMM(0x00010000)); // or [srr1],0x00010000 + UML_OR(block, SPR32(SPROEA_SRR1), SPR32(SPROEA_SRR1), 0x00010000); // or [srr1],0x00010000 if (exception == EXCEPTION_ITLBMISS || exception == EXCEPTION_DTLBMISSL || exception == EXCEPTION_DTLBMISSS) - UML_ROLINS(block, SPR32(SPROEA_SRR1), CR32(0), IMM(28), IMM(CRMASK(0))); // rolins [srr1],[cr0],28,crmask(0) + UML_ROLINS(block, SPR32(SPROEA_SRR1), CR32(0), 28, CRMASK(0)); // rolins [srr1],[cr0],28,crmask(0) } /* update MSR */ @@ -1338,99 +1338,99 @@ static void static_generate_exception(powerpc_state *ppc, UINT8 exception, int r msrormask |= MSR603_TGPR; else msrandmask |= MSR603_TGPR; - UML_MOV(block, IREG(0), MSR32); // mov i0,[msr] + UML_MOV(block, I0, MSR32); // mov i0,[msr] } - UML_AND(block, IREG(2), MSR32, IMM(~msrandmask)); // and i2,[msr],~andmask - UML_OR(block, IREG(2), IREG(2), IMM(msrormask)); // or i2,i2,ormask - UML_ROLINS(block, IREG(2), IREG(2), IMM(16), IMM(MSR_LE)); // rolins i2,u2,16,MSR_LE - UML_MOV(block, MSR32, IREG(2)); // mov [msr],i2 + UML_AND(block, I2, MSR32, ~msrandmask); // and i2,[msr],~andmask + UML_OR(block, I2, I2, msrormask); // or i2,i2,ormask + UML_ROLINS(block, I2, I2, 16, MSR_LE); // rolins i2,u2,16,MSR_LE + UML_MOV(block, MSR32, I2); // mov [msr],i2 if (ppc->cap & PPCCAP_603_MMU) { - UML_XOR(block, IREG(0), IREG(0), IREG(2)); // xor i0,i0,i2 - UML_TEST(block, IREG(0), IMM(MSR603_TGPR)); // test i0,tgpr - UML_CALLHc(block, IF_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz + UML_XOR(block, I0, I0, I2); // xor i0,i0,i2 + UML_TEST(block, I0, MSR603_TGPR); // test i0,tgpr + UML_CALLHc(block, COND_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz } generate_update_mode(ppc, block); // <update mode> /* determine our target PC */ if (ppc->flavor == PPC_MODEL_602) - UML_MOV(block, IREG(0), SPR32(SPR602_IBR)); // mov i0,[ibr] + UML_MOV(block, I0, SPR32(SPR602_IBR)); // mov i0,[ibr] else - UML_MOV(block, IREG(0), IMM(0x00000000)); // mov i0,0x00000000 - UML_TEST(block, MSR32, IMM(MSROEA_IP)); // test [msr],IP - UML_MOVc(block, IF_NZ, IREG(0), IMM(0xfff00000)); // mov i0,0xfff00000,nz - UML_OR(block, IREG(0), IREG(0), IREG(3)); // or i0,i0,i3 + UML_MOV(block, I0, 0x00000000); // mov i0,0x00000000 + UML_TEST(block, MSR32, MSROEA_IP); // test [msr],IP + UML_MOVc(block, COND_NZ, I0, 0xfff00000); // mov i0,0xfff00000,nz + UML_OR(block, I0, I0, I3); // or i0,i0,i3 } /* 4XX handling of exceptions */ if (ppc->cap & PPCCAP_4XX) { /* check registers to see the real source of our exception (EI exceptions only) */ - UML_MOV(block, IREG(3), IMM(vector)); // mov i3,vector + UML_MOV(block, I3, vector); // mov i3,vector if (exception == EXCEPTION_EI) { code_label notwdog, common; - UML_TEST(block, SPR32(SPR4XX_TSR), IMM(PPC4XX_TSR_PIS)); // test [tsr],PIS - UML_MOVc(block, IF_NZ, IREG(3), IMM(0x1000)); // mov i3,0x1000,NZ - UML_TEST(block, SPR32(SPR4XX_TSR), IMM(PPC4XX_TSR_FIS)); // test [tsr],FIS - UML_MOVc(block, IF_NZ, IREG(3), IMM(0x1010)); // mov i3,0x1010,NZ + UML_TEST(block, SPR32(SPR4XX_TSR), PPC4XX_TSR_PIS); // test [tsr],PIS + UML_MOVc(block, COND_NZ, I3, 0x1000); // mov i3,0x1000,NZ + UML_TEST(block, SPR32(SPR4XX_TSR), PPC4XX_TSR_FIS); // test [tsr],FIS + UML_MOVc(block, COND_NZ, I3, 0x1010); // mov i3,0x1010,NZ UML_TEST(block, SPR32(DCR4XX_EXISR), SPR32(DCR4XX_EXIER)); // test [exisr],[exier] - UML_MOVc(block, IF_NZ, IREG(3), IMM(vector)); // mov i3,vector,NZ - UML_TEST(block, SPR32(SPR4XX_TSR), IMM(PPC4XX_TSR_WIS)); // test [tsr],WIS - UML_JMPc(block, IF_Z, notwdog = label++); // jz notwdog - UML_MOV(block, IREG(3), IMM(0x1020)); // mov i3,0x1020 + UML_MOVc(block, COND_NZ, I3, vector); // mov i3,vector,NZ + UML_TEST(block, SPR32(SPR4XX_TSR), PPC4XX_TSR_WIS); // test [tsr],WIS + UML_JMPc(block, COND_Z, notwdog = label++); // jz notwdog + UML_MOV(block, I3, 0x1020); // mov i3,0x1020 /* exception PC goes into SRR2, MSR goes to SRR3 */ - UML_MOV(block, SPR32(SPR4XX_SRR2), IREG(0)); // mov [srr2],i0 + UML_MOV(block, SPR32(SPR4XX_SRR2), I0); // mov [srr2],i0 UML_MOV(block, SPR32(SPR4XX_SRR3), MSR32); // mov [srr3],[msr] - UML_AND(block, IREG(2), MSR32, IMM(~(MSR4XX_WE | MSR_PR | MSR4XX_CE | MSR_EE | MSR4XX_DE | MSR4XX_PE))); + UML_AND(block, I2, MSR32, ~(MSR4XX_WE | MSR_PR | MSR4XX_CE | MSR_EE | MSR4XX_DE | MSR4XX_PE)); UML_JMP(block, common = label++); // jmp common /* exception PC goes into SRR0, MSR goes to SRR1 */ UML_LABEL(block, notwdog); // notwdog: - UML_MOV(block, SPR32(SPR4XX_SRR0), IREG(0)); // mov [srr0],i0 + UML_MOV(block, SPR32(SPR4XX_SRR0), I0); // mov [srr0],i0 UML_MOV(block, SPR32(SPR4XX_SRR1), MSR32); // mov [srr1],[msr] - UML_AND(block, IREG(2), MSR32, IMM(~(MSR4XX_WE | MSR_PR | MSR_EE | MSR4XX_PE)));// and i2,[msr],~(bunch-o-flags) + UML_AND(block, I2, MSR32, ~(MSR4XX_WE | MSR_PR | MSR_EE | MSR4XX_PE));// and i2,[msr],~(bunch-o-flags) UML_LABEL(block, common); // common: } else { /* exception PC goes into SRR0, MSR goes to SRR1 */ - UML_MOV(block, SPR32(SPR4XX_SRR0), IREG(0)); // mov [srr0],i0 + UML_MOV(block, SPR32(SPR4XX_SRR0), I0); // mov [srr0],i0 UML_MOV(block, SPR32(SPR4XX_SRR1), MSR32); // mov [srr1],[msr] - UML_AND(block, IREG(2), MSR32, IMM(~(MSR4XX_WE | MSR_PR | MSR_EE | MSR4XX_PE)));// and i2,[msr],~(bunch-o-flags) + UML_AND(block, I2, MSR32, ~(MSR4XX_WE | MSR_PR | MSR_EE | MSR4XX_PE));// and i2,[msr],~(bunch-o-flags) } /* finish updating MSR */ - UML_ROLINS(block, IREG(2), IREG(2), IMM(16), IMM(MSR_LE)); // rolins i2,u2,16,MSR_LE - UML_MOV(block, MSR32, IREG(2)); // mov [msr],i2 + UML_ROLINS(block, I2, I2, 16, MSR_LE); // rolins i2,u2,16,MSR_LE + UML_MOV(block, MSR32, I2); // mov [msr],i2 generate_update_mode(ppc, block); // <update mode> /* program exception flags go to ESR */ if (exception == EXCEPTION_PROGRAM) { - UML_GETEXP(block, IREG(1)); // getexp i1 - UML_SHL(block, SPR32(SPR4XX_ESR), IREG(1), IMM(8)); // shl [esr],i1,8 + UML_GETEXP(block, I1); // getexp i1 + UML_SHL(block, SPR32(SPR4XX_ESR), I1, 8); // shl [esr],i1,8 } /* determine our target PC */ - UML_ROLINS(block, IREG(3), SPR32(SPR4XX_EVPR), IMM(0), IMM(0xffff0000)); // rolins i3,[evpr],0,0xffff0000 - UML_MOV(block, IREG(0), IREG(3)); // mov i0,i3 + UML_ROLINS(block, I3, SPR32(SPR4XX_EVPR), 0, 0xffff0000); // rolins i3,[evpr],0,0xffff0000 + UML_MOV(block, I0, I3); // mov i0,i3 } /* optionally print exceptions */ if ((PRINTF_EXCEPTIONS && exception != EXCEPTION_EI && exception != EXCEPTION_SYSCALL) || (PRINTF_MMU && (exception == EXCEPTION_ISI || exception == EXCEPTION_DSI))) { - UML_MOV(block, MEM(&ppc->param0), IMM(exception)); // mov [param0],exception + UML_MOV(block, mem(&ppc->param0), exception); // mov [param0],exception UML_CALLC(block, cfunc_printf_exception, ppc); // callc cfunc_printf_exception,ppc } /* adjust cycles */ - UML_SUB(block, MEM(&ppc->icount), MEM(&ppc->icount), IREG(1)); // sub icount,icount,cycles - UML_EXHc(block, IF_S, *ppc->impstate->out_of_cycles, IREG(0)); // exh out_of_cycles,i0 - UML_HASHJMP(block, MEM(&ppc->impstate->mode), IREG(0), *ppc->impstate->nocode); // hashjmp <mode>,i0,nocode + UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), I1); // sub icount,icount,cycles + UML_EXHc(block, COND_S, *ppc->impstate->out_of_cycles, I0); // exh out_of_cycles,i0 + UML_HASHJMP(block, mem(&ppc->impstate->mode), I0, *ppc->impstate->nocode); // hashjmp <mode>,i0,nocode block->end(); } @@ -1474,8 +1474,8 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si /* in little-endian mode, anything misaligned generates an exception */ if ((mode & MODE_LITTLE_ENDIAN) || masked == NULL || !(ppc->cap & PPCCAP_MISALIGNED)) { - UML_TEST(block, IREG(0), IMM(size - 1)); // test i0,size-1 - UML_JMPc(block, IF_NZ, alignex = label++); // jmp alignex,nz + UML_TEST(block, I0, size - 1); // test i0,size-1 + UML_JMPc(block, COND_NZ, alignex = label++); // jmp alignex,nz } /* in big-endian mode, it's more complicated */ @@ -1484,15 +1484,15 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si /* 8-byte accesses must be word-aligned */ if (size == 8) { - UML_TEST(block, IREG(0), IMM(3)); // test i0,3 - UML_JMPc(block, IF_NZ, alignex = label++); // jmp alignex,nz + UML_TEST(block, I0, 3); // test i0,3 + UML_JMPc(block, COND_NZ, alignex = label++); // jmp alignex,nz } /* unaligned 2 and 4 byte accesses need to be broken up */ else { - UML_TEST(block, IREG(0), IMM(size - 1)); // test i0,size-1 - UML_JMPc(block, IF_NZ, unaligned = label++); // jmp unaligned,nz + UML_TEST(block, I0, size - 1); // test i0,size-1 + UML_JMPc(block, COND_NZ, unaligned = label++); // jmp unaligned,nz } } } @@ -1500,16 +1500,16 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si /* general case: assume paging and perform a translation */ if (((ppc->cap & PPCCAP_OEA) && (mode & MODE_DATA_TRANSLATION)) || (iswrite && (ppc->cap & PPCCAP_4XX) && (mode & MODE_PROTECTION))) { - UML_SHR(block, IREG(3), IREG(0), IMM(12)); // shr i3,i0,12 - UML_LOAD(block, IREG(3), (void *)vtlb_table(ppc->vtlb), IREG(3), SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword - UML_TEST(block, IREG(3), IMM((UINT64)1 << translate_type)); // test i3,1 << translate_type - UML_JMPc(block, IF_Z, tlbmiss = label++); // jmp tlbmiss,z + UML_SHR(block, I3, I0, 12); // shr i3,i0,12 + UML_LOAD(block, I3, (void *)vtlb_table(ppc->vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword + UML_TEST(block, I3, (UINT64)1 << translate_type); // test i3,1 << translate_type + UML_JMPc(block, COND_Z, tlbmiss = label++); // jmp tlbmiss,z UML_LABEL(block, tlbreturn = label++); // tlbreturn: - UML_ROLINS(block, IREG(0), IREG(3), IMM(0), IMM(0xfffff000)); // rolins i0,i3,0,0xfffff000 + UML_ROLINS(block, I0, I3, 0, 0xfffff000); // rolins i0,i3,0,0xfffff000 } else if (ppc->cap & PPCCAP_4XX) - UML_AND(block, IREG(0), IREG(0), IMM(0x7fffffff)); // and i0,i0,0x7fffffff - UML_XOR(block, IREG(0), IREG(0), IMM((mode & MODE_LITTLE_ENDIAN) ? (8 - size) : 0)); // xor i0,i0,8-size + UML_AND(block, I0, I0, 0x7fffffff); // and i0,i0,0x7fffffff + UML_XOR(block, I0, I0, (mode & MODE_LITTLE_ENDIAN) ? (8 - size) : 0); // xor i0,i0,8-size if ((ppc->device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) for (ramnum = 0; ramnum < PPC_MAX_FASTRAM; ramnum++) @@ -1520,35 +1520,35 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si if (ppc->impstate->fastram[ramnum].end != 0xffffffff) { - UML_CMP(block, IREG(0), IMM(ppc->impstate->fastram[ramnum].end)); // cmp i0,end - UML_JMPc(block, IF_A, skip); // ja skip + UML_CMP(block, I0, ppc->impstate->fastram[ramnum].end); // cmp i0,end + UML_JMPc(block, COND_A, skip); // ja skip } if (ppc->impstate->fastram[ramnum].start != 0x00000000) { - UML_CMP(block, IREG(0), IMM(ppc->impstate->fastram[ramnum].start)); // cmp i0,fastram_start - UML_JMPc(block, IF_B, skip); // jb skip + UML_CMP(block, I0, ppc->impstate->fastram[ramnum].start); // cmp i0,fastram_start + UML_JMPc(block, COND_B, skip); // jb skip } if (!iswrite) { if (size == 1) { - UML_XOR(block, IREG(0), IREG(0), IMM(fastxor & 7)); // xor i0,i0,fastxor & 7 - UML_LOAD(block, IREG(0), fastbase, IREG(0), SIZE_BYTE, SCALE_x1); // load i0,fastbase,i0,byte + UML_XOR(block, I0, I0, fastxor & 7); // xor i0,i0,fastxor & 7 + UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1); // load i0,fastbase,i0,byte } else if (size == 2) { - UML_XOR(block, IREG(0), IREG(0), IMM(fastxor & 6)); // xor i0,i0,fastxor & 6 - UML_LOAD(block, IREG(0), fastbase, IREG(0), SIZE_WORD, SCALE_x1); // load i0,fastbase,i0,word_x1 + UML_XOR(block, I0, I0, fastxor & 6); // xor i0,i0,fastxor & 6 + UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1); // load i0,fastbase,i0,word_x1 } else if (size == 4) { - UML_XOR(block, IREG(0), IREG(0), IMM(fastxor & 4)); // xor i0,i0,fastxor & 4 - UML_LOAD(block, IREG(0), fastbase, IREG(0), SIZE_DWORD, SCALE_x1); // load i0,fastbase,i0,dword_x1 + UML_XOR(block, I0, I0, fastxor & 4); // xor i0,i0,fastxor & 4 + UML_LOAD(block, I0, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i0,fastbase,i0,dword_x1 } else if (size == 8) { - UML_DLOAD(block, IREG(0), fastbase, IREG(0), SIZE_QWORD, SCALE_x1); // dload i0,fastbase,i0,qword + UML_DLOAD(block, I0, fastbase, I0, SIZE_QWORD, SCALE_x1); // dload i0,fastbase,i0,qword } UML_RET(block); // ret } @@ -1556,38 +1556,38 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si { if (size == 1) { - UML_XOR(block, IREG(0), IREG(0), IMM(fastxor & 7)); // xor i0,i0,fastxor & 7 - UML_STORE(block, fastbase, IREG(0), IREG(1), SIZE_BYTE, SCALE_x1); // store fastbase,i0,i1,byte + UML_XOR(block, I0, I0, fastxor & 7); // xor i0,i0,fastxor & 7 + UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1); // store fastbase,i0,i1,byte } else if (size == 2) { - UML_XOR(block, IREG(0), IREG(0), IMM(fastxor & 6)); // xor i0,i0,fastxor & 6 - UML_STORE(block, fastbase, IREG(0), IREG(1), SIZE_WORD, SCALE_x1); // store fastbase,i0,i1,word_x1 + UML_XOR(block, I0, I0, fastxor & 6); // xor i0,i0,fastxor & 6 + UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1); // store fastbase,i0,i1,word_x1 } else if (size == 4) { - UML_XOR(block, IREG(0), IREG(0), IMM(fastxor & 4)); // xor i0,i0,fastxor & 4 + UML_XOR(block, I0, I0, fastxor & 4); // xor i0,i0,fastxor & 4 if (ismasked) { - UML_LOAD(block, IREG(3), fastbase, IREG(0), SIZE_DWORD, SCALE_x1); // load i3,fastbase,i0,dword_x1 - UML_AND(block, IREG(1), IREG(1), IREG(2)); // and i1,i1,i2 - UML_XOR(block, IREG(2), IREG(2), IMM(0xffffffff)); // xor i2,i2,0xfffffffff - UML_AND(block, IREG(3), IREG(3), IREG(2)); // and i3,i3,i2 - UML_OR(block, IREG(1), IREG(1), IREG(3)); // or i1,i1,i3 + UML_LOAD(block, I3, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i3,fastbase,i0,dword_x1 + UML_AND(block, I1, I1, I2); // and i1,i1,i2 + UML_XOR(block, I2, I2, 0xffffffff); // xor i2,i2,0xfffffffff + UML_AND(block, I3, I3, I2); // and i3,i3,i2 + UML_OR(block, I1, I1, I3); // or i1,i1,i3 } - UML_STORE(block, fastbase, IREG(0), IREG(1), SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1 + UML_STORE(block, fastbase, I0, I1, SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1 } else if (size == 8) { if (ismasked) { - UML_DLOAD(block, IREG(3), fastbase, IREG(0), SIZE_QWORD, SCALE_x1); // dload i3,fastbase,i0,qword_x1 - UML_DAND(block, IREG(1), IREG(1), IREG(2)); // dand i1,i1,i2 - UML_DXOR(block, IREG(2), IREG(2), IMM(U64(0xffffffffffffffff))); // dxor i2,i2,0xfffffffffffffffff - UML_DAND(block, IREG(3), IREG(3), IREG(2)); // dand i3,i3,i2 - UML_DOR(block, IREG(1), IREG(1), IREG(3)); // dor i1,i1,i3 + UML_DLOAD(block, I3, fastbase, I0, SIZE_QWORD, SCALE_x1); // dload i3,fastbase,i0,qword_x1 + UML_DAND(block, I1, I1, I2); // dand i1,i1,i2 + UML_DXOR(block, I2, I2, U64(0xffffffffffffffff)); // dxor i2,i2,0xfffffffffffffffff + UML_DAND(block, I3, I3, I2); // dand i3,i3,i2 + UML_DOR(block, I1, I1, I3); // dor i1,i1,i3 } - UML_DSTORE(block, fastbase, IREG(0), IREG(1), SIZE_QWORD, SCALE_x1); // dstore fastbase,i0,i1,qword_x1 + UML_DSTORE(block, fastbase, I0, I1, SIZE_QWORD, SCALE_x1); // dstore fastbase,i0,i1,qword_x1 } UML_RET(block); // ret } @@ -1599,25 +1599,25 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si { case 1: if (iswrite) - UML_WRITE(block, IREG(0), IREG(1), SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte + UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0,i1,program_byte else - UML_READ(block, IREG(0), IREG(0), SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte + UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0,i0,program_byte break; case 2: if (iswrite) { if (!ismasked) - UML_WRITE(block, IREG(0), IREG(1), SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word + UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word else - UML_WRITEM(block, IREG(0), IREG(1), IREG(2), SIZE_WORD, SPACE_PROGRAM); // writem i0,i2,i1,program_word + UML_WRITEM(block, I0, I1, I2, SIZE_WORD, SPACE_PROGRAM); // writem i0,i2,i1,program_word } else { if (!ismasked) - UML_READ(block, IREG(0), IREG(0), SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word + UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word else - UML_READM(block, IREG(0), IREG(0), IREG(2), SIZE_WORD, SPACE_PROGRAM); // readm i0,i0,i2,program_word + UML_READM(block, I0, I0, I2, SIZE_WORD, SPACE_PROGRAM); // readm i0,i0,i2,program_word } break; @@ -1625,16 +1625,16 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si if (iswrite) { if (!ismasked) - UML_WRITE(block, IREG(0), IREG(1), SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword + UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword else - UML_WRITEM(block, IREG(0), IREG(1), IREG(2), SIZE_DWORD, SPACE_PROGRAM); // writem i0,i2,i1,program_dword + UML_WRITEM(block, I0, I1, I2, SIZE_DWORD, SPACE_PROGRAM); // writem i0,i2,i1,program_dword } else { if (!ismasked) - UML_READ(block, IREG(0), IREG(0), SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword + UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword else - UML_READM(block, IREG(0), IREG(0), IREG(2), SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword + UML_READM(block, I0, I0, I2, SIZE_DWORD, SPACE_PROGRAM); // readm i0,i0,i2,program_dword } break; @@ -1642,16 +1642,16 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si if (iswrite) { if (!ismasked) - UML_DWRITE(block, IREG(0), IREG(1), SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword + UML_DWRITE(block, I0, I1, SIZE_QWORD, SPACE_PROGRAM); // dwrite i0,i1,program_qword else - UML_DWRITEM(block, IREG(0), IREG(1), IREG(2), SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i2,i1,program_qword + UML_DWRITEM(block, I0, I1, I2, SIZE_QWORD, SPACE_PROGRAM); // dwritem i0,i2,i1,program_qword } else { if (!ismasked) - UML_DREAD(block, IREG(0), IREG(0), SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword + UML_DREAD(block, I0, I0, SIZE_QWORD, SPACE_PROGRAM); // dread i0,i0,program_qword else - UML_DREADM(block, IREG(0), IREG(0), IREG(2), SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword + UML_DREADM(block, I0, I0, I2, SIZE_QWORD, SPACE_PROGRAM); // dreadm i0,i0,i2,program_qword } break; } @@ -1665,29 +1665,29 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si { if (iswrite) { - UML_MOV(block, MEM(&ppc->impstate->tempaddr), IREG(0)); // mov [tempaddr],i0 - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(1)); // mov [tempdata],i1 - UML_SUB(block, IREG(0), IREG(0), IMM(1)); // sub i0,i0,1 - UML_SHR(block, IREG(1), IREG(1), IMM(8)); // shr i1,i1,8 - UML_MOV(block, IREG(2), IMM(0x00ff)); // mov i2,0x00ff + UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I1); // mov [tempdata],i1 + UML_SUB(block, I0, I0, 1); // sub i0,i0,1 + UML_SHR(block, I1, I1, 8); // shr i1,i1,8 + UML_MOV(block, I2, 0x00ff); // mov i2,0x00ff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(1)); // add i0,[tempaddr],1 - UML_SHL(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l), IMM(8)); // shl i1,[tempdata],8 - UML_MOV(block, IREG(2), IMM(0xff00)); // mov i2,0xff00 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 + UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 8); // shl i1,[tempdata],8 + UML_MOV(block, I2, 0xff00); // mov i2,0xff00 UML_CALLH(block, *masked); // callh masked } else { - UML_MOV(block, MEM(&ppc->impstate->tempaddr), IREG(0)); // mov [tempaddr],i0 - UML_SUB(block, IREG(0), IREG(0), IMM(1)); // sub i0,i0,1 - UML_MOV(block, IREG(2), IMM(0x00ff)); // mov i2,0x00ff + UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_SUB(block, I0, I0, 1); // sub i0,i0,1 + UML_MOV(block, I2, 0x00ff); // mov i2,0x00ff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0), IMM(8)); // shl [tempdata],i0,8 - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(1)); // add i0,[tempaddr],1 - UML_MOV(block, IREG(2), IMM(0xff00)); // mov i2,0xff00 + UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 8); // shl [tempdata],i0,8 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 + UML_MOV(block, I2, 0xff00); // mov i2,0xff00 UML_CALLH(block, *masked); // callh masked - UML_SHR(block, IREG(0), IREG(0), IMM(8)); // shr i0,i0,8 - UML_OR(block, IREG(0), IREG(0), MEM(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_SHR(block, I0, I0, 8); // shr i0,i0,8 + UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] } } else if (size == 4) @@ -1695,79 +1695,79 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si int offs2, offs3; if (iswrite) { - UML_MOV(block, MEM(&ppc->impstate->tempaddr), IREG(0)); // mov [tempaddr],i0 - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(1)); // mov [tempdata],i1 - UML_TEST(block, IREG(0), IMM(2)); // test i0,i0,2 - UML_JMPc(block, IF_NZ, offs2 = label++); // jnz offs2 - UML_SUB(block, IREG(0), IREG(0), IMM(1)); // sub i0,i0,1 - UML_SHR(block, IREG(1), IREG(1), IMM(8)); // shr i1,i1,8 - UML_MOV(block, IREG(2), IMM(0x00ffffff)); // mov i2,0x00ffffff + UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I1); // mov [tempdata],i1 + UML_TEST(block, I0, 2); // test i0,i0,2 + UML_JMPc(block, COND_NZ, offs2 = label++); // jnz offs2 + UML_SUB(block, I0, I0, 1); // sub i0,i0,1 + UML_SHR(block, I1, I1, 8); // shr i1,i1,8 + UML_MOV(block, I2, 0x00ffffff); // mov i2,0x00ffffff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(3)); // add i0,[tempaddr],3 - UML_SHL(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l), IMM(24)); // shl i1,[tempdata],24 - UML_MOV(block, IREG(2), IMM(0xff000000)); // mov i2,0xff000000 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 3); // add i0,[tempaddr],3 + UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 24); // shl i1,[tempdata],24 + UML_MOV(block, I2, 0xff000000); // mov i2,0xff000000 UML_CALLH(block, *masked); // callh masked UML_RET(block); // ret UML_LABEL(block, offs2); // offs2: - UML_TEST(block, IREG(0), IMM(1)); // test i0,i0,1 - UML_JMPc(block, IF_NZ, offs3 = label++); // jnz offs3 - UML_SUB(block, IREG(0), IREG(0), IMM(2)); // sub i0,i0,2 - UML_SHR(block, IREG(1), IREG(1), IMM(16)); // shr i1,i1,16 - UML_MOV(block, IREG(2), IMM(0x0000ffff)); // mov i2,0x0000ffff + UML_TEST(block, I0, 1); // test i0,i0,1 + UML_JMPc(block, COND_NZ, offs3 = label++); // jnz offs3 + UML_SUB(block, I0, I0, 2); // sub i0,i0,2 + UML_SHR(block, I1, I1, 16); // shr i1,i1,16 + UML_MOV(block, I2, 0x0000ffff); // mov i2,0x0000ffff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(2)); // add i0,[tempaddr],2 - UML_SHL(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l), IMM(16)); // shl i1,[tempdata],16 - UML_MOV(block, IREG(2), IMM(0xffff0000)); // mov i2,0xffff0000 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 2); // add i0,[tempaddr],2 + UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 16); // shl i1,[tempdata],16 + UML_MOV(block, I2, 0xffff0000); // mov i2,0xffff0000 UML_CALLH(block, *masked); // callh masked UML_RET(block); // ret UML_LABEL(block, offs3); // offs3: - UML_SUB(block, IREG(0), IREG(0), IMM(3)); // sub i0,i0,3 - UML_SHR(block, IREG(1), IREG(1), IMM(24)); // shr i1,i1,24 - UML_MOV(block, IREG(2), IMM(0x000000ff)); // mov i2,0x000000ff + UML_SUB(block, I0, I0, 3); // sub i0,i0,3 + UML_SHR(block, I1, I1, 24); // shr i1,i1,24 + UML_MOV(block, I2, 0x000000ff); // mov i2,0x000000ff UML_CALLH(block, *masked); // callh masked - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(1)); // add i0,[tempaddr],1 - UML_SHL(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l), IMM(8)); // shl i1,[tempdata],8 - UML_MOV(block, IREG(2), IMM(0xffffff00)); // mov i2,0xffffff00 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 + UML_SHL(block, I1, mem(&ppc->impstate->tempdata.w.l), 8); // shl i1,[tempdata],8 + UML_MOV(block, I2, 0xffffff00); // mov i2,0xffffff00 UML_CALLH(block, *masked); // callh masked } else { - UML_MOV(block, MEM(&ppc->impstate->tempaddr), IREG(0)); // mov [tempaddr],i0 - UML_TEST(block, IREG(0), IMM(2)); // test i0,i0,2 - UML_JMPc(block, IF_NZ, offs2 = label++); // jnz offs2 - UML_SUB(block, IREG(0), IREG(0), IMM(1)); // sub i0,i0,1 - UML_MOV(block, IREG(2), IMM(0x00ffffff)); // mov i2,0x00ffffff + UML_MOV(block, mem(&ppc->impstate->tempaddr), I0); // mov [tempaddr],i0 + UML_TEST(block, I0, 2); // test i0,i0,2 + UML_JMPc(block, COND_NZ, offs2 = label++); // jnz offs2 + UML_SUB(block, I0, I0, 1); // sub i0,i0,1 + UML_MOV(block, I2, 0x00ffffff); // mov i2,0x00ffffff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0), IMM(8)); // shl [tempdata],i0,8 - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(3)); // add i0,[tempaddr],3 - UML_MOV(block, IREG(2), IMM(0xff000000)); // mov i2,0xff000000 + UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 8); // shl [tempdata],i0,8 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 3); // add i0,[tempaddr],3 + UML_MOV(block, I2, 0xff000000); // mov i2,0xff000000 UML_CALLH(block, *masked); // callh masked - UML_SHR(block, IREG(0), IREG(0), IMM(24)); // shr i0,i0,24 - UML_OR(block, IREG(0), IREG(0), MEM(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_SHR(block, I0, I0, 24); // shr i0,i0,24 + UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] UML_RET(block); // ret UML_LABEL(block, offs2); // offs2: - UML_TEST(block, IREG(0), IMM(1)); // test i0,i0,1 - UML_JMPc(block, IF_NZ, offs3 = label++); // jnz offs3 - UML_SUB(block, IREG(0), IREG(0), IMM(2)); // sub i0,i0,2 - UML_MOV(block, IREG(2), IMM(0x0000ffff)); // mov i2,0x0000ffff + UML_TEST(block, I0, 1); // test i0,i0,1 + UML_JMPc(block, COND_NZ, offs3 = label++); // jnz offs3 + UML_SUB(block, I0, I0, 2); // sub i0,i0,2 + UML_MOV(block, I2, 0x0000ffff); // mov i2,0x0000ffff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0), IMM(16)); // shl [tempdata],i0,16 - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(2)); // add i0,[tempaddr],2 - UML_MOV(block, IREG(2), IMM(0xffff0000)); // mov i2,0xffff0000 + UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 16); // shl [tempdata],i0,16 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 2); // add i0,[tempaddr],2 + UML_MOV(block, I2, 0xffff0000); // mov i2,0xffff0000 UML_CALLH(block, *masked); // callh masked - UML_SHR(block, IREG(0), IREG(0), IMM(16)); // shr i0,i0,16 - UML_OR(block, IREG(0), IREG(0), MEM(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_SHR(block, I0, I0, 16); // shr i0,i0,16 + UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] UML_RET(block); // ret UML_LABEL(block, offs3); // offs3: - UML_SUB(block, IREG(0), IREG(0), IMM(3)); // sub i0,i0,3 - UML_MOV(block, IREG(2), IMM(0x000000ff)); // mov i2,0x000000ff + UML_SUB(block, I0, I0, 3); // sub i0,i0,3 + UML_MOV(block, I2, 0x000000ff); // mov i2,0x000000ff UML_CALLH(block, *masked); // callh masked - UML_SHL(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0), IMM(24)); // shl [tempdata],i0,24 - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(1)); // add i0,[tempaddr],1 - UML_MOV(block, IREG(2), IMM(0xffffff00)); // mov i2,0xffffff00 + UML_SHL(block, mem(&ppc->impstate->tempdata.w.l), I0, 24); // shl [tempdata],i0,24 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 1); // add i0,[tempaddr],1 + UML_MOV(block, I2, 0xffffff00); // mov i2,0xffffff00 UML_CALLH(block, *masked); // callh masked - UML_SHR(block, IREG(0), IREG(0), IMM(8)); // shr i0,i0,8 - UML_OR(block, IREG(0), IREG(0), MEM(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] + UML_SHR(block, I0, I0, 8); // shr i0,i0,8 + UML_OR(block, I0, I0, mem(&ppc->impstate->tempdata.w.l)); // or i0,i0,[tempdata] } } UML_RET(block); // ret @@ -1778,46 +1778,46 @@ static void static_generate_memory_accessor(powerpc_state *ppc, int mode, int si { UML_LABEL(block, alignex); // alignex: UML_RECOVER(block, SPR32(SPROEA_DSISR), MAPVAR_DSISR); // recover [dsisr],DSISR - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ALIGN], IREG(0)); // exh align,i0 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_ALIGN], I0); // exh align,i0 } /* handle a TLB miss */ if (tlbmiss != 0) { UML_LABEL(block, tlbmiss); // tlbmiss: - UML_MOV(block, MEM(&ppc->param0), IREG(0)); // mov [param0],i0 - UML_MOV(block, MEM(&ppc->param1), IMM(translate_type)); // mov [param1],translate_type + UML_MOV(block, mem(&ppc->param0), I0); // mov [param0],i0 + UML_MOV(block, mem(&ppc->param1), translate_type); // mov [param1],translate_type UML_CALLC(block, (c_function)ppccom_tlb_fill, ppc); // callc tlbfill,ppc - UML_SHR(block, IREG(3), IREG(0), IMM(12)); // shr i3,i0,12 - UML_LOAD(block, IREG(3), (void *)vtlb_table(ppc->vtlb), IREG(3), SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword - UML_TEST(block, IREG(3), IMM((UINT64)1 << translate_type)); // test i3,1 << translate_type - UML_JMPc(block, IF_NZ, tlbreturn); // jmp tlbreturn,nz + UML_SHR(block, I3, I0, 12); // shr i3,i0,12 + UML_LOAD(block, I3, (void *)vtlb_table(ppc->vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb],i3,dword + UML_TEST(block, I3, (UINT64)1 << translate_type); // test i3,1 << translate_type + UML_JMPc(block, COND_NZ, tlbreturn); // jmp tlbreturn,nz /* 4XX case: protection exception */ if (ppc->cap & PPCCAP_4XX) { - UML_MOV(block, SPR32(SPR4XX_DEAR), IREG(0)); // mov [dear],i0 - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DSI], IREG(0)); // exh dsi,i0 + UML_MOV(block, SPR32(SPR4XX_DEAR), I0); // mov [dear],i0 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DSI], I0); // exh dsi,i0 } /* 603 case: TLBMISS exception */ else if (ppc->cap & PPCCAP_603_MMU) { - UML_MOV(block, SPR32(SPR603_DMISS), IREG(0)); // mov [dmiss],i0 - UML_MOV(block, SPR32(SPR603_DCMP), MEM(&ppc->mmu603_cmp)); // mov [dcmp],[mmu603_cmp] - UML_MOV(block, SPR32(SPR603_HASH1), MEM(&ppc->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] - UML_MOV(block, SPR32(SPR603_HASH2), MEM(&ppc->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] + UML_MOV(block, SPR32(SPR603_DMISS), I0); // mov [dmiss],i0 + UML_MOV(block, SPR32(SPR603_DCMP), mem(&ppc->mmu603_cmp)); // mov [dcmp],[mmu603_cmp] + UML_MOV(block, SPR32(SPR603_HASH1), mem(&ppc->mmu603_hash[0])); // mov [hash1],[mmu603_hash][0] + UML_MOV(block, SPR32(SPR603_HASH2), mem(&ppc->mmu603_hash[1])); // mov [hash2],[mmu603_hash][1] if (iswrite) - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DTLBMISSS], IREG(0)); // exh dtlbmisss,i0 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DTLBMISSS], I0); // exh dtlbmisss,i0 else - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DTLBMISSL], IREG(0)); // exh dtlbmissl,i0 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DTLBMISSL], I0); // exh dtlbmissl,i0 } /* general case: DSI exception */ else { - UML_MOV(block, SPR32(SPROEA_DSISR), MEM(&ppc->param0)); // mov [dsisr],[param0] - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DSI], IREG(0)); // exh dsi,i0 + UML_MOV(block, SPR32(SPROEA_DSISR), mem(&ppc->param0)); // mov [dsisr],[param0] + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_DSI], I0); // exh dsi,i0 } } @@ -1844,9 +1844,9 @@ static void static_generate_swap_tgpr(powerpc_state *ppc) UML_HANDLE(block, *ppc->impstate->swap_tgpr); // handle swap_tgpr for (regnum = 0; regnum < 4; regnum++) { - UML_MOV(block, IREG(1), R32(regnum)); // mov i1,r[regnum] - UML_MOV(block, R32(regnum), MEM(&ppc->mmu603_r[regnum])); // mov r[regnum],mmu603_r[regnum] - UML_MOV(block, MEM(&ppc->mmu603_r[regnum]), IREG(1)); // mov mmu603_r[regnum],i1 + UML_MOV(block, I1, R32(regnum)); // mov i1,r[regnum] + UML_MOV(block, R32(regnum), mem(&ppc->mmu603_r[regnum])); // mov r[regnum],mmu603_r[regnum] + UML_MOV(block, mem(&ppc->mmu603_r[regnum]), I1); // mov mmu603_r[regnum],i1 } UML_RET(block); // ret @@ -1879,30 +1879,30 @@ static void static_generate_lsw_entries(powerpc_state *ppc, int mode) alloc_handle(drcuml, &ppc->impstate->lsw[mode][regnum], temp); UML_HANDLE(block, *ppc->impstate->lsw[mode][regnum]); // handle lsw<regnum> UML_LABEL(block, regnum); // regnum: - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(0)); // add i0,[updateaddr],0 + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 0); // add i0,[updateaddr],0 UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 - UML_ROLAND(block, R32(regnum), IREG(0), IMM(24), IMM(0xff000000)); // roland reg,i0,24,0xff000000 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(1)); // add i0,[updateaddr],1 + UML_ROLAND(block, R32(regnum), I0, 24, 0xff000000); // roland reg,i0,24,0xff000000 + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 1); // add i0,[updateaddr],1 UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 - UML_ROLAND(block, IREG(0), IREG(0), IMM(16), IMM(0x00ff0000)); // roland i0,i0,16,0x00ff0000 - UML_OR(block, R32(regnum), R32(regnum), IREG(0)); // or reg,i0 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(2)); // add i0,[updateaddr],2 + UML_ROLAND(block, I0, I0, 16, 0x00ff0000); // roland i0,i0,16,0x00ff0000 + UML_OR(block, R32(regnum), R32(regnum), I0); // or reg,i0 + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 2); // add i0,[updateaddr],2 UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 - UML_ROLAND(block, IREG(0), IREG(0), IMM(8), IMM(0x0000ff00)); // roland i0,i0,8,0x0000ff00 - UML_OR(block, R32(regnum), R32(regnum), IREG(0)); // or reg,i0 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(3)); // add i0,[updateaddr],3 - UML_ADD(block, MEM(&ppc->impstate->updateaddr), IREG(0), IMM(1)); // add [updateaddr],i0,1 + UML_ROLAND(block, I0, I0, 8, 0x0000ff00); // roland i0,i0,8,0x0000ff00 + UML_OR(block, R32(regnum), R32(regnum), I0); // or reg,i0 + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 3); // add i0,[updateaddr],3 + UML_ADD(block, mem(&ppc->impstate->updateaddr), I0, 1); // add [updateaddr],i0,1 UML_CALLH(block, *ppc->impstate->read8[mode]); // callh read8 - UML_ROLAND(block, IREG(0), IREG(0), IMM(0), IMM(0x000000ff)); // roland i0,i0,0,0x000000ff - UML_OR(block, R32(regnum), R32(regnum), IREG(0)); // or reg,i0 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z + UML_ROLAND(block, I0, I0, 0, 0x000000ff); // roland i0,i0,0,0x000000ff + UML_OR(block, R32(regnum), R32(regnum), I0); // or reg,i0 + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z UML_JMP(block, (regnum + 1) % 32); // jmp nextreg } @@ -1935,27 +1935,27 @@ static void static_generate_stsw_entries(powerpc_state *ppc, int mode) alloc_handle(drcuml, &ppc->impstate->stsw[mode][regnum], temp); UML_HANDLE(block, *ppc->impstate->stsw[mode][regnum]); // handle stsw<regnum> UML_LABEL(block, regnum); // regnum: - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(0)); // add i0,[updateaddr],0 - UML_ROLAND(block, IREG(1), R32(regnum), IMM(8), IMM(0xff)); // roland i1,regnum,8,0xff + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 0); // add i0,[updateaddr],0 + UML_ROLAND(block, I1, R32(regnum), 8, 0xff); // roland i1,regnum,8,0xff UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(1)); // add i0,[updateaddr],1 - UML_ROLAND(block, IREG(1), R32(regnum), IMM(16), IMM(0xff)); // roland i1,regnum,16,0xff + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 1); // add i0,[updateaddr],1 + UML_ROLAND(block, I1, R32(regnum), 16, 0xff); // roland i1,regnum,16,0xff UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(2)); // add i0,[updateaddr],2 - UML_ROLAND(block, IREG(1), R32(regnum), IMM(24), IMM(0xff)); // roland i1,regnum,24,0xff + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 2); // add i0,[updateaddr],2 + UML_ROLAND(block, I1, R32(regnum), 24, 0xff); // roland i1,regnum,24,0xff UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z - UML_ADD(block, IREG(0), MEM(&ppc->impstate->updateaddr), IMM(3)); // add i0,[updateaddr],3 - UML_ADD(block, MEM(&ppc->impstate->updateaddr), IREG(0), IMM(1)); // add [updateaddr],i0,1 - UML_ROLAND(block, IREG(1), R32(regnum), IMM(0), IMM(0xff)); // roland i1,regnum,0,0xff + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z + UML_ADD(block, I0, mem(&ppc->impstate->updateaddr), 3); // add i0,[updateaddr],3 + UML_ADD(block, mem(&ppc->impstate->updateaddr), I0, 1); // add [updateaddr],i0,1 + UML_ROLAND(block, I1, R32(regnum), 0, 0xff); // roland i1,regnum,0,0xff UML_CALLH(block, *ppc->impstate->write8[mode]); // callh write8 - UML_SUB(block, MEM(&ppc->impstate->swcount), MEM(&ppc->impstate->swcount), IMM(1)); // sub [swcount],[swcount],1 - UML_RETc(block, IF_Z); // ret z + UML_SUB(block, mem(&ppc->impstate->swcount), mem(&ppc->impstate->swcount), 1); // sub [swcount],[swcount],1 + UML_RETc(block, COND_Z); // ret z UML_JMP(block, (regnum + 1) % 32); // jmp nextreg } @@ -1976,25 +1976,25 @@ static void static_generate_stsw_entries(powerpc_state *ppc, int mode) static void generate_update_mode(powerpc_state *ppc, drcuml_block *block) { /* LE in bit 0 of mode */ - UML_AND(block, IREG(0), MSR32, IMM(MSR_LE)); // and i0,msr,MSR_LE + UML_AND(block, I0, MSR32, MSR_LE); // and i0,msr,MSR_LE /* DR (OEA and 403GCX) in bit 1 of mode */ if ((ppc->cap & PPCCAP_OEA) || ppc->flavor == PPC_MODEL_403GCX) { - UML_ROLAND(block, IREG(1), MSR32, IMM(29), IMM(0x02)); // roland i1,[msr],29,0x02 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 + UML_ROLAND(block, I1, MSR32, 29, 0x02); // roland i1,[msr],29,0x02 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 } /* (4XX) in bit 1 of mode */ if (ppc->cap & PPCCAP_4XX) { - UML_ROLAND(block, IREG(1), MSR32, IMM(30), IMM(0x02)); // roland i1,[msr],30,0x02 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 + UML_ROLAND(block, I1, MSR32, 30, 0x02); // roland i1,[msr],30,0x02 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 } /* PR in bit 2 of mode */ - UML_ROLAND(block, IREG(1), MSR32, IMM(20), IMM(0x04)); // roland i1,[msr],20,0x04 - UML_OR(block, MEM(&ppc->impstate->mode), IREG(0), IREG(1)); // or [mode],i0,i1 + UML_ROLAND(block, I1, MSR32, 20, 0x04); // roland i1,[msr],20,0x04 + UML_OR(block, mem(&ppc->impstate->mode), I0, I1); // or [mode],i0,i1 } @@ -2012,12 +2012,12 @@ static void generate_update_cycles(powerpc_state *ppc, drcuml_block *block, comp code_label skip; compiler->checkints = FALSE; - UML_TEST(block, MEM(&ppc->irq_pending), IMM(~0)); // test [irq_pending],0 - UML_JMPc(block, IF_Z, skip = compiler->labelnum++); // jmp skip,Z - UML_TEST(block, MSR32, IMM(MSR_EE)); // test [msr],MSR_EE - UML_JMPc(block, IF_Z, skip); // jmp skip,Z - UML_MOV(block, IREG(0), param); // mov i0,nextpc - UML_MOV(block, IREG(1), IMM(compiler->cycles)); // mov i1,cycles + UML_TEST(block, mem(&ppc->irq_pending), ~0); // test [irq_pending],0 + UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z + UML_TEST(block, MSR32, MSR_EE); // test [msr],MSR_EE + UML_JMPc(block, COND_Z, skip); // jmp skip,Z + UML_MOV(block, I0, param); // mov i0,nextpc + UML_MOV(block, I1, compiler->cycles); // mov i1,cycles UML_CALLH(block, *ppc->impstate->exception_norecover[EXCEPTION_EI]); // callh interrupt_norecover UML_LABEL(block, skip); // skip: } @@ -2025,10 +2025,10 @@ static void generate_update_cycles(powerpc_state *ppc, drcuml_block *block, comp /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, MEM(&ppc->icount), MEM(&ppc->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 if (allow_exception) - UML_EXHc(block, IF_S, *ppc->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc + UML_EXHc(block, COND_S, *ppc->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; } @@ -2051,9 +2051,9 @@ static void generate_checksum_block(powerpc_state *ppc, drcuml_block *block, com if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP)) { void *base = ppc->direct->read_decrypted_ptr(seqhead->physpc, ppc->codexor); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,dword - UML_CMP(block, IREG(0), IMM(seqhead->opptr.l[0])); // cmp i0,*opptr - UML_EXHc(block, IF_NE, *ppc->impstate->nocode, IMM(seqhead->pc)); // exne nocode,seqhead->pc + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,dword + UML_CMP(block, I0, seqhead->opptr.l[0]); // cmp i0,*opptr + UML_EXHc(block, COND_NE, *ppc->impstate->nocode, seqhead->pc); // exne nocode,seqhead->pc } } @@ -2065,25 +2065,25 @@ static void generate_checksum_block(powerpc_state *ppc, drcuml_block *block, com if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { void *base = ppc->direct->read_decrypted_ptr(seqhead->physpc, ppc->codexor); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,dword - UML_CMP(block, IREG(0), IMM(curdesc->opptr.l[0])); // cmp i0,*opptr - UML_EXHc(block, IF_NE, *ppc->impstate->nocode, IMM(seqhead->pc)); // exne nocode,seqhead->pc + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,dword + UML_CMP(block, I0, curdesc->opptr.l[0]); // cmp i0,*opptr + UML_EXHc(block, COND_NE, *ppc->impstate->nocode, seqhead->pc); // exne nocode,seqhead->pc } #else UINT32 sum = 0; void *base = ppc->direct->read_decrypted_ptr(seqhead->physpc, ppc->codexor); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,dword + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,dword sum += seqhead->opptr.l[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { base = ppc->direct->read_decrypted_ptr(curdesc->physpc, ppc->codexor); - UML_LOAD(block, IREG(1), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, IREG(0), IREG(0), IREG(1)); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.l[0]; } - UML_CMP(block, IREG(0), IMM(sum)); // cmp i0,sum - UML_EXHc(block, IF_NE, *ppc->impstate->nocode, IMM(seqhead->pc)); // exne nocode,seqhead->pc + UML_CMP(block, I0, sum); // cmp i0,sum + UML_EXHc(block, COND_NE, *ppc->impstate->nocode, seqhead->pc); // exne nocode,seqhead->pc #endif } } @@ -2122,24 +2122,24 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc /* if we want a probe, add it here */ if (desc->pc == PROBE_ADDRESS) { - UML_MOV(block, MEM(&ppc->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc UML_CALLC(block, cfunc_printf_probe, (void *)desc->pc); // callc cfunc_printf_probe,desc->pc } /* if we are debugging, call the debugger */ if ((ppc->device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, MEM(&ppc->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(ppc, block); // <save fastregs> - UML_DEBUG(block, IMM(desc->pc)); // debug desc->pc + UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, MEM(&ppc->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(ppc, block); // <save fastregs> - UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE + UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } /* if we hit a compiler page fault, it's just like a TLB mismatch */ @@ -2148,11 +2148,11 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc if (PRINTF_MMU) { const char *text = "Compiler page fault @ %08X\n"; - UML_MOV(block, MEM(&ppc->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc + UML_MOV(block, mem(&ppc->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&ppc->impstate->arg0), desc->pc); // mov [arg0],desc->pc UML_CALLC(block, cfunc_printf_debug, ppc); // callc printf_debug } - UML_EXH(block, *ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0 + UML_EXH(block, *ppc->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 } /* validate our TLB entry at this PC; if we fail, we need to handle it */ @@ -2166,13 +2166,13 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc if (PRINTF_MMU) { const char *text = "Checking TLB at @ %08X\n"; - UML_MOV(block, MEM(&ppc->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc + UML_MOV(block, mem(&ppc->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&ppc->impstate->arg0), desc->pc); // mov [arg0],desc->pc UML_CALLC(block, cfunc_printf_debug, ppc); // callc printf_debug } - UML_LOAD(block, IREG(0), &tlbtable[desc->pc >> 12], IMM(0), SIZE_DWORD, SCALE_x4);// load i0,tlbtable[desc->pc >> 12],dword - UML_CMP(block, IREG(0), IMM(tlbtable[desc->pc >> 12])); // cmp i0,*tlbentry - UML_EXHc(block, IF_NE, *ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0,NE + UML_LOAD(block, I0, &tlbtable[desc->pc >> 12], 0, SIZE_DWORD, SCALE_x4);// load i0,tlbtable[desc->pc >> 12],dword + UML_CMP(block, I0, tlbtable[desc->pc >> 12]); // cmp i0,*tlbentry + UML_EXHc(block, COND_NE, *ppc->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0,NE } /* otherwise, we generate an unconditional exception */ @@ -2181,21 +2181,21 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc if (PRINTF_MMU) { const char *text = "No valid TLB @ %08X\n"; - UML_MOV(block, MEM(&ppc->impstate->format), IMM((FPTR)text)); // mov [format],text - UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc + UML_MOV(block, mem(&ppc->impstate->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&ppc->impstate->arg0), desc->pc); // mov [arg0],desc->pc UML_CALLC(block, cfunc_printf_debug, ppc); // callc printf_debug } - UML_EXH(block, *ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0 + UML_EXH(block, *ppc->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 } } /* if this is an invalid opcode, generate the exception now */ if (desc->flags & OPFLAG_INVALID_OPCODE) - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x80000)); // exh exception_program,0x80000 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000 /* if this is a privileged opcode in user mode, generate the exception */ else if ((desc->flags & OPFLAG_PRIVILEGED) && (ppc->impstate->mode & MODE_USER)) - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x40000)); // exh exception_program,0x40000 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x40000); // exh exception_program,0x40000 /* otherwise, unless this is a virtual no-op, it's a regular instruction */ else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP)) @@ -2203,8 +2203,8 @@ static void generate_sequence_instruction(powerpc_state *ppc, drcuml_block *bloc /* compile the instruction */ if (!generate_opcode(ppc, block, compiler, desc)) { - UML_MOV(block, MEM(&ppc->pc), IMM(desc->pc)); // mov [pc],desc->pc - UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],*desc->opptr.l + UML_MOV(block, mem(&ppc->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&ppc->impstate->arg0), desc->opptr.l[0]); // mov [arg0],*desc->opptr.l UML_CALLC(block, cfunc_unimplemented, ppc); // callc cfunc_unimplemented,ppc } } @@ -2236,9 +2236,9 @@ static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, cons /* semi-easy case: crfield only */ if (xermask == 0) { - UML_GETFLGS(block, IREG(0), FLAG_S | FLAG_Z); // getflgs i0,sz - UML_LOAD(block, IREG(0), ppc->impstate->sz_cr_table, IREG(0), SIZE_BYTE, SCALE_x1); // load i0,sz_cr_table,i0,byte - UML_OR(block, CR32(0), IREG(0), XERSO32); // or [cr0],i0,[xerso] + UML_GETFLGS(block, I0, FLAG_S | FLAG_Z); // getflgs i0,sz + UML_LOAD(block, I0, ppc->impstate->sz_cr_table, I0, SIZE_BYTE, SCALE_x1); // load i0,sz_cr_table,i0,byte + UML_OR(block, CR32(0), I0, XERSO32); // or [cr0],i0,[xerso] return; } @@ -2247,35 +2247,35 @@ static void generate_compute_flags(powerpc_state *ppc, drcuml_block *block, cons { if (xermask & XER_OV) { - UML_GETFLGS(block, IREG(0), xerflags); // getflgs i0,xerflags + UML_GETFLGS(block, I0, xerflags); // getflgs i0,xerflags if (invertcarry && (xermask & XER_CA)) - UML_XOR(block, IREG(0), IREG(0), IMM(FLAG_C)); // xor i0,i0,FLAG_C - UML_ROLINS(block, SPR32(SPR_XER), IREG(0), IMM(29), IMM(xermask)); // rolins [xer],i0,29,xermask - UML_SHR(block, IREG(0), IREG(0), IMM(1)); // shr i0,i0,1 - UML_OR(block, XERSO32, XERSO32, IREG(0)); // or [xerso],i0 + UML_XOR(block, I0, I0, FLAG_C); // xor i0,i0,FLAG_C + UML_ROLINS(block, SPR32(SPR_XER), I0, 29, xermask); // rolins [xer],i0,29,xermask + UML_SHR(block, I0, I0, 1); // shr i0,i0,1 + UML_OR(block, XERSO32, XERSO32, I0); // or [xerso],i0 } else { - UML_SETc(block, invertcarry ? IF_NC : IF_C, IREG(0)); // setc i0,nc/c - UML_ROLINS(block, SPR32(SPR_XER), IREG(0), IMM(29), IMM(XER_CA)); // rolins [xer],i0,29,XER_CA + UML_SETc(block, invertcarry ? COND_NC : COND_C, I0); // setc i0,nc/c + UML_ROLINS(block, SPR32(SPR_XER), I0, 29, XER_CA); // rolins [xer],i0,29,XER_CA } return; } /* tricky case: both */ - UML_GETFLGS(block, IREG(0), FLAG_S | FLAG_Z | xerflags); // getflgs i0,SZ | xerflags - UML_LOAD(block, IREG(1), ppc->impstate->sz_cr_table, IREG(0), SIZE_BYTE, SCALE_x1); // load i1,sz_cr_table,i0,byte + UML_GETFLGS(block, I0, FLAG_S | FLAG_Z | xerflags); // getflgs i0,SZ | xerflags + UML_LOAD(block, I1, ppc->impstate->sz_cr_table, I0, SIZE_BYTE, SCALE_x1); // load i1,sz_cr_table,i0,byte if (invertcarry && (xermask & XER_CA)) - UML_XOR(block, IREG(0), IREG(0), IMM(FLAG_C)); // xor i0,i0,FLAG_C - UML_ROLINS(block, SPR32(SPR_XER), IREG(0), IMM(29), IMM(xermask)); // rolins [xer],i0,29,xermask + UML_XOR(block, I0, I0, FLAG_C); // xor i0,i0,FLAG_C + UML_ROLINS(block, SPR32(SPR_XER), I0, 29, xermask); // rolins [xer],i0,29,xermask if (xermask & XER_OV) { - UML_ROLAND(block, IREG(0), IREG(0), IMM(31), IMM(1)); // roland i0,i0,31,0x0001 - UML_OR(block, XERSO32, XERSO32, IREG(0)); // or [xerso],i0 - UML_OR(block, CR32(0), IREG(1), IREG(0)); // or [cr0],i1,i0 + UML_ROLAND(block, I0, I0, 31, 1); // roland i0,i0,31,0x0001 + UML_OR(block, XERSO32, XERSO32, I0); // or [xerso],i0 + UML_OR(block, CR32(0), I1, I0); // or [cr0],i1,i0 } else - UML_OR(block, CR32(0), IREG(1), XERSO32); // or [cr0],i1,[xerso] + UML_OR(block, CR32(0), I1, XERSO32); // or [cr0],i1,[xerso] } /*------------------------------------------------- @@ -2288,7 +2288,7 @@ static void generate_fp_flags(powerpc_state *ppc, drcuml_block *block, const opc /* for now, only handle the FPRF field */ if (updatefprf) { - UML_MOV(block, MEM(&ppc->param0), IMM(G_RD(desc->opptr.l[0]))); + UML_MOV(block, mem(&ppc->param0), G_RD(desc->opptr.l[0])); UML_CALLC(block, (c_function)ppccom_update_fprf, ppc); } } @@ -2308,26 +2308,26 @@ static void generate_branch(powerpc_state *ppc, drcuml_block *block, compiler_st { if (desc->targetpc == BRANCH_TARGET_DYNAMIC && source == SPR_LR) { - UML_MOV(block, MEM(&ppc->impstate->tempaddr), MEM(srcptr)); // mov [tempaddr],[lr] + UML_MOV(block, mem(&ppc->impstate->tempaddr), mem(srcptr)); // mov [tempaddr],[lr] srcptr = &ppc->impstate->tempaddr; } - UML_MOV(block, SPR32(SPR_LR), IMM(desc->pc + 4)); // mov [lr],desc->pc + 4 + UML_MOV(block, SPR32(SPR_LR), desc->pc + 4); // mov [lr],desc->pc + 4 } /* update the cycles and jump through the hash table to the target */ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { - generate_update_cycles(ppc, block, &compiler_temp, IMM(desc->targetpc), TRUE); // <subtract cycles> + generate_update_cycles(ppc, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000 else - UML_HASHJMP(block, IMM(ppc->impstate->mode), IMM(desc->targetpc), *ppc->impstate->nocode); + UML_HASHJMP(block, ppc->impstate->mode, desc->targetpc, *ppc->impstate->nocode); // hashjmp <mode>,desc->targetpc,nocode } else { - generate_update_cycles(ppc, block, &compiler_temp, MEM(srcptr), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(ppc->impstate->mode), MEM(srcptr), *ppc->impstate->nocode); // hashjmp <mode>,<rsreg>,nocode + generate_update_cycles(ppc, block, &compiler_temp, mem(srcptr), TRUE); // <subtract cycles> + UML_HASHJMP(block, ppc->impstate->mode, mem(srcptr), *ppc->impstate->nocode); // hashjmp <mode>,<rsreg>,nocode } /* update the label */ @@ -2349,13 +2349,13 @@ static void generate_branch_bo(powerpc_state *ppc, drcuml_block *block, compiler if (!(bo & 0x04)) { - UML_SUB(block, SPR32(SPR_CTR), SPR32(SPR_CTR), IMM(1)); // sub [ctr],[ctr],1 - UML_JMPc(block, (bo & 0x02) ? IF_NZ : IF_Z, skip); // jmp skip,nz/z + UML_SUB(block, SPR32(SPR_CTR), SPR32(SPR_CTR), 1); // sub [ctr],[ctr],1 + UML_JMPc(block, (bo & 0x02) ? COND_NZ : COND_Z, skip); // jmp skip,nz/z } if (!(bo & 0x10)) { - UML_TEST(block, CR32(bi / 4), IMM(8 >> (bi % 4))); // test cr32(bi/4),8 >> (bi % 4) - UML_JMPc(block, (bo & 0x08) ? IF_Z : IF_NZ, skip); // jmp skip,z/nz + UML_TEST(block, CR32(bi / 4), 8 >> (bi % 4)); // test cr32(bi/4),8 >> (bi % 4) + UML_JMPc(block, (bo & 0x08) ? COND_Z : COND_NZ, skip); // jmp skip,z/nz } generate_branch(ppc, block, compiler, desc, source, link); // <branch> UML_LABEL(block, skip); // skip: @@ -2382,58 +2382,58 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta return FALSE; case 0x03: /* TWI */ - UML_CMP(block, R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // cmp ra,simm + UML_CMP(block, R32(G_RA(op)), (INT16)G_SIMM(op)); // cmp ra,simm if (G_TO(op) & 0x10) - UML_EXHc(block, IF_L, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,l + UML_EXHc(block, COND_L, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,l if (G_TO(op) & 0x08) - UML_EXHc(block, IF_G, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,g + UML_EXHc(block, COND_G, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,g if (G_TO(op) & 0x04) - UML_EXHc(block, IF_E, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,e + UML_EXHc(block, COND_E, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,e if (G_TO(op) & 0x02) - UML_EXHc(block, IF_B, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,b + UML_EXHc(block, COND_B, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b if (G_TO(op) & 0x01) - UML_EXHc(block, IF_A, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,a + UML_EXHc(block, COND_A, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a return TRUE; case 0x07: /* MULLI */ - UML_MULS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); + UML_MULS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), (INT16)G_SIMM(op)); // muls rd,rd,ra,simm return TRUE; case 0x0e: /* ADDI */ - UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add rd,ra,simm + UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add rd,ra,simm return TRUE; case 0x0f: /* ADDIS */ - UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), IMM(G_SIMM(op) << 16)); // add rd,ra,simm << 16 + UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), G_SIMM(op) << 16); // add rd,ra,simm << 16 return TRUE; case 0x0a: /* CMPLI */ - UML_CMP(block, R32(G_RA(op)), IMM(G_UIMM(op))); // cmp ra,uimm - UML_GETFLGS(block, IREG(0), FLAG_Z | FLAG_C); // getflgs i0,zc - UML_LOAD(block, IREG(0), ppc->impstate->cmpl_cr_table, IREG(0), SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte - UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + UML_CMP(block, R32(G_RA(op)), G_UIMM(op)); // cmp ra,uimm + UML_GETFLGS(block, I0, FLAG_Z | FLAG_C); // getflgs i0,zc + UML_LOAD(block, I0, ppc->impstate->cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x0b: /* CMPI */ - UML_CMP(block, R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // cmp ra,uimm - UML_GETFLGS(block, IREG(0), FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs - UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte - UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + UML_CMP(block, R32(G_RA(op)), (INT16)G_SIMM(op)); // cmp ra,uimm + UML_GETFLGS(block, I0, FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs + UML_LOAD(block, I0, ppc->impstate->cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x08: /* SUBFIC */ - UML_SUB(block, R32(G_RD(op)), IMM((INT16)G_SIMM(op)), R32(G_RA(op))); // sub rd,simm,ra + UML_SUB(block, R32(G_RD(op)), (INT16)G_SIMM(op), R32(G_RA(op))); // sub rd,simm,ra generate_compute_flags(ppc, block, desc, FALSE, XER_CA, TRUE); // <update flags> return TRUE; case 0x0c: /* ADDIC */ - UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add rd,ra,simm + UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), (INT16)G_SIMM(op)); // add rd,ra,simm generate_compute_flags(ppc, block, desc, FALSE, XER_CA, FALSE); // <update flags> return TRUE; case 0x0d: /* ADDIC. */ - UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add rd,ra,simm + UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), (INT16)G_SIMM(op)); // add rd,ra,simm generate_compute_flags(ppc, block, desc, TRUE, XER_CA, FALSE); // <update flags> return TRUE; @@ -2443,7 +2443,7 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta case 0x11: /* SC */ UML_MAPVAR(block, MAPVAR_PC, desc->pc + 4); // mapvar PC,desc->pc+4 - UML_EXH(block, *ppc->impstate->exception[EXCEPTION_SYSCALL], IMM(0)); // exh syscall,0 + UML_EXH(block, *ppc->impstate->exception[EXCEPTION_SYSCALL], 0); // exh syscall,0 return TRUE; case 0x12: /* Bx */ @@ -2454,49 +2454,49 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta return generate_instruction_13(ppc, block, compiler, desc); // <group13> case 0x14: /* RLWIMIx */ - UML_ROLINS(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_SH(op)), IMM(compute_rlw_mask(G_MB(op), G_ME(op)))); + UML_ROLINS(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op), compute_rlw_mask(G_MB(op), G_ME(op))); // rolins ra,rs,sh,mask if (op & M_RC) generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x15: /* RLWINMx */ - UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_SH(op)), IMM(compute_rlw_mask(G_MB(op), G_ME(op)))); + UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op), compute_rlw_mask(G_MB(op), G_ME(op))); // roland ra,rs,sh,mask if (op & M_RC) generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x17: /* RLWNMx */ - UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), IMM(compute_rlw_mask(G_MB(op), G_ME(op)))); + UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), compute_rlw_mask(G_MB(op), G_ME(op))); // roland ra,rs,rb,mask if (op & M_RC) generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x18: /* ORI */ - UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op))); // or ra,rs,uimm + UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // or ra,rs,uimm return TRUE; case 0x19: /* ORIS */ - UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op) << 16)); // or ra,rs,uimm << 16 + UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // or ra,rs,uimm << 16 return TRUE; case 0x1a: /* XORI */ - UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op))); // xor ra,rs,uimm + UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // xor ra,rs,uimm return TRUE; case 0x1b: /* XORIS */ - UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op) << 16)); // xor ra,rs,uimm << 16 + UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // xor ra,rs,uimm << 16 return TRUE; case 0x1c: /* ANDI. */ - UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op))); // and ra,rs,uimm + UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // and ra,rs,uimm generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x1d: /* ANDIS. */ - UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_UIMM(op) << 16)); // and ra,rs,uimm << 16 + UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // and ra,rs,uimm << 16 generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; @@ -2504,235 +2504,235 @@ static int generate_opcode(powerpc_state *ppc, drcuml_block *block, compiler_sta return generate_instruction_1f(ppc, block, compiler, desc); // <group1f> case 0x22: /* LBZ */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x28: /* LHZ */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2a: /* LHA */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_SEXT(block, R32(G_RD(op)), IREG(0), SIZE_WORD); // sext rd,i0,word - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x20: /* LWZ */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x23: /* LBZU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x29: /* LHZU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2b: /* LHAU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_SEXT(block, R32(G_RD(op)), IREG(0), SIZE_WORD); // sext rd,i0,word - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x21: /* LWZU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x26: /* STB */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2c: /* STH */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs,0xffff + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x24: /* STW */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x27: /* STBU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2d: /* STHU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs,0xffff - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x25: /* STWU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2e: /* LMW */ UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_MOV(block, MEM(&ppc->impstate->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra + UML_MOV(block, mem(&ppc->impstate->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra for (regnum = G_RD(op); regnum < 32; regnum++) { - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM((INT16)G_SIMM(op) + 4 * (regnum - G_RD(op)))); + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), (INT16)G_SIMM(op) + 4 * (regnum - G_RD(op))); // add i0,[tempaddr],simm + 4*(regnum-rd) UML_CALLH(block, *ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align - UML_MOV(block, R32(regnum), IREG(0)); // mov regnum,i0 + UML_MOV(block, R32(regnum), I0); // mov regnum,i0 } - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2f: /* STMW */ UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) - UML_MOV(block, MEM(&ppc->impstate->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra + UML_MOV(block, mem(&ppc->impstate->tempaddr), R32Z(G_RA(op))); // mov [tempaddr],ra for (regnum = G_RS(op); regnum < 32; regnum++) { - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM((INT16)G_SIMM(op) + 4 * (regnum - G_RS(op)))); + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), (INT16)G_SIMM(op) + 4 * (regnum - G_RS(op))); // add i0,[tempaddr],simm + 4*(regnum-rs) - UML_MOV(block, IREG(1), R32(regnum)); // mov i1,regnum + UML_MOV(block, I1, R32(regnum)); // mov i1,regnum UML_CALLH(block, *ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align } - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x30: /* LFS */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x32: /* LFD */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x31: /* LFSU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x33: /* LFDU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x34: /* STFS */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x36: /* STFD */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] + UML_ADD(block, I0, R32Z(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op) UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x35: /* STFSU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x37: /* STFDU */ - UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm - UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), (INT16)G_SIMM(op)); // add i0,ra,simm + UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op) UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x3b: /* 0x3b group */ @@ -2772,71 +2772,71 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x101: /* CRAND */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_AND(block, IREG(0), IREG(0), IREG(1)); // and i0,i1 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_AND(block, I0, I0, I1); // and i0,i1 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x081: /* CRANDC */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_XOR(block, IREG(1), IREG(1), IMM(~0)); // xor i1,~0 - UML_AND(block, IREG(0), IREG(0), IREG(1)); // and i0,i1 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_XOR(block, I1, I1, ~0); // xor i1,~0 + UML_AND(block, I0, I0, I1); // and i0,i1 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x0e1: /* CRNAND */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_AND(block, IREG(0), IREG(0), IREG(1)); // and i0,i1 - UML_XOR(block, IREG(0), IREG(0), IMM(~0)); // xor i0,~0 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_AND(block, I0, I0, I1); // and i0,i1 + UML_XOR(block, I0, I0, ~0); // xor i0,~0 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x1c1: /* CROR */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i1 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_OR(block, I0, I0, I1); // or i0,i1 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x1a1: /* CRORC */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_XOR(block, IREG(1), IREG(1), IMM(~0)); // xor i1,~0 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i1 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_XOR(block, I1, I1, ~0); // xor i1,~0 + UML_OR(block, I0, I0, I1); // or i0,i1 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x021: /* CRNOR */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i1 - UML_XOR(block, IREG(0), IREG(0), IMM(~0)); // xor i0,~0 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_OR(block, I0, I0, I1); // or i0,i1 + UML_XOR(block, I0, I0, ~0); // xor i0,~0 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x0c1: /* CRXOR */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_XOR(block, IREG(0), IREG(0), IREG(1)); // xor i0,i1 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_XOR(block, I0, I0, I1); // xor i0,i1 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; case 0x121: /* CREQV */ - UML_SHL(block, IREG(0), CR32(G_CRBA(op) / 4), IMM(G_CRBA(op) % 4)); // shl i0,cr(a / 4),a % 4 - UML_SHL(block, IREG(1), CR32(G_CRBB(op) / 4), IMM(G_CRBB(op) % 4)); // shl i1,cr(b / 4),b % 4 - UML_XOR(block, IREG(0), IREG(0), IREG(1)); // xor i0,i1 - UML_XOR(block, IREG(0), IREG(0), IMM(~0)); // xor i0,~0 - UML_ROLINS(block, CR32(G_CRBD(op) / 4), IREG(0), IMM(32 - G_CRBD(op) % 4), IMM(8 >> (G_CRBD(op) % 4))); + UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4 + UML_SHL(block, I1, CR32(G_CRBB(op) / 4), G_CRBB(op) % 4); // shl i1,cr(b / 4),b % 4 + UML_XOR(block, I0, I0, I1); // xor i0,i1 + UML_XOR(block, I0, I0, ~0); // xor i0,~0 + UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4)); // rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4) return TRUE; @@ -2844,15 +2844,15 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp if (ppc->cap & PPCCAP_OEA) { if (!(ppc->cap & PPCCAP_603_MMU)) - UML_ROLINS(block, MSR32, SPR32(SPROEA_SRR1), IMM(0), IMM(0x87c0ffff)); // rolins [msr],[srr1],0,0x87c0ffff + UML_ROLINS(block, MSR32, SPR32(SPROEA_SRR1), 0, 0x87c0ffff); // rolins [msr],[srr1],0,0x87c0ffff else { - UML_MOV(block, IREG(0), MSR32); // mov i0,[msr] - UML_ROLINS(block, MSR32, SPR32(SPROEA_SRR1), IMM(0), IMM(0x87c0ffff | MSR603_TGPR)); + UML_MOV(block, I0, MSR32); // mov i0,[msr] + UML_ROLINS(block, MSR32, SPR32(SPROEA_SRR1), 0, 0x87c0ffff | MSR603_TGPR); // rolins [msr],[srr1],0,0x87c0ffff | MSR603_TGPR - UML_XOR(block, IREG(0), IREG(0), MSR32); // xor i0,i0,[msr] - UML_TEST(block, IREG(0), IMM(MSR603_TGPR)); // test i0,tgpr - UML_CALLHc(block, IF_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz + UML_XOR(block, I0, I0, MSR32); // xor i0,i0,[msr] + UML_TEST(block, I0, MSR603_TGPR); // test i0,tgpr + UML_CALLHc(block, COND_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz } } else if (ppc->cap & PPCCAP_4XX) @@ -2860,7 +2860,7 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp generate_update_mode(ppc, block); // <update mode> compiler->checkints = TRUE; generate_update_cycles(ppc, block, compiler, SPR32(SPROEA_SRR0), TRUE); // <subtract cycles> - UML_HASHJMP(block, MEM(&ppc->impstate->mode), SPR32(SPROEA_SRR0), *ppc->impstate->nocode); + UML_HASHJMP(block, mem(&ppc->impstate->mode), SPR32(SPROEA_SRR0), *ppc->impstate->nocode); // hashjmp mode,[srr0],nocode return TRUE; @@ -2870,7 +2870,7 @@ static int generate_instruction_13(powerpc_state *ppc, drcuml_block *block, comp generate_update_mode(ppc, block); // <update mode> compiler->checkints = TRUE; generate_update_cycles(ppc, block, compiler, SPR32(SPR4XX_SRR2), TRUE); // <subtract cycles> - UML_HASHJMP(block, MEM(&ppc->impstate->mode), SPR32(SPR4XX_SRR2), *ppc->impstate->nocode); + UML_HASHJMP(block, mem(&ppc->impstate->mode), SPR32(SPR4XX_SRR2), *ppc->impstate->nocode); // hashjmp mode,[srr2],nocode return TRUE; @@ -2927,15 +2927,15 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x004: /* TW */ UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb if (G_TO(op) & 0x10) - UML_EXHc(block, IF_L, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,l + UML_EXHc(block, COND_L, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,l if (G_TO(op) & 0x08) - UML_EXHc(block, IF_G, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,g + UML_EXHc(block, COND_G, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,g if (G_TO(op) & 0x04) - UML_EXHc(block, IF_E, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,e + UML_EXHc(block, COND_E, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,e if (G_TO(op) & 0x02) - UML_EXHc(block, IF_B, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,b + UML_EXHc(block, COND_B, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b if (G_TO(op) & 0x01) - UML_EXHc(block, IF_A, *ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x20000));// exh program,0x20000,a + UML_EXHc(block, COND_A, *ppc->impstate->exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a return TRUE; case 0x10a: /* ADDx */ @@ -2954,7 +2954,7 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x08a: /* ADDEx */ case 0x28a: /* ADDEOx */ - UML_CARRY(block, SPR32(SPR_XER), IMM(29)); // carry [xer],XER_CA + UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // addc rd,ra,rb generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> @@ -2962,16 +2962,16 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x0ca: /* ADDZEx */ case 0x2ca: /* ADDZEOx */ - UML_CARRY(block, SPR32(SPR_XER), IMM(29)); // carry [xer],XER_CA - UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), IMM(0)); // addc rd,ra,0 + UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA + UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), 0); // addc rd,ra,0 generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; case 0x0ea: /* ADDMEx */ case 0x2ea: /* ADDMEOx */ - UML_CARRY(block, SPR32(SPR_XER), IMM(29)); // carry [xer],XER_CA - UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), IMM((UINT32)-1)); // addc rd,ra,-1 + UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA + UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), (UINT32)-1); // addc rd,ra,-1 generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE); // <update flags> return TRUE; @@ -2992,8 +2992,8 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x088: /* SUBFEx */ case 0x288: /* SUBFEOx */ - UML_XOR(block, IREG(0), SPR32(SPR_XER), IMM(XER_CA)); // xor i0,[xer],XER_CA - UML_CARRY(block, IREG(0), IMM(29)); // carry i0,XER_CA + UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA + UML_CARRY(block, I0, 29); // carry i0,XER_CA UML_SUBB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // subc rd,rb,ra generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> @@ -3001,57 +3001,57 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x0c8: /* SUBFZEx */ case 0x2c8: /* SUBFZEOx */ - UML_XOR(block, IREG(0), SPR32(SPR_XER), IMM(XER_CA)); // xor i0,[xer],XER_CA - UML_CARRY(block, IREG(0), IMM(29)); // carry i0,XER_CA - UML_SUBB(block, R32(G_RD(op)), IMM(0), R32(G_RA(op))); // subc rd,0,ra + UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA + UML_CARRY(block, I0, 29); // carry i0,XER_CA + UML_SUBB(block, R32(G_RD(op)), 0, R32(G_RA(op))); // subc rd,0,ra generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> return TRUE; case 0x0e8: /* SUBFMEx */ case 0x2e8: /* SUBFMEOx */ - UML_XOR(block, IREG(0), SPR32(SPR_XER), IMM(XER_CA)); // xor i0,[xer],XER_CA - UML_CARRY(block, IREG(0), IMM(29)); // carry i0,XER_CA - UML_SUBB(block, R32(G_RD(op)), IMM((UINT32)-1), R32(G_RA(op))); // subc rd,-1,ra + UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA + UML_CARRY(block, I0, 29); // carry i0,XER_CA + UML_SUBB(block, R32(G_RD(op)), (UINT32)-1, R32(G_RA(op))); // subc rd,-1,ra generate_compute_flags(ppc, block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE); // <update flags> return TRUE; case 0x068: /* NEGx */ case 0x268: /* NEGOx */ - UML_SUB(block, R32(G_RD(op)), IMM(0), R32(G_RA(op))); // sub rd,0,ra + UML_SUB(block, R32(G_RD(op)), 0, R32(G_RA(op))); // sub rd,0,ra generate_compute_flags(ppc, block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE); // <update flags> return TRUE; case 0x000: /* CMP */ UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb - UML_GETFLGS(block, IREG(0), FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs - UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte - UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + UML_GETFLGS(block, I0, FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs + UML_LOAD(block, I0, ppc->impstate->cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x020: /* CMPL */ UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb - UML_GETFLGS(block, IREG(0), FLAG_Z | FLAG_C); // getflgs i0,zc - UML_LOAD(block, IREG(0), ppc->impstate->cmpl_cr_table, IREG(0), SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte - UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + UML_GETFLGS(block, I0, FLAG_Z | FLAG_C); // getflgs i0,zc + UML_LOAD(block, I0, ppc->impstate->cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x00b: /* MULHWUx */ - UML_MULU(block, IREG(0), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // mulu i0,rd,ra,rb + UML_MULU(block, I0, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // mulu i0,rd,ra,rb if (op & M_RC) { - UML_TEST(block, R32(G_RD(op)), IMM(~0)); // test rd,~0 + UML_TEST(block, R32(G_RD(op)), ~0); // test rd,~0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> } return TRUE; case 0x04b: /* MULHWx */ - UML_MULS(block, IREG(0), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // muls i0,rd,ra,rb + UML_MULS(block, I0, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // muls i0,rd,ra,rb if (op & M_RC) { - UML_TEST(block, R32(G_RD(op)), IMM(~0)); // test rd,~0 + UML_TEST(block, R32(G_RD(op)), ~0); // test rd,~0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> } return TRUE; @@ -3080,14 +3080,14 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x03c: /* ANDCx */ - UML_XOR(block, IREG(0), R32(G_RB(op)), IMM(~0)); // xor i0,rb,~0 - UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), IREG(0)); // and ra,rs,i0 + UML_XOR(block, I0, R32(G_RB(op)), ~0); // xor i0,rb,~0 + UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), I0); // and ra,rs,i0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x1dc: /* NANDx */ - UML_AND(block, IREG(0), R32(G_RS(op)), R32(G_RB(op))); // and i0,rs,rb - UML_XOR(block, R32(G_RA(op)), IREG(0), IMM(~0)); // xor ra,i0,~0 + UML_AND(block, I0, R32(G_RS(op)), R32(G_RB(op))); // and i0,rs,rb + UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; @@ -3097,14 +3097,14 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x19c: /* ORCx */ - UML_XOR(block, IREG(0), R32(G_RB(op)), IMM(~0)); // xor i0,rb,~0 - UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), IREG(0)); // or ra,rs,i0 + UML_XOR(block, I0, R32(G_RB(op)), ~0); // xor i0,rb,~0 + UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), I0); // or ra,rs,i0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x07c: /* NORx */ - UML_OR(block, IREG(0), R32(G_RS(op)), R32(G_RB(op))); // or i0,rs,rb - UML_XOR(block, R32(G_RA(op)), IREG(0), IMM(~0)); // xor ra,i0,~0 + UML_OR(block, I0, R32(G_RS(op)), R32(G_RB(op))); // or i0,rs,rb + UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; @@ -3114,8 +3114,8 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x11c: /* EQVx */ - UML_XOR(block, IREG(0), R32(G_RS(op)), R32(G_RB(op))); // xor i0,rs,rb - UML_XOR(block, R32(G_RA(op)), IREG(0), IMM(~0)); // xor ra,i0,~0 + UML_XOR(block, I0, R32(G_RS(op)), R32(G_RB(op))); // xor i0,rs,rb + UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; @@ -3125,41 +3125,41 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x218: /* SRWx */ - UML_MOV(block, IREG(0), R32(G_RS(op))); // mov i0,rs - UML_TEST(block, R32(G_RB(op)), IMM(0x20)); // test rb,0x20 - UML_MOVc(block, IF_NZ, IREG(0), IMM(0)); // mov i0,0,nz - UML_SHR(block, R32(G_RA(op)), IREG(0), R32(G_RB(op))); // shr ra,i0,rb + UML_MOV(block, I0, R32(G_RS(op))); // mov i0,rs + UML_TEST(block, R32(G_RB(op)), 0x20); // test rb,0x20 + UML_MOVc(block, COND_NZ, I0, 0); // mov i0,0,nz + UML_SHR(block, R32(G_RA(op)), I0, R32(G_RB(op))); // shr ra,i0,rb generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x318: /* SRAWx */ - UML_MOV(block, IREG(2), R32(G_RB(op))); // mov i2,rb - UML_TEST(block, IREG(2), IMM(0x20)); // test i2,0x20 - UML_MOVc(block, IF_NZ, IREG(2), IMM(31)); // mov i2,31,nz + UML_MOV(block, I2, R32(G_RB(op))); // mov i2,rb + UML_TEST(block, I2, 0x20); // test i2,0x20 + UML_MOVc(block, COND_NZ, I2, 31); // mov i2,31,nz if (DISABLE_FLAG_OPTIMIZATIONS || (desc->regreq[3] & REGFLAG_XER_CA)) { - UML_SHL(block, IREG(1), IMM(0xffffffff), IREG(2)); // shl i1,0xffffffff,i2 - UML_XOR(block, IREG(1), IREG(1), IMM(~0)); // xor i1,i1,~0 - UML_AND(block, IREG(0), R32(G_RS(op)), IREG(1)); // and i0,rs,i1 - UML_SAR(block, IREG(1), R32(G_RS(op)), IMM(31)); // sar i1,rs,31 - UML_TEST(block, IREG(0), IREG(1)); // test i0,i1 - UML_SETc(block, IF_NZ, IREG(0)); // set i0,nz - UML_ROLINS(block, SPR32(SPR_XER), IREG(0), IMM(29), IMM(XER_CA)); // rolins [xer],i0,29,XER_CA + UML_SHL(block, I1, 0xffffffff, I2); // shl i1,0xffffffff,i2 + UML_XOR(block, I1, I1, ~0); // xor i1,i1,~0 + UML_AND(block, I0, R32(G_RS(op)), I1); // and i0,rs,i1 + UML_SAR(block, I1, R32(G_RS(op)), 31); // sar i1,rs,31 + UML_TEST(block, I0, I1); // test i0,i1 + UML_SETc(block, COND_NZ, I0); // set i0,nz + UML_ROLINS(block, SPR32(SPR_XER), I0, 29, XER_CA); // rolins [xer],i0,29,XER_CA } - UML_SAR(block, R32(G_RA(op)), R32(G_RS(op)), IREG(2)); // sar ra,rs,i2 + UML_SAR(block, R32(G_RA(op)), R32(G_RS(op)), I2); // sar ra,rs,i2 generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; case 0x338: /* SRAWIx */ if (DISABLE_FLAG_OPTIMIZATIONS || (desc->regreq[3] & REGFLAG_XER_CA)) { - UML_AND(block, IREG(0), R32(G_RS(op)), IMM(~(0xffffffff << (G_SH(op) & 31))));// and i0,rs,~(0xffffffff << (sh & 31)) - UML_SAR(block, IREG(1), R32(G_RS(op)), IMM(31)); // sar i1,rs,31 - UML_TEST(block, IREG(0), IREG(1)); // test i0,i1 - UML_SETc(block, IF_NZ, IREG(0)); // set i0,nz - UML_ROLINS(block, SPR32(SPR_XER), IREG(0), IMM(29), IMM(XER_CA)); // rolins [xer],i0,29,XER_CA + UML_AND(block, I0, R32(G_RS(op)), ~(0xffffffff << (G_SH(op) & 31)));// and i0,rs,~(0xffffffff << (sh & 31)) + UML_SAR(block, I1, R32(G_RS(op)), 31); // sar i1,rs,31 + UML_TEST(block, I0, I1); // test i0,i1 + UML_SETc(block, COND_NZ, I0); // set i0,nz + UML_ROLINS(block, SPR32(SPR_XER), I0, 29, XER_CA); // rolins [xer],i0,29,XER_CA } - UML_SAR(block, R32(G_RA(op)), R32(G_RS(op)), IMM(G_SH(op))); // sar ra,rs,sh + UML_SAR(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op)); // sar ra,rs,sh generate_compute_flags(ppc, block, desc, op & M_RC, 0, FALSE); // <update flags> return TRUE; @@ -3182,155 +3182,155 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x057: /* LBZX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x117: /* LHZX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x157: /* LHAX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_SEXT(block, R32(G_RD(op)), IREG(0), SIZE_WORD); // sext rd,i0,word - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x017: /* LWZX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x217: /* LFSX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x257: /* LFDX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x316: /* LHBRX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_BSWAP(block, IREG(0), IREG(0)); // bswap i0,i0 - UML_SHR(block, R32(G_RD(op)), IREG(0), IMM(16)); // shr rd,i0,16 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_BSWAP(block, I0, I0); // bswap i0,i0 + UML_SHR(block, R32(G_RD(op)), I0, 16); // shr rd,i0,16 + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x216: /* LWBRX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align - UML_BSWAP(block, R32(G_RD(op)), IREG(0)); // bswap rd,i0 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_BSWAP(block, R32(G_RD(op)), I0); // bswap rd,i0 + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x077: /* LBZUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) UML_CALLH(block, *ppc->impstate->read8[ppc->impstate->mode]); // callh read8 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x137: /* LHZUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x177: /* LHAUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) UML_CALLH(block, *ppc->impstate->read16[ppc->impstate->mode]); // callh read16 - UML_SEXT(block, R32(G_RD(op)), IREG(0), SIZE_WORD); // sext rd,i0,word - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x037: /* LWZUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x237: /* LFSUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read32[ppc->impstate->mode]); // callh read32 - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0 - UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), I0); // mov [tempdata],i0 + UML_FDFRFLT(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l), SIZE_DWORD); // fdfrflt fd,[tempdata],dword + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x277: /* LFDUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read64[ppc->impstate->mode]); // callh read64 - UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0 - UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_DMOV(block, mem(&ppc->impstate->tempdata.d), I0); // dmov [tempdata],i0 + UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata] + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x014: /* LWARX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align - UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0 + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x255: /* LSWI */ - UML_MOV(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra - UML_MOV(block, MEM(&ppc->impstate->swcount), IMM(((G_NB(op) - 1) & 0x1f) + 1)); // mov [swcount],G_NB + UML_MOV(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra + UML_MOV(block, mem(&ppc->impstate->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB UML_CALLH(block, *ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]); // call lsw[rd] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x215: /* LSWX */ - UML_ADD(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb - UML_AND(block, MEM(&ppc->impstate->swcount), SPR32(SPR_XER), IMM(0x7f)); // and [swcount],[xer],0x7f - UML_SUB(block, MEM(&ppc->icount), MEM(&ppc->icount), MEM(&ppc->impstate->swcount));// sub icount,icount,[swcount] - UML_CALLHc(block, IF_NZ, *ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]); // call lsw[rd],nz - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_ADD(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb + UML_AND(block, mem(&ppc->impstate->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f + UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), mem(&ppc->impstate->swcount));// sub icount,icount,[swcount] + UML_CALLHc(block, COND_NZ, *ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]); // call lsw[rd],nz + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x136: /* ECIWX */ @@ -3338,153 +3338,153 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return FALSE; case 0x0d7: /* STBX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x197: /* STHX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x097: /* STWX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x297: /* STFSX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x3d7: /* STFIWX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata.lo] + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata.lo] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2d7: /* STFDX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x396: /* STHBRX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_BSWAP(block, IREG(1), R32(G_RS(op))); // bswap i1,rs - UML_SHR(block, IREG(1), IREG(1), IMM(16)); // shr i1,i1,16 + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_BSWAP(block, I1, R32(G_RS(op))); // bswap i1,rs + UML_SHR(block, I1, I1, 16); // shr i1,i1,16 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x296: /* STWBRX */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_BSWAP(block, IREG(1), R32(G_RS(op))); // bswap i1,rs + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_BSWAP(block, I1, R32(G_RS(op))); // bswap i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x0f7: /* STBUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write8[ppc->impstate->mode]); // callh write8 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x1b7: /* STHUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs,0xffff - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write16[ppc->impstate->mode]); // callh write16 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x0b7: /* STWUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2b7: /* STFSUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword - UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_FSFRFLT(block, mem(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), SIZE_QWORD); // fsfrflt [tempdata],rs,qword + UML_MOV(block, I1, mem(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata] + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write32[ppc->impstate->mode]); // callh write32 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x2f7: /* STFDUX */ - UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs - UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] - UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0 + UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs + UML_DMOV(block, I1, mem(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata] + UML_MOV(block, mem(&ppc->impstate->updateaddr), I0); // mov [updateaddr],i0 UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 - UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_MOV(block, R32(G_RA(op)), mem(&ppc->impstate->updateaddr)); // mov ra,[updateaddr] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x096: /* STWCX. */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, *ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> - UML_CMP(block, IREG(0), IREG(0)); // cmp i0,i0 - UML_GETFLGS(block, IREG(0), FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs - UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte - UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + UML_CMP(block, I0, I0); // cmp i0,i0 + UML_GETFLGS(block, I0, FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs + UML_LOAD(block, I0, ppc->impstate->cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; case 0x2d5: /* STSWI */ - UML_MOV(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra - UML_MOV(block, MEM(&ppc->impstate->swcount), IMM(((G_NB(op) - 1) & 0x1f) + 1)); // mov [swcount],G_NB + UML_MOV(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra + UML_MOV(block, mem(&ppc->impstate->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB UML_CALLH(block, *ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]); // call stsw[rd] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x295: /* STSWX */ - UML_ADD(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb - UML_AND(block, MEM(&ppc->impstate->swcount), SPR32(SPR_XER), IMM(0x7f)); // and [swcount],[xer],0x7f - UML_SUB(block, MEM(&ppc->icount), MEM(&ppc->icount), MEM(&ppc->impstate->swcount));// sub icount,icount,[swcount] - UML_CALLHc(block, IF_NZ, *ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]); // call stsw[rd] - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_ADD(block, mem(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb + UML_AND(block, mem(&ppc->impstate->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f + UML_SUB(block, mem(&ppc->icount), mem(&ppc->icount), mem(&ppc->impstate->swcount));// sub icount,icount,[swcount] + UML_CALLHc(block, COND_NZ, *ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]); // call stsw[rd] + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x1b6: /* ECOWX */ @@ -3504,19 +3504,19 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x3f6: /* DCBZ */ - UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb - UML_AND(block, MEM(&ppc->impstate->tempaddr), IREG(0), IMM(~(ppc->cache_line_size - 1))); + UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb + UML_AND(block, mem(&ppc->impstate->tempaddr), I0, ~(ppc->cache_line_size - 1)); // and [tempaddr],i0,~(cache_line_size - 1) for (item = 0; item < ppc->cache_line_size / 8; item++) { - UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(8 * item)); // add i0,[tempaddr],8*item - UML_DMOV(block, IREG(1), IMM(0)); // dmov i1,0 + UML_ADD(block, I0, mem(&ppc->impstate->tempaddr), 8 * item); // add i0,[tempaddr],8*item + UML_DMOV(block, I1, 0); // dmov i1,0 UML_CALLH(block, *ppc->impstate->write64[ppc->impstate->mode]); // callh write64 } return TRUE; case 0x132: /* TLBIE */ - UML_MOV(block, MEM(&ppc->param0), R32(G_RB(op))); // mov [param0],rb + UML_MOV(block, mem(&ppc->param0), R32(G_RB(op))); // mov [param0],rb UML_CALLC(block, (c_function)ppccom_execute_tlbie, ppc); // callc ppccom_execute_tlbie,ppc return TRUE; @@ -3526,34 +3526,34 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x3d2: /* TLBLD */ assert(ppc->cap & PPCCAP_603_MMU); - UML_MOV(block, MEM(&ppc->param0), R32(G_RB(op))); // mov [param0],rb - UML_MOV(block, MEM(&ppc->param1), IMM(0)); // mov [param1],0 + UML_MOV(block, mem(&ppc->param0), R32(G_RB(op))); // mov [param0],rb + UML_MOV(block, mem(&ppc->param1), 0); // mov [param1],0 UML_CALLC(block, (c_function)ppccom_execute_tlbl, ppc); // callc ppccom_execute_tlbl,ppc return TRUE; case 0x3f2: /* TLBLI */ assert(ppc->cap & PPCCAP_603_MMU); - UML_MOV(block, MEM(&ppc->param0), R32(G_RB(op))); // mov [param0],rb - UML_MOV(block, MEM(&ppc->param1), IMM(1)); // mov [param1],1 + UML_MOV(block, mem(&ppc->param0), R32(G_RB(op))); // mov [param0],rb + UML_MOV(block, mem(&ppc->param1), 1); // mov [param1],1 UML_CALLC(block, (c_function)ppccom_execute_tlbl, ppc); // callc ppccom_execute_tlbl,ppc return TRUE; case 0x013: /* MFCR */ - UML_SHL(block, IREG(0), CR32(0), IMM(28)); // shl i0,cr(0),28 - UML_ROLAND(block, IREG(1), CR32(1), IMM(24), IMM(0x0f000000)); // roland i1,cr(1),24,0x0f000000 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLAND(block, IREG(1), CR32(2), IMM(20), IMM(0x00f00000)); // roland i1,cr(2),20,0x00f00000 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLAND(block, IREG(1), CR32(3), IMM(16), IMM(0x000f0000)); // roland i1,cr(3),16,0x000f0000 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLAND(block, IREG(1), CR32(4), IMM(12), IMM(0x0000f000)); // roland i1,cr(4),12,0x0000f000 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLAND(block, IREG(1), CR32(5), IMM(8), IMM(0x00000f00)); // roland i1,cr(5),8,0x00000f00 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLAND(block, IREG(1), CR32(6), IMM(4), IMM(0x000000f0)); // roland i1,cr(6),4,0x000000f0 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or i0,i0,i1 - UML_ROLAND(block, IREG(1), CR32(7), IMM(0), IMM(0x0000000f)); // roland i1,cr(7),0,0x0000000f - UML_OR(block, R32(G_RD(op)), IREG(0), IREG(1)); // or rd,i0,i1 + UML_SHL(block, I0, CR32(0), 28); // shl i0,cr(0),28 + UML_ROLAND(block, I1, CR32(1), 24, 0x0f000000); // roland i1,cr(1),24,0x0f000000 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLAND(block, I1, CR32(2), 20, 0x00f00000); // roland i1,cr(2),20,0x00f00000 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLAND(block, I1, CR32(3), 16, 0x000f0000); // roland i1,cr(3),16,0x000f0000 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLAND(block, I1, CR32(4), 12, 0x0000f000); // roland i1,cr(4),12,0x0000f000 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLAND(block, I1, CR32(5), 8, 0x00000f00); // roland i1,cr(5),8,0x00000f00 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLAND(block, I1, CR32(6), 4, 0x000000f0); // roland i1,cr(6),4,0x000000f0 + UML_OR(block, I0, I0, I1); // or i0,i0,i1 + UML_ROLAND(block, I1, CR32(7), 0, 0x0000000f); // roland i1,cr(7),0,0x0000000f + UML_OR(block, R32(G_RD(op)), I0, I1); // or rd,i0,i1 return TRUE; case 0x053: /* MFMSR */ @@ -3567,17 +3567,17 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_MOV(block, R32(G_RD(op)), SPR32(spr)); // mov rd,spr else if (spr == SPR_XER) { - UML_SHL(block, IREG(0), XERSO32, IMM(31)); // shl i0,[xerso],31 - UML_OR(block, R32(G_RD(op)), SPR32(spr), IREG(0)); // or [rd],[xer],i0 + UML_SHL(block, I0, XERSO32, 31); // shl i0,[xerso],31 + UML_OR(block, R32(G_RD(op)), SPR32(spr), I0); // or [rd],[xer],i0 } else if (spr == SPROEA_PVR) - UML_MOV(block, R32(G_RD(op)), IMM(ppc->flavor)); // mov rd,flavor + UML_MOV(block, R32(G_RD(op)), ppc->flavor); // mov rd,flavor else { - generate_update_cycles(ppc, block, compiler, IMM(desc->pc), TRUE); // <update cycles> - UML_MOV(block, MEM(&ppc->param0), IMM(spr)); // mov [param0],spr + generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr UML_CALLC(block, (c_function)ppccom_execute_mfspr, ppc); // callc ppccom_execute_mfspr,ppc - UML_MOV(block, R32(G_RD(op)), MEM(&ppc->param1)); // mov rd,[param1] + UML_MOV(block, R32(G_RD(op)), mem(&ppc->param1)); // mov rd,[param1] } return TRUE; } @@ -3587,8 +3587,8 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x293: /* MFSRIN */ - UML_SHR(block, IREG(0), R32(G_RB(op)), IMM(28)); // shr i0,G_RB,28 - UML_LOAD(block, R32(G_RD(op)), &ppc->sr[0], IREG(0), SIZE_DWORD, SCALE_x4); // load rd,sr,i0,dword + UML_SHR(block, I0, R32(G_RB(op)), 28); // shr i0,G_RB,28 + UML_LOAD(block, R32(G_RD(op)), &ppc->sr[0], I0, SIZE_DWORD, SCALE_x4); // load rd,sr,i0,dword return TRUE; case 0x173: /* MFTB */ @@ -3596,33 +3596,33 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UINT32 tbr = compute_spr(G_SPR(op)); if (tbr != SPRVEA_TBL_R && tbr != SPRVEA_TBU_R) return FALSE; - generate_update_cycles(ppc, block, compiler, IMM(desc->pc), TRUE); // <update cycles> - UML_MOV(block, MEM(&ppc->param0), IMM(tbr)); // mov [param0],tbr + generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->param0), tbr); // mov [param0],tbr UML_CALLC(block, (c_function)ppccom_execute_mftb, ppc); // callc ppccom_execute_mftb,ppc - UML_MOV(block, R32(G_RD(op)), MEM(&ppc->param1)); // mov rd,[param1] + UML_MOV(block, R32(G_RD(op)), mem(&ppc->param1)); // mov rd,[param1] return TRUE; } case 0x090: /* MTCRF */ - UML_MOV(block, IREG(0), R32(G_RS(op))); // mov i0,rs - if (G_CRM(op) & 0x80) UML_ROLAND(block, CR32(0), IREG(0), IMM(4), IMM(0xf)); // roland cr(0),i0,4,0x0f - if (G_CRM(op) & 0x40) UML_ROLAND(block, CR32(1), IREG(0), IMM(8), IMM(0xf)); // roland cr(1),i0,8,0x0f - if (G_CRM(op) & 0x20) UML_ROLAND(block, CR32(2), IREG(0), IMM(12), IMM(0xf)); // roland cr(2),i0,12,0x0f - if (G_CRM(op) & 0x10) UML_ROLAND(block, CR32(3), IREG(0), IMM(16), IMM(0xf)); // roland cr(3),i0,16,0x0f - if (G_CRM(op) & 0x08) UML_ROLAND(block, CR32(4), IREG(0), IMM(20), IMM(0xf)); // roland cr(4),i0,20,0x0f - if (G_CRM(op) & 0x04) UML_ROLAND(block, CR32(5), IREG(0), IMM(24), IMM(0xf)); // roland cr(5),i0,24,0x0f - if (G_CRM(op) & 0x02) UML_ROLAND(block, CR32(6), IREG(0), IMM(28), IMM(0xf)); // roland cr(6),i0,28,0x0f - if (G_CRM(op) & 0x01) UML_ROLAND(block, CR32(7), IREG(0), IMM(0), IMM(0xf)); // roland cr(7),i0,0,0x0f + UML_MOV(block, I0, R32(G_RS(op))); // mov i0,rs + if (G_CRM(op) & 0x80) UML_ROLAND(block, CR32(0), I0, 4, 0xf); // roland cr(0),i0,4,0x0f + if (G_CRM(op) & 0x40) UML_ROLAND(block, CR32(1), I0, 8, 0xf); // roland cr(1),i0,8,0x0f + if (G_CRM(op) & 0x20) UML_ROLAND(block, CR32(2), I0, 12, 0xf); // roland cr(2),i0,12,0x0f + if (G_CRM(op) & 0x10) UML_ROLAND(block, CR32(3), I0, 16, 0xf); // roland cr(3),i0,16,0x0f + if (G_CRM(op) & 0x08) UML_ROLAND(block, CR32(4), I0, 20, 0xf); // roland cr(4),i0,20,0x0f + if (G_CRM(op) & 0x04) UML_ROLAND(block, CR32(5), I0, 24, 0xf); // roland cr(5),i0,24,0x0f + if (G_CRM(op) & 0x02) UML_ROLAND(block, CR32(6), I0, 28, 0xf); // roland cr(6),i0,28,0x0f + if (G_CRM(op) & 0x01) UML_ROLAND(block, CR32(7), I0, 0, 0xf); // roland cr(7),i0,0,0x0f return TRUE; case 0x092: /* MTMSR */ if (ppc->cap & PPCCAP_603_MMU) - UML_XOR(block, IREG(0), MSR32, R32(G_RS(op))); // xor i0,msr32,rs + UML_XOR(block, I0, MSR32, R32(G_RS(op))); // xor i0,msr32,rs UML_MOV(block, MSR32, R32(G_RS(op))); // mov msr,rs if (ppc->cap & PPCCAP_603_MMU) { - UML_TEST(block, IREG(0), IMM(MSR603_TGPR)); // test i0,tgpr - UML_CALLHc(block, IF_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz + UML_TEST(block, I0, MSR603_TGPR); // test i0,tgpr + UML_CALLHc(block, COND_NZ, *ppc->impstate->swap_tgpr); // callh swap_tgpr,nz } generate_update_mode(ppc, block); // <update mode> return TRUE; @@ -3634,19 +3634,19 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_MOV(block, SPR32(spr), R32(G_RS(op))); // mov spr,rs else if (spr == SPR_XER) { - UML_AND(block, SPR32(spr), R32(G_RS(op)), IMM(~XER_SO)); // and spr,rs,~XER_SO - UML_SHR(block, XERSO32, R32(G_RS(op)), IMM(31)); // shr [xerso],rs,31 + UML_AND(block, SPR32(spr), R32(G_RS(op)), ~XER_SO); // and spr,rs,~XER_SO + UML_SHR(block, XERSO32, R32(G_RS(op)), 31); // shr [xerso],rs,31 } else if (spr == SPROEA_PVR) ; // read only else { - generate_update_cycles(ppc, block, compiler, IMM(desc->pc), TRUE); // <update cycles> - UML_MOV(block, MEM(&ppc->param0), IMM(spr)); // mov [param0],spr - UML_MOV(block, MEM(&ppc->param1), R32(G_RS(op))); // mov [param1],rs + generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr + UML_MOV(block, mem(&ppc->param1), R32(G_RS(op))); // mov [param1],rs UML_CALLC(block, (c_function)ppccom_execute_mtspr, ppc); // callc ppccom_execute_mtspr,ppc compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> } return TRUE; } @@ -3657,17 +3657,17 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x0f2: /* MTSRIN */ - UML_SHR(block, IREG(0), R32(G_RB(op)), IMM(28)); // shr i0,G_RB,28 - UML_STORE(block, &ppc->sr[0], IREG(0), R32(G_RS(op)), SIZE_DWORD, SCALE_x4); // store sr,i0,rs,dword + UML_SHR(block, I0, R32(G_RB(op)), 28); // shr i0,G_RB,28 + UML_STORE(block, &ppc->sr[0], I0, R32(G_RS(op)), SIZE_DWORD, SCALE_x4); // store sr,i0,rs,dword UML_CALLC(block, (c_function)ppccom_tlb_flush, ppc); // callc ppccom_tlb_flush,ppc return TRUE; case 0x200: /* MCRXR */ - UML_ROLAND(block, IREG(0), SPR32(SPR_XER), IMM(28), IMM(0x0f)); // roland i0,[xer],28,0x0f - UML_SHL(block, IREG(1), XERSO32, IMM(3)); // shl i1,[xerso],3 - UML_OR(block, CR32(G_CRFD(op)), IREG(0), IREG(1)); // or [crd],i0,i1 - UML_AND(block, SPR32(SPR_XER), SPR32(SPR_XER), IMM(~0xf0000000)); // and [xer],[xer],~0xf0000000 - UML_MOV(block, XERSO32, IMM(0)); // mov [xerso],0 + UML_ROLAND(block, I0, SPR32(SPR_XER), 28, 0x0f); // roland i0,[xer],28,0x0f + UML_SHL(block, I1, XERSO32, 3); // shl i1,[xerso],3 + UML_OR(block, CR32(G_CRFD(op)), I0, I1); // or [crd],i0,i1 + UML_AND(block, SPR32(SPR_XER), SPR32(SPR_XER), ~0xf0000000); // and [xer],[xer],~0xf0000000 + UML_MOV(block, XERSO32, 0); // mov [xerso],0 return TRUE; case 0x106: /* ICBT */ @@ -3680,17 +3680,17 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp case 0x1e6: /* DCREAD */ case 0x3e6: /* ICREAD */ assert(ppc->cap & PPCCAP_4XX); - UML_MOV(block, R32(G_RT(op)), IMM(0)); // mov rt,0 + UML_MOV(block, R32(G_RT(op)), 0); // mov rt,0 return TRUE; case 0x143: /* MFDCR */ { UINT32 spr = compute_spr(G_SPR(op)); assert(ppc->cap & PPCCAP_4XX); - generate_update_cycles(ppc, block, compiler, IMM(desc->pc), TRUE); // <update cycles> - UML_MOV(block, MEM(&ppc->param0), IMM(spr)); // mov [param0],spr + generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr UML_CALLC(block, (c_function)ppccom_execute_mfdcr, ppc); // callc ppccom_execute_mfdcr,ppc - UML_MOV(block, R32(G_RD(op)), MEM(&ppc->param1)); // mov rd,[param1] + UML_MOV(block, R32(G_RD(op)), mem(&ppc->param1)); // mov rd,[param1] return TRUE; } @@ -3698,32 +3698,32 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp { UINT32 spr = compute_spr(G_SPR(op)); assert(ppc->cap & PPCCAP_4XX); - generate_update_cycles(ppc, block, compiler, IMM(desc->pc), TRUE); // <update cycles> - UML_MOV(block, MEM(&ppc->param0), IMM(spr)); // mov [param0],spr - UML_MOV(block, MEM(&ppc->param1), R32(G_RS(op))); // mov [param1],rs + generate_update_cycles(ppc, block, compiler, desc->pc, TRUE); // <update cycles> + UML_MOV(block, mem(&ppc->param0), spr); // mov [param0],spr + UML_MOV(block, mem(&ppc->param1), R32(G_RS(op))); // mov [param1],rs UML_CALLC(block, (c_function)ppccom_execute_mtdcr, ppc); // callc ppccom_execute_mtdcr,ppc compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; } case 0x083: /* WRTEE */ assert(ppc->cap & PPCCAP_4XX); - UML_ROLINS(block, MSR32, R32(G_RS(op)), IMM(0), IMM(MSR_EE)); // rolins msr,rs,0,MSR_EE + UML_ROLINS(block, MSR32, R32(G_RS(op)), 0, MSR_EE); // rolins msr,rs,0,MSR_EE compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> return TRUE; case 0x0a3: /* WRTEEI */ assert(ppc->cap & PPCCAP_4XX); if (op & MSR_EE) { - UML_OR(block, MSR32, MSR32, IMM(MSR_EE)); // or msr,msr,MSR_EE + UML_OR(block, MSR32, MSR32, MSR_EE); // or msr,msr,MSR_EE compiler->checkints = TRUE; - generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + generate_update_cycles(ppc, block, compiler, desc->pc + 4, TRUE); // <update cycles> } else - UML_AND(block, MSR32, MSR32, IMM(~MSR_EE)); // and msr,msr,~MSR_EE + UML_AND(block, MSR32, MSR32, ~MSR_EE); // and msr,msr,~MSR_EE return TRUE; case 0x254: /* ESA */ @@ -3751,84 +3751,84 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp case 0x15: /* FADDSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDADD(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDADD(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x14: /* FSUBSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDSUB(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDSUB(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x19: /* FMULSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x12: /* FDIVSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDDIV(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDDIV(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fddiv f0,ra,rb + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x16: /* FSQRTSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDSQRT(block, FREG(0), F64(G_RB(op))); // fdsqrt f0,rb - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDSQRT(block, F0, F64(G_RB(op))); // fdsqrt f0,rb + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x18: /* FRESx */ - UML_FSFRFLT(block, FREG(0), F64(G_RB(op)), SIZE_QWORD); // fsfrlt f0,rb,qword - UML_FSRECIP(block, FREG(0), FREG(0)); // fsrecip f0,f0 - UML_FDFRFLT(block, F64(G_RD(op)), FREG(0), SIZE_DWORD); // fdfrflt rd,f0,dword + UML_FSFRFLT(block, F0, F64(G_RB(op)), SIZE_QWORD); // fsfrlt f0,rb,qword + UML_FSRECIP(block, F0, F0); // fsrecip f0,f0 + UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt rd,f0,dword generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1d: /* FMADDSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1c: /* FMSUBSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDSUB(block, FREG(0), FREG(0), F64(G_RB(op))); // fdsub f0,f0,rb - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDSUB(block, F0, F0, F64(G_RB(op))); // fdsub f0,f0,rb + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1f: /* FNMADDSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb - UML_FDNEG(block, FREG(0), FREG(0)); // fdneg f0,f0 - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb + UML_FDNEG(block, F0, F0); // fdneg f0,f0 + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1e: /* FNMSUBSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDSUB(block, FREG(0), F64(G_RB(op)), FREG(0)); // fdsub f0,rb,f0 - UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDSUB(block, F0, F64(G_RB(op)), F0); // fdsub f0,rb,f0 + UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; } @@ -3884,33 +3884,33 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x17: /* FSELx */ - UML_FDCMP(block, F64(G_RA(op)), MEM(&ppc->impstate->fp0)); // fdcmp f0,ra,[fp0] - UML_FDMOVc(block, IF_AE, F64(G_RD(op)), F64(G_REGC(op))); // fdmov rd,rc,AE - UML_FDMOVc(block, IF_B, F64(G_RD(op)), F64(G_RB(op))); // fdmov rd,rb,B + UML_FDCMP(block, F64(G_RA(op)), mem(&ppc->impstate->fp0)); // fdcmp f0,ra,[fp0] + UML_FDMOVc(block, COND_AE, F64(G_RD(op)), F64(G_REGC(op))); // fdmov rd,rc,AE + UML_FDMOVc(block, COND_B, F64(G_RD(op)), F64(G_RB(op))); // fdmov rd,rb,B return TRUE; case 0x1d: /* FMADDx */ - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDADD(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdadd rd,f0,rb + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDADD(block, F64(G_RD(op)), F0, F64(G_RB(op))); // fdadd rd,f0,rb generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1f: /* FNMADDx */ - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDADD(block, FREG(0), FREG(0), F64(G_RB(op))); // fdadd f0,f0,rb - UML_FDNEG(block, F64(G_RD(op)), FREG(0)); // fdneg rd,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb + UML_FDNEG(block, F64(G_RD(op)), F0); // fdneg rd,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1c: /* FMSUBx */ - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDSUB(block, F64(G_RD(op)), FREG(0), F64(G_RB(op))); // fdsub rd,f0,rb + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDSUB(block, F64(G_RD(op)), F0, F64(G_RB(op))); // fdsub rd,f0,rb generate_fp_flags(ppc, block, desc, TRUE); return TRUE; case 0x1e: /* FNMSUBx */ - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc - UML_FDSUB(block, F64(G_RD(op)), F64(G_RB(op)), FREG(0)); // fdsub rd,rb,f0 + UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc + UML_FDSUB(block, F64(G_RD(op)), F64(G_RB(op)), F0); // fdsub rd,rb,f0 generate_fp_flags(ppc, block, desc, TRUE); return TRUE; } @@ -3927,9 +3927,9 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp case 0x000: /* FCMPU */ case 0x020: /* FCMPO */ UML_FDCMP(block, F64(G_RA(op)), F64(G_RB(op))); // fdcmp ra,rb - UML_GETFLGS(block, IREG(0), FLAG_C | FLAG_Z | FLAG_U); // getflgs i0,czu - UML_LOAD(block, IREG(0), ppc->impstate->fcmp_cr_table, IREG(0), SIZE_BYTE, SCALE_x1);// load i0,fcmp_cr_table,i0,byte - UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + UML_GETFLGS(block, I0, FLAG_C | FLAG_Z | FLAG_U); // getflgs i0,czu + UML_LOAD(block, I0, ppc->impstate->fcmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,fcmp_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso] return TRUE; case 0x00c: /* FRSPx */ @@ -3938,15 +3938,15 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x00e: /* FCTIWx */ - UML_FDTOINT(block, IREG(0), F64(G_RB(op)), SIZE_DWORD, ROUND_DEFAULT); // fdtoint i0,rb,dword,default - UML_DAND(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0), IMM(0xffffffff));// dand i0,i0,0xffffffff - UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l)); // fdmovr rd,i0 + UML_FDTOINT(block, I0, F64(G_RB(op)), SIZE_DWORD, ROUND_DEFAULT); // fdtoint i0,rb,dword,default + UML_DAND(block, mem(&ppc->impstate->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff + UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l)); // fdmovr rd,i0 return TRUE; case 0x00f: /* FCTIWZx */ - UML_FDTOINT(block, IREG(0), F64(G_RB(op)), SIZE_DWORD, ROUND_TRUNC); // fdtoint i0,rb,dword,default - UML_DAND(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0), IMM(0xffffffff));// dand i0,i0,0xffffffff - UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l)); // fdmovr rd,i0 + UML_FDTOINT(block, I0, F64(G_RB(op)), SIZE_DWORD, ROUND_TRUNC); // fdtoint i0,rb,dword,default + UML_DAND(block, mem(&ppc->impstate->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff + UML_FDMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.w.l)); // fdmovr rd,i0 return TRUE; case 0x028: /* FNEGx */ @@ -3958,8 +3958,8 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x088: /* FNABSx */ - UML_FDABS(block, FREG(0), F64(G_RB(op))); // fdabs f0,rb - UML_FDNEG(block, F64(G_RD(op)), FREG(0)); // fdneg rd,f0 + UML_FDABS(block, F0, F64(G_RB(op))); // fdabs f0,rb + UML_FDNEG(block, F64(G_RD(op)), F0); // fdneg rd,f0 return TRUE; case 0x108: /* FABSx */ @@ -3967,32 +3967,32 @@ static int generate_instruction_3f(powerpc_state *ppc, drcuml_block *block, comp return TRUE; case 0x046: /* MTFSB0x */ - UML_AND(block, FPSCR32, FPSCR32, IMM(~(0x80000000 >> G_CRBD(op)))); // and fpscr32,fpscr32,~(0x80000000 >> G_CRBD) + UML_AND(block, FPSCR32, FPSCR32, ~(0x80000000 >> G_CRBD(op))); // and fpscr32,fpscr32,~(0x80000000 >> G_CRBD) return TRUE; case 0x026: /* MTFSB1x */ - UML_OR(block, FPSCR32, FPSCR32, IMM(0x80000000 >> G_CRBD(op))); // or fpscr32,fpscr32,(0x80000000 >> G_CRBD) + UML_OR(block, FPSCR32, FPSCR32, 0x80000000 >> G_CRBD(op)); // or fpscr32,fpscr32,(0x80000000 >> G_CRBD) return TRUE; case 0x040: /* MCRFS */ - UML_ROLAND(block, CR32(G_CRFD(op)), FPSCR32, IMM(((G_CRFS(op) - 7) & 7) * 4), IMM(0x0f)); + UML_ROLAND(block, CR32(G_CRFD(op)), FPSCR32, ((G_CRFS(op) - 7) & 7) * 4, 0x0f); // roland [crd],[fpscr],shift,0x0f - UML_AND(block, FPSCR32, FPSCR32, IMM(~CRMASK(G_CRFS(op)))); // and fpscr,fpscr,~crmask[crfs] + UML_AND(block, FPSCR32, FPSCR32, ~CRMASK(G_CRFS(op))); // and fpscr,fpscr,~crmask[crfs] return TRUE; case 0x247: /* MFFSx */ - UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), FPSCR32); // mov [tempdata],fpscr - UML_FSMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fsmov rd,fpscr + UML_MOV(block, mem(&ppc->impstate->tempdata.w.l), FPSCR32); // mov [tempdata],fpscr + UML_FSMOV(block, F64(G_RD(op)), mem(&ppc->impstate->tempdata.d)); // fsmov rd,fpscr return TRUE; case 0x2c7: /* MTFSFx */ - UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RB(op))); // fdmov [tempdata],fb - UML_ROLINS(block, FPSCR32, MEM(&ppc->impstate->tempdata.w.l), IMM(0), IMM(compute_crf_mask(G_FM(op)))); + UML_FDMOV(block, mem(&ppc->impstate->tempdata.d), F64(G_RB(op))); // fdmov [tempdata],fb + UML_ROLINS(block, FPSCR32, mem(&ppc->impstate->tempdata.w.l), 0, compute_crf_mask(G_FM(op))); // rolins fpscr,rb,0,crf_mask return TRUE; case 0x086: /* MTFSFIx */ - UML_ROLINS(block, FPSCR32, IMM(G_IMM(op)), IMM(28 - 4 * G_CRFD(op)), IMM(CRMASK(G_CRFD(op)))); + UML_ROLINS(block, FPSCR32, G_IMM(op), 28 - 4 * G_CRFD(op), CRMASK(G_CRFD(op))); // rolins fpscr,rb,0,crf_mask return TRUE; } diff --git a/src/emu/cpu/rsp/rspdrc.c b/src/emu/cpu/rsp/rspdrc.c index 0d0931441e1..52926d64a2c 100644 --- a/src/emu/cpu/rsp/rspdrc.c +++ b/src/emu/cpu/rsp/rspdrc.c @@ -52,8 +52,8 @@ extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op); ***************************************************************************/ /* map variables */ -#define MAPVAR_PC MVAR(0) -#define MAPVAR_CYCLES MVAR(1) +#define MAPVAR_PC M0 +#define MAPVAR_CYCLES M1 /* size of the execution code cache */ #define CACHE_SIZE (32 * 1024 * 1024) @@ -281,7 +281,7 @@ INLINE void load_fast_iregs(rsp_state *rsp, drcuml_block *block) for (regnum = 0; regnum < ARRAY_LENGTH(rsp->impstate->regmap); regnum++) if (rsp->impstate->regmap[regnum].is_int_register()) - UML_MOV(block, IREG(rsp->impstate->regmap[regnum].ireg() - REG_I0), MEM(&rsp->r[regnum])); + UML_MOV(block, ireg(rsp->impstate->regmap[regnum].ireg() - REG_I0), mem(&rsp->r[regnum])); } @@ -296,7 +296,7 @@ INLINE void save_fast_iregs(rsp_state *rsp, drcuml_block *block) for (regnum = 0; regnum < ARRAY_LENGTH(rsp->impstate->regmap); regnum++) if (rsp->impstate->regmap[regnum].is_int_register()) - UML_MOV(block, MEM(&rsp->r[regnum]), IREG(rsp->impstate->regmap[regnum].ireg() - REG_I0)); + UML_MOV(block, mem(&rsp->r[regnum]), ireg(rsp->impstate->regmap[regnum].ireg() - REG_I0)); } /*************************************************************************** @@ -667,23 +667,23 @@ static CPU_INIT( rsp ) rsp->impstate->drcuml->get_backend_info(beinfo); if (beinfo.direct_iregs > 2) { - rsp->impstate->regmap[30] = IREG(2); + rsp->impstate->regmap[30] = I2; } if (beinfo.direct_iregs > 3) { - rsp->impstate->regmap[31] = IREG(3); + rsp->impstate->regmap[31] = I3; } if (beinfo.direct_iregs > 4) { - rsp->impstate->regmap[2] = IREG(4); + rsp->impstate->regmap[2] = I4; } if (beinfo.direct_iregs > 5) { - rsp->impstate->regmap[3] = IREG(5); + rsp->impstate->regmap[3] = I5; } if (beinfo.direct_iregs > 6) { - rsp->impstate->regmap[4] = IREG(6); + rsp->impstate->regmap[4] = I6; } */ @@ -1110,52 +1110,52 @@ static int generate_lwc2(rsp_state *rsp, drcuml_block *block, compiler_state *co switch ((op >> 11) & 0x1f) { case 0x00: /* LBV */ - //UML_ADD(block, IREG(0), R32(RSREG), IMM(offset)); - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + //UML_ADD(block, I0, R32(RSREG), offset); + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lbv, rsp); return TRUE; case 0x01: /* LSV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lsv, rsp); return TRUE; case 0x02: /* LLV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_llv, rsp); return TRUE; case 0x03: /* LDV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_ldv, rsp); return TRUE; case 0x04: /* LQV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lqv, rsp); return TRUE; case 0x05: /* LRV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lrv, rsp); return TRUE; case 0x06: /* LPV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lpv, rsp); return TRUE; case 0x07: /* LUV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_luv, rsp); return TRUE; case 0x08: /* LHV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lhv, rsp); return TRUE; case 0x09: /* LFV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lfv, rsp); return TRUE; case 0x0a: /* LWV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_lwv, rsp); return TRUE; case 0x0b: /* LTV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_ltv, rsp); return TRUE; @@ -1597,51 +1597,51 @@ static int generate_swc2(rsp_state *rsp, drcuml_block *block, compiler_state *co switch ((op >> 11) & 0x1f) { case 0x00: /* SBV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_sbv, rsp); return TRUE; case 0x01: /* SSV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_ssv, rsp); return TRUE; case 0x02: /* SLV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_slv, rsp); return TRUE; case 0x03: /* SDV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_sdv, rsp); return TRUE; case 0x04: /* SQV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_sqv, rsp); return TRUE; case 0x05: /* SRV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_srv, rsp); return TRUE; case 0x06: /* SPV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_spv, rsp); return TRUE; case 0x07: /* SUV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_suv, rsp); return TRUE; case 0x08: /* SHV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_shv, rsp); return TRUE; case 0x09: /* SFV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_sfv, rsp); return TRUE; case 0x0a: /* SWV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_swv, rsp); return TRUE; case 0x0b: /* STV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_stv, rsp); return TRUE; @@ -3502,7 +3502,7 @@ static void code_compile_block(rsp_state *rsp, offs_t pc) else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc - UML_HASHJMP(block, IMM(0), IMM(seqhead->pc), *rsp->impstate->nocode); + UML_HASHJMP(block, 0, seqhead->pc, *rsp->impstate->nocode); // hashjmp <0>,seqhead->pc,nocode continue; } @@ -3528,11 +3528,11 @@ static void code_compile_block(rsp_state *rsp, offs_t pc) nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4; /* count off cycles and go there */ - generate_update_cycles(rsp, block, &compiler, IMM(nextpc), TRUE); // <subtract cycles> + generate_update_cycles(rsp, block, &compiler, nextpc, TRUE); // <subtract cycles> /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */ if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) - UML_HASHJMP(block, IMM(0), IMM(nextpc), *rsp->impstate->nocode); // hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, 0, nextpc, *rsp->impstate->nocode); // hashjmp <mode>,nextpc,nocode } /* end the sequence */ @@ -3603,7 +3603,7 @@ static void static_generate_entry_point(rsp_state *rsp) load_fast_iregs(rsp, block); /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, IMM(0), MEM(&rsp->pc), *rsp->impstate->nocode); + UML_HASHJMP(block, 0, mem(&rsp->pc), *rsp->impstate->nocode); // hashjmp <mode>,<pc>,nocode block->end(); } @@ -3625,10 +3625,10 @@ static void static_generate_nocode_handler(rsp_state *rsp) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &rsp->impstate->nocode, "nocode"); UML_HANDLE(block, *rsp->impstate->nocode); // handle nocode - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&rsp->pc), IREG(0)); // mov [pc],i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&rsp->pc), I0); // mov [pc],i0 save_fast_iregs(rsp, block); - UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); } @@ -3650,10 +3650,10 @@ static void static_generate_out_of_cycles(rsp_state *rsp) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &rsp->impstate->out_of_cycles, "out_of_cycles"); UML_HANDLE(block, *rsp->impstate->out_of_cycles); // handle out_of_cycles - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&rsp->pc), IREG(0)); // mov <pc>,i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&rsp->pc), I0); // mov <pc>,i0 save_fast_iregs(rsp, block); - UML_EXIT(block, IMM(EXECUTE_OUT_OF_CYCLES)); // exit EXECUTE_OUT_OF_CYCLES + UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); } @@ -3682,20 +3682,20 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit { if (size == 1) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IREG(0)); // mov [arg0],i0 ; address - UML_MOV(block, MEM(&rsp->impstate->arg1), IREG(1)); // mov [arg1],i1 ; data + UML_MOV(block, mem(&rsp->impstate->arg0), I0); // mov [arg0],i0 ; address + UML_MOV(block, mem(&rsp->impstate->arg1), I1); // mov [arg1],i1 ; data UML_CALLC(block, cfunc_write8, rsp); // callc cfunc_write8 } else if (size == 2) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IREG(0)); // mov [arg0],i0 ; address - UML_MOV(block, MEM(&rsp->impstate->arg1), IREG(1)); // mov [arg1],i1 ; data + UML_MOV(block, mem(&rsp->impstate->arg0), I0); // mov [arg0],i0 ; address + UML_MOV(block, mem(&rsp->impstate->arg1), I1); // mov [arg1],i1 ; data UML_CALLC(block, cfunc_write16, rsp); // callc cfunc_write16 } else if (size == 4) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IREG(0)); // mov [arg0],i0 ; address - UML_MOV(block, MEM(&rsp->impstate->arg1), IREG(1)); // mov [arg1],i1 ; data + UML_MOV(block, mem(&rsp->impstate->arg0), I0); // mov [arg0],i0 ; address + UML_MOV(block, mem(&rsp->impstate->arg1), I1); // mov [arg1],i1 ; data UML_CALLC(block, cfunc_write32, rsp); // callc cfunc_write32 } } @@ -3703,21 +3703,21 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit { if (size == 1) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IREG(0)); // mov [arg0],i0 ; address + UML_MOV(block, mem(&rsp->impstate->arg0), I0); // mov [arg0],i0 ; address UML_CALLC(block, cfunc_read8, rsp); // callc cfunc_printf_debug - UML_MOV(block, IREG(0), MEM(&rsp->impstate->arg0)); // mov i0,[arg0],i0 ; result + UML_MOV(block, I0, mem(&rsp->impstate->arg0)); // mov i0,[arg0],i0 ; result } else if (size == 2) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IREG(0)); // mov [arg0],i0 ; address + UML_MOV(block, mem(&rsp->impstate->arg0), I0); // mov [arg0],i0 ; address UML_CALLC(block, cfunc_read16, rsp); // callc cfunc_read16 - UML_MOV(block, IREG(0), MEM(&rsp->impstate->arg0)); // mov i0,[arg0],i0 ; result + UML_MOV(block, I0, mem(&rsp->impstate->arg0)); // mov i0,[arg0],i0 ; result } else if (size == 4) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IREG(0)); // mov [arg0],i0 ; address + UML_MOV(block, mem(&rsp->impstate->arg0), I0); // mov [arg0],i0 ; address UML_CALLC(block, cfunc_read32, rsp); // callc cfunc_read32 - UML_MOV(block, IREG(0), MEM(&rsp->impstate->arg0)); // mov i0,[arg0],i0 ; result + UML_MOV(block, I0, mem(&rsp->impstate->arg0)); // mov i0,[arg0],i0 ; result } } UML_RET(block); @@ -3741,9 +3741,9 @@ static void generate_update_cycles(rsp_state *rsp, drcuml_block *block, compiler /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, MEM(&rsp->icount), MEM(&rsp->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_SUB(block, mem(&rsp->icount), mem(&rsp->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 - UML_EXHc(block, IF_S, *rsp->impstate->out_of_cycles, param); + UML_EXHc(block, COND_S, *rsp->impstate->out_of_cycles, param); } compiler->cycles = 0; } @@ -3766,9 +3766,9 @@ static void generate_checksum_block(rsp_state *rsp, drcuml_block *block, compile if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP)) { void *base = rsp->direct->read_decrypted_ptr(seqhead->physpc | 0x1000); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,0,dword - UML_CMP(block, IREG(0), IMM(seqhead->opptr.l[0])); // cmp i0,opptr[0] - UML_EXHc(block, IF_NE, *rsp->impstate->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_CMP(block, I0, seqhead->opptr.l[0]); // cmp i0,opptr[0] + UML_EXHc(block, COND_NE, *rsp->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -3777,18 +3777,18 @@ static void generate_checksum_block(rsp_state *rsp, drcuml_block *block, compile { UINT32 sum = 0; void *base = rsp->direct->read_decrypted_ptr(seqhead->physpc | 0x1000); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword sum += seqhead->opptr.l[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { base = rsp->direct->read_decrypted_ptr(curdesc->physpc | 0x1000); - UML_LOAD(block, IREG(1), base, IMM(0), SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, IREG(0), IREG(0), IREG(1)); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.l[0]; } - UML_CMP(block, IREG(0), IMM(sum)); // cmp i0,sum - UML_EXHc(block, IF_NE, *rsp->impstate->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_CMP(block, I0, sum); // cmp i0,sum + UML_EXHc(block, COND_NE, *rsp->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -3819,18 +3819,18 @@ static void generate_sequence_instruction(rsp_state *rsp, drcuml_block *block, c /* if we are debugging, call the debugger */ if ((rsp->device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&rsp->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(rsp, block); - UML_DEBUG(block, IMM(desc->pc)); // debug desc->pc + UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ #if 0 if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&rsp->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(rsp, block); - UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE + UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } #endif @@ -3840,8 +3840,8 @@ static void generate_sequence_instruction(rsp_state *rsp, drcuml_block *block, c /* compile the instruction */ if (!generate_opcode(rsp, block, compiler, desc)) { - UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_unimplemented, rsp); // callc cfunc_unimplemented } } @@ -3859,14 +3859,14 @@ static void generate_delay_slot_and_branch(rsp_state *rsp, drcuml_block *block, /* fetch the target register if dynamic, in case it is modified by the delay slot */ if (desc->targetpc == BRANCH_TARGET_DYNAMIC) { - UML_AND(block, MEM(&rsp->impstate->jmpdest), R32(RSREG), IMM(0x00000fff)); - UML_OR(block, MEM(&rsp->impstate->jmpdest), MEM(&rsp->impstate->jmpdest), IMM(0x1000)); + UML_AND(block, mem(&rsp->impstate->jmpdest), R32(RSREG), 0x00000fff); + UML_OR(block, mem(&rsp->impstate->jmpdest), mem(&rsp->impstate->jmpdest), 0x1000); } /* set the link if needed -- before the delay slot */ if (linkreg != 0) { - UML_MOV(block, R32(linkreg), IMM((INT32)(desc->pc + 8))); // mov <linkreg>,desc->pc + 8 + UML_MOV(block, R32(linkreg), (INT32)(desc->pc + 8)); // mov <linkreg>,desc->pc + 8 } /* compile the delay slot using temporary compiler state */ @@ -3876,22 +3876,22 @@ static void generate_delay_slot_and_branch(rsp_state *rsp, drcuml_block *block, /* update the cycles and jump through the hash table to the target */ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { - generate_update_cycles(rsp, block, &compiler_temp, IMM(desc->targetpc), TRUE); // <subtract cycles> + generate_update_cycles(rsp, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) { UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc } else { - UML_HASHJMP(block, IMM(0), IMM(desc->targetpc), *rsp->impstate->nocode); + UML_HASHJMP(block, 0, desc->targetpc, *rsp->impstate->nocode); // hashjmp <mode>,desc->targetpc,nocode } } else { - generate_update_cycles(rsp, block, &compiler_temp, MEM(&rsp->impstate->jmpdest), TRUE); + generate_update_cycles(rsp, block, &compiler_temp, mem(&rsp->impstate->jmpdest), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&rsp->impstate->jmpdest), *rsp->impstate->nocode); + UML_HASHJMP(block, 0, mem(&rsp->impstate->jmpdest), *rsp->impstate->nocode); // hashjmp <mode>,<rsreg>,nocode } @@ -3921,197 +3921,197 @@ static int generate_vector_opcode(rsp_state *rsp, drcuml_block *block, compiler_ switch (op & 0x3f) { case 0x00: /* VMULF */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmulf, rsp); return TRUE; case 0x01: /* VMULU */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmulu, rsp); return TRUE; case 0x04: /* VMUDL */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmudl, rsp); return TRUE; case 0x05: /* VMUDM */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmudm, rsp); return TRUE; case 0x06: /* VMUDN */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmudn, rsp); return TRUE; case 0x07: /* VMUDH */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmudh, rsp); return TRUE; case 0x08: /* VMACF */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmacf, rsp); return TRUE; case 0x09: /* VMACU */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmacu, rsp); return TRUE; case 0x0c: /* VMADL */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmadl, rsp); return TRUE; case 0x0d: /* VMADM */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmadm, rsp); return TRUE; case 0x0e: /* VMADN */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmadn, rsp); return TRUE; case 0x0f: /* VMADH */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmadh, rsp); return TRUE; case 0x10: /* VADD */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vadd, rsp); return TRUE; case 0x11: /* VSUB */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vsub, rsp); return TRUE; case 0x13: /* VABS */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vabs, rsp); return TRUE; case 0x14: /* VADDC */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vaddc, rsp); return TRUE; case 0x15: /* VSUBC */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vsubc, rsp); return TRUE; case 0x1d: /* VSAW */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vsaw, rsp); return TRUE; case 0x20: /* VLT */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vlt, rsp); return TRUE; case 0x21: /* VEQ */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_veq, rsp); return TRUE; case 0x22: /* VNE */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vne, rsp); return TRUE; case 0x23: /* VGE */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vge, rsp); return TRUE; case 0x24: /* VCL */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vcl, rsp); return TRUE; case 0x25: /* VCH */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vch, rsp); return TRUE; case 0x26: /* VCR */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vcr, rsp); return TRUE; case 0x27: /* VMRG */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmrg, rsp); return TRUE; case 0x28: /* VAND */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vand, rsp); return TRUE; case 0x29: /* VNAND */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vnand, rsp); return TRUE; case 0x2a: /* VOR */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vor, rsp); return TRUE; case 0x2b: /* VNOR */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vnor, rsp); return TRUE; case 0x2c: /* VXOR */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vxor, rsp); return TRUE; case 0x2d: /* VNXOR */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vnxor, rsp); return TRUE; case 0x30: /* VRCP */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vrcp, rsp); return TRUE; case 0x31: /* VRCPL */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vrcpl, rsp); return TRUE; case 0x32: /* VRCPH */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vrcph, rsp); return TRUE; case 0x33: /* VMOV */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vmov, rsp); return TRUE; case 0x35: /* VRSQL */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vrsql, rsp); return TRUE; case 0x36: /* VRSQH */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_rsp_vrsqh, rsp); return TRUE; default: - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_unimplemented_opcode, rsp); return FALSE; } @@ -4146,14 +4146,14 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x04: /* BEQ - MIPS I */ UML_CMP(block, R32(RSREG), R32(RTREG)); // cmp <rsreg>,<rtreg> - UML_JMPc(block, IF_NE, skip = compiler->labelnum++); // jmp skip,NE + UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE generate_delay_slot_and_branch(rsp, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; case 0x05: /* BNE - MIPS I */ UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg> - UML_JMPc(block, IF_E, skip = compiler->labelnum++); // jmp skip,E + UML_JMPc(block, COND_E, skip = compiler->labelnum++); // jmp skip,E generate_delay_slot_and_branch(rsp, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -4161,8 +4161,8 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x06: /* BLEZ - MIPS I */ if (RSREG != 0) { - UML_CMP(block, R32(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_G, skip = compiler->labelnum++); // jmp skip,G + UML_CMP(block, R32(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_G, skip = compiler->labelnum++); // jmp skip,G generate_delay_slot_and_branch(rsp, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: } @@ -4171,8 +4171,8 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * return TRUE; case 0x07: /* BGTZ - MIPS I */ - UML_CMP(block, R32(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_LE, skip = compiler->labelnum++); // jmp skip,LE + UML_CMP(block, R32(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_LE, skip = compiler->labelnum++); // jmp skip,LE generate_delay_slot_and_branch(rsp, block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -4182,94 +4182,94 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x0f: /* LUI - MIPS I */ if (RTREG != 0) - UML_MOV(block, R32(RTREG), IMM(SIMMVAL << 16)); // dmov <rtreg>,SIMMVAL << 16 + UML_MOV(block, R32(RTREG), SIMMVAL << 16); // dmov <rtreg>,SIMMVAL << 16 return TRUE; case 0x08: /* ADDI - MIPS I */ case 0x09: /* ADDIU - MIPS I */ if (RTREG != 0) { - UML_ADD(block, R32(RTREG), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL,V + UML_ADD(block, R32(RTREG), R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL,V } return TRUE; case 0x0a: /* SLTI - MIPS I */ if (RTREG != 0) { - UML_CMP(block, R32(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_SETc(block, IF_L, R32(RTREG)); // dset <rtreg>,l + UML_CMP(block, R32(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_SETc(block, COND_L, R32(RTREG)); // dset <rtreg>,l } return TRUE; case 0x0b: /* SLTIU - MIPS I */ if (RTREG != 0) { - UML_CMP(block, R32(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL - UML_SETc(block, IF_B, R32(RTREG)); // dset <rtreg>,b + UML_CMP(block, R32(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL + UML_SETc(block, COND_B, R32(RTREG)); // dset <rtreg>,b } return TRUE; case 0x0c: /* ANDI - MIPS I */ if (RTREG != 0) - UML_AND(block, R32(RTREG), R32(RSREG), IMM(UIMMVAL)); // dand <rtreg>,<rsreg>,UIMMVAL + UML_AND(block, R32(RTREG), R32(RSREG), UIMMVAL); // dand <rtreg>,<rsreg>,UIMMVAL return TRUE; case 0x0d: /* ORI - MIPS I */ if (RTREG != 0) - UML_OR(block, R32(RTREG), R32(RSREG), IMM(UIMMVAL)); // dor <rtreg>,<rsreg>,UIMMVAL + UML_OR(block, R32(RTREG), R32(RSREG), UIMMVAL); // dor <rtreg>,<rsreg>,UIMMVAL return TRUE; case 0x0e: /* XORI - MIPS I */ if (RTREG != 0) - UML_XOR(block, R32(RTREG), R32(RSREG), IMM(UIMMVAL)); // dxor <rtreg>,<rsreg>,UIMMVAL + UML_XOR(block, R32(RTREG), R32(RSREG), UIMMVAL); // dxor <rtreg>,<rsreg>,UIMMVAL return TRUE; /* ----- memory load operations ----- */ case 0x20: /* LB - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *rsp->impstate->read8); // callh read8 if (RTREG != 0) - UML_SEXT(block, R32(RTREG), IREG(0), SIZE_BYTE); // dsext <rtreg>,i0,byte + UML_SEXT(block, R32(RTREG), I0, SIZE_BYTE); // dsext <rtreg>,i0,byte if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x21: /* LH - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *rsp->impstate->read16); // callh read16 if (RTREG != 0) - UML_SEXT(block, R32(RTREG), IREG(0), SIZE_WORD); // dsext <rtreg>,i0,word + UML_SEXT(block, R32(RTREG), I0, SIZE_WORD); // dsext <rtreg>,i0,word if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x23: /* LW - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *rsp->impstate->read32); // callh read32 if (RTREG != 0) - UML_MOV(block, R32(RTREG), IREG(0)); + UML_MOV(block, R32(RTREG), I0); if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x24: /* LBU - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *rsp->impstate->read8); // callh read8 if (RTREG != 0) - UML_AND(block, R32(RTREG), IREG(0), IMM(0xff)); // dand <rtreg>,i0,0xff + UML_AND(block, R32(RTREG), I0, 0xff); // dand <rtreg>,i0,0xff if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x25: /* LHU - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *rsp->impstate->read16); // callh read16 if (RTREG != 0) - UML_AND(block, R32(RTREG), IREG(0), IMM(0xffff)); // dand <rtreg>,i0,0xffff + UML_AND(block, R32(RTREG), I0, 0xffff); // dand <rtreg>,i0,0xffff if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x32: /* LWC2 - MIPS I */ @@ -4279,32 +4279,32 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * /* ----- memory store operations ----- */ case 0x28: /* SB - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *rsp->impstate->write8); // callh write8 if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x29: /* SH - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *rsp->impstate->write16); // callh write16 if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2b: /* SW - MIPS I */ - UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL - UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg> + UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL + UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> UML_CALLH(block, *rsp->impstate->write32); // callh write32 if (!in_delay_slot) - generate_update_cycles(rsp, block, compiler, IMM(desc->pc + 4), TRUE); + generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3a: /* SWC2 - MIPS I */ return generate_swc2(rsp, block, compiler, desc); - //UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + //UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l //UML_CALLC(block, cfunc_swc2, rsp); // callc cfunc_mfc2 //return TRUE; @@ -4315,7 +4315,7 @@ static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x12: /* COP2 - MIPS I */ return generate_cop2(rsp, block, compiler, desc); - //UML_EXH(block, rsp->impstate->exception[EXCEPTION_INVALIDOP], IMM(0));// exh invalidop,0 + //UML_EXH(block, rsp->impstate->exception[EXCEPTION_INVALIDOP], 0);// exh invalidop,0 //return TRUE; @@ -4346,21 +4346,21 @@ static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state case 0x00: /* SLL - MIPS I */ if (RDREG != 0) { - UML_SHL(block, R32(RDREG), R32(RTREG), IMM(SHIFT)); + UML_SHL(block, R32(RDREG), R32(RTREG), SHIFT); } return TRUE; case 0x02: /* SRL - MIPS I */ if (RDREG != 0) { - UML_SHR(block, R32(RDREG), R32(RTREG), IMM(SHIFT)); + UML_SHR(block, R32(RDREG), R32(RTREG), SHIFT); } return TRUE; case 0x03: /* SRA - MIPS I */ if (RDREG != 0) { - UML_SAR(block, R32(RDREG), R32(RTREG), IMM(SHIFT)); + UML_SAR(block, R32(RDREG), R32(RTREG), SHIFT); } return TRUE; @@ -4429,8 +4429,8 @@ static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state case 0x27: /* NOR - MIPS I */ if (RDREG != 0) { - UML_OR(block, IREG(0), R32(RSREG), R32(RTREG)); // dor i0,<rsreg>,<rtreg> - UML_XOR(block, R32(RDREG), IREG(0), IMM((UINT64)~0)); // dxor <rdreg>,i0,~0 + UML_OR(block, I0, R32(RSREG), R32(RTREG)); // dor i0,<rsreg>,<rtreg> + UML_XOR(block, R32(RDREG), I0, (UINT64)~0); // dxor <rdreg>,i0,~0 } return TRUE; @@ -4441,7 +4441,7 @@ static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state if (RDREG != 0) { UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg> - UML_SETc(block, IF_L, R32(RDREG)); // dset <rdreg>,l + UML_SETc(block, COND_L, R32(RDREG)); // dset <rdreg>,l } return TRUE; @@ -4449,7 +4449,7 @@ static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state if (RDREG != 0) { UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg> - UML_SETc(block, IF_B, R32(RDREG)); // dset <rdreg>,b + UML_SETc(block, COND_B, R32(RDREG)); // dset <rdreg>,b } return TRUE; @@ -4468,11 +4468,11 @@ static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state /* ----- system calls ----- */ case 0x0d: /* BREAK - MIPS I */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(3)); // mov [arg0],3 + UML_MOV(block, mem(&rsp->impstate->arg0), 3); // mov [arg0],3 UML_CALLC(block, cfunc_sp_set_status_cb, rsp); // callc cfunc_sp_set_status_cb - UML_MOV(block, MEM(&rsp->icount), IMM(0)); // mov icount, #0 + UML_MOV(block, mem(&rsp->icount), 0); // mov icount, #0 - UML_EXIT(block, IMM(EXECUTE_OUT_OF_CYCLES)); + UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); return TRUE; } return FALSE; @@ -4497,8 +4497,8 @@ static int generate_regimm(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x10: /* BLTZAL */ if (RSREG != 0) { - UML_CMP(block, R32(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_GE, skip = compiler->labelnum++); // jmp skip,GE + UML_CMP(block, R32(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_GE, skip = compiler->labelnum++); // jmp skip,GE generate_delay_slot_and_branch(rsp, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: @@ -4509,8 +4509,8 @@ static int generate_regimm(rsp_state *rsp, drcuml_block *block, compiler_state * case 0x11: /* BGEZAL */ if (RSREG != 0) { - UML_CMP(block, R32(RSREG), IMM(0)); // dcmp <rsreg>,0 - UML_JMPc(block, IF_L, skip = compiler->labelnum++); // jmp skip,L + UML_CMP(block, R32(RSREG), 0); // dcmp <rsreg>,0 + UML_JMPc(block, COND_L, skip = compiler->labelnum++); // jmp skip,L generate_delay_slot_and_branch(rsp, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: @@ -4538,28 +4538,28 @@ static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *co case 0x00: /* MFCz */ if (RTREG != 0) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_mfc2, rsp); // callc cfunc_mfc2 - //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword + //UML_SEXT(block, R32(RTREG), I0, DWORD); // dsext <rtreg>,i0,dword } return TRUE; case 0x02: /* CFCz */ if (RTREG != 0) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_cfc2, rsp); // callc cfunc_cfc2 - //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword + //UML_SEXT(block, R32(RTREG), I0, DWORD); // dsext <rtreg>,i0,dword } return TRUE; case 0x04: /* MTCz */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_mtc2, rsp); // callc cfunc_mtc2 return TRUE; case 0x06: /* CTCz */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_ctc2, rsp); // callc cfunc_ctc2 return TRUE; @@ -4584,15 +4584,15 @@ static int generate_cop0(rsp_state *rsp, drcuml_block *block, compiler_state *co case 0x00: /* MFCz */ if (RTREG != 0) { - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(RDREG)); // mov [arg0],<rdreg> - UML_MOV(block, MEM(&rsp->impstate->arg1), IMM(RTREG)); // mov [arg1],<rtreg> + UML_MOV(block, mem(&rsp->impstate->arg0), RDREG); // mov [arg0],<rdreg> + UML_MOV(block, mem(&rsp->impstate->arg1), RTREG); // mov [arg1],<rtreg> UML_CALLC(block, cfunc_get_cop0_reg, rsp); // callc cfunc_get_cop0_reg } return TRUE; case 0x04: /* MTCz */ - UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(RDREG)); // mov [arg0],<rdreg> - UML_MOV(block, MEM(&rsp->impstate->arg1), R32(RTREG)); // mov [arg1],rtreg + UML_MOV(block, mem(&rsp->impstate->arg0), RDREG); // mov [arg0],<rdreg> + UML_MOV(block, mem(&rsp->impstate->arg1), R32(RTREG)); // mov [arg1],rtreg UML_CALLC(block, cfunc_set_cop0_reg, rsp); // callc cfunc_set_cop0_reg return TRUE; } diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c index 2c057ca83be..10dc9313154 100644 --- a/src/emu/cpu/sh2/sh2drc.c +++ b/src/emu/cpu/sh2/sh2drc.c @@ -47,7 +47,7 @@ using namespace uml; #define LOG(x) do { if (VERBOSE) logerror x; } while (0) #if SET_EA -#define SETEA(x) UML_MOV(block, MEM(&sh2->ea), IREG(x)) +#define SETEA(x) UML_MOV(block, mem(&sh2->ea), ireg(x)) #else #define SETEA(x) #endif @@ -57,8 +57,8 @@ using namespace uml; ***************************************************************************/ /* map variables */ -#define MAPVAR_PC MVAR(0) -#define MAPVAR_CYCLES MVAR(1) +#define MAPVAR_PC M0 +#define MAPVAR_CYCLES M1 /* size of the execution code cache */ #define CACHE_SIZE (32 * 1024 * 1024) @@ -204,7 +204,7 @@ INLINE void load_fast_iregs(sh2_state *sh2, drcuml_block *block) { if (sh2->regmap[regnum].is_int_register()) { - UML_MOV(block, parameter::make_ireg(sh2->regmap[regnum].ireg()), MEM(&sh2->r[regnum])); + UML_MOV(block, parameter::make_ireg(sh2->regmap[regnum].ireg()), mem(&sh2->r[regnum])); } } } @@ -223,7 +223,7 @@ INLINE void save_fast_iregs(sh2_state *sh2, drcuml_block *block) { if (sh2->regmap[regnum].is_int_register()) { - UML_MOV(block, MEM(&sh2->r[regnum]), parameter::make_ireg(sh2->regmap[regnum].ireg())); + UML_MOV(block, mem(&sh2->r[regnum]), parameter::make_ireg(sh2->regmap[regnum].ireg())); } } } @@ -729,7 +729,7 @@ static CPU_INIT( sh2 ) /* compute the register parameters */ for (regnum = 0; regnum < 16; regnum++) { - sh2->regmap[regnum] = MEM(&sh2->r[regnum]); + sh2->regmap[regnum] = mem(&sh2->r[regnum]); } /* if we have registers to spare, assign r0, r1, r2 to leftovers */ @@ -739,15 +739,15 @@ static CPU_INIT( sh2 ) sh2->drcuml->get_backend_info(beinfo); if (beinfo.direct_iregs > 4) { - sh2->regmap[0] = IREG(4); + sh2->regmap[0] = I4; } if (beinfo.direct_iregs > 5) { - sh2->regmap[1] = IREG(5); + sh2->regmap[1] = I5; } if (beinfo.direct_iregs > 6) { - sh2->regmap[2] = IREG(6); + sh2->regmap[2] = I6; } } @@ -976,7 +976,7 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc) else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc | 0x80000000 - UML_HASHJMP(block, IMM(0), IMM(seqhead->pc), *sh2->nocode); + UML_HASHJMP(block, 0, seqhead->pc, *sh2->nocode); // hashjmp <mode>,seqhead->pc,nocode continue; } @@ -1009,12 +1009,12 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc) } /* count off cycles and go there */ - generate_update_cycles(sh2, block, &compiler, IMM(nextpc), TRUE); // <subtract cycles> + generate_update_cycles(sh2, block, &compiler, nextpc, TRUE); // <subtract cycles> /* SH2 has no modes */ if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) { - UML_HASHJMP(block, IMM(0), IMM(nextpc), *sh2->nocode); + UML_HASHJMP(block, 0, nextpc, *sh2->nocode); } // hashjmp <mode>,nextpc,nocode } @@ -1055,58 +1055,58 @@ static void static_generate_entry_point(sh2_state *sh2) load_fast_iregs(sh2, block); /* check for interrupts */ - UML_MOV(block, MEM(&sh2->irqline), IMM(0xffffffff)); // mov irqline, #-1 - UML_CMP(block, MEM(&sh2->pending_nmi), IMM(0)); // cmp pending_nmi, #0 - UML_JMPc(block, IF_Z, skip+2); // jz skip+2 + UML_MOV(block, mem(&sh2->irqline), 0xffffffff); // mov irqline, #-1 + UML_CMP(block, mem(&sh2->pending_nmi), 0); // cmp pending_nmi, #0 + UML_JMPc(block, COND_Z, skip+2); // jz skip+2 - UML_MOV(block, MEM(&sh2->pending_nmi), IMM(0)); // zap pending_nmi + UML_MOV(block, mem(&sh2->pending_nmi), 0); // zap pending_nmi UML_JMP(block, skip+1); // and then go take it (evec is already set) UML_LABEL(block, skip+2); // skip+2: - UML_MOV(block, MEM(&sh2->evec), IMM(0xffffffff)); // mov evec, -1 - UML_MOV(block, IREG(0), IMM(0xffffffff)); // mov r0, -1 (r0 = irq) - UML_AND(block, IREG(1), IREG(0), IMM(0xffff)); // and r1, 0xffff + UML_MOV(block, mem(&sh2->evec), 0xffffffff); // mov evec, -1 + UML_MOV(block, I0, 0xffffffff); // mov r0, -1 (r0 = irq) + UML_AND(block, I1, I0, 0xffff); // and r1, 0xffff - UML_LZCNT(block, IREG(1), MEM(&sh2->pending_irq)); // lzcnt r1, r1 - UML_CMP(block, IREG(1), IMM(32)); // cmp r1, #32 - UML_JMPc(block, IF_Z, skip+4); // jz skip+4 + UML_LZCNT(block, I1, mem(&sh2->pending_irq)); // lzcnt r1, r1 + UML_CMP(block, I1, 32); // cmp r1, #32 + UML_JMPc(block, COND_Z, skip+4); // jz skip+4 - UML_SUB(block, MEM(&sh2->irqline), IMM(31), IREG(1)); // sub irqline, #31, r1 + UML_SUB(block, mem(&sh2->irqline), 31, I1); // sub irqline, #31, r1 UML_LABEL(block, skip+4); // skip+4: - UML_CMP(block, MEM(&sh2->internal_irq_level), IMM(0xffffffff)); // cmp internal_irq_level, #-1 - UML_JMPc(block, IF_Z, skip+3); // jz skip+3 - UML_CMP(block, MEM(&sh2->internal_irq_level), MEM(&sh2->irqline)); // cmp internal_irq_level, irqline - UML_JMPc(block, IF_LE, skip+3); // jle skip+3 + UML_CMP(block, mem(&sh2->internal_irq_level), 0xffffffff); // cmp internal_irq_level, #-1 + UML_JMPc(block, COND_Z, skip+3); // jz skip+3 + UML_CMP(block, mem(&sh2->internal_irq_level), mem(&sh2->irqline)); // cmp internal_irq_level, irqline + UML_JMPc(block, COND_LE, skip+3); // jle skip+3 - UML_MOV(block, MEM(&sh2->irqline), MEM(&sh2->internal_irq_level)); // mov r0, internal_irq_level + UML_MOV(block, mem(&sh2->irqline), mem(&sh2->internal_irq_level)); // mov r0, internal_irq_level UML_LABEL(block, skip+3); // skip+3: - UML_CMP(block, MEM(&sh2->irqline), IMM(0xffffffff)); // cmp irqline, #-1 - UML_JMPc(block, IF_Z, skip+1); // jz skip+1 + UML_CMP(block, mem(&sh2->irqline), 0xffffffff); // cmp irqline, #-1 + UML_JMPc(block, COND_Z, skip+1); // jz skip+1 UML_CALLC(block, cfunc_fastirq, sh2); // callc fastirq UML_LABEL(block, skip+1); // skip+1: - UML_CMP(block, MEM(&sh2->evec), IMM(0xffffffff)); // cmp evec, 0xffffffff - UML_JMPc(block, IF_Z, skip); // jz skip + UML_CMP(block, mem(&sh2->evec), 0xffffffff); // cmp evec, 0xffffffff + UML_JMPc(block, COND_Z, skip); // jz skip - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), MEM(&sh2->irqsr)); // mov r1, irqsr + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, mem(&sh2->irqsr)); // mov r1, irqsr UML_CALLH(block, *sh2->write32); // call write32 - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), MEM(&sh2->pc)); // mov r1, pc + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, mem(&sh2->pc)); // mov r1, pc UML_CALLH(block, *sh2->write32); // call write32 - UML_MOV(block, MEM(&sh2->pc), MEM(&sh2->evec)); // mov pc, evec + UML_MOV(block, mem(&sh2->pc), mem(&sh2->evec)); // mov pc, evec UML_LABEL(block, skip); // skip: /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, IMM(0), MEM(&sh2->pc), *sh2->nocode); // hashjmp <mode>,<pc>,nocode + UML_HASHJMP(block, 0, mem(&sh2->pc), *sh2->nocode); // hashjmp <mode>,<pc>,nocode block->end(); } @@ -1127,10 +1127,10 @@ static void static_generate_nocode_handler(sh2_state *sh2) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &sh2->nocode, "nocode"); UML_HANDLE(block, *sh2->nocode); // handle nocode - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&sh2->pc), IREG(0)); // mov [pc],i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&sh2->pc), I0); // mov [pc],i0 save_fast_iregs(sh2, block); - UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); } @@ -1152,10 +1152,10 @@ static void static_generate_out_of_cycles(sh2_state *sh2) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &sh2->out_of_cycles, "out_of_cycles"); UML_HANDLE(block, *sh2->out_of_cycles); // handle out_of_cycles - UML_GETEXP(block, IREG(0)); // getexp i0 - UML_MOV(block, MEM(&sh2->pc), IREG(0)); // mov <pc>,i0 + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&sh2->pc), I0); // mov <pc>,i0 save_fast_iregs(sh2,block); - UML_EXIT(block, IMM(EXECUTE_OUT_OF_CYCLES)); // exit EXECUTE_OUT_OF_CYCLES + UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); } @@ -1182,13 +1182,13 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit // with internal handlers this becomes easier. // if addr < 0x40000000 AND it with AM and do the read/write, else just do the read/write - UML_TEST(block, IREG(0), IMM(0x80000000)); // test r0, #0x80000000 - UML_JMPc(block, IF_NZ, label); // if high bit is set, don't mask + UML_TEST(block, I0, 0x80000000); // test r0, #0x80000000 + UML_JMPc(block, COND_NZ, label); // if high bit is set, don't mask - UML_CMP(block, IREG(0), IMM(0x40000000)); // cmp #0x40000000, r0 - UML_JMPc(block, IF_AE, label); // bae label + UML_CMP(block, I0, 0x40000000); // cmp #0x40000000, r0 + UML_JMPc(block, COND_AE, label); // bae label - UML_AND(block, IREG(0), IREG(0), IMM(AM)); // and r0, r0, #AM (0xc7ffffff) + UML_AND(block, I0, I0, AM); // and r0, r0, #AM (0xc7ffffff) UML_LABEL(block, label++); // label: @@ -1197,15 +1197,15 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit switch (size) { case 1: - UML_WRITE(block, IREG(0), IREG(1), SIZE_BYTE, SPACE_PROGRAM); // write r0, r1, program_byte + UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write r0, r1, program_byte break; case 2: - UML_WRITE(block, IREG(0), IREG(1), SIZE_WORD, SPACE_PROGRAM); // write r0, r1, program_word + UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write r0, r1, program_word break; case 4: - UML_WRITE(block, IREG(0), IREG(1), SIZE_DWORD, SPACE_PROGRAM); // write r0, r1, program_dword + UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write r0, r1, program_dword break; } } @@ -1214,15 +1214,15 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit switch (size) { case 1: - UML_READ(block, IREG(0), IREG(0), SIZE_BYTE, SPACE_PROGRAM); // read r0, program_byte + UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read r0, program_byte break; case 2: - UML_READ(block, IREG(0), IREG(0), SIZE_WORD, SPACE_PROGRAM); // read r0, program_word + UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read r0, program_word break; case 4: - UML_READ(block, IREG(0), IREG(0), SIZE_DWORD, SPACE_PROGRAM); // read r0, program_dword + UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read r0, program_dword break; } } @@ -1429,52 +1429,52 @@ static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler compiler->labelnum += 4; /* check for interrupts */ - UML_MOV(block, MEM(&sh2->irqline), IMM(0xffffffff)); // mov irqline, #-1 - UML_CMP(block, MEM(&sh2->pending_nmi), IMM(0)); // cmp pending_nmi, #0 - UML_JMPc(block, IF_Z, skip+2); // jz skip+2 + UML_MOV(block, mem(&sh2->irqline), 0xffffffff); // mov irqline, #-1 + UML_CMP(block, mem(&sh2->pending_nmi), 0); // cmp pending_nmi, #0 + UML_JMPc(block, COND_Z, skip+2); // jz skip+2 - UML_MOV(block, MEM(&sh2->pending_nmi), IMM(0)); // zap pending_nmi + UML_MOV(block, mem(&sh2->pending_nmi), 0); // zap pending_nmi UML_JMP(block, skip+1); // and then go take it (evec is already set) UML_LABEL(block, skip+2); // skip+2: - UML_MOV(block, MEM(&sh2->evec), IMM(0xffffffff)); // mov evec, -1 - UML_MOV(block, IREG(0), IMM(0xffffffff)); // mov r0, -1 (r0 = irq) - UML_AND(block, IREG(1), IREG(0), IMM(0xffff)); // and r1, r0, 0xffff + UML_MOV(block, mem(&sh2->evec), 0xffffffff); // mov evec, -1 + UML_MOV(block, I0, 0xffffffff); // mov r0, -1 (r0 = irq) + UML_AND(block, I1, I0, 0xffff); // and r1, r0, 0xffff - UML_LZCNT(block, IREG(1), MEM(&sh2->pending_irq)); // lzcnt r1, pending_irq - UML_CMP(block, IREG(1), IMM(32)); // cmp r1, #32 - UML_JMPc(block, IF_Z, skip+4); // jz skip+4 + UML_LZCNT(block, I1, mem(&sh2->pending_irq)); // lzcnt r1, pending_irq + UML_CMP(block, I1, 32); // cmp r1, #32 + UML_JMPc(block, COND_Z, skip+4); // jz skip+4 - UML_SUB(block, MEM(&sh2->irqline), IMM(31), IREG(1)); // sub irqline, #31, r1 + UML_SUB(block, mem(&sh2->irqline), 31, I1); // sub irqline, #31, r1 UML_LABEL(block, skip+4); // skip+4: - UML_CMP(block, MEM(&sh2->internal_irq_level), IMM(0xffffffff)); // cmp internal_irq_level, #-1 - UML_JMPc(block, IF_Z, skip+3); // jz skip+3 - UML_CMP(block, MEM(&sh2->internal_irq_level), MEM(&sh2->irqline)); // cmp internal_irq_level, irqline - UML_JMPc(block, IF_LE, skip+3); // jle skip+3 + UML_CMP(block, mem(&sh2->internal_irq_level), 0xffffffff); // cmp internal_irq_level, #-1 + UML_JMPc(block, COND_Z, skip+3); // jz skip+3 + UML_CMP(block, mem(&sh2->internal_irq_level), mem(&sh2->irqline)); // cmp internal_irq_level, irqline + UML_JMPc(block, COND_LE, skip+3); // jle skip+3 - UML_MOV(block, MEM(&sh2->irqline), MEM(&sh2->internal_irq_level)); // mov r0, internal_irq_level + UML_MOV(block, mem(&sh2->irqline), mem(&sh2->internal_irq_level)); // mov r0, internal_irq_level UML_LABEL(block, skip+3); // skip+3: - UML_CMP(block, MEM(&sh2->irqline), IMM(0xffffffff)); // cmp irqline, #-1 - UML_JMPc(block, IF_Z, skip+1); // jz skip+1 + UML_CMP(block, mem(&sh2->irqline), 0xffffffff); // cmp irqline, #-1 + UML_JMPc(block, COND_Z, skip+1); // jz skip+1 UML_CALLC(block, cfunc_fastirq, sh2); // callc fastirq UML_LABEL(block, skip+1); // skip+1: - UML_CMP(block, MEM(&sh2->evec), IMM(0xffffffff)); // cmp evec, 0xffffffff - UML_JMPc(block, IF_Z, skip); // jz skip + UML_CMP(block, mem(&sh2->evec), 0xffffffff); // cmp evec, 0xffffffff + UML_JMPc(block, COND_Z, skip); // jz skip - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), MEM(&sh2->irqsr)); // mov r1, irqsr + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, mem(&sh2->irqsr)); // mov r1, irqsr UML_CALLH(block, *sh2->write32); // call write32 - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), param); // mov r1, nextpc + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, param); // mov r1, nextpc UML_CALLH(block, *sh2->write32); // call write32 - UML_HASHJMP(block, IMM(0), MEM(&sh2->evec), *sh2->nocode); // hashjmp sh2->evec + UML_HASHJMP(block, 0, mem(&sh2->evec), *sh2->nocode); // hashjmp sh2->evec UML_LABEL(block, skip); // skip: } @@ -1482,10 +1482,10 @@ static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, MEM(&sh2->icount), MEM(&sh2->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_SUB(block, mem(&sh2->icount), mem(&sh2->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 if (allow_exception) - UML_EXHc(block, IF_S, *sh2->out_of_cycles, param); + UML_EXHc(block, COND_S, *sh2->out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; @@ -1508,9 +1508,9 @@ static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compile if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP)) { void *base = sh2->direct->read_decrypted_ptr(seqhead->physpc, SH2_CODE_XOR(0)); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_WORD, SCALE_x2); // load i0,base,word - UML_CMP(block, IREG(0), IMM(seqhead->opptr.w[0])); // cmp i0,*opptr - UML_EXHc(block, IF_NE, *sh2->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_LOAD(block, I0, base, 0, SIZE_WORD, SCALE_x2); // load i0,base,word + UML_CMP(block, I0, seqhead->opptr.w[0]); // cmp i0,*opptr + UML_EXHc(block, COND_NE, *sh2->nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -1522,25 +1522,25 @@ static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compile if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { base = sh2->direct->read_decrypted_ptr(curdesc->physpc, SH2_CODE_XOR(0)); - UML_LOAD(block, IREG(0), curdesc->opptr.w, IMM(0), SIZE_WORD, SCALE_x2); // load i0,*opptr,0,word - UML_CMP(block, IREG(0), IMM(curdesc->opptr.w[0])); // cmp i0,*opptr - UML_EXHc(block, IF_NE, *sh2->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_LOAD(block, I0, curdesc->opptr.w, 0, SIZE_WORD, SCALE_x2); // load i0,*opptr,0,word + UML_CMP(block, I0, curdesc->opptr.w[0]); // cmp i0,*opptr + UML_EXHc(block, COND_NE, *sh2->nocode, epc(seqhead)); // exne nocode,seqhead->pc } #else UINT32 sum = 0; void *base = sh2->direct->read_decrypted_ptr(seqhead->physpc, SH2_CODE_XOR(0)); - UML_LOAD(block, IREG(0), base, IMM(0), SIZE_WORD, SCALE_x4); // load i0,base,word + UML_LOAD(block, I0, base, 0, SIZE_WORD, SCALE_x4); // load i0,base,word sum += seqhead->opptr.w[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { base = sh2->direct->read_decrypted_ptr(curdesc->physpc, SH2_CODE_XOR(0)); - UML_LOAD(block, IREG(1), base, IMM(0), SIZE_WORD, SCALE_x2); // load i1,*opptr,word - UML_ADD(block, IREG(0), IREG(0), IREG(1)); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_WORD, SCALE_x2); // load i1,*opptr,word + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.w[0]; } - UML_CMP(block, IREG(0), IMM(sum)); // cmp i0,sum - UML_EXHc(block, IF_NE, *sh2->nocode, IMM(epc(seqhead))); // exne nocode,seqhead->pc + UML_CMP(block, I0, sum); // cmp i0,sum + UML_EXHc(block, COND_NE, *sh2->nocode, epc(seqhead)); // exne nocode,seqhead->pc #endif } } @@ -1572,22 +1572,22 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c /* if we want a probe, add it here */ if (desc->pc == PROBE_ADDRESS) { - UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc UML_CALLC(block, cfunc_printf_probe, sh2); // callc cfunc_printf_probe,sh2 } /* if we are debugging, call the debugger */ if ((sh2->device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(sh2, block); - UML_DEBUG(block, IMM(desc->pc)); // debug desc->pc + UML_DEBUG(block, desc->pc); // debug desc->pc } else // not debug, see what other reasons there are for flushing the PC { if (sh2->drcoptions & SH2DRC_FLUSH_PC) // always flush? { - UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov sh2->pc, desc->pc + UML_MOV(block, mem(&sh2->pc), desc->pc); // mov sh2->pc, desc->pc } else // check for driver-selected flushes { @@ -1597,7 +1597,7 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c { if (desc->pc == sh2->pcflushes[pcflush]) { - UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov sh2->pc, desc->pc + UML_MOV(block, mem(&sh2->pc), desc->pc); // mov sh2->pc, desc->pc } } } @@ -1607,9 +1607,9 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov [pc],desc->pc + UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(sh2, block); - UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE + UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } /* if this is an invalid opcode, die */ @@ -1624,8 +1624,8 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c /* compile the instruction */ if (!generate_opcode(sh2, block, compiler, desc, ovrpc)) { - UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov [pc],desc->pc - UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); // mov [arg0],opcode + UML_MOV(block, mem(&sh2->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); // mov [arg0],opcode UML_CALLC(block, cfunc_unimplemented, sh2); // callc cfunc_unimplemented } } @@ -1667,13 +1667,13 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state * case 1: // MOVLS4 scratch = (opcode & 0x0f) * 4; - UML_ADD(block, IREG(0), R32(Rn), IMM(scratch)); // add r0, Rn, scratch - UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm + UML_ADD(block, I0, R32(Rn), scratch); // add r0, Rn, scratch + UML_MOV(block, I1, R32(Rm)); // mov r1, Rm SETEA(0); // set ea for debug UML_CALLH(block, *sh2->write32); if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 2: @@ -1685,13 +1685,13 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state * case 5: // MOVLL4 scratch = (opcode & 0x0f) * 4; - UML_ADD(block, IREG(0), R32(Rm), IMM(scratch)); // add r0, Rm, scratch + UML_ADD(block, I0, R32(Rm), scratch); // add r0, Rm, scratch SETEA(0); // set ea for debug UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, R32(Rn), IREG(0)); // mov Rn, r0 + UML_MOV(block, R32(Rn), I0); // mov Rn, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 6: @@ -1700,7 +1700,7 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state * case 7: // ADDI scratch = opcode & 0xff; scratch2 = (UINT32)(INT32)(INT16)(INT8)scratch; - UML_ADD(block, R32(Rn), R32(Rn), IMM(scratch2)); // add Rn, Rn, scratch2 + UML_ADD(block, R32(Rn), R32(Rn), scratch2); // add Rn, Rn, scratch2 return TRUE; case 8: @@ -1718,19 +1718,19 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state * if (sh2->drcoptions & SH2DRC_STRICT_PCREL) { - UML_MOV(block, IREG(0), IMM(scratch)); // mov r0, scratch + UML_MOV(block, I0, scratch); // mov r0, scratch SETEA(0); // set ea for debug UML_CALLH(block, *sh2->read16); // read16(r0, r1) - UML_SEXT(block, R32(Rn), IREG(0), SIZE_WORD); // sext Rn, r0, WORD + UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD } else { scratch2 = (UINT32)(INT32)(INT16) RW(sh2, scratch); - UML_MOV(block, R32(Rn), IMM(scratch2)); // mov Rn, scratch2 + UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2 } if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 10: // BRA @@ -1739,22 +1739,22 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state * generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2); - generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), IMM(sh2->ea), *sh2->nocode); // hashjmp sh2->ea + generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // hashjmp sh2->ea return TRUE; case 11: // BSR // panicstr @ 403da22 relies on the delay slot clobbering the PR set by a BSR, so // do this before running the delay slot - UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot) + UML_ADD(block, mem(&sh2->pr), desc->pc, 4); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot) disp = ((INT32)opcode << 20) >> 20; sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = pc+4 + disp*2 + 2 generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2); - generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), IMM(sh2->ea), *sh2->nocode); // hashjmp sh2->ea + generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // hashjmp sh2->ea return TRUE; case 12: @@ -1772,24 +1772,24 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state * if (sh2->drcoptions & SH2DRC_STRICT_PCREL) { - UML_MOV(block, IREG(0), IMM(scratch)); // mov r0, scratch + UML_MOV(block, I0, scratch); // mov r0, scratch UML_CALLH(block, *sh2->read32); // read32(r0, r1) - UML_MOV(block, R32(Rn), IREG(0)); // mov Rn, r0 + UML_MOV(block, R32(Rn), I0); // mov Rn, r0 } else { scratch2 = RL(sh2, scratch); - UML_MOV(block, R32(Rn), IMM(scratch2)); // mov Rn, scratch2 + UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2 } if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 14: // MOVI scratch = opcode & 0xff; scratch2 = (UINT32)(INT32)(INT16)(INT8)scratch; - UML_MOV(block, R32(Rn), IMM(scratch2)); + UML_MOV(block, R32(Rn), scratch2); return TRUE; case 15: // NOP @@ -1822,23 +1822,23 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state return TRUE; case 0x02: // STCSR(Rn); - UML_MOV(block, R32(Rn), MEM(&sh2->sr)); + UML_MOV(block, R32(Rn), mem(&sh2->sr)); return TRUE; case 0x03: // BSRF(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(4)); // add target, Rm, #4 - UML_ADD(block, MEM(&sh2->target), MEM(&sh2->target), IMM(desc->pc)); // add target, target, pc + UML_ADD(block, mem(&sh2->target), R32(Rn), 4); // add target, Rm, #4 + UML_ADD(block, mem(&sh2->target), mem(&sh2->target), desc->pc); // add target, target, pc // 32x Cosmic Carnage @ 6002cb0 relies on the delay slot // clobbering the calculated PR, so do it first - UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot) + UML_ADD(block, mem(&sh2->pr), desc->pc, 4); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot) generate_delay_slot(sh2, block, compiler, desc, sh2->target); - generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&sh2->target), *sh2->nocode); // jmp target + generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // jmp target return TRUE; } break; @@ -1847,36 +1847,36 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state case 0x14: // MOVBS0(Rm, Rn); case 0x24: // MOVBS0(Rm, Rn); case 0x34: // MOVBS0(Rm, Rn); - UML_ADD(block, IREG(0), R32(0), R32(Rn)); // add r0, R0, Rn - UML_AND(block, IREG(1), R32(Rm), IMM(0x000000ff)); // and r1, Rm, 0xff + UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn + UML_AND(block, I1, R32(Rm), 0x000000ff); // and r1, Rm, 0xff UML_CALLH(block, *sh2->write8); // call write8 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x05: // MOVWS0(Rm, Rn); case 0x15: // MOVWS0(Rm, Rn); case 0x25: // MOVWS0(Rm, Rn); case 0x35: // MOVWS0(Rm, Rn); - UML_ADD(block, IREG(0), R32(0), R32(Rn)); // add r0, R0, Rn - UML_AND(block, IREG(1), R32(Rm), IMM(0x0000ffff)); // and r1, Rm, 0xffff + UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn + UML_AND(block, I1, R32(Rm), 0x0000ffff); // and r1, Rm, 0xffff UML_CALLH(block, *sh2->write16); // call write16 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x06: // MOVLS0(Rm, Rn); case 0x16: // MOVLS0(Rm, Rn); case 0x26: // MOVLS0(Rm, Rn); case 0x36: // MOVLS0(Rm, Rn); - UML_ADD(block, IREG(0), R32(0), R32(Rn)); // add r0, R0, Rn - UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm + UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn + UML_MOV(block, I1, R32(Rm)); // mov r1, Rm UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x07: // MULL(Rm, Rn); @@ -1885,62 +1885,62 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state case 0x37: // MULL(Rm, Rn); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm + UML_MULU(block, mem(&sh2->macl), mem(&sh2->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm return TRUE; } break; case 0x08: // CLRT(); - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit) return TRUE; case 0x0a: // STSMACH(Rn); - UML_MOV(block, R32(Rn), MEM(&sh2->mach)); // mov Rn, mach + UML_MOV(block, R32(Rn), mem(&sh2->mach)); // mov Rn, mach return TRUE; case 0x0b: // RTS(); - UML_MOV(block, MEM(&sh2->target), MEM(&sh2->pr)); // mov target, pr (in case of d-slot shenanigans) + UML_MOV(block, mem(&sh2->target), mem(&sh2->pr)); // mov target, pr (in case of d-slot shenanigans) generate_delay_slot(sh2, block, compiler, desc, sh2->target); - generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&sh2->target), *sh2->nocode); + generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); return TRUE; case 0x0c: // MOVBL0(Rm, Rn); case 0x1c: // MOVBL0(Rm, Rn); case 0x2c: // MOVBL0(Rm, Rn); case 0x3c: // MOVBL0(Rm, Rn); - UML_ADD(block, IREG(0), R32(0), R32(Rm)); // add r0, R0, Rm + UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm UML_CALLH(block, *sh2->read8); // call read8 - UML_SEXT(block, R32(Rn), IREG(0), SIZE_BYTE); // sext Rn, r0, BYTE + UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x0d: // MOVWL0(Rm, Rn); case 0x1d: // MOVWL0(Rm, Rn); case 0x2d: // MOVWL0(Rm, Rn); case 0x3d: // MOVWL0(Rm, Rn); - UML_ADD(block, IREG(0), R32(0), R32(Rm)); // add r0, R0, Rm + UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm UML_CALLH(block, *sh2->read16); // call read16 - UML_SEXT(block, R32(Rn), IREG(0), SIZE_WORD); // sext Rn, r0, WORD + UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x0e: // MOVLL0(Rm, Rn); case 0x1e: // MOVLL0(Rm, Rn); case 0x2e: // MOVLL0(Rm, Rn); case 0x3e: // MOVLL0(Rm, Rn); - UML_ADD(block, IREG(0), R32(0), R32(Rm)); // add r0, R0, Rm + UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, R32(Rn), IREG(0)); // mov Rn, r0 + UML_MOV(block, R32(Rn), I0); // mov Rn, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x0f: // MAC_L(Rm, Rn); @@ -1950,7 +1950,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state if (sh2->cpu_type > CPU_TYPE_SH1) { save_fast_iregs(sh2, block); - UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); + UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); UML_CALLC(block, cfunc_MAC_L, sh2); load_fast_iregs(sh2, block); return TRUE; @@ -1958,19 +1958,19 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state break; case 0x12: // STCGBR(Rn); - UML_MOV(block, R32(Rn), MEM(&sh2->gbr)); // mov Rn, gbr + UML_MOV(block, R32(Rn), mem(&sh2->gbr)); // mov Rn, gbr return TRUE; case 0x18: // SETT(); - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T return TRUE; case 0x19: // DIV0U(); - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~(M|Q|T))); // and sr, sr, ~(M|Q|T) + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~(M|Q|T)); // and sr, sr, ~(M|Q|T) return TRUE; case 0x1a: // STSMACL(Rn); - UML_MOV(block, R32(Rn), MEM(&sh2->macl)); // mov Rn, macl + UML_MOV(block, R32(Rn), mem(&sh2->macl)); // mov Rn, macl return TRUE; case 0x1b: // SLEEP(); @@ -1978,85 +1978,85 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state // if an interrupt is taken, the return address is set to the next instruction UML_CALLC(block, cfunc_checkirqs, sh2); - UML_MOV(block, IREG(0), MEM(&sh2->evec)); // mov r0, evec - UML_CMP(block, IREG(0), IMM(0xffffffff)); // cmp r0, 0xffffffff - UML_JMPc(block, IF_Z, compiler->labelnum); // jz skip + UML_MOV(block, I0, mem(&sh2->evec)); // mov r0, evec + UML_CMP(block, I0, 0xffffffff); // cmp r0, 0xffffffff + UML_JMPc(block, COND_Z, compiler->labelnum); // jz skip - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), MEM(&sh2->irqsr)); // mov r1, irqsr + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, mem(&sh2->irqsr)); // mov r1, irqsr UML_CALLH(block, *sh2->write32); // call write32 - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), IMM(desc->pc+2)); // mov r1, nextpc + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, desc->pc+2); // mov r1, nextpc UML_CALLH(block, *sh2->write32); // call write32 - UML_HASHJMP(block, IMM(0), MEM(&sh2->evec), *sh2->nocode); // hashjmp sh2->evec + UML_HASHJMP(block, 0, mem(&sh2->evec), *sh2->nocode); // hashjmp sh2->evec UML_LABEL(block, compiler->labelnum++); // skip: // now go "out of cycles" if (compiler->cycles > 0) { - UML_MOV(block, MEM(&sh2->icount), IMM(0)); // mov icount, #0 + UML_MOV(block, mem(&sh2->icount), 0); // mov icount, #0 UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 - UML_EXH(block, *sh2->out_of_cycles, IMM(desc->pc)); // go out of cycles + UML_EXH(block, *sh2->out_of_cycles, desc->pc); // go out of cycles } else { - UML_HASHJMP(block, IMM(0), IMM(desc->pc), *sh2->nocode); + UML_HASHJMP(block, 0, desc->pc, *sh2->nocode); } return TRUE; case 0x22: // STCVBR(Rn); - UML_MOV(block, R32(Rn), MEM(&sh2->vbr)); // mov Rn, vbr + UML_MOV(block, R32(Rn), mem(&sh2->vbr)); // mov Rn, vbr return TRUE; case 0x23: // BRAF(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(desc->pc+4)); // add target, Rn, pc+4 + UML_ADD(block, mem(&sh2->target), R32(Rn), desc->pc+4); // add target, Rn, pc+4 generate_delay_slot(sh2, block, compiler, desc, sh2->target); - generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&sh2->target), *sh2->nocode); // jmp target + generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // jmp target return TRUE; } break; case 0x28: // CLRMAC(); - UML_MOV(block, MEM(&sh2->macl), IMM(0)); // mov macl, #0 - UML_MOV(block, MEM(&sh2->mach), IMM(0)); // mov mach, #0 + UML_MOV(block, mem(&sh2->macl), 0); // mov macl, #0 + UML_MOV(block, mem(&sh2->mach), 0); // mov mach, #0 return TRUE; case 0x29: // MOVT(Rn); - UML_AND(block, R32(Rn), MEM(&sh2->sr), IMM(T)); // and Rn, sr, T + UML_AND(block, R32(Rn), mem(&sh2->sr), T); // and Rn, sr, T return TRUE; case 0x2a: // STSPR(Rn); - UML_MOV(block, R32(Rn), MEM(&sh2->pr)); // mov Rn, pr + UML_MOV(block, R32(Rn), mem(&sh2->pr)); // mov Rn, pr return TRUE; case 0x2b: // RTE(); generate_delay_slot(sh2, block, compiler, desc, 0xffffffff); - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 + UML_MOV(block, I0, R32(15)); // mov r0, R15 UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, MEM(&sh2->pc), IREG(0)); // mov pc, r0 - UML_ADD(block, R32(15), R32(15), IMM(4)); // add R15, R15, #4 + UML_MOV(block, mem(&sh2->pc), I0); // mov pc, r0 + UML_ADD(block, R32(15), R32(15), 4); // add R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 + UML_MOV(block, I0, R32(15)); // mov r0, R15 UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sr, r0 - UML_ADD(block, R32(15), R32(15), IMM(4)); // add R15, R15, #4 + UML_MOV(block, mem(&sh2->sr), I0); // mov sr, r0 + UML_ADD(block, R32(15), R32(15), 4); // add R15, R15, #4 compiler->checkints = TRUE; - UML_MOV(block, MEM(&sh2->ea), MEM(&sh2->pc)); // mov ea, pc - generate_update_cycles(sh2, block, compiler, MEM(&sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&sh2->pc), *sh2->nocode); // and jump to the "resume PC" + UML_MOV(block, mem(&sh2->ea), mem(&sh2->pc)); // mov ea, pc + generate_update_cycles(sh2, block, compiler, mem(&sh2->ea), TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, mem(&sh2->pc), *sh2->nocode); // and jump to the "resume PC" return TRUE; } @@ -2069,138 +2069,138 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state switch (opcode & 15) { case 0: // MOVBS(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_AND(block, IREG(1), R32(Rm), IMM(0xff)); // and r1, Rm, 0xff + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_AND(block, I1, R32(Rm), 0xff); // and r1, Rm, 0xff UML_CALLH(block, *sh2->write8); if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 1: // MOVWS(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_AND(block, IREG(1), R32(Rm), IMM(0xffff)); // and r1, Rm, 0xffff + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_AND(block, I1, R32(Rm), 0xffff); // and r1, Rm, 0xffff UML_CALLH(block, *sh2->write16); if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 2: // MOVLS(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, R32(Rm)); // mov r1, Rm UML_CALLH(block, *sh2->write32); if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 3: // NOP(); return TRUE; case 4: // MOVBM(Rm, Rn); - UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm - UML_SUB(block, R32(Rn), R32(Rn), IMM(1)); // sub Rn, Rn, 1 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, R32(Rm)); // mov r1, Rm + UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn UML_CALLH(block, *sh2->write8); // call write8 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 5: // MOVWM(Rm, Rn); - UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm - UML_SUB(block, R32(Rn), R32(Rn), IMM(2)); // sub Rn, Rn, 2 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, R32(Rm)); // mov r1, Rm + UML_SUB(block, R32(Rn), R32(Rn), 2); // sub Rn, Rn, 2 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn UML_CALLH(block, *sh2->write16); // call write16 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 6: // MOVLM(Rm, Rn); - UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, R32(Rm)); // mov r1, Rm + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 13: // XTRCT(Rm, Rn); - UML_SHL(block, IREG(0), R32(Rm), IMM(16)); // shl r0, Rm, #16 - UML_AND(block, IREG(0), IREG(0), IMM(0xffff0000)); // and r0, r0, #0xffff0000 + UML_SHL(block, I0, R32(Rm), 16); // shl r0, Rm, #16 + UML_AND(block, I0, I0, 0xffff0000); // and r0, r0, #0xffff0000 - UML_SHR(block, IREG(1), R32(Rn), IMM(16)); // shr, r1, Rn, #16 - UML_AND(block, IREG(1), IREG(1), IMM(0xffff)); // and r1, r1, #0x0000ffff + UML_SHR(block, I1, R32(Rn), 16); // shr, r1, Rn, #16 + UML_AND(block, I1, I1, 0xffff); // and r1, r1, #0x0000ffff - UML_OR(block, R32(Rn), IREG(0), IREG(1)); // or Rn, r0, r1 + UML_OR(block, R32(Rn), I0, I1); // or Rn, r0, r1 return TRUE; case 7: // DIV0S(Rm, Rn); - UML_MOV(block, IREG(0), MEM(&sh2->sr)); // move r0, sr - UML_AND(block, IREG(0), IREG(0), IMM(~(Q|M|T))); // and r0, r0, ~(Q|M|T) (clear the Q,M, and T bits) + UML_MOV(block, I0, mem(&sh2->sr)); // move r0, sr + UML_AND(block, I0, I0, ~(Q|M|T)); // and r0, r0, ~(Q|M|T) (clear the Q,M, and T bits) - UML_TEST(block, R32(Rn), IMM(0x80000000)); // test Rn, #0x80000000 - UML_JMPc(block, IF_Z, compiler->labelnum); // jz labelnum + UML_TEST(block, R32(Rn), 0x80000000); // test Rn, #0x80000000 + UML_JMPc(block, COND_Z, compiler->labelnum); // jz labelnum - UML_OR(block, IREG(0), IREG(0), IMM(Q)); // or r0, r0, Q + UML_OR(block, I0, I0, Q); // or r0, r0, Q UML_LABEL(block, compiler->labelnum++); // labelnum: - UML_TEST(block, R32(Rm), IMM(0x80000000)); // test Rm, #0x80000000 - UML_JMPc(block, IF_Z, compiler->labelnum); // jz labelnum + UML_TEST(block, R32(Rm), 0x80000000); // test Rm, #0x80000000 + UML_JMPc(block, COND_Z, compiler->labelnum); // jz labelnum - UML_OR(block, IREG(0), IREG(0), IMM(M)); // or r0, r0, M + UML_OR(block, I0, I0, M); // or r0, r0, M UML_LABEL(block, compiler->labelnum++); // labelnum: - UML_XOR(block, IREG(1), R32(Rn), R32(Rm)); // xor r1, Rn, Rm - UML_TEST(block, IREG(1), IMM(0x80000000)); // test r1, #0x80000000 - UML_JMPc(block, IF_Z, compiler->labelnum); // jz labelnum + UML_XOR(block, I1, R32(Rn), R32(Rm)); // xor r1, Rn, Rm + UML_TEST(block, I1, 0x80000000); // test r1, #0x80000000 + UML_JMPc(block, COND_Z, compiler->labelnum); // jz labelnum - UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T + UML_OR(block, I0, I0, T); // or r0, r0, T UML_LABEL(block, compiler->labelnum++); // labelnum: - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sr, r0 + UML_MOV(block, mem(&sh2->sr), I0); // mov sr, r0 return TRUE; case 8: // TST(Rm, Rn); - UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) + UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit) UML_TEST(block, R32(Rm), R32(Rn)); // test Rm, Rn - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum - UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T + UML_OR(block, I0, I0, T); // or r0, r0, T UML_LABEL(block, compiler->labelnum++); // desc->pc: - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 + UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0 return TRUE; case 12: // CMPSTR(Rm, Rn); - UML_XOR(block, IREG(0), R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp) + UML_XOR(block, I0, R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp) - UML_SHR(block, IREG(1), IREG(0), IMM(24)); // shr r1, r0, #24 (HH) - UML_AND(block, IREG(1), IREG(1), IMM(0xff)); // and r1, r1, #0xff + UML_SHR(block, I1, I0, 24); // shr r1, r0, #24 (HH) + UML_AND(block, I1, I1, 0xff); // and r1, r1, #0xff - UML_SHR(block, IREG(2), IREG(0), IMM(16)); // shr r2, r0, #16 (HL) - UML_AND(block, IREG(2), IREG(2), IMM(0xff)); // and r2, r2, #0xff + UML_SHR(block, I2, I0, 16); // shr r2, r0, #16 (HL) + UML_AND(block, I2, I2, 0xff); // and r2, r2, #0xff - UML_SHR(block, IREG(3), IREG(0), IMM(8)); // shr r3, r0, #8 (LH) - UML_AND(block, IREG(3), IREG(3), IMM(0xff)); // and r3, r3, #0xff + UML_SHR(block, I3, I0, 8); // shr r3, r0, #8 (LH) + UML_AND(block, I3, I3, 0xff); // and r3, r3, #0xff - UML_AND(block, IREG(7), IREG(0), IMM(0xff)); // and r7, r0, #0xff (LL) + UML_AND(block, I7, I0, 0xff); // and r7, r0, #0xff (LL) - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit) + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit) - UML_CMP(block, IREG(1), IMM(0)); // cmp r1, #0 - UML_JMPc(block, IF_Z, compiler->labelnum); // jnz labelnum - UML_CMP(block, IREG(2), IMM(0)); // cmp r2, #0 - UML_JMPc(block, IF_Z, compiler->labelnum); // jnz labelnum - UML_CMP(block, IREG(3), IMM(0)); // cmp r3, #0 - UML_JMPc(block, IF_Z, compiler->labelnum); // jnz labelnum - UML_CMP(block, IREG(7), IMM(0)); // cmp r7, #0 - UML_JMPc(block, IF_NZ, compiler->labelnum+1); // jnz labelnum + UML_CMP(block, I1, 0); // cmp r1, #0 + UML_JMPc(block, COND_Z, compiler->labelnum); // jnz labelnum + UML_CMP(block, I2, 0); // cmp r2, #0 + UML_JMPc(block, COND_Z, compiler->labelnum); // jnz labelnum + UML_CMP(block, I3, 0); // cmp r3, #0 + UML_JMPc(block, COND_Z, compiler->labelnum); // jnz labelnum + UML_CMP(block, I7, 0); // cmp r7, #0 + UML_JMPc(block, COND_NZ, compiler->labelnum+1); // jnz labelnum UML_LABEL(block, compiler->labelnum++); // labelnum: - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T UML_LABEL(block, compiler->labelnum++); // labelnum+1: return TRUE; @@ -2218,15 +2218,15 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state return TRUE; case 14: // MULU(Rm, Rn); - UML_AND(block, IREG(0), R32(Rm), IMM(0xffff)); // and r0, Rm, 0xffff - UML_AND(block, IREG(1), R32(Rn), IMM(0xffff)); // and r1, Rn, 0xffff - UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->ea), IREG(0), IREG(1)); // mulu macl, ea, r0, r1 + UML_AND(block, I0, R32(Rm), 0xffff); // and r0, Rm, 0xffff + UML_AND(block, I1, R32(Rn), 0xffff); // and r1, Rn, 0xffff + UML_MULU(block, mem(&sh2->macl), mem(&sh2->ea), I0, I1); // mulu macl, ea, r0, r1 return TRUE; case 15: // MULS(Rm, Rn); - UML_SEXT(block, IREG(0), R32(Rm), SIZE_WORD); // sext r0, Rm - UML_SEXT(block, IREG(1), R32(Rn), SIZE_WORD); // sext r1, Rn - UML_MULS(block, MEM(&sh2->macl), MEM(&sh2->ea), IREG(0), IREG(1)); // muls macl, ea, r0, r1 + UML_SEXT(block, I0, R32(Rm), SIZE_WORD); // sext r0, Rm + UML_SEXT(block, I1, R32(Rn), SIZE_WORD); // sext r1, Rn + UML_MULS(block, mem(&sh2->macl), mem(&sh2->ea), I0, I1); // muls macl, ea, r0, r1 return TRUE; } @@ -2239,32 +2239,32 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state { case 0: // CMPEQ(Rm, Rn); (equality) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm - UML_SETc(block, IF_E, IREG(0)); // set E, r0 - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 + UML_SETc(block, COND_E, I0); // set E, r0 + UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1 return TRUE; case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm - UML_SETc(block, IF_AE, IREG(0)); // set AE, r0 - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 + UML_SETc(block, COND_AE, I0); // set AE, r0 + UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1 return TRUE; case 3: // CMPGE(Rm, Rn); (signed greater than or equal) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm - UML_SETc(block, IF_GE, IREG(0)); // set GE, r0 - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 + UML_SETc(block, COND_GE, I0); // set GE, r0 + UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1 return TRUE; case 6: // CMPHI(Rm, Rn); (unsigned greater than) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm - UML_SETc(block, IF_A, IREG(0)); // set A, r0 - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 + UML_SETc(block, COND_A, I0); // set A, r0 + UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1 return TRUE; case 7: // CMPGT(Rm, Rn); (signed greater than) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm - UML_SETc(block, IF_G, IREG(0)); // set G, r0 - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 + UML_SETc(block, COND_G, I0); // set G, r0 + UML_ROLINS(block, mem(&sh2->sr), I0, 0, 1); // rolins sr, r0, 0, 1 return TRUE; case 1: // NOP(); @@ -2273,7 +2273,7 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state case 4: // DIV1(Rm, Rn); save_fast_iregs(sh2, block); - UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); + UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); UML_CALLC(block, cfunc_DIV1, sh2); load_fast_iregs(sh2, block); return TRUE; @@ -2281,7 +2281,7 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state case 5: // DMULU(Rm, Rn); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->mach), R32(Rn), R32(Rm)); + UML_MULU(block, mem(&sh2->macl), mem(&sh2->mach), R32(Rn), R32(Rm)); return TRUE; } break; @@ -2289,7 +2289,7 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state case 13: // DMULS(Rm, Rn); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_MULS(block, MEM(&sh2->macl), MEM(&sh2->mach), R32(Rn), R32(Rm)); + UML_MULS(block, mem(&sh2->macl), mem(&sh2->mach), R32(Rn), R32(Rm)); return TRUE; } break; @@ -2303,40 +2303,40 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state return TRUE; case 10: // SUBC(Rm, Rn); - UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry = T (T is bit 0 of SR) + UML_CARRY(block, mem(&sh2->sr), 0); // carry = T (T is bit 0 of SR) UML_SUBB(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm - UML_SETc(block, IF_C, IREG(0)); // setc i0, C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T + UML_SETc(block, COND_C, I0); // setc i0, C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T return TRUE; case 11: // SUBV(Rm, Rn); #if ADDSUBV_DIRECT UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm - UML_SETc(block, IF_V, IREG(0)); // setc i0, V - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T + UML_SETc(block, COND_V, I0); // setc i0, V + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T #else save_fast_iregs(sh2, block); - UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); + UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); UML_CALLC(block, cfunc_SUBV, sh2); load_fast_iregs(sh2, block); #endif return TRUE; case 14: // ADDC(Rm, Rn); - UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry = T (T is bit 0 of SR) + UML_CARRY(block, mem(&sh2->sr), 0); // carry = T (T is bit 0 of SR) UML_ADDC(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm - UML_SETc(block, IF_C, IREG(0)); // setc i0, C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T + UML_SETc(block, COND_C, I0); // setc i0, C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T return TRUE; case 15: // ADDV(Rm, Rn); #if ADDSUBV_DIRECT UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm - UML_SETc(block, IF_V, IREG(0)); // setc i0, V - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T + UML_SETc(block, COND_V, I0); // setc i0, V + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T #else save_fast_iregs(sh2, block); - UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); + UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); UML_CALLC(block, cfunc_ADDV, sh2); load_fast_iregs(sh2, block); #endif @@ -2350,118 +2350,118 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state switch (opcode & 0x3F) { case 0x00: // SHLL(Rn); - UML_SHL(block, R32(Rn), R32(Rn), IMM(1)); // shl Rn, Rn, 1 - UML_SETc(block, IF_C, IREG(0)); // set i0,C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T + UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1 + UML_SETc(block, COND_C, I0); // set i0,C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T return TRUE; case 0x01: // SHLR(Rn); - UML_SHR(block, R32(Rn), R32(Rn), IMM(1)); // shr Rn, Rn, 1 - UML_SETc(block, IF_C, IREG(0)); // set i0,C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T + UML_SHR(block, R32(Rn), R32(Rn), 1); // shr Rn, Rn, 1 + UML_SETc(block, COND_C, I0); // set i0,C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T return TRUE; case 0x04: // ROTL(Rn); - UML_ROL(block, R32(Rn), R32(Rn), IMM(1)); // rol Rn, Rn, 1 - UML_SETc(block, IF_C, IREG(0)); // set i0,C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T + UML_ROL(block, R32(Rn), R32(Rn), 1); // rol Rn, Rn, 1 + UML_SETc(block, COND_C, I0); // set i0,C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T return TRUE; case 0x05: // ROTR(Rn); - UML_ROR(block, R32(Rn), R32(Rn), IMM(1)); // ror Rn, Rn, 1 - UML_SETc(block, IF_C, IREG(0)); // set i0,C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T + UML_ROR(block, R32(Rn), R32(Rn), 1); // ror Rn, Rn, 1 + UML_SETc(block, COND_C, I0); // set i0,C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins [sr],i0,0,T return TRUE; case 0x02: // STSMMACH(Rn); - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_MOV(block, IREG(1), MEM(&sh2->mach)); // mov r1, mach + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, mem(&sh2->mach)); // mov r1, mach SETEA(0); // set ea for debug UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x03: // STCMSR(Rn); - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_MOV(block, IREG(1), MEM(&sh2->sr)); // mov r1, sr + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, mem(&sh2->sr)); // mov r1, sr SETEA(0); // set ea for debug UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x06: // LDSMMACH(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read32); // call read32 - UML_ADD(block, R32(Rn), R32(Rn), IMM(4)); // add Rn, #4 - UML_MOV(block, MEM(&sh2->mach), IREG(0)); // mov mach, r0 + UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4 + UML_MOV(block, mem(&sh2->mach), I0); // mov mach, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x07: // LDCMSR(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read32); // call read32 - UML_ADD(block, R32(Rn), R32(Rn), IMM(4)); // add Rn, #4 - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sr, r0 + UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4 + UML_MOV(block, mem(&sh2->sr), I0); // mov sr, r0 compiler->checkints = TRUE; if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x08: // SHLL2(Rn); - UML_SHL(block, R32(Rn), R32(Rn), IMM(2)); + UML_SHL(block, R32(Rn), R32(Rn), 2); return TRUE; case 0x09: // SHLR2(Rn); - UML_SHR(block, R32(Rn), R32(Rn), IMM(2)); + UML_SHR(block, R32(Rn), R32(Rn), 2); return TRUE; case 0x18: // SHLL8(Rn); - UML_SHL(block, R32(Rn), R32(Rn), IMM(8)); + UML_SHL(block, R32(Rn), R32(Rn), 8); return TRUE; case 0x19: // SHLR8(Rn); - UML_SHR(block, R32(Rn), R32(Rn), IMM(8)); + UML_SHR(block, R32(Rn), R32(Rn), 8); return TRUE; case 0x28: // SHLL16(Rn); - UML_SHL(block, R32(Rn), R32(Rn), IMM(16)); + UML_SHL(block, R32(Rn), R32(Rn), 16); return TRUE; case 0x29: // SHLR16(Rn); - UML_SHR(block, R32(Rn), R32(Rn), IMM(16)); + UML_SHR(block, R32(Rn), R32(Rn), 16); return TRUE; case 0x0a: // LDSMACH(Rn); - UML_MOV(block, MEM(&sh2->mach), R32(Rn)); // mov mach, Rn + UML_MOV(block, mem(&sh2->mach), R32(Rn)); // mov mach, Rn return TRUE; case 0x0b: // JSR(Rn); - UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn + UML_MOV(block, mem(&sh2->target), R32(Rn)); // mov target, Rn - UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot) + UML_ADD(block, mem(&sh2->pr), desc->pc, 4); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot) generate_delay_slot(sh2, block, compiler, desc, sh2->target-4); - generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&sh2->target), *sh2->nocode); // and do the jump + generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // and do the jump return TRUE; case 0x0e: // LDCSR(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_AND(block, IREG(0), IREG(0), IMM(FLAGS)); // and r0, r0, FLAGS - UML_MOV(block, MEM(&sh2->sr), IREG(0)); + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_AND(block, I0, I0, FLAGS); // and r0, r0, FLAGS + UML_MOV(block, mem(&sh2->sr), I0); compiler->checkints = TRUE; return TRUE; @@ -2471,7 +2471,7 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state case 0x2f: // MAC_W(Rm, Rn); case 0x3f: // MAC_W(Rm, Rn); save_fast_iregs(sh2, block); - UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); + UML_MOV(block, mem(&sh2->arg0), desc->opptr.w[0]); UML_CALLC(block, cfunc_MAC_W, sh2); load_fast_iregs(sh2, block); return TRUE; @@ -2479,207 +2479,207 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state case 0x10: // DT(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) - UML_SUB(block, R32(Rn), R32(Rn), IMM(1)); // sub Rn, Rn, 1 - UML_JMPc(block, IF_NZ, compiler->labelnum); // jz compiler->labelnum + UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit) + UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1 + UML_JMPc(block, COND_NZ, compiler->labelnum); // jz compiler->labelnum - UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T + UML_OR(block, I0, I0, T); // or r0, r0, T UML_LABEL(block, compiler->labelnum++); // desc->pc: - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 + UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0 return TRUE; } break; case 0x11: // CMPPZ(Rn); - UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) + UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit) - UML_CMP(block, R32(Rn), IMM(0)); // cmp Rn, 0 - UML_JMPc(block, IF_S, compiler->labelnum); // js compiler->labelnum (if negative) + UML_CMP(block, R32(Rn), 0); // cmp Rn, 0 + UML_JMPc(block, COND_S, compiler->labelnum); // js compiler->labelnum (if negative) - UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T + UML_OR(block, I0, I0, T); // or r0, r0, T UML_LABEL(block, compiler->labelnum++); // desc->pc: - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 + UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0 return TRUE; case 0x15: // CMPPL(Rn); - UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) + UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit) - UML_CMP(block, R32(Rn), IMM(0)); // cmp Rn, 0 + UML_CMP(block, R32(Rn), 0); // cmp Rn, 0 - UML_JMPc(block, IF_S, compiler->labelnum); // js compiler->labelnum (if negative) - UML_JMPc(block, IF_Z, compiler->labelnum); // jz compiler->labelnum (if zero) + UML_JMPc(block, COND_S, compiler->labelnum); // js compiler->labelnum (if negative) + UML_JMPc(block, COND_Z, compiler->labelnum); // jz compiler->labelnum (if zero) - UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T + UML_OR(block, I0, I0, T); // or r0, r0, T UML_LABEL(block, compiler->labelnum++); // desc->pc: - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 + UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0 return TRUE; case 0x12: // STSMMACL(Rn); - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_MOV(block, IREG(1), MEM(&sh2->macl)); // mov r1, macl + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, mem(&sh2->macl)); // mov r1, macl SETEA(0); // set ea for debug UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x13: // STCMGBR(Rn); - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn - UML_MOV(block, IREG(1), MEM(&sh2->gbr)); // mov r1, gbr + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn + UML_MOV(block, I1, mem(&sh2->gbr)); // mov r1, gbr SETEA(0); // set ea for debug UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x16: // LDSMMACL(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read32); // call read32 - UML_ADD(block, R32(Rn), R32(Rn), IMM(4)); // add Rn, #4 - UML_MOV(block, MEM(&sh2->macl), IREG(0)); // mov macl, r0 + UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4 + UML_MOV(block, mem(&sh2->macl), I0); // mov macl, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x17: // LDCMGBR(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read32); // call read32 - UML_ADD(block, R32(Rn), R32(Rn), IMM(4)); // add Rn, #4 - UML_MOV(block, MEM(&sh2->gbr), IREG(0)); // mov gbr, r0 + UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4 + UML_MOV(block, mem(&sh2->gbr), I0); // mov gbr, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x1a: // LDSMACL(Rn); - UML_MOV(block, MEM(&sh2->macl), R32(Rn)); // mov macl, Rn + UML_MOV(block, mem(&sh2->macl), R32(Rn)); // mov macl, Rn return TRUE; case 0x1b: // TAS(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read8); // call read8 - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T - UML_CMP(block, IREG(0), IMM(0)); // cmp r0, #0 - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz labelnum + UML_CMP(block, I0, 0); // cmp r0, #0 + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz labelnum - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T UML_LABEL(block, compiler->labelnum++); // labelnum: - UML_OR(block, IREG(1), IREG(0), IMM(0x80)); // or r1, r0, #0x80 + UML_OR(block, I1, I0, 0x80); // or r1, r0, #0x80 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn UML_CALLH(block, *sh2->write8); // write the value back if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x1e: // LDCGBR(Rn); - UML_MOV(block, MEM(&sh2->gbr), R32(Rn)); // mov gbr, Rn + UML_MOV(block, mem(&sh2->gbr), R32(Rn)); // mov gbr, Rn return TRUE; case 0x20: // SHAL(Rn); - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T - UML_SHR(block, IREG(0), R32(Rn), IMM(31)); // shr r0, Rn, 31 - UML_AND(block, IREG(0), IREG(0), IMM(T)); // and r0, r0, T - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IREG(0)); // or sr, sr, r0 - UML_SHL(block, R32(Rn), R32(Rn), IMM(1)); // shl Rn, Rn, 1 + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T + UML_SHR(block, I0, R32(Rn), 31); // shr r0, Rn, 31 + UML_AND(block, I0, I0, T); // and r0, r0, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), I0); // or sr, sr, r0 + UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1 return TRUE; case 0x21: // SHAR(Rn); - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T - UML_AND(block, IREG(0), R32(Rn), IMM(T)); // and r0, Rn, T - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IREG(0)); // or sr, sr, r0 - UML_SAR(block, R32(Rn), R32(Rn), IMM(1)); // sar Rn, Rn, 1 + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T + UML_AND(block, I0, R32(Rn), T); // and r0, Rn, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), I0); // or sr, sr, r0 + UML_SAR(block, R32(Rn), R32(Rn), 1); // sar Rn, Rn, 1 return TRUE; case 0x22: // STSMPR(Rn); - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); - UML_MOV(block, IREG(1), MEM(&sh2->pr)); // mov r1, pr + UML_MOV(block, I1, mem(&sh2->pr)); // mov r1, pr UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x23: // STCMVBR(Rn); - UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4 + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); - UML_MOV(block, IREG(1), MEM(&sh2->vbr)); // mov r1, vbr + UML_MOV(block, I1, mem(&sh2->vbr)); // mov r1, vbr UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x24: // ROTCL(Rn); - UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry sr,0 - UML_ROLC(block, R32(Rn), R32(Rn), IMM(1)); // rolc Rn,Rn,1 - UML_SETc(block, IF_C, IREG(0)); // set i0,C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T + UML_CARRY(block, mem(&sh2->sr), 0); // carry sr,0 + UML_ROLC(block, R32(Rn), R32(Rn), 1); // rolc Rn,Rn,1 + UML_SETc(block, COND_C, I0); // set i0,C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T return TRUE; case 0x25: // ROTCR(Rn); - UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry sr,0 - UML_RORC(block, R32(Rn), R32(Rn), IMM(1)); // rorc Rn,Rn,1 - UML_SETc(block, IF_C, IREG(0)); // set i0,C - UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T + UML_CARRY(block, mem(&sh2->sr), 0); // carry sr,0 + UML_RORC(block, R32(Rn), R32(Rn), 1); // rorc Rn,Rn,1 + UML_SETc(block, COND_C, I0); // set i0,C + UML_ROLINS(block, mem(&sh2->sr), I0, 0, T); // rolins sr,i0,0,T return TRUE; case 0x26: // LDSMPR(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, MEM(&sh2->pr), IREG(0)); // mov sh2->pr, r0 - UML_ADD(block, R32(Rn), R32(Rn), IMM(4)); // add Rn, Rn, #4 + UML_MOV(block, mem(&sh2->pr), I0); // mov sh2->pr, r0 + UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x27: // LDCMVBR(Rn); - UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn + UML_MOV(block, I0, R32(Rn)); // mov r0, Rn SETEA(0); UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, MEM(&sh2->vbr), IREG(0)); // mov sh2->vbr, r0 - UML_ADD(block, R32(Rn), R32(Rn), IMM(4)); // add Rn, Rn, #4 + UML_MOV(block, mem(&sh2->vbr), I0); // mov sh2->vbr, r0 + UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 0x2a: // LDSPR(Rn); - UML_MOV(block, MEM(&sh2->pr), R32(Rn)); // mov sh2->pr, Rn + UML_MOV(block, mem(&sh2->pr), R32(Rn)); // mov sh2->pr, Rn return TRUE; case 0x2b: // JMP(Rn); - UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn + UML_MOV(block, mem(&sh2->target), R32(Rn)); // mov target, Rn generate_delay_slot(sh2, block, compiler, desc, sh2->target); - generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), MEM(&sh2->target), *sh2->nocode); // jmp (target) + generate_update_cycles(sh2, block, compiler, mem(&sh2->target), TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, mem(&sh2->target), *sh2->nocode); // jmp (target) return TRUE; case 0x2e: // LDCVBR(Rn); - UML_MOV(block, MEM(&sh2->vbr), R32(Rn)); // mov vbr, Rn + UML_MOV(block, mem(&sh2->vbr), R32(Rn)); // mov vbr, Rn return TRUE; case 0x0c: // NOP(); @@ -2715,33 +2715,33 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state switch (opcode & 15) { case 0: // MOVBL(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm + UML_MOV(block, I0, R32(Rm)); // mov r0, Rm SETEA(0); // debug: ea = r0 UML_CALLH(block, *sh2->read8); // call read8 - UML_SEXT(block, R32(Rn), IREG(0), SIZE_BYTE); // sext Rn, r0, BYTE + UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 1: // MOVWL(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm + UML_MOV(block, I0, R32(Rm)); // mov r0, Rm SETEA(0); // debug: ea = r0 UML_CALLH(block, *sh2->read16); // call read16 - UML_SEXT(block, R32(Rn), IREG(0), SIZE_WORD); // sext Rn, r0, WORD + UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 2: // MOVLL(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm + UML_MOV(block, I0, R32(Rm)); // mov r0, Rm SETEA(0); // debug: ea = r0 UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, R32(Rn), IREG(0)); // mov Rn, r0 + UML_MOV(block, R32(Rn), I0); // mov Rn, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 3: // MOV(Rm, Rn); @@ -2749,23 +2749,23 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state return TRUE; case 7: // NOT(Rm, Rn); - UML_XOR(block, R32(Rn), R32(Rm), IMM(0xffffffff)); // xor Rn, Rm, 0xffffffff + UML_XOR(block, R32(Rn), R32(Rm), 0xffffffff); // xor Rn, Rm, 0xffffffff return TRUE; case 9: // SWAPW(Rm, Rn); - UML_ROL(block, R32(Rn), R32(Rm), IMM(16)); // rol Rn, Rm, 16 + UML_ROL(block, R32(Rn), R32(Rm), 16); // rol Rn, Rm, 16 return TRUE; case 11: // NEG(Rm, Rn); - UML_SUB(block, R32(Rn), IMM(0), R32(Rm)); // sub Rn, 0, Rm + UML_SUB(block, R32(Rn), 0, R32(Rm)); // sub Rn, 0, Rm return TRUE; case 12: // EXTUB(Rm, Rn); - UML_AND(block, R32(Rn), R32(Rm), IMM(0x000000ff)); // and Rn, Rm, 0xff + UML_AND(block, R32(Rn), R32(Rm), 0x000000ff); // and Rn, Rm, 0xff return TRUE; case 13: // EXTUW(Rm, Rn); - UML_AND(block, R32(Rn), R32(Rm), IMM(0x0000ffff)); // and Rn, Rm, 0xffff + UML_AND(block, R32(Rn), R32(Rm), 0x0000ffff); // and Rn, Rm, 0xffff return TRUE; case 14: // EXTSB(Rm, Rn); @@ -2777,60 +2777,60 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state return TRUE; case 4: // MOVBP(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm + UML_MOV(block, I0, R32(Rm)); // mov r0, Rm UML_CALLH(block, *sh2->read8); // call read8 - UML_SEXT(block, R32(Rn), IREG(0), SIZE_BYTE); // sext Rn, r0, BYTE + UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE if (Rm != Rn) - UML_ADD(block, R32(Rm), R32(Rm), IMM(1)); // add Rm, Rm, #1 + UML_ADD(block, R32(Rm), R32(Rm), 1); // add Rm, Rm, #1 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 5: // MOVWP(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm + UML_MOV(block, I0, R32(Rm)); // mov r0, Rm UML_CALLH(block, *sh2->read16); // call read16 - UML_SEXT(block, R32(Rn), IREG(0), SIZE_WORD); // sext Rn, r0, WORD + UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD if (Rm != Rn) - UML_ADD(block, R32(Rm), R32(Rm), IMM(2)); // add Rm, Rm, #2 + UML_ADD(block, R32(Rm), R32(Rm), 2); // add Rm, Rm, #2 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 6: // MOVLP(Rm, Rn); - UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm + UML_MOV(block, I0, R32(Rm)); // mov r0, Rm UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, R32(Rn), IREG(0)); // mov Rn, r0 + UML_MOV(block, R32(Rn), I0); // mov Rn, r0 if (Rm != Rn) - UML_ADD(block, R32(Rm), R32(Rm), IMM(4)); // add Rm, Rm, #4 + UML_ADD(block, R32(Rm), R32(Rm), 4); // add Rm, Rm, #4 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 8: // SWAPB(Rm, Rn); - UML_AND(block, IREG(0), R32(Rm), IMM(0xffff0000)); // and r0, Rm, #0xffff0000 - UML_AND(block, IREG(1), R32(Rm), IMM(0x000000ff)); // and r0, Rm, #0x000000ff - UML_AND(block, IREG(2), R32(Rm), IMM(0x0000ff00)); // and r0, Rm, #0x0000ff00 - UML_SHL(block, IREG(1), IREG(1), IMM(8)); // shl r1, r1, #8 - UML_SHR(block, IREG(2), IREG(2), IMM(8)); // shr r2, r2, #8 - UML_OR(block, IREG(0), IREG(0), IREG(1)); // or r0, r0, r1 - UML_OR(block, R32(Rn), IREG(0), IREG(2)); // or Rn, r0, r2 + UML_AND(block, I0, R32(Rm), 0xffff0000); // and r0, Rm, #0xffff0000 + UML_AND(block, I1, R32(Rm), 0x000000ff); // and r0, Rm, #0x000000ff + UML_AND(block, I2, R32(Rm), 0x0000ff00); // and r0, Rm, #0x0000ff00 + UML_SHL(block, I1, I1, 8); // shl r1, r1, #8 + UML_SHR(block, I2, I2, 8); // shr r2, r2, #8 + UML_OR(block, I0, I0, I1); // or r0, r0, r1 + UML_OR(block, R32(Rn), I0, I2); // or Rn, r0, r2 return TRUE; case 10: // NEGC(Rm, Rn); - UML_MOV(block, IREG(0), MEM(&sh2->sr)); // mov r0, sr (save SR) - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit) - UML_CARRY(block, IREG(0), IMM(0)); // carry = T (T is bit 0 of SR) - UML_SUBB(block, R32(Rn), IMM(0), R32(Rm)); // subb Rn, #0, Rm + UML_MOV(block, I0, mem(&sh2->sr)); // mov r0, sr (save SR) + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit) + UML_CARRY(block, I0, 0); // carry = T (T is bit 0 of SR) + UML_SUBB(block, R32(Rn), 0, R32(Rm)); // subb Rn, #0, Rm - UML_JMPc(block, IF_NC, compiler->labelnum); // jnc labelnum + UML_JMPc(block, COND_NC, compiler->labelnum); // jnc labelnum - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T UML_LABEL(block, compiler->labelnum++); // labelnum: @@ -2850,22 +2850,22 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state { case 0 << 8: // MOVBS4(opcode & 0x0f, Rm); udisp = (opcode & 0x0f); - UML_ADD(block, IREG(0), R32(Rm), IMM(udisp)); // add r0, Rm, udisp - UML_MOV(block, IREG(1), R32(0)); // mov r1, R0 + UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp + UML_MOV(block, I1, R32(0)); // mov r1, R0 UML_CALLH(block, *sh2->write8); // call write8 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 1 << 8: // MOVWS4(opcode & 0x0f, Rm); udisp = (opcode & 0x0f) * 2; - UML_ADD(block, IREG(0), R32(Rm), IMM(udisp)); // add r0, Rm, udisp - UML_MOV(block, IREG(1), R32(0)); // mov r1, R0 + UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp + UML_MOV(block, I1, R32(0)); // mov r1, R0 UML_CALLH(block, *sh2->write16); // call write16 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 2<< 8: // NOP(); @@ -2879,61 +2879,61 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state case 4<< 8: // MOVBL4(Rm, opcode & 0x0f); udisp = opcode & 0x0f; - UML_ADD(block, IREG(0), R32(Rm), IMM(udisp)); // add r0, Rm, udisp + UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp SETEA(0); UML_CALLH(block, *sh2->read8); // call read8 - UML_SEXT(block, R32(0), IREG(0), SIZE_BYTE); // sext R0, r0, BYTE + UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 5<< 8: // MOVWL4(Rm, opcode & 0x0f); udisp = (opcode & 0x0f)*2; - UML_ADD(block, IREG(0), R32(Rm), IMM(udisp)); // add r0, Rm, udisp + UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp SETEA(0); UML_CALLH(block, *sh2->read16); // call read16 - UML_SEXT(block, R32(0), IREG(0), SIZE_WORD); // sext R0, r0, WORD + UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 8<< 8: // CMPIM(opcode & 0xff); - UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) + UML_AND(block, I0, mem(&sh2->sr), ~T); // and r0, sr, ~T (clear the T bit) - UML_SEXT(block, IREG(1), IMM(opcode&0xff), SIZE_BYTE); // sext r1, opcode&0xff, BYTE - UML_CMP(block, IREG(1), R32(0)); // cmp r1, R0 - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum (if negative) + UML_SEXT(block, I1, opcode&0xff, SIZE_BYTE); // sext r1, opcode&0xff, BYTE + UML_CMP(block, I1, R32(0)); // cmp r1, R0 + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum (if negative) - UML_OR(block, IREG(0), IREG(0), IMM(T)); // or r0, r0, T + UML_OR(block, I0, I0, T); // or r0, r0, T UML_LABEL(block, compiler->labelnum++); // labelnum: - UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 + UML_MOV(block, mem(&sh2->sr), I0); // mov sh2->sr, r0 return TRUE; case 9<< 8: // BT(opcode & 0xff); - UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T - UML_JMPc(block, IF_Z, compiler->labelnum); // jz compiler->labelnum + UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T + UML_JMPc(block, COND_Z, compiler->labelnum); // jz compiler->labelnum disp = ((INT32)opcode << 24) >> 24; sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination - generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), IMM(sh2->ea), *sh2->nocode); // jmp sh2->ea + generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; case 11<< 8: // BF(opcode & 0xff); - UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum + UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum disp = ((INT32)opcode << 24) >> 24; sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination - generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), IMM(sh2->ea), *sh2->nocode); // jmp sh2->ea + generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; @@ -2941,8 +2941,8 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state case 13<< 8: // BTS(opcode & 0xff); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T - UML_JMPc(block, IF_Z, compiler->labelnum); // jz compiler->labelnum + UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T + UML_JMPc(block, COND_Z, compiler->labelnum); // jz compiler->labelnum disp = ((INT32)opcode << 24) >> 24; sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination @@ -2951,8 +2951,8 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state compiler->labelnum++; // make sure the delay slot doesn't use it generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2); - generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), IMM(sh2->ea), *sh2->nocode); // jmp sh2->ea + generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea UML_LABEL(block, templabel); // labelnum: return TRUE; @@ -2962,8 +2962,8 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state case 15<< 8: // BFS(opcode & 0xff); if (sh2->cpu_type > CPU_TYPE_SH1) { - UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum + UML_TEST(block, mem(&sh2->sr), T); // test sh2->sr, T + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz compiler->labelnum disp = ((INT32)opcode << 24) >> 24; sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination @@ -2972,8 +2972,8 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state compiler->labelnum++; // make sure the delay slot doesn't use it generate_delay_slot(sh2, block, compiler, desc, sh2->ea-2); // delay slot only if the branch is taken - generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> - UML_HASHJMP(block, IMM(0), IMM(sh2->ea), *sh2->nocode); // jmp sh2->ea + generate_update_cycles(sh2, block, compiler, sh2->ea, TRUE); // <subtract cycles> + UML_HASHJMP(block, 0, sh2->ea, *sh2->nocode); // jmp sh2->ea UML_LABEL(block, templabel); // labelnum: return TRUE; @@ -2992,156 +2992,156 @@ static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state { case 0<<8: // MOVBSG(opcode & 0xff); scratch = (opcode & 0xff); - UML_ADD(block, IREG(0), MEM(&sh2->gbr), IMM(scratch)); // add r0, gbr, scratch - UML_AND(block, IREG(1), R32(0), IMM(0xff)); // and r1, R0, 0xff + UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch + UML_AND(block, I1, R32(0), 0xff); // and r1, R0, 0xff UML_CALLH(block, *sh2->write8); // call write8 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 1<<8: // MOVWSG(opcode & 0xff); scratch = (opcode & 0xff) * 2; - UML_ADD(block, IREG(0), MEM(&sh2->gbr), IMM(scratch)); // add r0, gbr, scratch - UML_AND(block, IREG(1), R32(0), IMM(0xffff)); // and r1, R0, 0xffff + UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch + UML_AND(block, I1, R32(0), 0xffff); // and r1, R0, 0xffff UML_CALLH(block, *sh2->write16); // call write16 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 2<<8: // MOVLSG(opcode & 0xff); scratch = (opcode & 0xff) * 4; - UML_ADD(block, IREG(0), MEM(&sh2->gbr), IMM(scratch)); // add r0, gbr, scratch - UML_MOV(block, IREG(1), R32(0)); // mov r1, R0 + UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch + UML_MOV(block, I1, R32(0)); // mov r1, R0 UML_CALLH(block, *sh2->write32); // call write32 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 3<<8: // TRAPA(opcode & 0xff); scratch = (opcode & 0xff) * 4; - UML_ADD(block, MEM(&sh2->ea), MEM(&sh2->vbr), IMM(scratch)); // add ea, vbr, scratch + UML_ADD(block, mem(&sh2->ea), mem(&sh2->vbr), scratch); // add ea, vbr, scratch - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), MEM(&sh2->sr)); // mov r1, sr + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, mem(&sh2->sr)); // mov r1, sr UML_CALLH(block, *sh2->write32); // write32 - UML_SUB(block, R32(15), R32(15), IMM(4)); // sub R15, R15, #4 - UML_MOV(block, IREG(0), R32(15)); // mov r0, R15 - UML_MOV(block, IREG(1), IMM(desc->pc+2)); // mov r1, pc+2 + UML_SUB(block, R32(15), R32(15), 4); // sub R15, R15, #4 + UML_MOV(block, I0, R32(15)); // mov r0, R15 + UML_MOV(block, I1, desc->pc+2); // mov r1, pc+2 UML_CALLH(block, *sh2->write32); // write32 - UML_MOV(block, IREG(0), MEM(&sh2->ea)); // mov r0, ea + UML_MOV(block, I0, mem(&sh2->ea)); // mov r0, ea UML_CALLH(block, *sh2->read32); // read32 - UML_HASHJMP(block, IMM(0), IREG(0), *sh2->nocode); // jmp (r0) + UML_HASHJMP(block, 0, I0, *sh2->nocode); // jmp (r0) return TRUE; case 4<<8: // MOVBLG(opcode & 0xff); scratch = (opcode & 0xff); - UML_ADD(block, IREG(0), MEM(&sh2->gbr), IMM(scratch)); // add r0, gbr, scratch + UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch UML_CALLH(block, *sh2->read8); // call read16 - UML_SEXT(block, R32(0), IREG(0), SIZE_BYTE); // sext R0, r0, BYTE + UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 5<<8: // MOVWLG(opcode & 0xff); scratch = (opcode & 0xff) * 2; - UML_ADD(block, IREG(0), MEM(&sh2->gbr), IMM(scratch)); // add r0, gbr, scratch + UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch UML_CALLH(block, *sh2->read16); // call read16 - UML_SEXT(block, R32(0), IREG(0), SIZE_WORD); // sext R0, r0, WORD + UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 6<<8: // MOVLLG(opcode & 0xff); scratch = (opcode & 0xff) * 4; - UML_ADD(block, IREG(0), MEM(&sh2->gbr), IMM(scratch)); // add r0, gbr, scratch + UML_ADD(block, I0, mem(&sh2->gbr), scratch); // add r0, gbr, scratch UML_CALLH(block, *sh2->read32); // call read32 - UML_MOV(block, R32(0), IREG(0)); // mov R0, r0 + UML_MOV(block, R32(0), I0); // mov R0, r0 if (!in_delay_slot) - generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); + generate_update_cycles(sh2, block, compiler, desc->pc + 2, TRUE); return TRUE; case 7<<8: // MOVA(opcode & 0xff); scratch = (opcode & 0xff) * 4; scratch += ((desc->pc + 4) & ~3); - UML_MOV(block, R32(0), IMM(scratch)); // mov R0, scratch + UML_MOV(block, R32(0), scratch); // mov R0, scratch return TRUE; case 8<<8: // TSTI(opcode & 0xff); scratch = opcode & 0xff; - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit) - UML_AND(block, IREG(0), R32(0), IMM(scratch)); // and r0, R0, scratch - UML_CMP(block, IREG(0), IMM(0)); // cmp r0, #0 - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz labelnum + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit) + UML_AND(block, I0, R32(0), scratch); // and r0, R0, scratch + UML_CMP(block, I0, 0); // cmp r0, #0 + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz labelnum - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; case 9<<8: // ANDI(opcode & 0xff); - UML_AND(block, R32(0), R32(0), IMM(opcode & 0xff)); // and r0, r0, opcode & 0xff + UML_AND(block, R32(0), R32(0), opcode & 0xff); // and r0, r0, opcode & 0xff return TRUE; case 10<<8: // XORI(opcode & 0xff); - UML_XOR(block, R32(0), R32(0), IMM(opcode & 0xff)); // xor r0, r0, opcode & 0xff + UML_XOR(block, R32(0), R32(0), opcode & 0xff); // xor r0, r0, opcode & 0xff return TRUE; case 11<<8: // ORI(opcode & 0xff); - UML_OR(block, R32(0), R32(0), IMM(opcode & 0xff)); // or r0, r0, opcode & 0xff + UML_OR(block, R32(0), R32(0), opcode & 0xff); // or r0, r0, opcode & 0xff return TRUE; case 12<<8: // TSTM(opcode & 0xff); - UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit) - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_AND(block, mem(&sh2->sr), mem(&sh2->sr), ~T); // and sr, sr, ~T (clear the T bit) + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr UML_CALLH(block, *sh2->read8); // read8 - UML_AND(block, IREG(0), IREG(0), IMM(opcode & 0xff)); - UML_CMP(block, IREG(0), IMM(0)); // cmp r0, #0 - UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz labelnum + UML_AND(block, I0, I0, opcode & 0xff); + UML_CMP(block, I0, 0); // cmp r0, #0 + UML_JMPc(block, COND_NZ, compiler->labelnum); // jnz labelnum - UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T + UML_OR(block, mem(&sh2->sr), mem(&sh2->sr), T); // or sr, sr, T UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; case 13<<8: // ANDM(opcode & 0xff); - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr UML_CALLH(block, *sh2->read8); // read8 - UML_AND(block, IREG(1), IREG(0), IMM(opcode&0xff)); // and r1, r0, #opcode&0xff - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_AND(block, I1, I0, opcode&0xff); // and r1, r0, #opcode&0xff + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr SETEA(0); UML_CALLH(block, *sh2->write8); // write8 return TRUE; case 14<<8: // XORM(opcode & 0xff); - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr UML_CALLH(block, *sh2->read8); // read8 - UML_XOR(block, IREG(1), IREG(0), IMM(opcode&0xff)); // xor r1, r0, #opcode&0xff - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_XOR(block, I1, I0, opcode&0xff); // xor r1, r0, #opcode&0xff + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr SETEA(0); UML_CALLH(block, *sh2->write8); // write8 return TRUE; case 15<<8: // ORM(opcode & 0xff); - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr UML_CALLH(block, *sh2->read8); // read8 - UML_OR(block, IREG(1), IREG(0), IMM(opcode&0xff)); // or r1, r0, #opcode&0xff - UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr + UML_OR(block, I1, I0, opcode&0xff); // or r1, r0, #opcode&0xff + UML_ADD(block, I0, R32(0), mem(&sh2->gbr)); // add r0, R0, gbr SETEA(0); UML_CALLH(block, *sh2->write8); // write8 return TRUE; diff --git a/src/emu/cpu/uml.h b/src/emu/cpu/uml.h index cda2b85ab1d..25e7e6de1d2 100644 --- a/src/emu/cpu/uml.h +++ b/src/emu/cpu/uml.h @@ -637,6 +637,9 @@ namespace uml inline parameter vreg(int n) { return parameter::make_vreg(REG_V0 + n); } inline parameter mapvar(int n) { return parameter::make_mapvar(MAPVAR_M0 + n); } + // global inline functions to define memory parameters + inline parameter mem(const void *ptr) { return parameter::make_memory(ptr); } + // global register objects for direct access const parameter I0(parameter::make_ireg(REG_I0 + 0)); const parameter I1(parameter::make_ireg(REG_I0 + 1)); |