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-rw-r--r--src/emu/cpu/melps4/m58846.c29
-rw-r--r--src/emu/cpu/melps4/melps4.c18
-rw-r--r--src/emu/cpu/melps4/melps4.h10
-rw-r--r--src/emu/cpu/melps4/melps4op.inc17
4 files changed, 51 insertions, 23 deletions
diff --git a/src/emu/cpu/melps4/m58846.c b/src/emu/cpu/melps4/m58846.c
index 17161da2fb5..2fb0d2107f8 100644
--- a/src/emu/cpu/melps4/m58846.c
+++ b/src/emu/cpu/melps4/m58846.c
@@ -62,8 +62,6 @@ void m58846_device::device_start()
void m58846_device::device_reset()
{
melps4_cpu_device::device_reset();
-
- // timer 1 runs continuously
reset_timer();
}
@@ -75,8 +73,7 @@ void m58846_device::device_reset()
void m58846_device::reset_timer()
{
- // reset 7-bit prescaler
- attotime base = attotime::from_ticks(6 * 128, unscaled_clock());
+ attotime base = attotime::from_ticks(6, unscaled_clock());
m_timer->adjust(base);
}
@@ -85,9 +82,25 @@ void m58846_device::device_timer(emu_timer &timer, device_timer_id id, int param
if (id != 0)
return;
- // timer 1 overflow
- m_irqflag[1] = true;
- m_possible_irq = true;
+ // timer 1: 7-bit fixed counter (manual specifically says 127)
+ if (++m_tmr_count[0] == 127)
+ {
+ m_tmr_count[0] = 0;
+ m_irqflag[1] = true;
+ m_possible_irq = true;
+ }
+
+ // timer 2: 8-bit user defined counter with auto-reload
+ if (m_v & 8 && ++m_tmr_count[1] == 0)
+ {
+ m_tmr_count[1] = m_tmr_reload;
+ m_irqflag[2] = true;
+ m_possible_irq = true;
+ m_port_t ^= 1;
+ m_write_t(m_port_t);
+ }
+
+ // schedule next timeout
reset_timer();
}
@@ -96,7 +109,7 @@ void m58846_device::write_v(UINT8 data)
// d0: enable timer 1 irq
// d1: enable timer 2 irq? (TODO)
// d2: ?
- // d3: timer 2 enable?
+ // d3: timer 2 enable
m_tmr_irq_enabled[0] = (data & 1) ? true : false;
m_possible_irq = true;
diff --git a/src/emu/cpu/melps4/melps4.c b/src/emu/cpu/melps4/melps4.c
index e6291a485da..1e9b51be0a9 100644
--- a/src/emu/cpu/melps4/melps4.c
+++ b/src/emu/cpu/melps4/melps4.c
@@ -106,6 +106,7 @@ void melps4_cpu_device::device_start()
m_port_d = 0;
m_port_s = 0;
m_port_f = 0;
+ m_port_t = 0;
m_sm = m_sms = false;
m_ba_flag = false;
@@ -115,12 +116,15 @@ void melps4_cpu_device::device_start()
m_inte = 0;
m_intp = 1;
m_irqflag[0] = m_irqflag[1] = m_irqflag[2] = false;
- m_tmr_irq_enabled[0] = m_tmr_irq_enabled[1] = false;
m_int_state = 0;
- m_t_state = 0;
+ m_t_in_state = 0;
m_prohibit_irq = false;
m_possible_irq = false;
+ memset(m_tmr_count, 0, sizeof(m_tmr_count));
+ m_tmr_reload = 0;
+ m_tmr_irq_enabled[0] = m_tmr_irq_enabled[1] = false;
+
m_a = 0;
m_b = 0;
m_e = 0;
@@ -146,6 +150,7 @@ void melps4_cpu_device::device_start()
save_item(NAME(m_port_d));
save_item(NAME(m_port_s));
save_item(NAME(m_port_f));
+ save_item(NAME(m_port_t));
save_item(NAME(m_sm));
save_item(NAME(m_sms));
@@ -156,12 +161,15 @@ void melps4_cpu_device::device_start()
save_item(NAME(m_inte));
save_item(NAME(m_intp));
save_item(NAME(m_irqflag));
- save_item(NAME(m_tmr_irq_enabled));
save_item(NAME(m_int_state));
- save_item(NAME(m_t_state));
+ save_item(NAME(m_t_in_state));
save_item(NAME(m_prohibit_irq));
save_item(NAME(m_possible_irq));
+ save_item(NAME(m_tmr_count));
+ save_item(NAME(m_tmr_reload));
+ save_item(NAME(m_tmr_irq_enabled));
+
save_item(NAME(m_a));
save_item(NAME(m_b));
save_item(NAME(m_e));
@@ -227,7 +235,7 @@ void melps4_cpu_device::device_reset()
write_gen_port(MELPS4_PORTF, 0);
write_gen_port(MELPS4_PORTG, 0);
write_gen_port(MELPS4_PORTU, 0);
- m_write_t(0);
+ m_write_t(0); m_port_t = 0;
}
diff --git a/src/emu/cpu/melps4/melps4.h b/src/emu/cpu/melps4/melps4.h
index 5a7d2327198..ac0724778f3 100644
--- a/src/emu/cpu/melps4/melps4.h
+++ b/src/emu/cpu/melps4/melps4.h
@@ -195,6 +195,7 @@ protected:
UINT16 m_port_d; // last written port data
UINT8 m_port_s; // "
UINT8 m_port_f; // "
+ UINT8 m_port_t; // "
bool m_sm, m_sms; // subroutine mode flag + irq stack
bool m_ba_flag; // temp flag indicates BA opcode was executed
@@ -204,12 +205,15 @@ protected:
UINT8 m_inte; // interrupt enable flag
int m_intp; // external interrupt polarity ('40 to '44)
bool m_irqflag[3]; // irq flags: exf, 1f, 2f (external, timer 1, timer 2)
- bool m_tmr_irq_enabled[2];
int m_int_state; // INT pin state
- int m_t_state; // T input pin state
+ int m_t_in_state; // T input pin state
bool m_prohibit_irq; // interrupt is prohibited during certain opcodes
bool m_possible_irq; // indicate that irq needs to be rechecked
+ UINT8 m_tmr_count[2]; // timer active count
+ UINT8 m_tmr_reload; // timer(2) auto reload
+ bool m_tmr_irq_enabled[2];
+
// work registers (unless specified, each is 4-bit)
UINT8 m_a; // accumulator
UINT8 m_b; // generic
@@ -238,7 +242,7 @@ protected:
devcb_write8 m_write_u;
devcb_write_line m_write_t;
- virtual void write_t_in(int state) { m_t_state = state; }
+ virtual void write_t_in(int state) { m_t_in_state = state; }
virtual void write_v(UINT8 data) { m_v = data; }
virtual void write_w(UINT8 data) { m_w = data; }
virtual void do_interrupt(int which);
diff --git a/src/emu/cpu/melps4/melps4op.inc b/src/emu/cpu/melps4/melps4op.inc
index 1ac63b0f2a2..4d57c075905 100644
--- a/src/emu/cpu/melps4/melps4op.inc
+++ b/src/emu/cpu/melps4/melps4op.inc
@@ -67,8 +67,8 @@ void melps4_cpu_device::op_teab()
void melps4_cpu_device::op_tabe()
{
// TABE(undocumented): transfer E to A and B
- m_b = m_e >> 4;
m_a = m_e & 0xf;
+ m_b = m_e >> 4;
}
void melps4_cpu_device::op_tepa()
@@ -406,37 +406,40 @@ void melps4_cpu_device::op_szj()
void melps4_cpu_device::op_t1ab()
{
// T1AB: transfer A and B to timer 1
- op_illegal();
+ m_tmr_count[0] = m_b << 4 | m_a;
}
void melps4_cpu_device::op_trab()
{
// TRAB: transfer A and B to timer 2 reload
- op_illegal();
+ m_tmr_reload = m_b << 4 | m_a;
}
void melps4_cpu_device::op_t2ab()
{
// T2AB: transfer A and B to timer 2 and timer 2 reload
- //op_illegal();
+ m_tmr_reload = m_tmr_count[1] = m_b << 4 | m_a;
}
void melps4_cpu_device::op_tab1()
{
// TAB1: transfer timer 1 to A and B
- op_illegal();
+ m_a = m_tmr_count[0] & 0xf;
+ m_b = m_tmr_count[0] >> 4;
}
void melps4_cpu_device::op_tabr()
{
// TABR: transfer timer 2 reload to A and B
- op_illegal();
+ m_a = m_tmr_reload & 0xf;
+ m_b = m_tmr_reload >> 4;
}
void melps4_cpu_device::op_tab2()
{
// TAB2: transfer timer 2 to A and B
- op_illegal();
+ m_a = m_tmr_count[1] & 0xf;
+ m_b = m_tmr_count[1] >> 4;
}
void melps4_cpu_device::op_tva()