diff options
Diffstat (limited to 'src/lib/netlist/examples/vs_cs.c')
-rw-r--r-- | src/lib/netlist/examples/vs_cs.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/lib/netlist/examples/vs_cs.c b/src/lib/netlist/examples/vs_cs.c index 9b39106a540..252eb9cad3f 100644 --- a/src/lib/netlist/examples/vs_cs.c +++ b/src/lib/netlist/examples/vs_cs.c @@ -11,20 +11,20 @@ NETLIST_START(rc) - /* - * delay circuit - * - */ + /* + * delay circuit + * + */ - /* Standard stuff */ + /* Standard stuff */ - SOLVER(Solver, 48000) - PARAM(Solver.ACCURACY, 1e-6) - CLOCK(clk, 20000) + SOLVER(Solver, 48000) + PARAM(Solver.ACCURACY, 1e-6) + CLOCK(clk, 20000) /* Voltage source. Inner resistance will make clock visible */ - RES(R1, 1000) + RES(R1, 1000) VS(VS1, 1) NET_C(R1.1, clk) NET_C(R1.2, VS1.P) @@ -34,8 +34,8 @@ NETLIST_START(rc) * need negative current */ - RES(R2, 1000) - RES(R3, 1000) + RES(R2, 1000) + RES(R3, 1000) CS(CS1, -0.001) NET_C(CS1.P, R2.1) NET_C(R2.2, R3.1) @@ -46,7 +46,7 @@ NETLIST_START(rc) NET_C(C1.2, R3.2) - LOG(tt, VS1.P) - LOG(tx, R2.2) + LOG(tt, VS1.P) + LOG(tx, R2.2) NETLIST_END() |