summaryrefslogtreecommitdiffstatshomepage
path: root/src/lib/netlist/devices/nld_82S16.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/lib/netlist/devices/nld_82S16.cpp')
-rw-r--r--src/lib/netlist/devices/nld_82S16.cpp73
1 files changed, 50 insertions, 23 deletions
diff --git a/src/lib/netlist/devices/nld_82S16.cpp b/src/lib/netlist/devices/nld_82S16.cpp
index 7441f6c677e..e3176c7b30f 100644
--- a/src/lib/netlist/devices/nld_82S16.cpp
+++ b/src/lib/netlist/devices/nld_82S16.cpp
@@ -6,7 +6,7 @@
*/
#include "nld_82S16.h"
-#include "../nl_base.h"
+#include "netlist/nl_base.h"
namespace netlist
{
@@ -15,19 +15,55 @@ namespace netlist
NETLIB_OBJECT(82S16)
{
NETLIB_CONSTRUCTOR(82S16)
- , m_A(*this, {{"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7" }})
- , m_CE1Q(*this, "CE1Q")
- , m_CE2Q(*this, "CE2Q")
- , m_CE3Q(*this, "CE3Q")
+ , m_A(*this, {{"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7" }}, NETLIB_DELEGATE(82S16, addr))
+ , m_CE1Q(*this, "CE1Q", NETLIB_DELEGATE(82S16, enq))
+ , m_CE2Q(*this, "CE2Q", NETLIB_DELEGATE(82S16, enq))
+ , m_CE3Q(*this, "CE3Q", NETLIB_DELEGATE(82S16, enq))
, m_WEQ(*this, "WEQ")
, m_DIN(*this, "DIN")
, m_DOUTQ(*this, "DOUTQ")
, m_ram(*this, "m_ram", 0)
+ , m_addr(*this, "m_addr", 0)
+ , m_enq(*this, "m_enq", 0)
{
}
NETLIB_RESETI();
NETLIB_UPDATEI();
+ NETLIB_HANDLERI(addr)
+ {
+ uint8_t adr = 0;
+ for (std::size_t i=0; i<8; i++)
+ {
+ //m_A[i].activate();
+ adr |= (m_A[i]() << i);
+ }
+ m_addr = adr;
+ NETLIB_NAME(82S16)::update();
+ }
+ NETLIB_HANDLERI(enq)
+ {
+ const auto last = m_enq;
+ m_enq = m_CE1Q() || m_CE2Q() || m_CE3Q();
+ if (!last && m_enq)
+ {
+ // FIXME: Outputs are tristate. This needs to be properly implemented
+ m_DOUTQ.push(1, NLTIME_FROM_NS(20));
+ for (std::size_t i=0; i<8; i++)
+ m_A[i].inactivate();
+ m_WEQ.inactivate();
+ m_DIN.inactivate();
+ }
+ else if (last && !m_enq)
+ {
+ for (std::size_t i=0; i<8; i++)
+ m_A[i].activate();
+ m_WEQ.activate();
+ m_DIN.activate();
+ NETLIB_NAME(82S16)::update();
+ }
+ }
+
protected:
object_array_t<logic_input_t, 8> m_A;
@@ -38,7 +74,9 @@ namespace netlist
logic_input_t m_DIN;
logic_output_t m_DOUTQ;
- state_var<uint64_t[4]> m_ram; // 256 bits
+ state_array<uint64_t, 4> m_ram; // 256 bits
+ state_var_u8 m_addr; // 256 bits
+ state_var_sig m_enq;
};
NETLIB_OBJECT_DERIVED(82S16_dip, 82S16)
@@ -69,22 +107,9 @@ namespace netlist
// FIXME: optimize device (separate address decoder!)
NETLIB_UPDATE(82S16)
{
- if (m_CE1Q() || m_CE2Q() || m_CE3Q())
+ if (!m_enq)
{
- // FIXME: Outputs are tristate. This needs to be properly implemented
- m_DOUTQ.push(1, NLTIME_FROM_NS(20));
- //for (int i=0; i<8; i++)
- //m_A[i].inactivate();
- }
- else
- {
- unsigned int adr = 0;
- for (std::size_t i=0; i<8; i++)
- {
- //m_A[i].activate();
- adr |= (m_A[i]() << i);
- }
-
+ const auto adr(m_addr);
if (!m_WEQ())
{
m_ram[adr >> 6] = (m_ram[adr >> 6]
@@ -101,10 +126,12 @@ namespace netlist
{
m_ram[i] = 0;
}
+ m_addr = 0;
+ m_enq = 0;
}
- NETLIB_DEVICE_IMPL(82S16)
- NETLIB_DEVICE_IMPL(82S16_dip)
+ NETLIB_DEVICE_IMPL(82S16, "TTL_82S16", "")
+ NETLIB_DEVICE_IMPL(82S16_dip, "TTL_82S16_DIP", "")
} //namespace devices
} // namespace netlist