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-rw-r--r--src/emu/cpu/mips/mips3.h2
-rw-r--r--src/emu/cpu/mips/mips3drc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/emu/cpu/mips/mips3.h b/src/emu/cpu/mips/mips3.h
index 2cbdf93c28f..b8d9330cffb 100644
--- a/src/emu/cpu/mips/mips3.h
+++ b/src/emu/cpu/mips/mips3.h
@@ -421,7 +421,7 @@ private:
UINT32 * offset_base32; /* base in memory where the RAM lives, 32-bit pointer, with the start offset pre-applied */
} m_fastram[MIPS3_MAX_FASTRAM];
- UINT64 m_debugger_temp;
+ UINT32 m_debugger_temp;
/* core state */
drc_cache m_cache; /* pointer to the DRC code cache */
diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c
index 74cdace57ce..635d01c3ae4 100644
--- a/src/emu/cpu/mips/mips3drc.c
+++ b/src/emu/cpu/mips/mips3drc.c
@@ -778,7 +778,7 @@ void mips3_device::static_generate_exception(UINT8 exception, int recover, const
/* choose our target PC */
UML_ADD(block, I0, I3, 0xbfc00200); // add i0,i3,0xbfc00200
- UML_TEST(block, I1, SR_BEV); // test i1,SR_BEV
+ UML_TEST(block, CPR032(COP0_Status), SR_BEV); // test CPR032(COP0_Status),SR_BEV
UML_JMPc(block, COND_NZ, skip); // jnz <skip>
UML_ADD(block, I0, I3, 0x80000000); // add i0,i3,0x80000000,z
UML_LABEL(block, skip); // <skip>: