diff options
Diffstat (limited to 'src/emu/cpu')
62 files changed, 810 insertions, 582 deletions
diff --git a/src/emu/cpu/alto2/a2roms.h b/src/emu/cpu/alto2/a2roms.h index f1ffba032da..abd218344c9 100644 --- a/src/emu/cpu/alto2/a2roms.h +++ b/src/emu/cpu/alto2/a2roms.h @@ -30,7 +30,7 @@ typedef struct { } prom_load_t; #define ZERO 0 -#define KEEP ~0 +#define KEEP ~0U #define AMAP_DEFAULT {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15} #define AMAP_CONST_PROM {3,2,1,4,5,6,7,0,} diff --git a/src/emu/cpu/apexc/apexc.c b/src/emu/cpu/apexc/apexc.c index 7a982e01f53..77e5c919f44 100644 --- a/src/emu/cpu/apexc/apexc.c +++ b/src/emu/cpu/apexc/apexc.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /* cpu/apexc/apexc.c: APE(X)C CPU emulation diff --git a/src/emu/cpu/apexc/apexc.h b/src/emu/cpu/apexc/apexc.h index 98ebc825f35..538d903ab44 100644 --- a/src/emu/cpu/apexc/apexc.h +++ b/src/emu/cpu/apexc/apexc.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /* register names for apexc_get_reg & apexc_set_reg */ #pragma once diff --git a/src/emu/cpu/apexc/apexcdsm.c b/src/emu/cpu/apexc/apexcdsm.c index c79359c7025..81effc58b0e 100644 --- a/src/emu/cpu/apexc/apexcdsm.c +++ b/src/emu/cpu/apexc/apexcdsm.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /* cpu/apexc/apexcsm.c : APE(X)C CPU disassembler diff --git a/src/emu/cpu/arm7/arm7.c b/src/emu/cpu/arm7/arm7.c index b030275602b..65125f265f6 100644 --- a/src/emu/cpu/arm7/arm7.c +++ b/src/emu/cpu/arm7/arm7.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /***************************************************************************** * @@ -8,18 +8,6 @@ * Copyright Steve Ellenoff, all rights reserved. * Thumb, DSP, and MMU support and many bugfixes by R. Belmont and Ryan Holtz. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999' * #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76) diff --git a/src/emu/cpu/arm7/arm7.h b/src/emu/cpu/arm7/arm7.h index cb444cf69e4..9b98151494f 100644 --- a/src/emu/cpu/arm7/arm7.h +++ b/src/emu/cpu/arm7/arm7.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /***************************************************************************** * @@ -7,18 +7,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999' * #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76) diff --git a/src/emu/cpu/arm7/arm7core.h b/src/emu/cpu/arm7/arm7core.h index ba75a0ddf01..0883bae8291 100644 --- a/src/emu/cpu/arm7/arm7core.h +++ b/src/emu/cpu/arm7/arm7core.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /***************************************************************************** * @@ -7,18 +7,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999' * #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76) diff --git a/src/emu/cpu/arm7/arm7core.inc b/src/emu/cpu/arm7/arm7core.inc index 51abd756b1f..736d42b0262 100644 --- a/src/emu/cpu/arm7/arm7core.inc +++ b/src/emu/cpu/arm7/arm7core.inc @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /***************************************************************************** * @@ -7,18 +7,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999' * #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76) diff --git a/src/emu/cpu/arm7/arm7dasm.c b/src/emu/cpu/arm7/arm7dasm.c index 50bcae74a1e..b749d3624a2 100644 --- a/src/emu/cpu/arm7/arm7dasm.c +++ b/src/emu/cpu/arm7/arm7dasm.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /***************************************************************************** * @@ -7,18 +7,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999' * #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76) diff --git a/src/emu/cpu/arm7/arm7drc.inc b/src/emu/cpu/arm7/arm7drc.inc index 61b004c457e..fc97e35da1f 100644 --- a/src/emu/cpu/arm7/arm7drc.inc +++ b/src/emu/cpu/arm7/arm7drc.inc @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /***************************************************************************** * @@ -9,18 +9,6 @@ * Thumb, DSP, and MMU support and many bugfixes by R. Belmont and Ryan Holtz. * Dyanmic Recompiler (DRC) / Just In Time Compiler (JIT) by Ryan Holtz. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999' * #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76) diff --git a/src/emu/cpu/arm7/arm7help.h b/src/emu/cpu/arm7/arm7help.h index 307da0e44ef..5625318b942 100644 --- a/src/emu/cpu/arm7/arm7help.h +++ b/src/emu/cpu/arm7/arm7help.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz /* ARM7 core helper Macros / Functions */ diff --git a/src/emu/cpu/arm7/arm7ops.c b/src/emu/cpu/arm7/arm7ops.c index 151299e1e98..9b96ca9054c 100644 --- a/src/emu/cpu/arm7/arm7ops.c +++ b/src/emu/cpu/arm7/arm7ops.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz #include "emu.h" #include "arm7.h" diff --git a/src/emu/cpu/arm7/arm7tdrc.inc b/src/emu/cpu/arm7/arm7tdrc.inc index e9847a97642..ee0573a32e7 100644 --- a/src/emu/cpu/arm7/arm7tdrc.inc +++ b/src/emu/cpu/arm7/arm7tdrc.inc @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz #include "emu.h" #include "arm7core.h" diff --git a/src/emu/cpu/arm7/arm7thmb.c b/src/emu/cpu/arm7/arm7thmb.c index 5e67464d284..3dfd46094aa 100644 --- a/src/emu/cpu/arm7/arm7thmb.c +++ b/src/emu/cpu/arm7/arm7thmb.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz #include "emu.h" #include "arm7.h" diff --git a/src/emu/cpu/cp1610/cp1610.c b/src/emu/cpu/cp1610/cp1610.c index 1dc911adf5e..1279a2cdd91 100644 --- a/src/emu/cpu/cp1610/cp1610.c +++ b/src/emu/cpu/cp1610/cp1610.c @@ -7,16 +7,6 @@ * * Copyright Frank Palazzolo, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * palazzol@comcast.net - * - This entire notice must remain in the source code. - * * This work is based on Juergen Buchmueller's F8 emulation, * and the 'General Instruments CP1610' data sheets. * Special thanks to Joe Zbiciak for his GPL'd CP1610 emulator diff --git a/src/emu/cpu/cp1610/cp1610.h b/src/emu/cpu/cp1610/cp1610.h index 1b2e8657892..670fb0deac8 100644 --- a/src/emu/cpu/cp1610/cp1610.h +++ b/src/emu/cpu/cp1610/cp1610.h @@ -7,16 +7,6 @@ * * Copyright Frank Palazzolo, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * palazzol@comcast.net - * - This entire notice must remain in the source code. - * *****************************************************************************/ #pragma once diff --git a/src/emu/cpu/hmcs40/hmcs40.c b/src/emu/cpu/hmcs40/hmcs40.c index 1adef6ea242..dabc9740004 100644 --- a/src/emu/cpu/hmcs40/hmcs40.c +++ b/src/emu/cpu/hmcs40/hmcs40.c @@ -90,7 +90,7 @@ ADDRESS_MAP_END // device definitions hmcs43_cpu_device::hmcs43_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT16 polarity, const char *shortname) - : hmcs40_cpu_device(mconfig, type, name, tag, owner, clock, FAMILY_HMCS43, polarity, 3, 10, 11, ADDRESS_MAP_NAME(program_1k), 7, ADDRESS_MAP_NAME(data_80x4), shortname, __FILE__) + : hmcs40_cpu_device(mconfig, type, name, tag, owner, clock, FAMILY_HMCS43, polarity, 3 /* stack levels */, 10 /* pc width */, 11 /* prg width */, ADDRESS_MAP_NAME(program_1k), 7 /* data width */, ADDRESS_MAP_NAME(data_80x4), shortname, __FILE__) { } hd38750_device::hd38750_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) @@ -188,6 +188,7 @@ void hmcs40_cpu_device::device_start() m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hmcs40_cpu_device::simple_timer_cb), this)); reset_prescaler(); + // resolve callbacks m_read_r0.resolve_safe(0); m_read_r1.resolve_safe(0); m_read_r2.resolve_safe(0); @@ -215,6 +216,7 @@ void hmcs40_cpu_device::device_start() m_prev_op = 0; m_i = 0; m_eint_line = 0; + m_halt = 0; m_pc = 0; m_prev_pc = 0; m_page = 0; @@ -242,6 +244,8 @@ void hmcs40_cpu_device::device_start() save_item(NAME(m_prev_op)); save_item(NAME(m_i)); save_item(NAME(m_eint_line)); + save_item(NAME(m_halt)); + save_item(NAME(m_timer_halted_remain)); save_item(NAME(m_pc)); save_item(NAME(m_prev_pc)); save_item(NAME(m_page)); @@ -477,9 +481,25 @@ void hmcs40_cpu_device::do_interrupt() void hmcs40_cpu_device::execute_set_input(int line, int state) { + state = (state) ? 1 : 0; + + // halt/unhalt mcu + if (line == HMCS40_INPUT_LINE_HLT && state != m_halt) + { + if (state) + { + m_timer_halted_remain = m_timer->remaining(); + m_timer->reset(); + } + else + m_timer->adjust(m_timer_halted_remain); + + m_halt = state; + return; + } + if (line != 0 && line != 1) return; - state = (state) ? 1 : 0; // external interrupt request on rising edge if (state && !m_int[line]) @@ -551,6 +571,13 @@ inline void hmcs40_cpu_device::increment_pc() void hmcs40_cpu_device::execute_run() { + // in HLT state, the internal clock is not running + if (m_halt) + { + m_icount = 0; + return; + } + while (m_icount > 0) { // LPU is handled 1 cycle later diff --git a/src/emu/cpu/hmcs40/hmcs40.h b/src/emu/cpu/hmcs40/hmcs40.h index 9e722f595a6..8b912739541 100644 --- a/src/emu/cpu/hmcs40/hmcs40.h +++ b/src/emu/cpu/hmcs40/hmcs40.h @@ -26,7 +26,6 @@ #define MCFG_HMCS40_WRITE_D_CB(_devcb) \ hmcs40_cpu_device::set_write_d_callback(*device, DEVCB_##_devcb); - enum { HMCS40_PORT_R0X = 0, @@ -39,6 +38,13 @@ enum HMCS40_PORT_R7X }; +enum +{ + HMCS40_INPUT_LINE_INT0 = 0, + HMCS40_INPUT_LINE_INT1, + HMCS40_INPUT_LINE_HLT +}; + // pinout reference @@ -181,6 +187,8 @@ protected: UINT8 m_i; // 4-bit immediate opcode param int m_eint_line; // which input_line caused an interrupt emu_timer *m_timer; + int m_halt; // internal HLT state + attotime m_timer_halted_remain; int m_icount; UINT16 m_pc; // Program Counter diff --git a/src/emu/cpu/i8089/i8089.c b/src/emu/cpu/i8089/i8089.c index 23b25d891a0..b81869bda1d 100644 --- a/src/emu/cpu/i8089/i8089.c +++ b/src/emu/cpu/i8089/i8089.c @@ -33,7 +33,7 @@ const device_type I8089 = &device_creator<i8089_device>; //------------------------------------------------- i8089_device::i8089_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : - cpu_device(mconfig, I8089, "Intel 8089", tag, owner, clock, "i8089", __FILE__), + cpu_device(mconfig, I8089, "I8089", tag, owner, clock, "i8089", __FILE__), m_icount(0), m_ch1(*this, "1"), m_ch2(*this, "2"), diff --git a/src/emu/cpu/i8089/i8089_channel.c b/src/emu/cpu/i8089/i8089_channel.c index 171a7ce0d24..fe7666ac17c 100644 --- a/src/emu/cpu/i8089/i8089_channel.c +++ b/src/emu/cpu/i8089/i8089_channel.c @@ -51,10 +51,13 @@ const device_type I8089_CHANNEL = &device_creator<i8089_channel>; i8089_channel::i8089_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, I8089_CHANNEL, "Intel 8089 I/O Channel", tag, owner, clock, "i8089_channel", __FILE__), m_write_sintr(*this), + m_iop(NULL), m_icount(0), m_xfer_pending(false), m_dma_value(0), - m_dma_state(DMA_IDLE) + m_dma_state(DMA_IDLE), + m_drq(0), + m_prio(PRIO_IDLE) { } @@ -74,6 +77,7 @@ void i8089_channel::device_start() save_item(NAME(m_xfer_pending)); save_item(NAME(m_dma_value)); save_item(NAME(m_dma_state)); + save_item(NAME(m_drq)); save_item(NAME(m_prio)); for (int i = 0; i < ARRAY_LENGTH(m_r); i++) @@ -246,11 +250,13 @@ int i8089_channel::execute_run() break; case DMA_WAIT_FOR_SOURCE_DRQ: - fatalerror("%s('%s'): wait for source drq not supported\n", shortname(), tag()); + if (m_drq) + m_dma_state = DMA_FETCH; + break; case DMA_FETCH: if (VERBOSE_DMA) - logerror("%s('%s'): entering state: DMA_FETCH", shortname(), tag()); + logerror("%s('%s'): entering state: DMA_FETCH\n", shortname(), tag()); // source is 16-bit? if (BIT(m_r[PSW].w, 1)) @@ -306,7 +312,9 @@ int i8089_channel::execute_run() fatalerror("%s('%s'): dma translate requested\n", shortname(), tag()); case DMA_WAIT_FOR_DEST_DRQ: - fatalerror("%s('%s'): wait for destination drq not supported\n", shortname(), tag()); + if (m_drq) + m_dma_state = DMA_STORE; + break; case DMA_STORE: if (VERBOSE_DMA) @@ -834,5 +842,7 @@ WRITE_LINE_MEMBER( i8089_channel::ext_w ) WRITE_LINE_MEMBER( i8089_channel::drq_w ) { if (VERBOSE) - logerror("%s('%s'): ext_w: %d\n", shortname(), tag(), state); + logerror("%s('%s'): drq_w: %d\n", shortname(), tag(), state); + + m_drq = state; } diff --git a/src/emu/cpu/i8089/i8089_channel.h b/src/emu/cpu/i8089/i8089_channel.h index 9b4034603e5..7c1f5a6e445 100644 --- a/src/emu/cpu/i8089/i8089_channel.h +++ b/src/emu/cpu/i8089/i8089_channel.h @@ -186,6 +186,7 @@ private: bool m_xfer_pending; UINT16 m_dma_value; int m_dma_state; + bool m_drq; // dma state enum diff --git a/src/emu/cpu/i86/i86.c b/src/emu/cpu/i86/i86.c index 7a308da61a9..299d85b1f59 100644 --- a/src/emu/cpu/i86/i86.c +++ b/src/emu/cpu/i86/i86.c @@ -282,6 +282,8 @@ i8086_common_cpu_device::i8086_common_cpu_device(const machine_config &mconfig, , m_irq_state(0) , m_test_state(1) , m_pc(0) + , m_lock(false) + , m_lock_handler(*this) { static const BREGS reg_name[8]={ AL, CL, DL, BL, AH, CH, DH, BH }; @@ -391,6 +393,8 @@ void i8086_common_cpu_device::device_start() state_add(STATE_GENFLAGS, "GENFLAGS", m_TF).callimport().callexport().formatstr("%16s").noshow(); m_icountptr = &m_icount; + + m_lock_handler.resolve_safe(); } @@ -438,6 +442,7 @@ void i8086_common_cpu_device::device_reset() m_dst = 0; m_src = 0; m_halt = false; + m_lock = false; } @@ -1910,7 +1915,9 @@ bool i8086_common_cpu_device::common_op(UINT8 op) break; case 0xe4: // i_inal + if (m_lock) m_lock_handler(1); m_regs.b[AL] = read_port_byte( fetch() ); + if (m_lock) { m_lock_handler(0); m_lock = false; } CLK(IN_IMM8); break; @@ -2011,6 +2018,7 @@ bool i8086_common_cpu_device::common_op(UINT8 op) case 0xf0: // i_lock logerror("%s: %06x: Warning - BUSLOCK\n", tag(), pc()); + m_lock = true; m_no_interrupt = 1; CLK(NOP); break; diff --git a/src/emu/cpu/i86/i86.h b/src/emu/cpu/i86/i86.h index ff1c56c2e92..6e48fecd71e 100644 --- a/src/emu/cpu/i86/i86.h +++ b/src/emu/cpu/i86/i86.h @@ -14,6 +14,10 @@ extern const device_type I8088; #define INPUT_LINE_TEST 20 +#define MCFG_I8086_LOCK_HANDLER(_write) \ + devcb = &i8086_common_cpu_device::set_lock_handler(*device, DEVCB_##_write); + + enum { I8086_PC=0, @@ -29,6 +33,9 @@ public: // construction/destruction i8086_common_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + template<class _Object> static devcb_base &set_lock_handler(device_t &device, _Object object) + { return downcast<i8086_common_cpu_device &>(device).m_lock_handler.set_callback(object); } + protected: enum { @@ -325,6 +332,9 @@ protected: UINT8 m_timing[200]; bool m_halt; + + bool m_lock; + devcb_write_line m_lock_handler; }; class i8086_cpu_device : public i8086_common_cpu_device diff --git a/src/emu/cpu/lr35902/lr35902d.c b/src/emu/cpu/lr35902/lr35902d.c index 64af29a544c..cf6d61bd7d6 100644 --- a/src/emu/cpu/lr35902/lr35902d.c +++ b/src/emu/cpu/lr35902/lr35902d.c @@ -5,20 +5,6 @@ * lr35902d.c * Portable Sharp LR35902 disassembler * - * Copyright The MESS Team. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * *****************************************************************************/ #include "emu.h" diff --git a/src/emu/cpu/m6809/hd6309.c b/src/emu/cpu/m6809/hd6309.c index 027c9b7511b..5b270d26c90 100644 --- a/src/emu/cpu/m6809/hd6309.c +++ b/src/emu/cpu/m6809/hd6309.c @@ -313,7 +313,7 @@ offs_t hd6309_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *o // read_operand //------------------------------------------------- -ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand() +inline UINT8 hd6309_device::read_operand() { switch(m_addressing_mode) { @@ -332,7 +332,7 @@ ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand() // read_operand //------------------------------------------------- -ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand(int ordinal) +inline UINT8 hd6309_device::read_operand(int ordinal) { switch(m_addressing_mode) { @@ -356,7 +356,7 @@ ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand(int ordinal) // write_operand //------------------------------------------------- -ATTR_FORCE_INLINE void hd6309_device::write_operand(UINT8 data) +inline void hd6309_device::write_operand(UINT8 data) { switch(m_addressing_mode) { @@ -375,7 +375,7 @@ ATTR_FORCE_INLINE void hd6309_device::write_operand(UINT8 data) // write_operand //------------------------------------------------- -ATTR_FORCE_INLINE void hd6309_device::write_operand(int ordinal, UINT8 data) +inline void hd6309_device::write_operand(int ordinal, UINT8 data) { switch(m_addressing_mode) { @@ -398,7 +398,7 @@ ATTR_FORCE_INLINE void hd6309_device::write_operand(int ordinal, UINT8 data) // bittest_register //------------------------------------------------- -ATTR_FORCE_INLINE UINT8 &hd6309_device::bittest_register() +inline UINT8 &hd6309_device::bittest_register() { switch(m_temp_im & 0xC0) { @@ -414,7 +414,7 @@ ATTR_FORCE_INLINE UINT8 &hd6309_device::bittest_register() // bittest_source //------------------------------------------------- -ATTR_FORCE_INLINE bool hd6309_device::bittest_source() +inline bool hd6309_device::bittest_source() { return (m_temp.b.l & (1 << ((m_temp_im >> 3) & 0x07))) ? true : false; } @@ -424,7 +424,7 @@ ATTR_FORCE_INLINE bool hd6309_device::bittest_source() // bittest_dest //------------------------------------------------- -ATTR_FORCE_INLINE bool hd6309_device::bittest_dest() +inline bool hd6309_device::bittest_dest() { return (bittest_register() & (1 << ((m_temp_im >> 0) & 0x07))) ? true : false; } @@ -434,7 +434,7 @@ ATTR_FORCE_INLINE bool hd6309_device::bittest_dest() // bittest_set //------------------------------------------------- -ATTR_FORCE_INLINE void hd6309_device::bittest_set(bool result) +inline void hd6309_device::bittest_set(bool result) { if (result) bittest_register() |= (1 << ((m_temp_im >> 0) & 0x07)); @@ -448,7 +448,7 @@ ATTR_FORCE_INLINE void hd6309_device::bittest_set(bool result) // read_exgtfr_register //------------------------------------------------- -ATTR_FORCE_INLINE m6809_base_device::exgtfr_register hd6309_device::read_exgtfr_register(UINT8 reg) +inline m6809_base_device::exgtfr_register hd6309_device::read_exgtfr_register(UINT8 reg) { UINT16 value = 0; @@ -486,7 +486,7 @@ ATTR_FORCE_INLINE m6809_base_device::exgtfr_register hd6309_device::read_exgtfr_ // write_exgtfr_register //------------------------------------------------- -ATTR_FORCE_INLINE void hd6309_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value) +inline void hd6309_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value) { switch(reg & 0x0F) { @@ -517,7 +517,7 @@ ATTR_FORCE_INLINE void hd6309_device::write_exgtfr_register(UINT8 reg, m6809_bas // tfr_read //------------------------------------------------- -ATTR_FORCE_INLINE bool hd6309_device::tfr_read(UINT8 opcode, UINT8 arg, UINT8 &data) +inline bool hd6309_device::tfr_read(UINT8 opcode, UINT8 arg, UINT8 &data) { PAIR16 *reg; @@ -550,7 +550,7 @@ ATTR_FORCE_INLINE bool hd6309_device::tfr_read(UINT8 opcode, UINT8 arg, UINT8 &d // tfr_write //------------------------------------------------- -ATTR_FORCE_INLINE bool hd6309_device::tfr_write(UINT8 opcode, UINT8 arg, UINT8 data) +inline bool hd6309_device::tfr_write(UINT8 opcode, UINT8 arg, UINT8 data) { PAIR16 *reg; @@ -789,7 +789,7 @@ bool hd6309_device::divd() // execute_one - try to execute a single instruction //------------------------------------------------- -ATTR_FORCE_INLINE void hd6309_device::execute_one() +inline void hd6309_device::execute_one() { switch(pop_state()) { diff --git a/src/emu/cpu/m6809/konami.c b/src/emu/cpu/m6809/konami.c index d86f44651d2..8dc2bf3ab78 100644 --- a/src/emu/cpu/m6809/konami.c +++ b/src/emu/cpu/m6809/konami.c @@ -120,7 +120,7 @@ offs_t konami_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT // read_operand //------------------------------------------------- -inline ATTR_FORCE_INLINE UINT8 konami_cpu_device::read_operand() +inline UINT8 konami_cpu_device::read_operand() { return super::read_operand(); } @@ -130,7 +130,7 @@ inline ATTR_FORCE_INLINE UINT8 konami_cpu_device::read_operand() // read_operand //------------------------------------------------- -inline ATTR_FORCE_INLINE UINT8 konami_cpu_device::read_operand(int ordinal) +inline UINT8 konami_cpu_device::read_operand(int ordinal) { switch(m_addressing_mode) { @@ -146,7 +146,7 @@ inline ATTR_FORCE_INLINE UINT8 konami_cpu_device::read_operand(int ordinal) // write_operand //------------------------------------------------- -ATTR_FORCE_INLINE void konami_cpu_device::write_operand(UINT8 data) +inline void konami_cpu_device::write_operand(UINT8 data) { super::write_operand(data); } @@ -157,7 +157,7 @@ ATTR_FORCE_INLINE void konami_cpu_device::write_operand(UINT8 data) // write_operand //------------------------------------------------- -ATTR_FORCE_INLINE void konami_cpu_device::write_operand(int ordinal, UINT8 data) +inline void konami_cpu_device::write_operand(int ordinal, UINT8 data) { switch(m_addressing_mode) { @@ -173,7 +173,7 @@ ATTR_FORCE_INLINE void konami_cpu_device::write_operand(int ordinal, UINT8 data) // ireg //------------------------------------------------- -ATTR_FORCE_INLINE UINT16 &konami_cpu_device::ireg() +inline UINT16 &konami_cpu_device::ireg() { switch(m_opcode & 0x70) { @@ -194,7 +194,7 @@ ATTR_FORCE_INLINE UINT16 &konami_cpu_device::ireg() // read_exgtfr_register //------------------------------------------------- -ATTR_FORCE_INLINE m6809_base_device::exgtfr_register konami_cpu_device::read_exgtfr_register(UINT8 reg) +inline m6809_base_device::exgtfr_register konami_cpu_device::read_exgtfr_register(UINT8 reg) { exgtfr_register result; result.word_value = 0x00FF; @@ -217,7 +217,7 @@ ATTR_FORCE_INLINE m6809_base_device::exgtfr_register konami_cpu_device::read_exg // write_exgtfr_register //------------------------------------------------- -ATTR_FORCE_INLINE void konami_cpu_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value) +inline void konami_cpu_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value) { switch(reg & 0x07) { @@ -287,7 +287,7 @@ template<class T> T konami_cpu_device::safe_shift_left(T value, UINT32 shift) // lmul //------------------------------------------------- -ATTR_FORCE_INLINE void konami_cpu_device::lmul() +inline void konami_cpu_device::lmul() { PAIR result; @@ -313,7 +313,7 @@ ATTR_FORCE_INLINE void konami_cpu_device::lmul() // divx //------------------------------------------------- -ATTR_FORCE_INLINE void konami_cpu_device::divx() +inline void konami_cpu_device::divx() { UINT16 result; UINT8 remainder; @@ -357,7 +357,7 @@ void konami_cpu_device::set_lines(UINT8 data) // execute_one - try to execute a single instruction //------------------------------------------------- -ATTR_FORCE_INLINE void konami_cpu_device::execute_one() +inline void konami_cpu_device::execute_one() { switch(pop_state()) { diff --git a/src/emu/cpu/m6809/m6809.c b/src/emu/cpu/m6809/m6809.c index 3b7fc33d94f..1b7b0e1e777 100644 --- a/src/emu/cpu/m6809/m6809.c +++ b/src/emu/cpu/m6809/m6809.c @@ -456,7 +456,7 @@ const char *m6809_base_device::inputnum_string(int inputnum) // read_exgtfr_register //------------------------------------------------- -ATTR_FORCE_INLINE m6809_base_device::exgtfr_register m6809_base_device::read_exgtfr_register(UINT8 reg) +m6809_base_device::exgtfr_register m6809_base_device::read_exgtfr_register(UINT8 reg) { exgtfr_register result; result.byte_value = 0xFF; @@ -483,7 +483,7 @@ ATTR_FORCE_INLINE m6809_base_device::exgtfr_register m6809_base_device::read_exg // write_exgtfr_register //------------------------------------------------- -ATTR_FORCE_INLINE void m6809_base_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value) +void m6809_base_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value) { switch(reg & 0x0F) { @@ -516,7 +516,7 @@ void m6809_base_device::log_illegal() // execute_one - try to execute a single instruction //------------------------------------------------- -ATTR_FORCE_INLINE void m6809_base_device::execute_one() +void m6809_base_device::execute_one() { switch(pop_state()) { diff --git a/src/emu/cpu/m6809/m6809.h b/src/emu/cpu/m6809/m6809.h index eb0633af44c..7b14a6882e5 100644 --- a/src/emu/cpu/m6809/m6809.h +++ b/src/emu/cpu/m6809/m6809.h @@ -147,27 +147,27 @@ protected: devcb_write_line m_lic_func; // LIC pin on the 6809E // eat cycles - ATTR_FORCE_INLINE void eat(int cycles) { m_icount -= cycles; } + inline void eat(int cycles) { m_icount -= cycles; } void eat_remaining(); // read a byte from given memory location - ATTR_FORCE_INLINE UINT8 read_memory(UINT16 address) { eat(1); return m_addrspace[AS_PROGRAM]->read_byte(address); } + inline UINT8 read_memory(UINT16 address) { eat(1); return m_addrspace[AS_PROGRAM]->read_byte(address); } // write a byte to given memory location - ATTR_FORCE_INLINE void write_memory(UINT16 address, UINT8 data) { eat(1); m_addrspace[AS_PROGRAM]->write_byte(address, data); } + inline void write_memory(UINT16 address, UINT8 data) { eat(1); m_addrspace[AS_PROGRAM]->write_byte(address, data); } // read_opcode() is like read_memory() except it is used for reading opcodes. In the case of a system // with memory mapped I/O, this function can be used to greatly speed up emulation. - ATTR_FORCE_INLINE UINT8 read_opcode(UINT16 address) { eat(1); return m_direct->read_decrypted_byte(address); } + inline UINT8 read_opcode(UINT16 address) { eat(1); return m_direct->read_decrypted_byte(address); } // read_opcode_arg() is identical to read_opcode() except it is used for reading opcode arguments. This // difference can be used to support systems that use different encoding mechanisms for opcodes // and opcode arguments. - ATTR_FORCE_INLINE UINT8 read_opcode_arg(UINT16 address) { eat(1); return m_direct->read_raw_byte(address); } + inline UINT8 read_opcode_arg(UINT16 address) { eat(1); return m_direct->read_raw_byte(address); } // read_opcode() and bump the program counter - ATTR_FORCE_INLINE UINT8 read_opcode() { return read_opcode(m_pc.w++); } - ATTR_FORCE_INLINE UINT8 read_opcode_arg() { return read_opcode_arg(m_pc.w++); } + inline UINT8 read_opcode() { return read_opcode(m_pc.w++); } + inline UINT8 read_opcode_arg() { return read_opcode_arg(m_pc.w++); } // state stack - implemented as a UINT32 void push_state(UINT8 state) { m_state = (m_state << 8) | state; } @@ -219,15 +219,15 @@ protected: template<class T> T set_flags(UINT8 mask, T r); // branch conditions - ATTR_FORCE_INLINE bool cond_hi() { return !(m_cc & CC_ZC); } // BHI/BLS - ATTR_FORCE_INLINE bool cond_cc() { return !(m_cc & CC_C); } // BCC/BCS - ATTR_FORCE_INLINE bool cond_ne() { return !(m_cc & CC_Z); } // BNE/BEQ - ATTR_FORCE_INLINE bool cond_vc() { return !(m_cc & CC_V); } // BVC/BVS - ATTR_FORCE_INLINE bool cond_pl() { return !(m_cc & CC_N); } // BPL/BMI - ATTR_FORCE_INLINE bool cond_ge() { return (m_cc & CC_N ? true : false) == (m_cc & CC_V ? true : false); } // BGE/BLT - ATTR_FORCE_INLINE bool cond_gt() { return cond_ge() && !(m_cc & CC_Z); } // BGT/BLE - ATTR_FORCE_INLINE void set_cond(bool cond) { m_cond = cond; } - ATTR_FORCE_INLINE bool branch_taken() { return m_cond; } + inline bool cond_hi() { return !(m_cc & CC_ZC); } // BHI/BLS + inline bool cond_cc() { return !(m_cc & CC_C); } // BCC/BCS + inline bool cond_ne() { return !(m_cc & CC_Z); } // BNE/BEQ + inline bool cond_vc() { return !(m_cc & CC_V); } // BVC/BVS + inline bool cond_pl() { return !(m_cc & CC_N); } // BPL/BMI + inline bool cond_ge() { return (m_cc & CC_N ? true : false) == (m_cc & CC_V ? true : false); } // BGE/BLT + inline bool cond_gt() { return cond_ge() && !(m_cc & CC_Z); } // BGT/BLE + inline void set_cond(bool cond) { m_cond = cond; } + inline bool branch_taken() { return m_cond; } // interrupt registers bool firq_saves_entire_state() { return false; } @@ -235,8 +235,8 @@ protected: UINT16 entire_state_registers() { return 0xFF; } // miscellaneous - exgtfr_register read_exgtfr_register(UINT8 reg); - void write_exgtfr_register(UINT8 reg, exgtfr_register value); + inline exgtfr_register read_exgtfr_register(UINT8 reg); + inline void write_exgtfr_register(UINT8 reg, exgtfr_register value); bool is_register_addressing_mode(); bool is_ea_addressing_mode() { return m_addressing_mode == ADDRESSING_MODE_EA; } UINT16 get_pending_interrupt(); @@ -255,7 +255,7 @@ private: int m_clock_divider; // functions - void execute_one(); + inline void execute_one(); const char *inputnum_string(int inputnum); }; diff --git a/src/emu/cpu/mcs51/mcs51.c b/src/emu/cpu/mcs51/mcs51.c index 94811d9851e..d3c73ecf0c6 100644 --- a/src/emu/cpu/mcs51/mcs51.c +++ b/src/emu/cpu/mcs51/mcs51.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff, Manuel Abadia, Couriersud /***************************************************************************** * @@ -13,18 +13,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Intel(tm) MC51 Microcontroller Family Users Manual' and * #2) 8051 simulator by Travis Marlatte diff --git a/src/emu/cpu/mcs51/mcs51.h b/src/emu/cpu/mcs51/mcs51.h index e90b7d421c9..89caacafa49 100644 --- a/src/emu/cpu/mcs51/mcs51.h +++ b/src/emu/cpu/mcs51/mcs51.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff, Manuel Abadia, Couriersud /***************************************************************************** * @@ -13,18 +13,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Intel(tm) MC51 Microcontroller Family Users Manual' and * #2) 8051 simulator by Travis Marlatte diff --git a/src/emu/cpu/mcs51/mcs51dasm.c b/src/emu/cpu/mcs51/mcs51dasm.c index 62187d4a692..0d16048855f 100644 --- a/src/emu/cpu/mcs51/mcs51dasm.c +++ b/src/emu/cpu/mcs51/mcs51dasm.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Steve Ellenoff /***************************************************************************** * @@ -13,18 +13,6 @@ * * Copyright Steve Ellenoff, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * sellenoff@hotmail.com - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * This work is based on: * #1) 'Intel(tm) MC51 Microcontroller Family Users Manual' and * #2) 8051 simulator by Travis Marlatte diff --git a/src/emu/cpu/mcs96/i8xc196.c b/src/emu/cpu/mcs96/i8xc196.c index 8e80da19cdb..19553280de2 100644 --- a/src/emu/cpu/mcs96/i8xc196.c +++ b/src/emu/cpu/mcs96/i8xc196.c @@ -69,4 +69,8 @@ UINT16 i8xc196_device::io_r16(UINT8 adr) return data; } +void i8xc196_device::do_exec_partial() +{ +} + #include "cpu/mcs96/i8xc196.inc" diff --git a/src/emu/cpu/mcs96/i8xc196.h b/src/emu/cpu/mcs96/i8xc196.h index cb41e693fe8..299f6c9128d 100644 --- a/src/emu/cpu/mcs96/i8xc196.h +++ b/src/emu/cpu/mcs96/i8xc196.h @@ -23,7 +23,6 @@ public: virtual void do_exec_full(); virtual void do_exec_partial(); - virtual void next(int cycles); virtual void io_w8(UINT8 adr, UINT8 data); virtual void io_w16(UINT8 adr, UINT16 data); virtual UINT8 io_r8(UINT8 adr); diff --git a/src/emu/cpu/melps4/m58846.c b/src/emu/cpu/melps4/m58846.c index e4842d28a6a..ac14baf797d 100644 --- a/src/emu/cpu/melps4/m58846.c +++ b/src/emu/cpu/melps4/m58846.c @@ -30,7 +30,7 @@ ADDRESS_MAP_END // device definitions m58846_device::m58846_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : melps4_cpu_device(mconfig, M58846, "M58846", tag, owner, clock, 11, ADDRESS_MAP_NAME(program_2kx9), 7, ADDRESS_MAP_NAME(data_128x4), "m58846", __FILE__) + : melps4_cpu_device(mconfig, M58846, "M58846", tag, owner, clock, 11, ADDRESS_MAP_NAME(program_2kx9), 7, ADDRESS_MAP_NAME(data_128x4), 12 /* number of D pins */, 2 /* subroutine page */, 1 /* interrupt page */, "m58846", __FILE__) { } @@ -50,10 +50,6 @@ offs_t m58846_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *o void m58846_device::device_start() { melps4_cpu_device::device_start(); - - // set fixed state - m_bm_page = 2; - m_int_page = 1; } @@ -115,6 +111,7 @@ void m58846_device::execute_one() case 0x0b: op_ose(); break; case 0x0c: op_tya(); break; case 0x0f: op_cma(); break; + // 0x18 RAR undocumented? case 0x10: op_cls(); break; case 0x11: op_clds(); break; diff --git a/src/emu/cpu/melps4/melps4.c b/src/emu/cpu/melps4/melps4.c index b9172f7745d..5fdd2b1cab6 100644 --- a/src/emu/cpu/melps4/melps4.c +++ b/src/emu/cpu/melps4/melps4.c @@ -23,11 +23,13 @@ *M58496: 72-pin QFP CMOS, 2Kx10 ROM, 128x4 internal + 256x4 external RAM, 1 timer, low-power *M58497: almost same as M58496 - MELPS 760 subfamily has more differences, document them when needed. + MELPS 760 family has more differences, document them when needed. + MELPS 720 family as well References: - - 1982 Mitsubishi LSI Data Book + - 1980 and 1982 Mitsubishi LSI Data Books + - M34550Mx-XXXFP datasheet (this one is MELPS 720 family) */ @@ -44,9 +46,10 @@ void melps4_cpu_device::state_string_export(const device_state_entry &entry, std { // obviously not from a single flags register, letters are made up case STATE_GENFLAGS: - strprintf(str, "%c%c%c%c", + strprintf(str, "%c%c%c%c%c", m_intp ? 'P':'p', m_inte ? 'I':'i', + m_sm ? 'S':'s', m_cps ? 'D':'d', m_cy ? 'C':'c' ); @@ -74,6 +77,20 @@ void melps4_cpu_device::device_start() m_data = &space(AS_DATA); m_prgmask = (1 << m_prgwidth) - 1; m_datamask = (1 << m_datawidth) - 1; + m_d_mask = (1 << m_d_pins) - 1; + + // resolve callbacks + m_read_k.resolve_safe(0); + m_read_d.resolve_safe(0); + m_read_s.resolve_safe(0); + m_read_f.resolve_safe(0); + + m_write_d.resolve_safe(); + m_write_s.resolve_safe(); + m_write_f.resolve_safe(); + m_write_g.resolve_safe(); + m_write_u.resolve_safe(); + m_write_t.resolve_safe(); // zerofill m_pc = 0; @@ -82,11 +99,19 @@ void melps4_cpu_device::device_start() m_op = 0; m_prev_op = 0; m_bitmask = 0; - + + m_port_d = 0; + m_port_s = 0; + m_port_f = 0; + + m_sm = m_sms = false; + m_ba_flag = false; + m_sp_param = 0; m_cps = 0; m_skip = false; m_inte = 0; m_intp = 1; + m_prohibit_irq = false; m_a = 0; m_b = 0; @@ -110,10 +135,19 @@ void melps4_cpu_device::device_start() save_item(NAME(m_prev_op)); save_item(NAME(m_bitmask)); + save_item(NAME(m_port_d)); + save_item(NAME(m_port_s)); + save_item(NAME(m_port_f)); + + save_item(NAME(m_sm)); + save_item(NAME(m_sms)); + save_item(NAME(m_ba_flag)); + save_item(NAME(m_sp_param)); save_item(NAME(m_cps)); save_item(NAME(m_skip)); save_item(NAME(m_inte)); save_item(NAME(m_intp)); + save_item(NAME(m_prohibit_irq)); save_item(NAME(m_a)); save_item(NAME(m_b)); @@ -131,7 +165,7 @@ void melps4_cpu_device::device_start() // register state for debugger state_add(STATE_GENPC, "curpc", m_pc).formatstr("%04X").noshow(); - state_add(STATE_GENFLAGS, "GENFLAGS", m_cy).formatstr("%4s").noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_cy).formatstr("%5s").noshow(); state_add(MELPS4_PC, "PC", m_pc).formatstr("%04X"); state_add(MELPS4_A, "A", m_a).formatstr("%2d"); // show in decimal @@ -158,6 +192,11 @@ void melps4_cpu_device::device_start() void melps4_cpu_device::device_reset() { + m_sm = m_sms = false; + m_ba_flag = false; + m_prohibit_irq = false; + + m_skip = false; m_op = m_prev_op = 0; m_pc = m_prev_pc = 0; m_inte = 0; @@ -166,6 +205,88 @@ void melps4_cpu_device::device_reset() m_v = 0; m_w = 0; + + // clear ports + write_d_pin(MELPS4_PORTD_CLR, 0); + write_gen_port(MELPS4_PORTS, 0); + write_gen_port(MELPS4_PORTF, 0); + write_gen_port(MELPS4_PORTG, 0); + write_gen_port(MELPS4_PORTU, 0); + m_write_t(0); +} + + + +//------------------------------------------------- +// i/o handling +//------------------------------------------------- + +UINT8 melps4_cpu_device::read_gen_port(int port) +{ + // input generic port + switch (port) + { + case MELPS4_PORTS: + return m_port_s | m_read_s(port, 0xff); + case MELPS4_PORTF: + return m_port_f | (m_read_f(port, 0xff) & 0xf); + + default: + break; + } + + return 0; +} + +void melps4_cpu_device::write_gen_port(int port, UINT8 data) +{ + // output generic port + switch (port) + { + case MELPS4_PORTS: + m_port_s = data; + m_write_s(port, data, 0xff); + break; + case MELPS4_PORTF: + m_port_f = data & 0xf; + m_write_f(port, data & 0xf, 0xff); + break; + case MELPS4_PORTG: + m_write_g(port, data & 0xf, 0xff); + break; + case MELPS4_PORTU: + m_write_u(port, data & 1, 0xff); + break; + + default: + break; + } +} + +int melps4_cpu_device::read_d_pin(int bit) +{ + // read port D, return state of selected pin + bit &= 0xf; + UINT16 d = (m_port_d | m_read_d(bit, 0xffff)) & m_d_mask; + return d >> bit & 1; +} + +void melps4_cpu_device::write_d_pin(int bit, int state) +{ + // clear all port D pins + if (bit == MELPS4_PORTD_CLR) + { + m_port_d = 0; + m_write_d(bit, 0, 0xffff); + } + + // set/reset one port D pin + else + { + bit &= 0xf; + m_port_d = ((m_port_d & (~(1 << bit))) | (state << bit)) & m_d_mask; + m_write_d(bit, m_port_d, 0xffff); + } } @@ -192,6 +313,10 @@ void melps4_cpu_device::execute_run() // remember previous state m_prev_op = m_op; m_prev_pc = m_pc; + + // irq is not accepted during skip or LXY, LA, EI, DI, RT/RTS/RTI or any branch + //.. + m_prohibit_irq = false; // fetch next opcode debugger_instruction_hook(this, m_pc); @@ -201,6 +326,13 @@ void melps4_cpu_device::execute_run() m_pc = (m_pc & ~0x7f) | ((m_pc + 1) & 0x7f); // stays in the same page // handle opcode if it's not skipped - execute_one(); + if (m_skip) + { + // if it's a long jump, skip next one as well + if (m_op != m_ba_op && (m_op & ~0xf) != m_sp_mask) + m_skip = false; + } + else + execute_one(); } } diff --git a/src/emu/cpu/melps4/melps4.h b/src/emu/cpu/melps4/melps4.h index d8b9380f7d7..023b0b9ba02 100644 --- a/src/emu/cpu/melps4/melps4.h +++ b/src/emu/cpu/melps4/melps4.h @@ -12,6 +12,56 @@ #include "emu.h" +// I/O ports setup + +// K input or A/D input port, up to 16 pins +#define MCFG_MELPS4_READ_K_CB(_devcb) \ + melps4_cpu_device::set_read_k_callback(*device, DEVCB_##_devcb); + +// D discrete I/O port, up to 16 pins - offset 0-15 for bit, 16 for all pins clear +#define MCFG_MELPS4_READ_D_CB(_devcb) \ + melps4_cpu_device::set_read_d_callback(*device, DEVCB_##_devcb); +#define MCFG_MELPS4_WRITE_D_CB(_devcb) \ + melps4_cpu_device::set_write_d_callback(*device, DEVCB_##_devcb); + +// 8-bit S generic I/O port +#define MCFG_MELPS4_READ_S_CB(_devcb) \ + melps4_cpu_device::set_read_s_callback(*device, DEVCB_##_devcb); +#define MCFG_MELPS4_WRITE_S_CB(_devcb) \ + melps4_cpu_device::set_write_s_callback(*device, DEVCB_##_devcb); + +// 4-bit F generic I/O port +#define MCFG_MELPS4_READ_F_CB(_devcb) \ + melps4_cpu_device::set_read_f_callback(*device, DEVCB_##_devcb); +#define MCFG_MELPS4_WRITE_F_CB(_devcb) \ + melps4_cpu_device::set_write_f_callback(*device, DEVCB_##_devcb); + +// 4-bit G generic output port +#define MCFG_MELPS4_WRITE_G_CB(_devcb) \ + melps4_cpu_device::set_write_g_callback(*device, DEVCB_##_devcb); + +// 1-bit U generic output port +#define MCFG_MELPS4_WRITE_U_CB(_devcb) \ + melps4_cpu_device::set_write_u_callback(*device, DEVCB_##_devcb); + +// T timer I/O pin (use execute_set_input for reads) +#define MCFG_MELPS4_WRITE_T_CB(_devcb) \ + melps4_cpu_device::set_write_t_callback(*device, DEVCB_##_devcb); + + +#define MELPS4_PORTD_CLR 16 + +// only generic ports here +enum +{ + MELPS4_PORTS = 0, + MELPS4_PORTF, + MELPS4_PORTG, + MELPS4_PORTU +}; + + + // pinout reference /* @@ -45,18 +95,44 @@ class melps4_cpu_device : public cpu_device { public: // construction/destruction - melps4_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source) + melps4_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, int d_pins, UINT8 sm_page, UINT8 int_page, const char *shortname, const char *source) : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) , m_program_config("program", ENDIANNESS_LITTLE, 16, prgwidth, -1, program) , m_data_config("data", ENDIANNESS_LITTLE, 8, datawidth, 0, data) , m_prgwidth(prgwidth) , m_datawidth(datawidth) - , m_stack_levels(3) - , m_bm_page(14) - , m_int_page(12) + , m_d_pins(d_pins) + , m_sm_page(sm_page) + , m_int_page(int_page) , m_xami_mask(0xf) + , m_sp_mask(0x7<<4) + , m_ba_op(0x01) + , m_stack_levels(3) + , m_read_k(*this) + , m_read_d(*this) + , m_read_s(*this) + , m_read_f(*this) + , m_write_d(*this) + , m_write_s(*this) + , m_write_f(*this) + , m_write_g(*this) + , m_write_u(*this) + , m_write_t(*this) { } + // static configuration helpers + template<class _Object> static devcb_base &set_read_k_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_read_k.set_callback(object); } + template<class _Object> static devcb_base &set_read_d_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_read_d.set_callback(object); } + template<class _Object> static devcb_base &set_read_s_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_read_s.set_callback(object); } + template<class _Object> static devcb_base &set_read_f_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_read_f.set_callback(object); } + + template<class _Object> static devcb_base &set_write_d_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_write_d.set_callback(object); } + template<class _Object> static devcb_base &set_write_s_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_write_s.set_callback(object); } + template<class _Object> static devcb_base &set_write_f_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_write_f.set_callback(object); } + template<class _Object> static devcb_base &set_write_g_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_write_g.set_callback(object); } + template<class _Object> static devcb_base &set_write_u_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_write_u.set_callback(object); } + template<class _Object> static devcb_base &set_write_t_callback(device_t &device, _Object object) { return downcast<melps4_cpu_device &>(device).m_write_t.set_callback(object); } + protected: // device-level overrides virtual void device_start(); @@ -86,29 +162,41 @@ protected: int m_icount; - // fixed settings or mask options - int m_prgwidth; // number of bits and bitmask for ROM/RAM size + // fixed settings or mask options that differ between MCU type + int m_prgwidth; // number of bits and bitmask for ROM/RAM size: see melps4.c for info int m_datawidth; // " int m_prgmask; // " int m_datamask; // " + int m_d_pins; // number of D port pins and bitmask: 11 on '40,'41,'42,'44, 8 on '43, 12 on '45,'46, 16 on '47 + int m_d_mask; // " - UINT8 m_stack_levels; // 3 levels on MELPS 4, 12 levels on MELPS 41/42 - UINT8 m_bm_page; // short BM default page: 14 on '40 to '44, 2 on '45,'46, 0 on '47 + UINT8 m_sm_page; // subroutine default page: 14 on '40 to '44, 2 on '45,'46, 0 on '47 UINT8 m_int_page; // interrupt routine page: 12 on '40 to '44, 1 on '45,'46, 2 on '47 UINT8 m_xami_mask; // mask option for XAMI opcode on '40,'41,'45 (0xf for others) + UINT16 m_sp_mask; // SP opcode location(middle 4 bits): 7 on '40 to '46, 3 on '47 + UINT16 m_ba_op; // BA opcode location: 1 on '40 to '46, N/A on '47 + UINT8 m_stack_levels; // 3 levels on MELPS 4, 12 levels on MELPS 41/42 // internal state, misc regs UINT16 m_pc; // program counter (11 or 10-bit) UINT16 m_prev_pc; - UINT16 m_stack[12]; // callstack + UINT16 m_stack[12]; // callstack (SK0-SKx, same size as PC) UINT16 m_op; UINT16 m_prev_op; UINT8 m_bitmask; // opcode bit argument - + + UINT16 m_port_d; // last written port data + UINT8 m_port_s; // " + UINT8 m_port_f; // " + + bool m_sm, m_sms; // subroutine mode flag + stack + bool m_ba_flag; // temp flag indicates BA opcode was executed + UINT8 m_sp_param; // temp register holding SP opcode parameter UINT8 m_cps; // DP,CY or DP',CY' selected bool m_skip; // skip next opcode UINT8 m_inte; // interrupt enable flag UINT8 m_intp; // external interrupt polarity ('40 to '44) + bool m_prohibit_irq; // interrupt is prohibited during certain opcodes // work registers (unless specified, each is 4-bit) UINT8 m_a; // accumulator @@ -125,6 +213,24 @@ protected: UINT8 m_v; // timer control V UINT8 m_w; // timer control W + // i/o handlers + devcb_read16 m_read_k; + devcb_read16 m_read_d; + devcb_read8 m_read_s; + devcb_read8 m_read_f; + + devcb_write16 m_write_d; + devcb_write8 m_write_s; + devcb_write8 m_write_f; + devcb_write8 m_write_g; + devcb_write8 m_write_u; + devcb_write_line m_write_t; + + UINT8 read_gen_port(int port); + void write_gen_port(int port, UINT8 data); + int read_d_pin(int bit); + void write_d_pin(int bit, int state); + // misc internal helpers UINT8 ram_r(); void ram_w(UINT8 data); diff --git a/src/emu/cpu/melps4/melps4op.inc b/src/emu/cpu/melps4/melps4op.inc index 296a5b1a39a..476de900e93 100644 --- a/src/emu/cpu/melps4/melps4op.inc +++ b/src/emu/cpu/melps4/melps4op.inc @@ -19,10 +19,16 @@ inline void melps4_cpu_device::ram_w(UINT8 data) void melps4_cpu_device::pop_pc() { + m_pc = m_stack[0]; + for (int i = 0; i < m_stack_levels-1; i++) + m_stack[i] = m_stack[i+1]; } void melps4_cpu_device::push_pc() { + for (int i = m_stack_levels-1; i >= 1; i--) + m_stack[i] = m_stack[i-1]; + m_stack[0] = m_pc; } @@ -82,6 +88,7 @@ void melps4_cpu_device::op_tax() void melps4_cpu_device::op_lxy() { // LXY x,y: load immediate into X,Y, skip any next LXY + m_prohibit_irq = true; if ((m_op & ~0x3f) != (m_prev_op & ~0x3f)) { m_x = m_op >> 4 & 3; @@ -181,6 +188,7 @@ void melps4_cpu_device::op_xami() void melps4_cpu_device::op_la() { // LA n: load immediate into A, skip any next LA + m_prohibit_irq = true; if ((m_op & ~0xf) != (m_prev_op & ~0xf)) m_a = m_op & 0xf; } @@ -411,13 +419,13 @@ void melps4_cpu_device::op_tab2() void melps4_cpu_device::op_tva() { // TVA: transfer A to timer control V - op_illegal(); + m_v = m_a; } void melps4_cpu_device::op_twa() { // TWA: transfer A to timer control W - op_illegal(); + m_w = m_a; } void melps4_cpu_device::op_snz1() @@ -437,26 +445,57 @@ void melps4_cpu_device::op_snz2() void melps4_cpu_device::op_ba() { - // BA: x - op_illegal(); + // BA: indicate next branch is indirect + m_prohibit_irq = true; + m_ba_flag = true; } void melps4_cpu_device::op_sp() { - // SP: set page - op_illegal(); + // SP: set page for next branch + // note: mnemonic is guessed, manual names it BL or BML + m_prohibit_irq = true; + m_sp_param = m_op & 0xf; } void melps4_cpu_device::op_b() { - // B xy: branch in current page - op_illegal(); + // B xy: branch + m_prohibit_irq = true; + + // determine new page: + // - short call: subroutine page + // - short jump: current page, or sub. page + 1 when in sub. mode + // - long jump/call(B/BM preceded by SP): temp SP register + UINT8 page = m_pc >> 7; + if ((m_prev_op & ~0xf) == m_sp_mask) + { + m_sm = false; + page = m_sp_param; + } + else if (m_sm) + page = m_sm_page | (m_op >> 7 & 1); + + m_pc = page << 7 | (m_op & 0x7f); + + // if BA opcode was executed, set PC low 4 bits to A + if (m_ba_flag) + { + m_ba_flag = false; + m_pc = (m_pc & ~0xf) | m_a; + } } void melps4_cpu_device::op_bm() { - // BM xy call subroutine on page 14 - op_illegal(); + // BM xy call subroutine + // don't push stack on short calls when in subroutine mode + if (!m_sm || (m_prev_op & ~0xf) == m_sp_mask) + push_pc(); + + // set subroutine mode - it is reset after long jump/call or return + m_sm = true; + op_b(); } @@ -465,7 +504,9 @@ void melps4_cpu_device::op_bm() void melps4_cpu_device::op_rt() { // RT: return from subroutine - op_illegal(); + m_prohibit_irq = true; + m_sm = false; + pop_pc(); } void melps4_cpu_device::op_rts() @@ -478,7 +519,8 @@ void melps4_cpu_device::op_rts() void melps4_cpu_device::op_rti() { // RTI: return from interrupt routine - op_illegal(); + op_rt(); + m_sm = m_sms; } @@ -487,43 +529,44 @@ void melps4_cpu_device::op_rti() void melps4_cpu_device::op_cld() { // CLD: clear port D - op_illegal(); + write_d_pin(MELPS4_PORTD_CLR, 0); } void melps4_cpu_device::op_cls() { // CLS: clear port S - op_illegal(); + write_gen_port(MELPS4_PORTS, 0); } void melps4_cpu_device::op_clds() { // CLDS: CLD, CLS - op_illegal(); + op_cld(); + op_cls(); } void melps4_cpu_device::op_sd() { - // SD: set port D bit designated by Y - op_illegal(); + // SD: set port D pin designated by Y + write_d_pin(m_y, 1); } void melps4_cpu_device::op_rd() { - // RD: reset port D bit designated by Y - op_illegal(); + // RD: reset port D pin designated by Y + write_d_pin(m_y, 0); } void melps4_cpu_device::op_szd() { - // SZD: skip next if port D bit designated by Y is 0 - op_illegal(); + // SZD: skip next if port D pin designated by Y is 0 + m_skip = !read_d_pin(m_y); } void melps4_cpu_device::op_osab() { // OSAB: output A and B to port S - op_illegal(); + write_gen_port(MELPS4_PORTS, m_b << 4 | m_a); } void melps4_cpu_device::op_ospa() @@ -535,49 +578,50 @@ void melps4_cpu_device::op_ospa() void melps4_cpu_device::op_ose() { // OSE: output E to port S - op_illegal(); + write_gen_port(MELPS4_PORTS, m_e); } void melps4_cpu_device::op_ias() { // IAS i: transfer port S(hi/lo) to A - op_illegal(); + int shift = (m_op & 1) ? 0 : 4; + m_a = read_gen_port(MELPS4_PORTS) >> shift & 0xf; } void melps4_cpu_device::op_ofa() { // OFA: output A to port F - op_illegal(); + write_gen_port(MELPS4_PORTF, m_a); } void melps4_cpu_device::op_iaf() { // IAF: input port F to A - op_illegal(); + m_a = read_gen_port(MELPS4_PORTF); } void melps4_cpu_device::op_oga() { // OGA: output A to port G - op_illegal(); + write_gen_port(MELPS4_PORTG, m_a); } void melps4_cpu_device::op_iak() { // IAK: input port K to A - op_illegal(); + m_a = m_read_k(0, 0xffff) & 0xf; } void melps4_cpu_device::op_szk() { // SZK j: skip next if port K bit is reset - op_illegal(); + m_skip = !(m_read_k(0, 0xffff) & m_bitmask); } void melps4_cpu_device::op_su() { // SU/RU: set/reset port U - op_illegal(); + write_gen_port(MELPS4_PORTU, m_op & 1); } @@ -586,12 +630,14 @@ void melps4_cpu_device::op_su() void melps4_cpu_device::op_ei() { // EI: enable interrupt flag + m_prohibit_irq = true; m_inte = 1; } void melps4_cpu_device::op_di() { // DI: disable interrupt flag + m_prohibit_irq = true; m_inte = 0; } diff --git a/src/emu/cpu/mips/mips3.c b/src/emu/cpu/mips/mips3.c index 1b196f0fa4d..3b377dfa64f 100644 --- a/src/emu/cpu/mips/mips3.c +++ b/src/emu/cpu/mips/mips3.c @@ -1010,8 +1010,7 @@ inline bool mips3_device::RBYTE(offs_t address, UINT32 *result) { continue; } - UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start; - *result = fastbase[tlbaddress ^ m_byte_xor]; + *result = m_fastram[ramnum].offset_base8[tlbaddress ^ m_byte_xor]; return true; } *result = (*m_memory.read_byte)(*m_program, tlbaddress); @@ -1044,8 +1043,7 @@ inline bool mips3_device::RHALF(offs_t address, UINT32 *result) { continue; } - UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start; - *result = ((UINT16*)fastbase)[(tlbaddress ^ m_word_xor) >> 1]; + *result = m_fastram[ramnum].offset_base16[(tlbaddress ^ m_word_xor) >> 1]; return true; } *result = (*m_memory.read_word)(*m_program, tlbaddress); @@ -1078,8 +1076,7 @@ inline bool mips3_device::RWORD(offs_t address, UINT32 *result) { continue; } - UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start; - *result = ((UINT32*)fastbase)[tlbaddress >> 2]; + *result = m_fastram[ramnum].offset_base32[tlbaddress >> 2]; return true; } *result = (*m_memory.read_dword)(*m_program, tlbaddress); @@ -1181,8 +1178,7 @@ inline void mips3_device::WBYTE(offs_t address, UINT8 data) { continue; } - UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start; - fastbase[tlbaddress ^ m_byte_xor] = data; + m_fastram[ramnum].offset_base8[tlbaddress ^ m_byte_xor] = data; return; } (*m_memory.write_byte)(*m_program, tlbaddress, data); @@ -1216,8 +1212,7 @@ inline void mips3_device::WHALF(offs_t address, UINT16 data) { continue; } - void *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start; - ((UINT16*)fastbase)[(tlbaddress ^ m_word_xor) >> 1] = data; + m_fastram[ramnum].offset_base16[(tlbaddress ^ m_word_xor) >> 1] = data; return; } (*m_memory.write_word)(*m_program, tlbaddress, data); @@ -1251,8 +1246,7 @@ inline void mips3_device::WWORD(offs_t address, UINT32 data) { continue; } - void *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start; - ((UINT32*)fastbase)[tlbaddress >> 2] = data; + m_fastram[ramnum].offset_base32[tlbaddress >> 2] = data; return; } (*m_memory.write_dword)(*m_program, tlbaddress, data); diff --git a/src/emu/cpu/mips/mips3.h b/src/emu/cpu/mips/mips3.h index f0b860619ff..2cbdf93c28f 100644 --- a/src/emu/cpu/mips/mips3.h +++ b/src/emu/cpu/mips/mips3.h @@ -416,6 +416,9 @@ private: offs_t end; /* end of the RAM block */ UINT8 readonly; /* TRUE if read-only */ void * base; /* base in memory where the RAM lives */ + UINT8 * offset_base8; /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */ + UINT16 * offset_base16; /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied */ + UINT32 * offset_base32; /* base in memory where the RAM lives, 32-bit pointer, with the start offset pre-applied */ } m_fastram[MIPS3_MAX_FASTRAM]; UINT64 m_debugger_temp; diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index 3e73d96f206..70c31df2220 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -182,6 +182,9 @@ void mips3_device::add_fastram(offs_t start, offs_t end, UINT8 readonly, void *b m_fastram[m_fastram_select].end = end; m_fastram[m_fastram_select].readonly = readonly; m_fastram[m_fastram_select].base = base; + m_fastram[m_fastram_select].offset_base8 = (UINT8*)base - start; + m_fastram[m_fastram_select].offset_base16 = (UINT16*)((UINT8*)base - start); + m_fastram[m_fastram_select].offset_base32 = (UINT32*)((UINT8*)base - start); m_fastram_select++; } } diff --git a/src/emu/cpu/mn10200/mn10200.c b/src/emu/cpu/mn10200/mn10200.c index e05c032c91c..0fdb1edd946 100644 --- a/src/emu/cpu/mn10200/mn10200.c +++ b/src/emu/cpu/mn10200/mn10200.c @@ -35,28 +35,88 @@ enum mn10200_flag FLAG_D15 = 0x8000 // ? }; -const device_type MN1020012A = &device_creator<mn10200_device>; -static ADDRESS_MAP_START( mn1020012_internal_map, AS_PROGRAM, 16, mn10200_device ) +const device_type MN1020012A = &device_creator<mn1020012a_device>; + +// internal memory maps +static ADDRESS_MAP_START( mn1020012a_internal_map, AS_PROGRAM, 16, mn10200_device ) AM_RANGE(0x00fc00, 0x00ffff) AM_READWRITE8(io_control_r, io_control_w, 0xffff) ADDRESS_MAP_END -mn10200_device::mn10200_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : cpu_device(mconfig, MN1020012A, "MN1020012A", tag, owner, clock, "mn1020012a", __FILE__), - m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(mn1020012_internal_map)), - m_io_config("data", ENDIANNESS_LITTLE, 8, 8, 0) + +// device definitions +mn1020012a_device::mn1020012a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mn10200_device(mconfig, MN1020012A, "MN1020012A", tag, owner, clock, ADDRESS_MAP_NAME(mn1020012a_internal_map), "mn1020012a", __FILE__) +{ } + + +// disasm +void mn10200_device::state_string_export(const device_state_entry &entry, std::string &str) +{ + switch (entry.index()) + { + case STATE_GENFLAGS: + strprintf(str, "S=%d irq=%s im=%d %c%c%c%c %c%c%c%c", + (m_psw >> 12) & 3, + m_psw & FLAG_IE ? "on " : "off", + (m_psw >> 8) & 7, + m_psw & FLAG_VX ? 'V' : '-', + m_psw & FLAG_CX ? 'C' : '-', + m_psw & FLAG_NX ? 'N' : '-', + m_psw & FLAG_ZX ? 'Z' : '-', + m_psw & FLAG_VF ? 'v' : '-', + m_psw & FLAG_CF ? 'c' : '-', + m_psw & FLAG_NF ? 'n' : '-', + m_psw & FLAG_ZF ? 'z' : '-'); + break; + } +} + +offs_t mn10200_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { + extern CPU_DISASSEMBLE( mn10200 ); + return CPU_DISASSEMBLE_NAME(mn10200)(this, buffer, pc, oprom, opram, options); } + //------------------------------------------------- // device_start - device-specific startup //------------------------------------------------- +enum +{ + MN10200_PC = 0, + MN10200_PSW, + MN10200_MDR, + MN10200_D0, + MN10200_D1, + MN10200_D2, + MN10200_D3, + MN10200_A0, + MN10200_A1, + MN10200_A2, + MN10200_A3, + MN10200_NMICR, + MN10200_IAGR +}; + void mn10200_device::device_start() { m_program = &space(AS_PROGRAM); - m_io = &space(AS_IO); + + // resolve callbacks + m_read_port0.resolve_safe(0xff); + m_read_port1.resolve_safe(0xff); + m_read_port2.resolve_safe(0xff); + m_read_port3.resolve_safe(0xff); + m_read_port4.resolve_safe(0xff); + + m_write_port0.resolve_safe(); + m_write_port1.resolve_safe(); + m_write_port2.resolve_safe(); + m_write_port3.resolve_safe(); + m_write_port4.resolve_safe(); // init and register for savestates save_item(NAME(m_pc)); @@ -176,34 +236,6 @@ void mn10200_device::device_start() } -void mn10200_device::state_string_export(const device_state_entry &entry, std::string &str) -{ - switch (entry.index()) - { - case STATE_GENFLAGS: - strprintf(str, "S=%d irq=%s im=%d %c%c%c%c %c%c%c%c", - (m_psw >> 12) & 3, - m_psw & FLAG_IE ? "on " : "off", - (m_psw >> 8) & 7, - m_psw & FLAG_VX ? 'V' : '-', - m_psw & FLAG_CX ? 'C' : '-', - m_psw & FLAG_NX ? 'N' : '-', - m_psw & FLAG_ZX ? 'Z' : '-', - m_psw & FLAG_VF ? 'v' : '-', - m_psw & FLAG_CF ? 'c' : '-', - m_psw & FLAG_NF ? 'n' : '-', - m_psw & FLAG_ZF ? 'z' : '-'); - break; - } -} - - -offs_t mn10200_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) -{ - extern CPU_DISASSEMBLE( mn10200 ); - return CPU_DISASSEMBLE_NAME(mn10200)(this, buffer, pc, oprom, opram, options); -} - //------------------------------------------------- // device_reset - device-specific reset @@ -234,7 +266,10 @@ void mn10200_device::device_reset() } -// interrupts + +//------------------------------------------------- +// interrupts +//------------------------------------------------- void mn10200_device::take_irq(int level, int group) { @@ -332,7 +367,10 @@ void mn10200_device::execute_set_input(int irqnum, int state) } -// 8-bit timers + +//------------------------------------------------- +// timers +//------------------------------------------------- int mn10200_device::timer_tick_simple(int tmr) { @@ -405,7 +443,10 @@ TIMER_CALLBACK_MEMBER( mn10200_device::simple_timer_cb ) } -// opcode handlers + +//------------------------------------------------- +// opcode helpers +//------------------------------------------------- void mn10200_device::illegal(UINT8 prefix, UINT8 op) { @@ -479,9 +520,9 @@ void mn10200_device::do_jsr(UINT32 to, UINT32 ret) change_pc(to); } -void mn10200_device::do_branch(bool state) +void mn10200_device::do_branch(int condition) { - if (state) + if (condition) { m_cycles -= 1; change_pc(m_pc + (INT8)read_arg8(m_pc)); @@ -490,10 +531,15 @@ void mn10200_device::do_branch(bool state) +//------------------------------------------------- +// execute loop +//------------------------------------------------- + void mn10200_device::execute_run() { while (m_cycles > 0) { + // internal peripheral, external pin, or prev instruction may have changed irq state while (m_possible_irq) { @@ -579,13 +625,13 @@ void mn10200_device::execute_run() // add dn, dm case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: - m_d[op&3] = do_add(m_d[op&3], m_d[op>>2&3], 0); + m_d[op&3] = do_add(m_d[op&3], m_d[op>>2&3]); break; // sub dn, dm case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7: case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: - m_d[op&3] = do_sub(m_d[op&3], m_d[op>>2&3], 0); + m_d[op&3] = do_sub(m_d[op&3], m_d[op>>2&3]); break; // extx dn @@ -634,19 +680,19 @@ void mn10200_device::execute_run() // add imm8, an case 0xd0: case 0xd1: case 0xd2: case 0xd3: - m_a[op&3] = do_add(m_a[op&3], (INT8)read_arg8(m_pc), 0); + m_a[op&3] = do_add(m_a[op&3], (INT8)read_arg8(m_pc)); m_pc += 1; break; // add imm8, dn case 0xd4: case 0xd5: case 0xd6: case 0xd7: - m_d[op&3] = do_add(m_d[op&3], (INT8)read_arg8(m_pc), 0); + m_d[op&3] = do_add(m_d[op&3], (INT8)read_arg8(m_pc)); m_pc += 1; break; // cmp imm8, dn case 0xd8: case 0xd9: case 0xda: case 0xdb: - do_sub(m_d[op&3], (INT8)read_arg8(m_pc), 0); + do_sub(m_d[op&3], (INT8)read_arg8(m_pc)); m_pc += 1; break; @@ -718,7 +764,7 @@ void mn10200_device::execute_run() // bra label8 case 0xea: - do_branch(true); + do_branch(); m_pc += 1; break; @@ -733,7 +779,7 @@ void mn10200_device::execute_run() // cmp imm16, an case 0xec: case 0xed: case 0xee: case 0xef: - do_sub(m_a[op&3], read_arg16(m_pc), 0); + do_sub(m_a[op&3], read_arg16(m_pc)); m_pc += 2; break; @@ -904,17 +950,17 @@ void mn10200_device::execute_run() { // add dm, an case 0x00: - m_a[op&3] = do_add(m_a[op&3], m_d[op>>2&3], 0); + m_a[op&3] = do_add(m_a[op&3], m_d[op>>2&3]); break; // sub dm, an case 0x10: - m_a[op&3] = do_sub(m_a[op&3], m_d[op>>2&3], 0); + m_a[op&3] = do_sub(m_a[op&3], m_d[op>>2&3]); break; // cmp dm, an case 0x20: - do_sub(m_a[op&3], m_d[op>>2&3], 0); + do_sub(m_a[op&3], m_d[op>>2&3]); break; // mov dm, an @@ -924,17 +970,17 @@ void mn10200_device::execute_run() // add an, am case 0x40: - m_a[op&3] = do_add(m_a[op&3], m_a[op>>2&3], 0); + m_a[op&3] = do_add(m_a[op&3], m_a[op>>2&3]); break; // sub an, am case 0x50: - m_a[op&3] = do_sub(m_a[op&3], m_a[op>>2&3], 0); + m_a[op&3] = do_sub(m_a[op&3], m_a[op>>2&3]); break; // cmp an, am case 0x60: - do_sub(m_a[op&3], m_a[op>>2&3], 0); + do_sub(m_a[op&3], m_a[op>>2&3]); break; // mov an, am @@ -962,17 +1008,17 @@ void mn10200_device::execute_run() // add an, dm case 0xc0: - m_d[op&3] = do_add(m_d[op&3], m_a[op>>2&3], 0); + m_d[op&3] = do_add(m_d[op&3], m_a[op>>2&3]); break; // sub an, dm case 0xd0: - m_d[op&3] = do_sub(m_d[op&3], m_a[op>>2&3], 0); + m_d[op&3] = do_sub(m_d[op&3], m_a[op>>2&3]); break; // cmp an, dm case 0xe0: - do_sub(m_d[op&3], m_a[op>>2&3], 0); + do_sub(m_d[op&3], m_a[op>>2&3]); break; // mov an, dm @@ -1123,7 +1169,7 @@ void mn10200_device::execute_run() // cmp dn, dm case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: - do_sub(m_d[op&3], m_d[op>>2&3], 0); + do_sub(m_d[op&3], m_d[op>>2&3]); break; // mov dn, mdr @@ -1221,22 +1267,22 @@ void mn10200_device::execute_run() // add imm24, dn case 0x60: case 0x61: case 0x62: case 0x63: - m_d[op&3] = do_add(m_d[op&3], read_arg24(m_pc), 0); + m_d[op&3] = do_add(m_d[op&3], read_arg24(m_pc)); break; // add imm24, an case 0x64: case 0x65: case 0x66: case 0x67: - m_a[op&3] = do_add(m_a[op&3], read_arg24(m_pc), 0); + m_a[op&3] = do_add(m_a[op&3], read_arg24(m_pc)); break; // sub imm24, dn case 0x68: case 0x69: case 0x6a: case 0x6b: - m_d[op&3] = do_sub(m_d[op&3], read_arg24(m_pc), 0); + m_d[op&3] = do_sub(m_d[op&3], read_arg24(m_pc)); break; // sub imm24, an case 0x6c: case 0x6d: case 0x6e: case 0x6f: - m_a[op&3] = do_sub(m_a[op&3], read_arg24(m_pc), 0); + m_a[op&3] = do_sub(m_a[op&3], read_arg24(m_pc)); break; // mov imm24, dn @@ -1251,12 +1297,12 @@ void mn10200_device::execute_run() // cmp imm24, dn case 0x78: case 0x79: case 0x7a: case 0x7b: - do_sub(m_d[op&3], read_arg24(m_pc), 0); + do_sub(m_d[op&3], read_arg24(m_pc)); break; // cmp imm24, an case 0x7c: case 0x7d: case 0x7e: case 0x7f: - do_sub(m_a[op&3], read_arg24(m_pc), 0); + do_sub(m_a[op&3], read_arg24(m_pc)); break; // mov (d24, an), dm @@ -1514,12 +1560,12 @@ void mn10200_device::execute_run() // add imm16, an case 0x08: case 0x09: case 0x0a: case 0x0b: - m_a[op&3] = do_add(m_a[op&3], (INT16)read_arg16(m_pc), 0); + m_a[op&3] = do_add(m_a[op&3], (INT16)read_arg16(m_pc)); break; // sub imm16, an case 0x0c: case 0x0d: case 0x0e: case 0x0f: - m_a[op&3] = do_sub(m_a[op&3], (INT16)read_arg16(m_pc), 0); + m_a[op&3] = do_sub(m_a[op&3], (INT16)read_arg16(m_pc)); break; // and imm16, psw @@ -1537,12 +1583,12 @@ void mn10200_device::execute_run() // add imm16, dn case 0x18: case 0x19: case 0x1a: case 0x1b: - m_d[op&3] = do_add(m_d[op&3], (INT16)read_arg16(m_pc), 0); + m_d[op&3] = do_add(m_d[op&3], (INT16)read_arg16(m_pc)); break; // sub imm16, dn case 0x1c: case 0x1d: case 0x1e: case 0x1f: - m_d[op&3] = do_sub(m_d[op&3], (INT16)read_arg16(m_pc), 0); + m_d[op&3] = do_sub(m_d[op&3], (INT16)read_arg16(m_pc)); break; // mov an, (abs16) @@ -1564,7 +1610,7 @@ void mn10200_device::execute_run() // cmp imm16, dn case 0x48: case 0x49: case 0x4a: case 0x4b: - do_sub(m_d[op&3], (INT16)read_arg16(m_pc), 0); + do_sub(m_d[op&3], (INT16)read_arg16(m_pc)); break; // xor imm16, dn @@ -1644,7 +1690,10 @@ void mn10200_device::execute_run() } -// internal i/o + +//------------------------------------------------- +// internal i/o +//------------------------------------------------- WRITE8_MEMBER(mn10200_device::io_control_w) { @@ -2007,19 +2056,19 @@ WRITE8_MEMBER(mn10200_device::io_control_w) // outputs case 0x3c0: m_port[0].out = data; - m_io->write_byte(MN10200_PORT0, m_port[0].out | (m_port[0].dir ^ 0xff)); + m_write_port0(MN10200_PORT0, m_port[0].out | (m_port[0].dir ^ 0xff), 0xff); break; case 0x264: m_port[1].out = data; - m_io->write_byte(MN10200_PORT1, m_port[1].out | (m_port[1].dir ^ 0xff)); + m_write_port1(MN10200_PORT1, m_port[1].out | (m_port[1].dir ^ 0xff), 0xff); break; case 0x3c2: m_port[2].out = data & 0x0f; - m_io->write_byte(MN10200_PORT2, m_port[2].out | (m_port[2].dir ^ 0x0f)); + m_write_port2(MN10200_PORT2, m_port[2].out | (m_port[2].dir ^ 0x0f), 0xff); break; case 0x3c3: m_port[3].out = data & 0x1f; - m_io->write_byte(MN10200_PORT3, m_port[3].out | (m_port[3].dir ^ 0x1f)); + m_write_port3(MN10200_PORT3, m_port[3].out | (m_port[3].dir ^ 0x1f), 0xff); break; // directions (0=input, 1=output) @@ -2049,7 +2098,6 @@ WRITE8_MEMBER(mn10200_device::io_control_w) } - READ8_MEMBER(mn10200_device::io_control_r) { switch (offset) @@ -2151,13 +2199,13 @@ READ8_MEMBER(mn10200_device::io_control_r) // inputs case 0x3d0: - return m_io->read_byte(MN10200_PORT0) | m_port[0].dir; + return m_read_port0(MN10200_PORT0, 0xff) | m_port[0].dir; case 0x3d1: - return m_io->read_byte(MN10200_PORT1) | m_port[1].dir; + return m_read_port1(MN10200_PORT1, 0xff) | m_port[1].dir; case 0x3d2: - return (m_io->read_byte(MN10200_PORT2) & 0x0f) | m_port[2].dir; + return (m_read_port2(MN10200_PORT2, 0xff) & 0x0f) | m_port[2].dir; case 0x3d3: - return (m_io->read_byte(MN10200_PORT3) & 0x1f) | m_port[3].dir; + return (m_read_port3(MN10200_PORT3, 0xff) & 0x1f) | m_port[3].dir; // directions (0=input, 1=output) case 0x3e0: diff --git a/src/emu/cpu/mn10200/mn10200.h b/src/emu/cpu/mn10200/mn10200.h index 61ebb96fb0c..59be253f852 100644 --- a/src/emu/cpu/mn10200/mn10200.h +++ b/src/emu/cpu/mn10200/mn10200.h @@ -8,27 +8,14 @@ */ -#pragma once - #ifndef MN10200_H #define MN10200_H -enum -{ - MN10200_PC = 0, - MN10200_PSW, - MN10200_MDR, - MN10200_D0, - MN10200_D1, - MN10200_D2, - MN10200_D3, - MN10200_A0, - MN10200_A1, - MN10200_A2, - MN10200_A3, - MN10200_NMICR, - MN10200_IAGR -}; +// port setup +#define MCFG_MN10200_READ_PORT_CB(X, _devcb) \ + mn10200_device::set_read_port##X##_callback(*device, DEVCB_##_devcb); +#define MCFG_MN10200_WRITE_PORT_CB(X, _devcb) \ + mn10200_device::set_write_port##X##_callback(*device, DEVCB_##_devcb); enum { @@ -50,9 +37,6 @@ enum }; -extern const device_type MN1020012A; - - #define MN10200_NUM_PRESCALERS (2) #define MN10200_NUM_TIMERS_8BIT (10) #define MN10200_NUM_IRQ_GROUPS (31) @@ -62,7 +46,25 @@ class mn10200_device : public cpu_device { public: // construction/destruction - mn10200_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + mn10200_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor program, const char *shortname, const char *source) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) + , m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, program) + , m_read_port0(*this), m_read_port1(*this), m_read_port2(*this), m_read_port3(*this), m_read_port4(*this) + , m_write_port0(*this), m_write_port1(*this), m_write_port2(*this), m_write_port3(*this), m_write_port4(*this) + { } + + // static configuration helpers + template<class _Object> static devcb_base &set_read_port0_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_read_port0.set_callback(object); } + template<class _Object> static devcb_base &set_read_port1_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_read_port1.set_callback(object); } + template<class _Object> static devcb_base &set_read_port2_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_read_port2.set_callback(object); } + template<class _Object> static devcb_base &set_read_port3_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_read_port3.set_callback(object); } + template<class _Object> static devcb_base &set_read_port4_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_read_port4.set_callback(object); } + + template<class _Object> static devcb_base &set_write_port0_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_write_port0.set_callback(object); } + template<class _Object> static devcb_base &set_write_port1_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_write_port1.set_callback(object); } + template<class _Object> static devcb_base &set_write_port2_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_write_port2.set_callback(object); } + template<class _Object> static devcb_base &set_write_port3_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_write_port3.set_callback(object); } + template<class _Object> static devcb_base &set_write_port4_callback(device_t &device, _Object object) { return downcast<mn10200_device &>(device).m_write_port4.set_callback(object); } DECLARE_READ8_MEMBER(io_control_r); DECLARE_WRITE8_MEMBER(io_control_w); @@ -76,16 +78,13 @@ protected: virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 2 - 1) / 2; } // internal /2 divider virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 2); } // internal /2 divider virtual UINT32 execute_min_cycles() const { return 1; } - virtual UINT32 execute_max_cycles() const { return 13; } + virtual UINT32 execute_max_cycles() const { return 13+7; } // max opcode cycles + interrupt duration virtual UINT32 execute_input_lines() const { return 4; } virtual void execute_run(); virtual void execute_set_input(int inputnum, int state); // device_memory_interface overrides - virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const - { - return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); - } + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } // device_state_interface overrides void state_string_export(const device_state_entry &entry, std::string &str); @@ -97,10 +96,11 @@ protected: private: address_space_config m_program_config; - address_space_config m_io_config; - address_space *m_program; - address_space *m_io; + + // i/o handlers + devcb_read8 m_read_port0, m_read_port1, m_read_port2, m_read_port3, m_read_port4; + devcb_write8 m_write_port0, m_write_port1, m_write_port2, m_write_port3, m_write_port4; int m_cycles; @@ -112,6 +112,10 @@ private: UINT16 m_mdr; // interrupts + void take_irq(int level, int group); + void check_irq(); + void check_ext_irq(); + UINT8 m_icrl[MN10200_NUM_IRQ_GROUPS]; UINT8 m_icrh[MN10200_NUM_IRQ_GROUPS]; @@ -122,6 +126,11 @@ private: bool m_possible_irq; // timers + void refresh_timer(int tmr); + void refresh_all_timers(); + int timer_tick_simple(int tmr); + TIMER_CALLBACK_MEMBER( simple_timer_cb ); + attotime m_sysclock_base; emu_timer *m_timer_timers[MN10200_NUM_TIMERS_8BIT]; @@ -185,20 +194,25 @@ private: inline void change_pc(UINT32 pc) { m_pc = pc & 0xffffff; } - void take_irq(int level, int group); - void check_irq(); - void check_ext_irq(); - void refresh_timer(int tmr); - void refresh_all_timers(); - int timer_tick_simple(int tmr); - TIMER_CALLBACK_MEMBER( simple_timer_cb ); + // opcode helpers void illegal(UINT8 prefix, UINT8 op); - UINT32 do_add(UINT32 a, UINT32 b, UINT32 c); - UINT32 do_sub(UINT32 a, UINT32 b, UINT32 c); + UINT32 do_add(UINT32 a, UINT32 b, UINT32 c = 0); + UINT32 do_sub(UINT32 a, UINT32 b, UINT32 c = 0); void test_nz16(UINT16 v); void do_jsr(UINT32 to, UINT32 ret); - void do_branch(bool state); + void do_branch(int condition = 1); }; -#endif +class mn1020012a_device : public mn10200_device +{ +public: + mn1020012a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + + +extern const device_type MN1020012A; + + +#endif // MN10200_H diff --git a/src/emu/cpu/pdp1/pdp1.c b/src/emu/cpu/pdp1/pdp1.c index 3c414bd5ed6..bb7beee4128 100644 --- a/src/emu/cpu/pdp1/pdp1.c +++ b/src/emu/cpu/pdp1/pdp1.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /* * Note: Original Java source written by: diff --git a/src/emu/cpu/pdp1/pdp1.h b/src/emu/cpu/pdp1/pdp1.h index c4c9c8c465e..f4d1281aa07 100644 --- a/src/emu/cpu/pdp1/pdp1.h +++ b/src/emu/cpu/pdp1/pdp1.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet #pragma once diff --git a/src/emu/cpu/pdp1/pdp1dasm.c b/src/emu/cpu/pdp1/pdp1dasm.c index 036aa3e2f22..c8682ca1491 100644 --- a/src/emu/cpu/pdp1/pdp1dasm.c +++ b/src/emu/cpu/pdp1/pdp1dasm.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet #include "emu.h" #include "cpu/pdp1/pdp1.h" diff --git a/src/emu/cpu/pdp1/tx0.c b/src/emu/cpu/pdp1/tx0.c index 1a3ab230f4b..03c8441d88f 100644 --- a/src/emu/cpu/pdp1/tx0.c +++ b/src/emu/cpu/pdp1/tx0.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /* TX-0 emulator diff --git a/src/emu/cpu/pdp1/tx0.h b/src/emu/cpu/pdp1/tx0.h index bdb492bbfc3..e88172bc8ff 100644 --- a/src/emu/cpu/pdp1/tx0.h +++ b/src/emu/cpu/pdp1/tx0.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet #pragma once diff --git a/src/emu/cpu/pdp1/tx0dasm.c b/src/emu/cpu/pdp1/tx0dasm.c index 8eef06f832e..3d8a1daf9e1 100644 --- a/src/emu/cpu/pdp1/tx0dasm.c +++ b/src/emu/cpu/pdp1/tx0dasm.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet #include "emu.h" #include "cpu/pdp1/tx0.h" diff --git a/src/emu/cpu/pic16c62x/pic16c62x.c b/src/emu/cpu/pic16c62x/pic16c62x.c index 42e92b0addf..1d2dae52b95 100644 --- a/src/emu/cpu/pic16c62x/pic16c62x.c +++ b/src/emu/cpu/pic16c62x/pic16c62x.c @@ -57,6 +57,15 @@ #include "pic16c62x.h" +const device_type PIC16C620 = &device_creator<pic16c620_device>; +const device_type PIC16C620A = &device_creator<pic16c620a_device>; +const device_type PIC16C621 = &device_creator<pic16c621_device>; +const device_type PIC16C621A = &device_creator<pic16c621a_device>; +const device_type PIC16C622 = &device_creator<pic16c622_device>; +const device_type PIC16C622A = &device_creator<pic16c622a_device>; + + + /**************************************************************************** * Internal Memory Map ****************************************************************************/ diff --git a/src/emu/cpu/rsp/rspcp2.c b/src/emu/cpu/rsp/rspcp2.c index 8371583c948..c7d15bec393 100644 --- a/src/emu/cpu/rsp/rspcp2.c +++ b/src/emu/cpu/rsp/rspcp2.c @@ -131,6 +131,7 @@ rsp_cop2::rsp_cop2(rsp_device &rsp, running_machine &machine) memset(m_v, 0, sizeof(m_v)); memset(m_vflag, 0, sizeof(m_vflag)); memset(m_accum, 0, sizeof(m_accum)); + m_rspcop2_state = (internal_rspcop2_state *)rsp.m_cache.alloc_near(sizeof(internal_rspcop2_state)); } rsp_cop2::~rsp_cop2() @@ -2567,7 +2568,7 @@ void rsp_cop2::handle_cop2(UINT32 op) inline void rsp_cop2::mfc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int el = (op >> 7) & 0xf; UINT16 b1 = VREG_B(VS1REG, (el+0) & 0xf); @@ -2577,7 +2578,7 @@ inline void rsp_cop2::mfc2() inline void rsp_cop2::cfc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; if (RTREG) { switch(RDREG) @@ -2636,7 +2637,7 @@ inline void rsp_cop2::cfc2() inline void rsp_cop2::mtc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int el = (op >> 7) & 0xf; VREG_B(VS1REG, (el+0) & 0xf) = (RTVAL >> 8) & 0xff; VREG_B(VS1REG, (el+1) & 0xf) = (RTVAL >> 0) & 0xff; @@ -2644,7 +2645,7 @@ inline void rsp_cop2::mtc2() inline void rsp_cop2::ctc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; switch(RDREG) { case 0: diff --git a/src/emu/cpu/rsp/rspcp2.h b/src/emu/cpu/rsp/rspcp2.h index 15857bd687c..18e9d59fbff 100644 --- a/src/emu/cpu/rsp/rspcp2.h +++ b/src/emu/cpu/rsp/rspcp2.h @@ -135,8 +135,13 @@ protected: UINT16 SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive); UINT16 SATURATE_ACCUM1(int accum, UINT16 negative, UINT16 positive); - UINT32 m_op; + // Data that needs to be stored close to the generated DRC code + struct internal_rspcop2_state + { + UINT32 op; + }; + internal_rspcop2_state *m_rspcop2_state; rsp_device& m_rsp; running_machine& m_machine; UINT32 m_vres[8]; /* used for temporary vector results */ diff --git a/src/emu/cpu/rsp/rspcp2d.c b/src/emu/cpu/rsp/rspcp2d.c index 3a5ca09b9ee..779fea5819c 100644 --- a/src/emu/cpu/rsp/rspcp2d.c +++ b/src/emu/cpu/rsp/rspcp2d.c @@ -94,7 +94,7 @@ static void cfunc_ctc2(void *param); #define CLEAR_CLIP2_FLAG(x) { m_vflag[CLIP2][x & 7] = 0; } #define CACHE_VALUES() \ - const int op = m_op; \ + const int op = m_rspcop2_state->op; \ const int vdreg = VDREG; \ const int vs1reg = VS1REG; \ const int vs2reg = VS2REG; \ @@ -137,10 +137,10 @@ void rsp_cop2_drc::cfunc_unimplemented_opcode() if ((m_machine.debug_flags & DEBUG_FLAG_ENABLED) != 0) { char string[200]; - rsp_dasm_one(string, ppc, m_op); + rsp_dasm_one(string, ppc, m_rspcop2_state->op); osd_printf_debug("%08X: %s\n", ppc, string); } - fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", m_op >> 26, m_op, ppc); + fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", m_rspcop2_state->op >> 26, m_rspcop2_state->op, ppc); } static void unimplemented_opcode(void *param) @@ -267,7 +267,7 @@ void rsp_cop2_drc::state_string_export(const int index, std::string &str) void rsp_cop2_drc::lbv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; UINT32 ea = 0; int dest = (op >> 16) & 0x1f; @@ -300,7 +300,7 @@ static void cfunc_lbv(void *param) void rsp_cop2_drc::lsv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xe; @@ -336,7 +336,7 @@ static void cfunc_lsv(void *param) void rsp_cop2_drc::llv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; UINT32 ea = 0; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; @@ -375,7 +375,7 @@ static void cfunc_llv(void *param) void rsp_cop2_drc::ldv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; UINT32 ea = 0; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; @@ -414,7 +414,7 @@ static void cfunc_ldv(void *param) void rsp_cop2_drc::lqv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int offset = (op & 0x7f); @@ -452,7 +452,7 @@ static void cfunc_lqv(void *param) void rsp_cop2_drc::lrv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -491,7 +491,7 @@ static void cfunc_lrv(void *param) void rsp_cop2_drc::lpv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -526,7 +526,7 @@ static void cfunc_lpv(void *param) void rsp_cop2_drc::luv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -561,7 +561,7 @@ static void cfunc_luv(void *param) void rsp_cop2_drc::lhv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -595,7 +595,7 @@ static void cfunc_lhv(void *param) void rsp_cop2_drc::lfv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -636,7 +636,7 @@ static void cfunc_lfv(void *param) void rsp_cop2_drc::lwv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -673,7 +673,7 @@ static void cfunc_lwv(void *param) void rsp_cop2_drc::ltv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -720,62 +720,62 @@ int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state switch ((op >> 11) & 0x1f) { case 0x00: /* LBV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lbv, this); return TRUE; case 0x01: /* LSV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lsv, this); return TRUE; case 0x02: /* LLV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_llv, this); return TRUE; case 0x03: /* LDV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_ldv, this); return TRUE; case 0x04: /* LQV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lqv, this); return TRUE; case 0x05: /* LRV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lrv, this); return TRUE; case 0x06: /* LPV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lpv, this); return TRUE; case 0x07: /* LUV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_luv, this); return TRUE; case 0x08: /* LHV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lhv, this); return TRUE; case 0x09: /* LFV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lfv, this); return TRUE; case 0x0a: /* LWV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_lwv, this); return TRUE; case 0x0b: /* LTV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [m_op],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l UML_CALLC(block, cfunc_ltv, this); return TRUE; @@ -800,7 +800,7 @@ int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state void rsp_cop2_drc::sbv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -831,7 +831,7 @@ static void cfunc_sbv(void *param) void rsp_cop2_drc::ssv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -868,7 +868,7 @@ static void cfunc_ssv(void *param) void rsp_cop2_drc::slv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -905,7 +905,7 @@ static void cfunc_slv(void *param) void rsp_cop2_drc::sdv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0x8; @@ -941,7 +941,7 @@ static void cfunc_sdv(void *param) void rsp_cop2_drc::sqv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -977,7 +977,7 @@ static void cfunc_sqv(void *param) void rsp_cop2_drc::srv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1017,7 +1017,7 @@ static void cfunc_srv(void *param) void rsp_cop2_drc::spv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1060,7 +1060,7 @@ static void cfunc_spv(void *param) void rsp_cop2_drc::suv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1103,7 +1103,7 @@ static void cfunc_suv(void *param) void rsp_cop2_drc::shv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1141,7 +1141,7 @@ static void cfunc_shv(void *param) void rsp_cop2_drc::sfv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1182,7 +1182,7 @@ static void cfunc_sfv(void *param) void rsp_cop2_drc::swv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1221,7 +1221,7 @@ static void cfunc_swv(void *param) void rsp_cop2_drc::stv() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int dest = (op >> 16) & 0x1f; int base = (op >> 21) & 0x1f; int index = (op >> 7) & 0xf; @@ -1270,62 +1270,62 @@ int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state switch ((op >> 11) & 0x1f) { case 0x00: /* SBV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_sbv, this); return TRUE; case 0x01: /* SSV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_ssv, this); return TRUE; case 0x02: /* SLV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_slv, this); return TRUE; case 0x03: /* SDV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_sdv, this); return TRUE; case 0x04: /* SQV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_sqv, this); return TRUE; case 0x05: /* SRV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_srv, this); return TRUE; case 0x06: /* SPV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_spv, this); return TRUE; case 0x07: /* SUV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_suv, this); return TRUE; case 0x08: /* SHV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_shv, this); return TRUE; case 0x09: /* SFV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_sfv, this); return TRUE; case 0x0a: /* SWV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_swv, this); return TRUE; case 0x0b: /* STV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_stv, this); return TRUE; @@ -2079,7 +2079,7 @@ static void cfunc_vaddb(void *param) void rsp_cop2_drc::vsaw() { - const int op = m_op; + const int op = m_rspcop2_state->op; const int vdreg = VDREG; const int el = EL; @@ -3264,217 +3264,217 @@ int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compil switch (op & 0x3f) { case 0x00: /* VMULF */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmulf, this); return TRUE; case 0x01: /* VMULU */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmulu, this); return TRUE; case 0x04: /* VMUDL */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmudl, this); return TRUE; case 0x05: /* VMUDM */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmudm, this); return TRUE; case 0x06: /* VMUDN */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmudn, this); return TRUE; case 0x07: /* VMUDH */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmudh, this); return TRUE; case 0x08: /* VMACF */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmacf, this); return TRUE; case 0x09: /* VMACU */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmacu, this); return TRUE; case 0x0c: /* VMADL */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmadl, this); return TRUE; case 0x0d: /* VMADM */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmadm, this); return TRUE; case 0x0e: /* VMADN */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmadn, this); return TRUE; case 0x0f: /* VMADH */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmadh, this); return TRUE; case 0x10: /* VADD */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vadd, this); return TRUE; case 0x11: /* VSUB */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vsub, this); return TRUE; case 0x13: /* VABS */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vabs, this); return TRUE; case 0x14: /* VADDC */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vaddc, this); return TRUE; case 0x15: /* VSUBC */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vsubc, this); return TRUE; case 0x16: /* VADDB */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vaddb, this); return TRUE; case 0x17: /* VSUBB (reserved, functionally identical to VADDB) */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vaddb, this); return TRUE; case 0x18: /* VACCB (reserved, functionally identical to VADDB) */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vaddb, this); return TRUE; case 0x19: /* VSUCB (reserved, functionally identical to VADDB) */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vaddb, this); return TRUE; case 0x1d: /* VSAW */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vsaw, this); return TRUE; case 0x20: /* VLT */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vlt, this); return TRUE; case 0x21: /* VEQ */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_veq, this); return TRUE; case 0x22: /* VNE */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vne, this); return TRUE; case 0x23: /* VGE */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vge, this); return TRUE; case 0x24: /* VCL */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vcl, this); return TRUE; case 0x25: /* VCH */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vch, this); return TRUE; case 0x26: /* VCR */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vcr, this); return TRUE; case 0x27: /* VMRG */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmrg, this); return TRUE; case 0x28: /* VAND */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vand, this); return TRUE; case 0x29: /* VNAND */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vnand, this); return TRUE; case 0x2a: /* VOR */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vor, this); return TRUE; case 0x2b: /* VNOR */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vnor, this); return TRUE; case 0x2c: /* VXOR */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vxor, this); return TRUE; case 0x2d: /* VNXOR */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vnxor, this); return TRUE; case 0x30: /* VRCP */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vrcp, this); return TRUE; case 0x31: /* VRCPL */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vrcpl, this); return TRUE; case 0x32: /* VRCPH */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vrcph, this); return TRUE; case 0x33: /* VMOV */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vmov, this); return TRUE; case 0x34: /* VRSQ */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vrsq, this); return TRUE; case 0x35: /* VRSQL */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vrsql, this); return TRUE; case 0x36: /* VRSQH */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_vrsqh, this); return TRUE; @@ -3483,7 +3483,7 @@ int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compil return TRUE; default: - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, unimplemented_opcode, &m_rsp); return FALSE; } @@ -3496,7 +3496,7 @@ int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compil void rsp_cop2_drc::mfc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int el = (op >> 7) & 0xf; UINT16 b1 = VREG_B(VS1REG, (el+0) & 0xf); @@ -3511,7 +3511,7 @@ static void cfunc_mfc2(void *param) void rsp_cop2_drc::cfc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; if (RTREG) { switch(RDREG) @@ -3576,7 +3576,7 @@ static void cfunc_cfc2(void *param) void rsp_cop2_drc::mtc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; int el = (op >> 7) & 0xf; VREG_B(VS1REG, (el+0) & 0xf) = (RTVAL >> 8) & 0xff; VREG_B(VS1REG, (el+1) & 0xf) = (RTVAL >> 0) & 0xff; @@ -3590,7 +3590,7 @@ static void cfunc_mtc2(void *param) void rsp_cop2_drc::ctc2() { - UINT32 op = m_op; + UINT32 op = m_rspcop2_state->op; switch(RDREG) { case 0: @@ -3706,7 +3706,7 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state case 0x00: /* MFCz */ if (RTREG != 0) { - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_mfc2, this); // callc mfc2 } return TRUE; @@ -3714,18 +3714,18 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state case 0x02: /* CFCz */ if (RTREG != 0) { - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_cfc2, this); // callc cfc2 } return TRUE; case 0x04: /* MTCz */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_mtc2, this); // callc mtc2 return TRUE; case 0x06: /* CTCz */ - UML_MOV(block, mem(&m_op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l UML_CALLC(block, cfunc_ctc2, this); // callc ctc2 return TRUE; diff --git a/src/emu/cpu/sc61860/sc61860.c b/src/emu/cpu/sc61860/sc61860.c index d0006cb4f23..a36c02a658a 100644 --- a/src/emu/cpu/sc61860/sc61860.c +++ b/src/emu/cpu/sc61860/sc61860.c @@ -8,18 +8,6 @@ * * Copyright Peter Trauner, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * peter.trauner@jk.uni-linz.ac.at - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * History of changes: * 29.7.2001 Several changes listed below taken by Mario Konegger * (konegger@itp.tu-graz.ac.at) diff --git a/src/emu/cpu/sc61860/sc61860.h b/src/emu/cpu/sc61860/sc61860.h index 51791715fcd..e34197f83f9 100644 --- a/src/emu/cpu/sc61860/sc61860.h +++ b/src/emu/cpu/sc61860/sc61860.h @@ -8,18 +8,6 @@ * * Copyright Peter Trauner, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * peter.trauner@jk.uni-linz.ac.at - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * *****************************************************************************/ #pragma once diff --git a/src/emu/cpu/sc61860/scdasm.c b/src/emu/cpu/sc61860/scdasm.c index 8d7cc3ad43e..047ba7fae30 100644 --- a/src/emu/cpu/sc61860/scdasm.c +++ b/src/emu/cpu/sc61860/scdasm.c @@ -8,18 +8,6 @@ * * Copyright Peter Trauner, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * peter.trauner@jk.uni-linz.ac.at - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * *****************************************************************************/ #include "emu.h" diff --git a/src/emu/cpu/sc61860/scops.inc b/src/emu/cpu/sc61860/scops.inc index a432d5a4c5f..bde6edd53e1 100644 --- a/src/emu/cpu/sc61860/scops.inc +++ b/src/emu/cpu/sc61860/scops.inc @@ -8,18 +8,6 @@ * * Copyright Peter Trauner, all rights reserved. * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * peter.trauner@jk.uni-linz.ac.at - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * * History of changes: * 21.07.2001 Several changes listed below were made by Mario Konegger * (konegger@itp.tu-graz.ac.at) diff --git a/src/emu/cpu/scudsp/scudsp.c b/src/emu/cpu/scudsp/scudsp.c index 887c94cec1b..14d1565caa2 100644 --- a/src/emu/cpu/scudsp/scudsp.c +++ b/src/emu/cpu/scudsp/scudsp.c @@ -7,17 +7,6 @@ * * copyright Angelo Salese & Mariusz Wojcieszek, all rights reserved * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * lordkale@libero.it or <insert_marusz_wojcieszek_mail_here> - * - This entire notice must remain in the source code. - * - * * Changelog: * 131010: Angelo Salese * - Converted to CPU structure diff --git a/src/emu/cpu/ssp1601/ssp1601.c b/src/emu/cpu/ssp1601/ssp1601.c index e9a5f39ac1c..94720fd7e73 100644 --- a/src/emu/cpu/ssp1601/ssp1601.c +++ b/src/emu/cpu/ssp1601/ssp1601.c @@ -1,4 +1,4 @@ -// license:BSD-3-Clause +// license:??? // copyright-holders:Pierpaolo Prazzoli,Grazvydas Ignotas /* * Samsung SSP1601 DSP emulator diff --git a/src/emu/cpu/tms0980/tms0980.c b/src/emu/cpu/tms0980/tms0980.c index 50f61788086..8275f09d815 100644 --- a/src/emu/cpu/tms0980/tms0980.c +++ b/src/emu/cpu/tms0980/tms0980.c @@ -187,6 +187,7 @@ const device_type TMS0270 = &device_creator<tms0270_cpu_device>; // 40-pin DIP, // TMS0260 is similar? except opla is 32 instead of 48 terms +// internal memory maps static ADDRESS_MAP_START(program_11bit_9, AS_PROGRAM, 16, tms1xxx_cpu_device) AM_RANGE(0x000, 0xfff) AM_ROM ADDRESS_MAP_END @@ -218,8 +219,9 @@ static ADDRESS_MAP_START(data_64x9_as4, AS_DATA, 8, tms1xxx_cpu_device) ADDRESS_MAP_END +// device definitions tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : tms1xxx_cpu_device(mconfig, TMS1000, "TMS1000", tag, owner, clock, 8, 11, 6, 8, 2, 10, ADDRESS_MAP_NAME(program_10bit_8), 6, ADDRESS_MAP_NAME(data_64x4), "tms1000", __FILE__) + : tms1xxx_cpu_device(mconfig, TMS1000, "TMS1000", tag, owner, clock, 8 /* o pins */, 11 /* r pins */, 6 /* pc bits */, 8 /* byte width */, 2 /* x width */, 10 /* prg width */, ADDRESS_MAP_NAME(program_10bit_8), 6 /* data width */, ADDRESS_MAP_NAME(data_64x4), "tms1000", __FILE__) { } tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source) @@ -316,7 +318,7 @@ tms0270_cpu_device::tms0270_cpu_device(const machine_config &mconfig, const char { } - +// machine configs static MACHINE_CONFIG_FRAGMENT(tms1000) // microinstructions PLA, output PLA @@ -402,7 +404,7 @@ machine_config_constructor tms0270_cpu_device::device_mconfig_additions() const } - +// disasm offs_t tms1000_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { extern CPU_DISASSEMBLE(tms1000); @@ -448,16 +450,17 @@ void tms1xxx_cpu_device::device_start() m_program = &space(AS_PROGRAM); m_data = &space(AS_DATA); - m_read_k.resolve_safe(0); - m_write_o.resolve_safe(); - m_write_r.resolve_safe(); - m_power_off.resolve_safe(); - m_o_mask = (1 << m_o_pins) - 1; m_r_mask = (1 << m_r_pins) - 1; m_pc_mask = (1 << m_pc_bits) - 1; m_x_mask = (1 << m_x_bits) - 1; + // resolve callbacks + m_read_k.resolve_safe(0); + m_write_o.resolve_safe(); + m_write_r.resolve_safe(); + m_power_off.resolve_safe(); + // zerofill m_pc = 0; m_sr = 0; diff --git a/src/emu/cpu/tms9900/9900dasm.c b/src/emu/cpu/tms9900/9900dasm.c index 010908290ed..7b3153e6c4c 100644 --- a/src/emu/cpu/tms9900/9900dasm.c +++ b/src/emu/cpu/tms9900/9900dasm.c @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /***************************************************************************** * diff --git a/src/emu/cpu/tms9900/99xxcore.h b/src/emu/cpu/tms9900/99xxcore.h index 794be20fcb4..cb94fac286f 100644 --- a/src/emu/cpu/tms9900/99xxcore.h +++ b/src/emu/cpu/tms9900/99xxcore.h @@ -1,4 +1,4 @@ -// license:??? +// license:BSD-3-Clause // copyright-holders:Raphael Nabet /*************************************************************************** diff --git a/src/emu/cpu/ucom4/ucom4.c b/src/emu/cpu/ucom4/ucom4.c index 11d1513ed03..ceb074728e5 100644 --- a/src/emu/cpu/ucom4/ucom4.c +++ b/src/emu/cpu/ucom4/ucom4.c @@ -62,7 +62,7 @@ ADDRESS_MAP_END // device definitions upd553_cpu_device::upd553_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : ucom4_cpu_device(mconfig, NEC_D553, "uPD553", tag, owner, clock, NEC_UCOM43, 3, 11, ADDRESS_MAP_NAME(program_2k), 7, ADDRESS_MAP_NAME(data_96x4), "upd553", __FILE__) + : ucom4_cpu_device(mconfig, NEC_D553, "uPD553", tag, owner, clock, NEC_UCOM43, 3 /* stack levels */, 11 /* prg width */, ADDRESS_MAP_NAME(program_2k), 7 /* data width */, ADDRESS_MAP_NAME(data_96x4), "upd553", __FILE__) { } upd650_cpu_device::upd650_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) @@ -124,6 +124,7 @@ void ucom4_cpu_device::device_start() m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(ucom4_cpu_device::simple_timer_cb), this)); + // resolve callbacks m_read_a.resolve_safe(0xf); m_read_b.resolve_safe(0xf); m_read_c.resolve_safe(0xf); |