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Diffstat (limited to 'src/devices/machine/68230pit.cpp')
-rw-r--r--src/devices/machine/68230pit.cpp188
1 files changed, 94 insertions, 94 deletions
diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp
index fe84888ffbf..ed9cfee7327 100644
--- a/src/devices/machine/68230pit.cpp
+++ b/src/devices/machine/68230pit.cpp
@@ -46,7 +46,7 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
//-------------------------------------------------
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
- device_execute_interface (mconfig, *this)
+ device_execute_interface (mconfig, *this)
, m_icount (0)
, m_pa_out_cb(*this)
, m_pa_in_cb(*this)
@@ -70,9 +70,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_psr(0)
, m_tcr(0)
, m_cpr(0)
- // , m_cprh(0)
- // , m_cprm(0)
- // , m_cprl(0)
+ // , m_cprh(0)
+ // , m_cprm(0)
+ // , m_cprl(0)
, m_cntr(0)
{
}
@@ -80,7 +80,7 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
- device_execute_interface (mconfig, *this)
+ device_execute_interface (mconfig, *this)
, m_icount (0)
, m_pa_out_cb (*this)
, m_pa_in_cb(*this)
@@ -104,9 +104,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_psr(0)
, m_tcr(0)
, m_cpr(0)
- // , m_cprh(0)
- // , m_cprm(0)
- // , m_cprl(0)
+ // , m_cprh(0)
+ // , m_cprm(0)
+ // , m_cprl(0)
, m_cntr(0)
{
}
@@ -263,70 +263,70 @@ void pit68230_device::wr_pitreg_psr(UINT8 data)
/* The timer control register (TCR) determines all operations of the timer. Bits 7-5 configure the PC3/TOUT
and PC7/TIACKpins for port C, square wave, vectored interrupt, or autovectored interrupt operation bit
-4 specifies whether the counter receives data from the counter preload register or continues counting when
-zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
-and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
-at all times. All bits are cleared to zero when the RESET pin is asserted.
+4 specifies whether the counter receives data from the counter preload register or continues counting when
+zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
+and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
+at all times. All bits are cleared to zero when the RESET pin is asserted.
TCR bits
7 6 5 TOUT/TIACK Control
----------------------------
- 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
- 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
- output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
- pin PC7/TIACK carries the PC7 function.
- 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
- a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
- The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
- negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
- 5.1.3. Timer Interrupt Acknowledge Cycles for details.
- 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
- The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
- input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
- supports vectored timer interrupts.
- 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
- request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
- pin PC7/TIACK carries the PC7 function.
- 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
- The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
+ 0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
+ 0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
+ output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
+ pin PC7/TIACK carries the PC7 function.
+ 1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
+ a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
+ The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
+ negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
+ 5.1.3. Timer Interrupt Acknowledge Cycles for details.
+ 1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
+ The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
+ input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
+ supports vectored timer interrupts.
+ 1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
+ request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
+ pin PC7/TIACK carries the PC7 function.
+ 1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
+ The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
TCR bit 4 - Zero Detect Control
- 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
- zero detect, then resumes counting.
- 1 The counter rolls over on zero detect, then continues counting.
+ 0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
+ zero detect, then resumes counting.
+ 1 The counter rolls over on zero detect, then continues counting.
TCR bit 3 - Unused and is always read as zero.
TCR bits
2 1 Clock Control
0 0 The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The
- prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
- rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
- to $1F. The timer enable bit determines whether the timer is in the run or halt state.
- 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
- is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
- over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
- The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
- the timer is in the halt state.
- 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
- following the rising transition of the TIN pin after being synchronized with the internal clock. The
- 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
- prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
- run or halt state.
- 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
- rolls over, or is loaded from the counter preload registers following the rising edge of
- the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
- the timer is in the run or halt state.
+ prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
+ rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
+ to $1F. The timer enable bit determines whether the timer is in the run or halt state.
+ 0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
+ is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
+ over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
+ The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
+ the timer is in the halt state.
+ 1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
+ following the rising transition of the TIN pin after being synchronized with the internal clock. The
+ 24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
+ prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
+ run or halt state.
+ 1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
+ rolls over, or is loaded from the counter preload registers following the rising edge of
+ the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
+ the timer is in the run or halt state.
TCR bit 0 - Timer Enable
- 0 Disabled
- 1 Enabled
+ 0 Disabled
+ 1 Enabled
*/
void pit68230_device::wr_pitreg_tcr(UINT8 data)
{
- LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
- FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
+ LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
+ FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
m_tcr = data;
}
@@ -335,7 +335,7 @@ void pit68230_device::wr_pitreg_cprh(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0xff0000;
m_cpr |= ((data << 16) & 0xff0000);
- // m_cprh = data;
+ // m_cprh = data;
}
void pit68230_device::wr_pitreg_cprm(UINT8 data)
@@ -343,7 +343,7 @@ void pit68230_device::wr_pitreg_cprm(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x00ff00;
m_cpr |= ((data << 8) & 0x00ff00);
- // m_cprm = data;
+ // m_cprm = data;
}
void pit68230_device::wr_pitreg_cprl(UINT8 data)
@@ -351,28 +351,28 @@ void pit68230_device::wr_pitreg_cprl(UINT8 data)
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_cpr &= ~0x0000ff;
m_cpr |= ((data << 0) & 0x0000ff);
- // m_cprl = data;
+ // m_cprl = data;
}
WRITE8_MEMBER (pit68230_device::write)
{
LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) {
- case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
- case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
- case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
- case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
- case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
- case PIT_68230_PACR: wr_pitreg_pacr(data); break;
- case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
- case PIT_68230_PADR: wr_pitreg_padr(data); break;
- case PIT_68230_PAAR: break; // RO register so ignored
- case PIT_68230_PBAR: break; // RO register so ignored
- case PIT_68230_PSR: wr_pitreg_psr(data); break;
- case PIT_68230_TCR: wr_pitreg_tcr(data); break;
- case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
- case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
- case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
+ case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
+ case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
+ case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
+ case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
+ case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
+ case PIT_68230_PACR: wr_pitreg_pacr(data); break;
+ case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
+ case PIT_68230_PADR: wr_pitreg_padr(data); break;
+ case PIT_68230_PAAR: break; // RO register so ignored
+ case PIT_68230_PBAR: break; // RO register so ignored
+ case PIT_68230_PSR: wr_pitreg_psr(data); break;
+ case PIT_68230_TCR: wr_pitreg_tcr(data); break;
+ case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
+ case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
+ case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
default:
LOG (("Unhandled Write of %02x to register %02x", data, offset));
}
@@ -458,22 +458,22 @@ UINT8 pit68230_device::rr_pitreg_pbdr()
return m_pbdr;
}
-/* The port A alternate register is an alternate register for reading the port A pins.
+/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
-the instantaneous pin level is read and no input latching is performed except at the
+the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_paar()
{
- // NOTE: no side effect emulated so using ..padr
+ // NOTE: no side effect emulated so using ..padr
UINT8 ret;
ret = m_pa_in_cb();
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
return ret;
}
-/* The port B alternate register is an alternate register for reading the port B pins.
+/* The port B alternate register is an alternate register for reading the port B pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
-the instantaneous pin level is read and no input latching is performed except at the
+the instantaneous pin level is read and no input latching is performed except at the
data bus interface.Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_pbar()
{
@@ -518,21 +518,21 @@ READ8_MEMBER (pit68230_device::read){
UINT8 data;
switch (offset) {
- case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
- case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
- case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
- case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
- case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
- case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
- case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
- case PIT_68230_PADR: data = rr_pitreg_padr(); break;
- case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
- case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
- case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
- case PIT_68230_PSR: data = rr_pitreg_psr(); break;
- case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
- case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
- case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
+ case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
+ case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
+ case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
+ case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
+ case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
+ case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
+ case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
+ case PIT_68230_PADR: data = rr_pitreg_padr(); break;
+ case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
+ case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
+ case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
+ case PIT_68230_PSR: data = rr_pitreg_psr(); break;
+ case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
+ case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
+ case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
default:
LOG (("Unhandled read register %02x\n", offset));
data = 0;