diff options
Diffstat (limited to 'src/devices/cpu/unsp/unsp_extended.cpp')
-rw-r--r-- | src/devices/cpu/unsp/unsp_extended.cpp | 1140 |
1 files changed, 108 insertions, 1032 deletions
diff --git a/src/devices/cpu/unsp/unsp_extended.cpp b/src/devices/cpu/unsp/unsp_extended.cpp index a3986d124b8..44f2a2d263d 100644 --- a/src/devices/cpu/unsp/unsp_extended.cpp +++ b/src/devices/cpu/unsp/unsp_extended.cpp @@ -9,6 +9,10 @@ #include "unspdasm.h" +// TODO: the call conventions and general use of 'do_basic_alu_ops' from unsp_other.cpp could be cleaned up +// at the moment things like the 'Store' opcode make things more complex than they need to be, and require +// the passing of a store address each time, they make the regular use of the code a little awkward too tho. + void unsp_device::execute_extended_group(uint16_t op) { // shouldn't get here anyway @@ -26,122 +30,27 @@ void unsp_20_device::execute_extended_group(uint16_t op) { case 0x00: case 0x10: { - // Ext Register Ra = Ra op Rb + // Ext Register + // Ra = Ra op Rb + // A = B op C uint8_t aluop = (ximm & 0xf000) >> 12; uint8_t rb = (ximm & 0x000f) >> 0; uint8_t ra = (ximm & 0x0e00) >> 9; ra |= (ximm & 0x0100) >> 5; - switch (aluop) - { - case 0x00: // add - // A += B - logerror( "(Extended group 0) %s += %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x01: // adc - // A += B, Carry - logerror( "(Extended group 0) %s += %s, carry\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x02: // sub - // A -= B - logerror( "(Extended group 0) %s -= %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x03: // sbc - // A -= B, Carry - logerror( "(Extended group 0) %s -= %s, carry\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x04: // cmp - // CMP A,B - logerror( "(Extended group 0) cmp %s, %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x06: // neg - // A = -B - logerror( "(Extended group 0) %s = -%s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x08: // xor - // A ^= B - logerror( "(Extended group 0) %s ^= %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; + uint16_t b = m_core->m_r[ra]; + uint16_t c = m_core->m_r[rb]; + uint32_t lres; + uint32_t storeaddr = b; // dest address for STORE - case 0x09: // load - // A = B - logerror( "(Extended group 0) %s = %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; + bool write = do_basic_alu_ops(aluop, lres, b, c, storeaddr, (ra != 7)); - case 0x0a: // or - // A |= B - logerror( "(Extended group 0) %s |= %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0b: // and - // A &= B - logerror( "(Extended group 0) %s &= %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0c: // test - // TEST A,B - logerror( "(Extended group 0) test %s, %s\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0d: // store - // B = A - logerror( "(Extended group 0) %s = %s\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 0) <INVALID Ra = Ra op Rb form>\n"); - unimplemented_opcode(op, ximm); - return; - break; + if (write) + { + // a = Ra + m_core->m_r[ra] = (uint16_t)lres; } - - unimplemented_opcode(op, ximm); return; } case 0x02: @@ -151,8 +60,6 @@ void unsp_20_device::execute_extended_group(uint16_t op) // Ext Push/Pop if (ximm & 0x8000) { - // just skip for now, as nothing really even uses the extended registers yet - uint8_t rb = (ximm & 0x000f) >> 0; uint8_t size = (ximm & 0x7000) >> 12; uint8_t rx = (ximm & 0x0e00) >> 9; @@ -166,10 +73,7 @@ void unsp_20_device::execute_extended_group(uint16_t op) while (size--) { - if (rb & 0x8) - push(m_secondary_r[rx--], &m_secondary_r[rb & 0x7]); - else - push(m_secondary_r[rx--], &m_core->m_r[rb & 0x7]); + push(m_core->m_r[(rx--) + 8], &m_core->m_r[rb]); } } else @@ -177,7 +81,7 @@ void unsp_20_device::execute_extended_group(uint16_t op) logerror("(Ext) push <BAD>\n"); unimplemented_opcode(op, ximm); } - + return; } else @@ -192,15 +96,15 @@ void unsp_20_device::execute_extended_group(uint16_t op) if ((rx - (size - 1)) >= 0) { //logerror("(Ext) pop %s, %s from [%s]\n", - // extregs[rx - size], extregs[rx], (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); + // extregs[rx - size], extregs[rx], (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); int realrx = 7 - rx; while (size--) { if (rb & 0x8) - m_secondary_r[realrx++] = pop(&m_secondary_r[rb & 0x07]); + m_core->m_r[(realrx++) + 8] = pop(&m_core->m_r[(rb & 0x07) + 8]); else - m_secondary_r[realrx++] = pop(&m_core->m_r[rb & 0x07]); + m_core->m_r[(realrx++) + 8] = pop(&m_core->m_r[rb & 0x07]); } } else @@ -219,135 +123,33 @@ void unsp_20_device::execute_extended_group(uint16_t op) uint16_t imm16_2 = read16(UNSP_LPC); add_lpc(1); - // Ra=Rb op IMM16 + // Ra = Rb op IMM16 + // A = B op C + uint8_t aluop = (ximm & 0xf000) >> 12; uint8_t rb = (ximm & 0x000f) >> 0; uint8_t ra = (ximm & 0x0e00) >> 9; ra |= (ximm & 0x0100) >> 5; - switch (aluop) - { - case 0x00: // add - // A = B + C - logerror( "(Extended group 1) %s = %s + %04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x01: // adc - // A = B + C, Carry - logerror( "(Extended group 1) %s = %s + %04x, carry\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x02: // sub - // A = B - C - logerror( "(Extended group 1) %s = %s - %04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x03: // sbc - // A = B - C, Carry - logerror( "(Extended group 1) %s = %s - %04x, carry\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + uint16_t b = m_core->m_r[rb]; + uint32_t lres; + uint32_t storeaddr = 0;// m_core->m_r[ra]; // dest address for STORE (invalid anyway?) - case 0x04: // cmp - // CMP B,C - logerror( "(Extended group 1) cmp %s, %04x\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x06: // neg - // A = -C - logerror( "(Extended group 1) %s = -%04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x08: // xor - // A = B ^ C - logerror( "(Extended group 1) %s = %s ^ %04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x09: // load + if (aluop == 0xd) { - // A = C - //logerror("(Extended group 1) %s = %04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - // , imm16_2); - m_core->m_icount -= 1; // TODO - - uint16_t lres = imm16_2; - update_nz(lres); - if (ra & 0x8) - { - m_secondary_r[ra & 0x7] = (uint16_t)lres; - } - else - { - m_core->m_r[ra & 0x7] = (uint16_t)lres; - } - - return; - break; - } - case 0x0a: // or - // A = B | C - logerror( "(Extended group 1) %s = %s | %04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); + // store is invalid? unimplemented_opcode(op, ximm, imm16_2); - return; - break; + } - case 0x0b: // and - // A = B & C - logerror( "(Extended group 1) %s = %s & %04x\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + bool write = do_basic_alu_ops(aluop, lres, b, imm16_2, storeaddr, (ra != 7)); - case 0x0c: // test - // TEST B,C - logerror( "(Extended group 1) test %s, %04x\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0d: // store, C = B, invalid for this mode (would store to immediate) - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 1) <INVALID Ra=Rb op IMM16 form>\n"); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + if (write) + { + // a = Ra + m_core->m_r[ra] = (uint16_t)lres; } - unimplemented_opcode(op, ximm, imm16_2); return; } @@ -357,891 +159,165 @@ void unsp_20_device::execute_extended_group(uint16_t op) uint16_t imm16_2 = read16(UNSP_LPC); add_lpc(1); - // Ra=Rb op [A16] + // Ra = Rb op [A16] + // A = B op C + uint8_t aluop = (ximm & 0xf000) >> 12; uint8_t rb = (ximm & 0x000f) >> 0; uint8_t ra = (ximm & 0x0e00) >> 9; ra |= (ximm & 0x0100) >> 5; - switch (aluop) - { - case 0x00: // add - // A = B + C - logerror( "(Extended group 2) %s = %s + [%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + uint16_t b = m_core->m_r[rb]; + uint16_t c = read16(imm16_2); + uint32_t storeaddr = imm16_2; // dest address for STORE + uint32_t lres; - case 0x01: // adc - // A = B + C, Carry - logerror( "(Extended group 2) %s = %s + [%04x], carry\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x02: // sub - // A = B - C - logerror( "(Extended group 2) %s = %s - [%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + bool write = do_basic_alu_ops(aluop, lres, b, c, storeaddr, (ra != 7)); - case 0x03: // sbc - // A = B - C, Carry - logerror( "(Extended group 2) %s = %s - [%04x], carry\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x04: // cmp - // CMP B,C - logerror( "(Extended group 2) cmp %s, [%04x]\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x06: // neg - // A = -C - logerror( "(Extended group 2) %s = -[%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x08: // xor - // A = B ^ C - logerror( "(Extended group 2) %s = %s ^ [%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x09: // load + if (write) { - // A = C - //logerror("(Extended group 2) %s = [%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - // , imm16_2); - //unimplemented_opcode(op, ximm, imm16_2); - - m_core->m_icount -= 1; // TODO - - //uin32_t lreg = UNSP_LREG_I(imm16_2); - - uint16_t lres = read16(imm16_2); - update_nz(lres); - if (ra & 0x8) - { - m_secondary_r[ra & 0x7] = (uint16_t)lres; - } - else - { - m_core->m_r[ra & 0x7] = (uint16_t)lres; - } - - return; - break; + // a = Ra + m_core->m_r[ra] = (uint16_t)lres; } - case 0x0a: // or - // A = B | C - logerror( "(Extended group 2) %s = %s | [%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0b: // and - // A = B & C - logerror( "(Extended group 2) %s = %s & [%04x]\n", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0c: // test - // TEST B,C - logerror( "(Extended group 2) test %s, [%04x]\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , imm16_2); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0d: // store - // C = B - logerror( "(Extended group 2) [%04x] = %s\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 2) <INVALID Ra = Rb op [A16] form>\n"); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - } - - unimplemented_opcode(op, ximm, imm16_2); return; } case 0x07: case 0x17: { + // this decoding / hookup might be incorrect, only seen Store used, and that the decode seems strange for that + uint16_t imm16_2 = read16(UNSP_LPC); add_lpc(1); //[A16] = Ra op Rb + // A = B op C + uint8_t aluop = (ximm & 0xf000) >> 12; uint8_t rb = (ximm & 0x000f) >> 0; uint8_t ra = (ximm & 0x0e00) >> 9; ra |= (ximm & 0x0100) >> 5; - switch (aluop) - { - case 0x00: // add - // A = B + C - logerror( "(Extended group 3) [%04x] = %s + %s\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + uint16_t a = imm16_2; + uint16_t b = m_core->m_r[ra]; + uint16_t c = m_core->m_r[rb]; + uint32_t lres; + uint32_t r2 = a; - case 0x01: // adc - // A = B + C, Carry - logerror( "(Extended group 3) [%04x] = %s + %s, carry\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + bool write = do_basic_alu_ops(aluop, lres, b, c, r2, true); - case 0x02: // sub - // A = B - C - logerror( "(Extended group 3) [%04x] = %s - %s\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x03: // sbc - // A = B - C, Carry - logerror( "(Extended group 3) [%04x] = %s - %s, carry\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x04: // cmp (is this even a valid form? [A16] not even used) - // CMP B,C - logerror( "(Extended group 3) cmp %s, %s\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x06: // neg - // A = -C - logerror( "(Extended group 3) [%04x] = -%s\n", imm16_2 - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x08: // xor - // A = B ^ C - logerror( "(Extended group 3) [%04x] = %s ^ %s\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x09: // load - // A = C - logerror( "(Extended group 3) [%04x] = %s\n", imm16_2 - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0a: // or - // A = B | C - logerror( "(Extended group 3) [%04x] = %s | %s\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0b: // and - // A = B & C - logerror( "(Extended group 3) [%04x] = %s & %s\n", imm16_2 - , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0c: // test (is this even a valid form? [A16] not even used) - // TEST B,C - logerror( "(Extended group 3) test %s, %s\n", (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] - , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7]); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; - - case 0x0d: // store (is this even a valid form? [A16] not even used if C = B form below is used, code needs to write to A) + if (write) { - // C = B - //logerror( "(Extended group 3) [%04x] = %s\n", imm16_2 - // , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); - m_core->m_icount -= 1; // TODO - - if (ra != rb) - { - logerror("(Extended group 3) store ra != rb"); - unimplemented_opcode(op, ximm, imm16_2); - } - - if (rb & 0x8) - { - write16(imm16_2, m_secondary_r[rb & 0x07]); - } - else - { - write16(imm16_2, m_core->m_r[rb & 0x07]); - } - - return; - break; - } - - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 3) <INVALID [A16] = Ra op Rb form>\n"); - unimplemented_opcode(op, ximm, imm16_2); - return; - break; + // a = [A16] + write16(imm16_2, lres); } - unimplemented_opcode(op, ximm, imm16_2); return; } case 0x08: case 0x09: { - // Ext Indirect Rx=Rx op [Ry@] - uint8_t aluop = (ximm & 0xf000) >> 12; - uint8_t ry = (ximm & 0x0007) >> 0; - uint8_t form = (ximm & 0x0018) >> 3; - uint8_t rx = (ximm & 0x0e00) >> 9; + // Ext Indirect + // Rx = Rx op [Ry@] + // A = B op C - switch (aluop) - { - case 0x00: // add - // A += B - logerror( "(Extended group 4) %s += ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x01: // adc - // A += B, Carry - logerror( "(Extended group 4) %s += ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror( ", carry"); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x02: // sub - // A -= B - logerror( "(Extended group 4) %s -= ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x03: // sbc - // A -= B, Carry - logerror( "(Extended group 4) %s -= ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror( ", carry"); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x04: // cmp - // CMP A,B - logerror( "(Extended group 4) cmp %s, ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x06: // neg - // A = -B - logerror( "(Extended group 4) %s = -", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x08: // xor - // A ^= B - logerror( "(Extended group 4) %s ^= ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x09: // load - // A = B - logerror( "(Extended group 4) %s = ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0a: // or - // A |= B - logerror( "(Extended group 4) %s |= ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0b: // and - // A &= B - logerror( "(Extended group 4) %s &= ", extregs[rx]); - logerror( forms[form], extregs[ry]); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0c: // test - // TEST A,B - logerror( "(Extended group 4) test %s, ", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0d: // store - // B = A - logerror( "(Extended group 4) "); - logerror( forms[form], extregs[ry]); - logerror( " = %s", extregs[rx]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 4) <INVALID Indirect Rx=Rx op [Ry@] form>\n"); - unimplemented_opcode(op, ximm); - return; - break; - } + //uint8_t aluop = (ximm & 0xf000) >> 12; + //uint8_t ry = (ximm & 0x0007) >> 0; + //uint8_t form = (ximm & 0x0018) >> 3; + //uint8_t rx = (ximm & 0x0e00) >> 9; + logerror("(Extended group 4 'Rx=Rx op [Ry@]' form) unimplemented "); unimplemented_opcode(op, ximm); return; } case 0x0a: case 0x0b: { // Ext DS_Indirect Rx=Rx op ds:[Ry@] - uint8_t aluop = (ximm & 0xf000) >> 12; - uint8_t ry = (ximm & 0x0007) >> 0; - uint8_t form = (ximm & 0x0018) >> 3; - uint8_t rx = (ximm & 0x0e00) >> 9; - switch (aluop) - { - case 0x00: // add - // A += B - logerror( "(Extended group 5) %s += ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x01: // adc - // A += B, Carry - logerror( "(Extended group 5) %s += ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror( ", carry"); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; + //uint8_t aluop = (ximm & 0xf000) >> 12; + //uint8_t ry = (ximm & 0x0007) >> 0; + //uint8_t form = (ximm & 0x0018) >> 3; + //uint8_t rx = (ximm & 0x0e00) >> 9; - case 0x02: // sub - // A -= B - logerror( "(Extended group 5) %s -= ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x03: // sbc - // A -= B, Carry - logerror( "(Extended group 5) %s -= ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror( ", carry"); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x04: // cmp - // CMP A,B - logerror( "(Extended group 5) cmp %s, ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x06: // neg - // A = -B - logerror( "(Extended group 5) %s = -ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x08: // xor - // A ^= B - logerror( "(Extended group 5) %s ^= ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x09: // load - // A = B - logerror( "(Extended group 5) %s = ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0a: // or - // A |= B - logerror( "(Extended group 5) %s |= ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0b: // and - // A &= B - logerror( "(Extended group 5) %s &= ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0c: // test - // TEST A,B - logerror( "(Extended group 5) test %s, ds:", extregs[rx]); - logerror( forms[form], extregs[ry]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0d: // store - // B = A - logerror( "(Extended group 5) ds:"); - logerror( forms[form], extregs[ry]); - logerror( " = %s", extregs[rx]); - logerror("\n"); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 5) <INVALID DS_Indirect Rx=Rx op ds:[Ry@] form>\n"); - unimplemented_opcode(op, ximm); - return; - break; - } + logerror("(Extended group 5 'Rx=Rx op ds:[Ry@]' form) unimplemented "); unimplemented_opcode(op, ximm); return; } case 0x18: case 0x19: case 0x1a: case 0x1b: { - // Ext IM6 Rx=Rx op IM6 + // Ext IM6 + // Rx = Rx op IM6 + // A = B op C + uint8_t aluop = (ximm & 0xf000) >> 12; uint8_t rx = (ximm & 0x0e00) >> 9; uint8_t imm6 = (ximm & 0x003f) >> 0; - switch (aluop) - { - case 0x00: // add - // A += B - logerror("(Extended group 6) %s += %02x\n", extregs[rx], imm6); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x01: // adc - // A += B, Carry - logerror("(Extended group 6) %s += %02x, carry\n", extregs[rx], imm6); - unimplemented_opcode(op, ximm); - return; - break; + uint16_t b = m_core->m_r[rx + 8]; + uint16_t c = imm6; - case 0x02: // sub - // A -= B - logerror("(Extended group 6) %s -= %02x\n", extregs[rx], imm6); - unimplemented_opcode(op, ximm); - return; - break; + uint32_t storeaddr = 0; // dest address for STORE + uint32_t lres; - case 0x03: // sbc - // A -= B, Carry - logerror("(Extended group 6) %s -= %02x, carry\n", extregs[rx], imm6); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x04: // cmp + if (aluop == 0xd) { - // CMP A,B - //logerror("(Extended group 6) cmp %s, %02x\n", extregs[rx], imm6); - - m_core->m_icount -= 1; // TODO - - uint16_t lres = m_secondary_r[rx] + (uint16_t)(~imm6) + uint32_t(1); - update_nzsc(lres, m_secondary_r[rx] , ~imm6); - - //unimplemented_opcode(op, ximm); - return; - break; - } - case 0x06: // neg - // A = -B - logerror( "(Extended group 6) %s = -%02x\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x08: // xor - // A ^= B - logerror( "(Extended group 6) %s ^= %02x\n", extregs[rx], imm6 ); + // store is invalid? unimplemented_opcode(op, ximm); - return; - break; - - case 0x09: // load - { - // A = B - //logerror( "(Extended group 6) %s = %02x\n", extregs[rx], imm6 ); - - m_core->m_icount -= 1; // TODO - - uint16_t lres = imm6; - update_nz(lres); - m_secondary_r[rx] = (uint16_t)lres; - - return; - break; } - case 0x0a: // or - // A |= B - logerror( "(Extended group 6) %s |= %02x\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0b: // and - // A &= B - logerror( "(Extended group 6) %s &= %02x\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; + bool write = do_basic_alu_ops(aluop, lres, b, c, storeaddr, true); - case 0x0c: // test - // TEST A,B - logerror( "(Extended group 6) test %s, %02x\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0d: // store, B = A (invalid for this type) - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 6) <INVALID IM6 Rx=Rx op IM6 form>\n"); - unimplemented_opcode(op, ximm); - return; - break; + if (write) + { + // A = Rx + m_core->m_r[rx + 8] = (uint16_t)lres; } - unimplemented_opcode(op, ximm); return; } case 0x0c: case 0x0d: case 0x0e: case 0x0f: { - // Ext Base+Disp6 Rx=Rx op [BP+IM6] + // Ext Base+Disp6 + // Rx = Rx op [BP+IM6] + // A = B op C + uint8_t aluop = (ximm & 0xf000) >> 12; uint8_t rx = (ximm & 0x0e00) >> 9; uint8_t imm6 = (ximm & 0x003f) >> 0; - switch (aluop) - { - case 0x00: // add - // A += B - logerror( "(Extended group 7) %s += [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x01: // adc - // A += B, Carry - logerror( "(Extended group 7) %s += [BP+%02x], carry\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; + uint32_t addr = (uint16_t)(m_core->m_r[REG_BP] + (imm6 & 0x3f)); - case 0x02: // sub - // A -= B - logerror( "(Extended group 7) %s -= [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; + uint16_t b = m_core->m_r[rx + 8]; + uint16_t c = read16(addr); - case 0x03: // sbc - // A -= B, Carry - logerror( "(Extended group 7) %s -= [BP+%02x], carry\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; + uint32_t storeaddr = addr; // dest address for STORE + uint32_t lres; - case 0x04: // cmp - // CMP A,B - logerror( "(Extended group 7) cmp %s, [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x06: // neg - // A = -B - logerror( "(Extended group 7) %s = -[BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x08: // xor - // A ^= B - logerror( "(Extended group 7) %s ^= [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x09: // load - // A = B - logerror( "(Extended group 7) %s = [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0a: // or - // A |= B - logerror( "(Extended group 7) %s |= [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0b: // and - // A &= B - logerror( "(Extended group 7) %s &= [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0c: // test - // TEST A,B - logerror( "(Extended group 7) test %s, [BP+%02x]\n", extregs[rx], imm6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0d: // store - // B = A - logerror( "(Extended group 7) [BP+%02x] = %s\n", imm6, extregs[rx] ); - unimplemented_opcode(op, ximm); - return; - break; + bool write = do_basic_alu_ops(aluop, lres, b, c, storeaddr, true); - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 7) <INVALID Base+Disp6 Rx=Rx op [BP+IM6] form>\n"); - unimplemented_opcode(op, ximm); - return; - break; + if (write) + { + // A = Rx + m_core->m_r[rx + 8] = (uint16_t)lres; } - unimplemented_opcode(op, ximm); return; } case 0x1c: case 0x1d: case 0x1e: case 0x1f: { - // Ext A6 Rx=Rx op [A6] - uint8_t aluop = (ximm & 0xf000) >> 12; - uint8_t rx = (ximm & 0x0e00) >> 9; - uint8_t a6 = (ximm & 0x003f) >> 0; - - switch (aluop) - { - case 0x00: // add - // A += B - logerror( "(Extended group 8) %s += [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x01: // adc - // A += B, Carry - logerror( "(Extended group 8) %s += [%02x], carry\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x02: // sub - // A -= B - logerror( "(Extended group 8) %s -= [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x03: // sbc - // A -= B, Carry - logerror( "(Extended group 8) %s -= [%02x], carry\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x04: // cmp - // CMP A,B - logerror( "(Extended group 8) cmp %s, [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x06: // neg - // A = -B - logerror( "(Extended group 8) %s = -[%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x08: // xor - // A ^= B - logerror( "(Extended group 8) %s ^= [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x09: // load - // A = B - logerror( "(Extended group 8) %s = [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0a: // or - // A |= B - logerror( "(Extended group 8) %s |= [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; + // Ext A6 + // Rx = Rx op [A6] + // A = B op C - case 0x0b: // and - // A &= B - logerror( "(Extended group 8) %s &= [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0c: // test - // TEST A,B - logerror( "(Extended group 8) test %s, [%02x]\n", extregs[rx], a6 ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x0d: // store - // B = A - logerror( "(Extended group 8) [%02x] = %s\n", a6, extregs[rx] ); - unimplemented_opcode(op, ximm); - return; - break; - - case 0x05: // invalid - case 0x07: // invalid - case 0x0e: // invalid - case 0x0f: // invalid - logerror( "(Extended group 8) <INVALID A6 Rx=Rx op [A6] form>\n"); - unimplemented_opcode(op, ximm); - return; - break; - } + //uint8_t aluop = (ximm & 0xf000) >> 12; + //uint8_t rx = (ximm & 0x0e00) >> 9; + //uint8_t a6 = (ximm & 0x003f) >> 0; + logerror("(Extended group 8 'Rx=Rx op [A6]' form) unimplemented "); unimplemented_opcode(op, ximm); return; |