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-rw-r--r--src/devices/cpu/sparc/mb86901.cpp32
-rw-r--r--src/devices/cpu/sparc/sparc.h4
-rw-r--r--src/devices/cpu/sparc/sparc_intf.h2
-rw-r--r--src/devices/cpu/sparc/sparcdefs.h10
4 files changed, 24 insertions, 24 deletions
diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp
index 751e39610e3..8ec274535ad 100644
--- a/src/devices/cpu/sparc/mb86901.cpp
+++ b/src/devices/cpu/sparc/mb86901.cpp
@@ -50,7 +50,7 @@ mb86901_device::mb86901_device(const machine_config &mconfig, const char *tag, d
: cpu_device(mconfig, MB86901, tag, owner, clock)
, m_mmu(*this, finder_base::DUMMY_TAG)
{
- m_default_config = address_space_config("program", ENDIANNESS_BIG, 32, 32);
+ m_default_config = address_space_config("program", ENDIANNESS_BIG, 32, 32);
}
@@ -471,8 +471,8 @@ void mb86901_device::device_reset()
device_memory_interface::space_config_vector mb86901_device::memory_space_config() const
{
- space_config_vector config_vector;
- config_vector.push_back(std::make_pair(AS_PROGRAM, &m_default_config));
+ space_config_vector config_vector;
+ config_vector.push_back(std::make_pair(AS_PROGRAM, &m_default_config));
return config_vector;
}
@@ -3376,26 +3376,26 @@ void mb86901_device::execute_trap()
/* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156)
illegal_IU_instr :- (
- if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
- or
- ( ((op=11) or (op=10)) and (op3=unassigned) )
- then 1 else 0
+ if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
+ or
+ ( ((op=11) or (op=10)) and (op3=unassigned) )
+ then 1 else 0
if (illegal_IU_instr = 1) then (
- trap <- 1
- illegal_instruction <- 1
+ trap <- 1
+ illegal_instruction <- 1
);
if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then (
- trap <- 1;
- fp_disabled <- 1
+ trap <- 1;
+ fp_disabled <- 1
);
if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then (
- trap <- 1;
- cp_disabled <- 1
+ trap <- 1;
+ cp_disabled <- 1
);
next;
if (trap = 0) then (
- { code for specific instruction, defined below }
+ { code for specific instruction, defined below }
);
*/
@@ -3653,8 +3653,8 @@ void mb86901_device::run_loop()
{
/*if (HOLD_BUS)
{
- m_icount--;
- continue;
+ m_icount--;
+ continue;
}*/
if (CHECK_DEBUG)
diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h
index 1bbcccc44fe..14edcd19d01 100644
--- a/src/devices/cpu/sparc/sparc.h
+++ b/src/devices/cpu/sparc/sparc.h
@@ -124,7 +124,7 @@ protected:
required_device<sparc_mmu_interface> m_mmu;
// address spaces
- address_space_config m_default_config;
+ address_space_config m_default_config;
// memory access
uint32_t read_sized_word(const uint8_t asi, const uint32_t address, const uint32_t mem_mask);
@@ -300,4 +300,4 @@ enum
SPARC_RESET
};
-#endif // MAME_CPU_SPARC_SPARC_H \ No newline at end of file
+#endif // MAME_CPU_SPARC_SPARC_H
diff --git a/src/devices/cpu/sparc/sparc_intf.h b/src/devices/cpu/sparc/sparc_intf.h
index a203abd92ea..5e904b4f04f 100644
--- a/src/devices/cpu/sparc/sparc_intf.h
+++ b/src/devices/cpu/sparc/sparc_intf.h
@@ -27,4 +27,4 @@ public:
virtual void write_asi(uint8_t asi, uint32_t offset, uint32_t data, uint32_t mem_mask) = 0;
};
-#endif // MAME_CPU_SPARC_SPARC_INTF_H \ No newline at end of file
+#endif // MAME_CPU_SPARC_SPARC_INTF_H
diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h
index 050f1aa1f74..385392feacb 100644
--- a/src/devices/cpu/sparc/sparcdefs.h
+++ b/src/devices/cpu/sparc/sparcdefs.h
@@ -81,7 +81,7 @@
#define WIM m_wim
#define TBR m_tbr
-#define OP_NS (op & 0xc0000000)
+#define OP_NS (op & 0xc0000000)
#define OP (op >> 30)
#define OP2 ((op >> 22) & 7)
@@ -155,10 +155,10 @@
#define OP_ALU u32(2)
#define OP_LDST u32(3)
-#define OP_TYPE0_NS (OP_TYPE0 << 30)
-#define OP_CALL_NS (OP_CALL << 30)
-#define OP_ALU_NS (OP_ALU << 30)
-#define OP_LDST_NS (OP_LDST << 30)
+#define OP_TYPE0_NS (OP_TYPE0 << 30)
+#define OP_CALL_NS (OP_CALL << 30)
+#define OP_ALU_NS (OP_ALU << 30)
+#define OP_LDST_NS (OP_LDST << 30)
#define OP2_UNIMP 0
#define OP2_BICC 2