diff options
Diffstat (limited to 'src/devices/cpu/m6805/m68705.cpp')
-rw-r--r-- | src/devices/cpu/m6805/m68705.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/devices/cpu/m6805/m68705.cpp b/src/devices/cpu/m6805/m68705.cpp index b006727904f..814a0ca57d6 100644 --- a/src/devices/cpu/m6805/m68705.cpp +++ b/src/devices/cpu/m6805/m68705.cpp @@ -119,6 +119,7 @@ DEFINE_DEVICE_TYPE(M6805R2, m6805r2_device, "m6805r2", "Motorola MC6805R2") DEFINE_DEVICE_TYPE(M6805R3, m6805r3_device, "m6805r3", "Motorola MC6805R3") DEFINE_DEVICE_TYPE(M6805U2, m6805u2_device, "m6805u2", "Motorola MC6805U2") DEFINE_DEVICE_TYPE(M6805U3, m6805u3_device, "m6805u3", "Motorola MC6805U3") +DEFINE_DEVICE_TYPE(HD6805S1, hd6805s1_device, "hd6805s1", "Hitachi HD6805S1") DEFINE_DEVICE_TYPE(HD6805U1, hd6805u1_device, "hd6805u1", "Hitachi HD6805U1") /**************************************************************************** @@ -817,6 +818,15 @@ m6805u3_device::m6805u3_device(machine_config const &mconfig, char const *tag, d m_timer.set_options(m6805_timer::TIMER_PGM); } +hd6805s1_device::hd6805s1_device(machine_config const &mconfig, char const *tag, device_t *owner, uint32_t clock) + : m6805_mrom_device(mconfig, tag, owner, clock, HD6805S1, 11, 64) +{ + m_timer.set_options(m6805_timer::TIMER_NPC); + + set_port_mask<2>(0xf0); // Port C is four bits wide + set_port_mask<3>(0xff); // Port D isn't present +} + hd6805u1_device::hd6805u1_device(machine_config const &mconfig, char const *tag, device_t *owner, uint32_t clock) : m6805_mrom_device(mconfig, tag, owner, clock, HD6805U1, 12, 96) { @@ -858,14 +868,24 @@ void m6805_mrom_device::internal_map(address_map &map) * * Device Reg/RAM Page Zero Main User Self Check Vectors * 6805P2 0000-007f 0080-00ff 03c0-07b3 07b4-07f7 07f8-07ff + * 6805P4 0000-007f 0080-00ff 03c0-0783 0784-07f7 07f8-07ff * 6805P6 0000-007f 0080-00ff 0100-07b3 07b4-07f7 07f8-07ff * 6805R2 0000-007f 0080-00ff 07c0-0f37 0f38-0ff7 0ff8-0fff * 6805R3 0000-007f 0080-0f37 0f38-0ff7 0ff8-0fff * 6805S2 0000-007f 0080-00ff 09c0-0eff 0f00-0ff7 0ff8-0fff * 6805S3 0000-007f 0080-00ff 0100-0eff 0f00-0ff7 0ff8-0fff + * 6805T2 0000-007f 0080-07ff 0d40-0f83 0f84-0ff7 0ff8-0fff * 6805U2 0000-007f 0080-00ff 07c0-0f37 0f38-0ff7 0ff8-0fff * 6805U3 0000-007f 0080-0f37 0f38-0ff7 0ff8-0fff + * + * Hitachi NMOS variants: + * + * Device Reg/RAM Page Zero Main User Self Check Vectors + * 6805S1 0000-007f 0080-00ff 03c0-0783 0784-07f7 07f8-07ff + * 6805S6 0000-007f 0080-00ff 0100-0783 0784-07f7 07f8-07ff * 6805U1 0000-007f 0080-00ff 0800-0f7f 0f80-0ff7 0ff8-0fff + * 6805V1 0000-007f 0080-00ff 0100-0f7f 0f80-0ff7 0ff8-0fff + * 6805W1 0000-007f 0080-00ff 0100-0f79 0f7a-0ff1 0ff2-0fff * * This code assumes that dumps are captured contiguously from address 0 to * the end of the address range, and are not split by range. Register, RAM |