diff options
Diffstat (limited to 'src/devices/cpu/dsp16/dsp16.cpp')
-rw-r--r-- | src/devices/cpu/dsp16/dsp16.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/devices/cpu/dsp16/dsp16.cpp b/src/devices/cpu/dsp16/dsp16.cpp index bd9003fb9b6..a4ff22587e9 100644 --- a/src/devices/cpu/dsp16/dsp16.cpp +++ b/src/devices/cpu/dsp16/dsp16.cpp @@ -32,7 +32,7 @@ There's a 15-word "cache" that the DSP can execute from without the cost of instruction fetches. There's an instruction to cache the - next N instructions and repeat them M times, and in instruction to + next N instructions and repeat them M times, and an instruction to execute the currently cached instructions M times. Interrupts are not serviced while executing from cache, and not all instructions can be cached. @@ -854,7 +854,7 @@ template <bool Debugger, bool Caching> inline void dsp16_device_base::execute_so m_phase = phase::OP2; break; - case 0x0e: // do K { instr1...instrIN } # redo K + case 0x0e: // do K { instr1...instrNI } # redo K { u16 const ni(op_ni(op)); if (ni) @@ -1601,7 +1601,7 @@ inline bool dsp16_device_base::op_interruptible(u16 op) return true; case 0x00: // goto JA case 0x01: - case 0x0e: // do K { instre1...instrNI } # redo K + case 0x0e: // do K { instr1...instrNI } # redo K case 0x10: // call JA case 0x11: case 0x18: // goto B |