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-rw-r--r--src/devices/cpu/arm7/arm7core.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/devices/cpu/arm7/arm7core.h b/src/devices/cpu/arm7/arm7core.h
index c33bdee9dd2..9ae499ae109 100644
--- a/src/devices/cpu/arm7/arm7core.h
+++ b/src/devices/cpu/arm7/arm7core.h
@@ -470,6 +470,11 @@ enum
COND_NV /* 0 never */
};
+#define LSL(v, s) ((v) << (s))
+#define LSR(v, s) ((v) >> (s))
+#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s))))
+#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s))))
+
/* Convenience Macros */
#define R15 m_r[eR15]
#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18]